24th week of 2009 patent applcation highlights part 42 |
Patent application number | Title | Published |
20090148975 | Method of manufacturing nitride semiconductor device - A method of manufacturing a nitride semiconductor device includes: a working region forming step of forming a working region in a group III nitride semiconductor substrate by converging a laser beam having a wavelength of 500 nm to 700 nm in the group III nitride semiconductor substrate and by scanning a convergent point of the laser beam in a prescribed scanning direction in the interior of the group III nitride semiconductor substrate; and a dividing step of dividing the group III nitride semiconductor substrate by generating a crack from the working region without processing a surface of the group III nitride semiconductor substrate. | 2009-06-11 |
20090148976 | Method for fabricating semiconductor epitaxial layers using metal islands - Disclosed is a method for fabricating a GaN semiconductor epitaxial layer. The method includes the steps of: (a) providing a substrate within a reaction furnace; (b) setting a temperature range of the substrate to be 200° C.˜1,300° C.; (C) supplying a Ga metallic source on the substrate; (d) changing the supplied Ga metallic source on the substrate, to Ga metal islands; (e) supplying a nitrogenous source to the Ga metal islands after suspending supply of the Ga metallic source; (f) forming GaN islands by reacting the Ga metal islands with the nitrogenous source; and (g) growing a GaN epitaxial layer by basing the GaN islands as a seed. | 2009-06-11 |
20090148977 | PACKAGING METHOD FOR IMAGE SENSOR IC - The method contains the following steps. First, a number of circuit blocks are formed in one or more tightly populated array on an uncut substrate. The substrate is then placed on a flat platform where a number of pins on the platform threading through corresponding holes of the substrate. A number of image sensor ICs are then fixed on the circuit blocks, respectively, and the ICs are wire-bonded to their underlying circuit blocks. Subsequently, gaps between the ICs are filled with an adhesive until the adhesive is slightly over a top side of the ICs. An uncut filtering glass is placed on the adhesive and the pins of the platform before the adhesive is thermally cured. To separate packaged image sensor IC modules, cutting is performed in the middle of the cured adhesive between two adjacent rows and columns of ICs. | 2009-06-11 |
20090148978 | PROCESSES FOR FORMING PHOTOVOLTAIC CONDUCTIVE FEATURES FROM MULTIPLE INKS - Photovoltaic conductive features and processes for forming photovoltaic conductive features are described. The process comprises (a) providing a substrate comprising a passivation layer disposed on a silicon layer; (b) depositing a surface modifying material onto at least a portion of the passivation layer; (c) depositing a composition comprising at least one of metallic nanoparticles comprising a metal or a metal precursor to the metal onto at least a portion of the substrate; and (d) heating the composition such that it forms at least a portion of a photovoltaic conductive feature in electrical contact with the silicon layer, wherein at least one of the composition or the surface modifying material etches a region of the passivation layer. When the surface modifying material is a UV-curable material, the process comprises the additional step of curing the UV-curable material. | 2009-06-11 |
20090148979 | FABRICATING APPARATUS WITH DOPED ORGANIC SEMICONDUCTORS - A method includes forming a semiconducting region including polyaromatic molecules on a surface of a substrate. The method also includes forming over the region a substantially oxygen impermeable dielectric layer. The act of forming a semiconducting region includes exposing the molecules to oxygen while exposing the molecules to visible or ultraviolet light. | 2009-06-11 |
20090148980 | METHOD FOR FORMING PHASE-CHANGE MEMORY ELEMENT - A method for forming a phase-change memory element. The method includes providing a substrate with an electrode formed thereon; sequentially forming a conductive layer and a first dielectric layer on the substrate; forming a patterned photoresist layer on the first dielectric layer; subjecting the patterned photoresist layer to a trimming process, remaining a photoresist pillar; etching the first dielectric layer with the photoresist pillar as etching mask, remaining a dielectric pillar; comformally forming a first phase-change material layer on the conductive layer and the dielectric pillar to cover the top surface and side walls of the dielectric pillar; forming a second dielectric layer to cover the first phase-change material layer; subjecting to the second dielectric layer and the first phase-change material layer to a planarization until exposing the top surface of the dielectric pillar; and forming a second phase-change material layer on the second dielectric layer. | 2009-06-11 |
20090148981 | METHOD FOR FORMING SELF-ALIGNED THERMAL ISOLATION CELL FOR A VARIABLE RESISTANCE MEMORY ARRAY - A non-volatile memory with a self-aligned RRAM element includes a lower electrode element, generally planar in form, having an inner contact surface; an upper electrode element, spaced from the lower electrode element; a containment structure extends between the upper electrode element and the lower electrode element, with a sidewall spacer element having a generally funnel-shaped central cavity with a central aperture; and a spandrel element positioned between the sidewall spacer element and the lower electrode. A RRAM element extends between the lower electrode element and the upper electrode, occupying at least a portion of the sidewall spacer element central cavity and projecting from the sidewall spacer terminal edge toward and making contact with the lower electrode. In this manner, the spandrel element inner surface is spaced from the RRAM element to define a thermal isolation cell adjacent the RRAM element. | 2009-06-11 |
20090148982 | Method of Manufacturing Compound Semiconductor Devices - A compound semiconductor device and method of manufacturing the same. The method includes coating a plurality of spherical balls on a substrate and selectively growing a compound semiconductor thin film on the substrate on which the spherical balls are coated. The entire process can be simplified and a high-quality compound semiconductor thin film can be grown in a short amount of time in comparison to an epitaxial lateral overgrowth (ELO) method. | 2009-06-11 |
20090148983 | Method of Manufacturing Flexible Semiconductor Assemblies - A method for producing flexible semiconductor assemblies is described. For example, an integrated circuit package consisting of an X-Y axes sensor die and a Z-axis sensor die disposed at 90 degrees to each other may be formed by applying a flexible dielectric membrane to a semiconductor wafer, creating bending gaps between the sensor dice, singulating the IC package from the wafer, and bending the flexible dielectric membrane so that the sensor dice are disposed orthogonally to each other. This method eliminates the need to precisely position previously singulated sensor dice relative to each other in order to apply a flexible dielectric membrane for purposes of interconnecting the dice. | 2009-06-11 |
20090148984 | BULK GaN AND AlGaN SINGLE CRYSTALS - Bulk GaN and AlGaN single crystal boules, preferably fabricated using a modified HVPE process, are provided. The single crystal boules typically have a volume in excess of 4 cubic centimeters with a minimum dimension of approximately 1 centimeter. If desired, the bulk material can be doped during growth, for example to achieve n-, i-, or p-type conductivity. | 2009-06-11 |
20090148985 | Method for Fabricating a Nitride FET Including Passivation Layers - A method for fabricating a nitride-based FET device that provides reduced electron trapping and gate current leakage. The fabrication method provides a device that includes a relatively thick passivation layer to reduce traps caused by device processing and a thin passivation layer below the gate terminal to reduce gate current leakage. Semiconductor device layers are deposited on a substrate. A plurality of passivation layers are deposited on the semiconductor device layers, where at least two of the layers are made of a different dielectric material to provide an etch stop. One or more of the passivation layers can be removed using the interfaces between the layers as an etch stop so that the distance between the gate terminal and the semiconductor device layers can be tightly controlled, where the distance can be made very thin to increase device performance and reduce gate current leakage. | 2009-06-11 |
20090148986 | METHOD OF MAKING A FINFET DEVICE STRUCTURE HAVING DUAL METAL AND HIGH-K GATES - A method of making a FinFET device structure, includes: providing a semiconductor-on-insulator (SOI) substrate having a semiconductor layer on an insulating layer on a base (e.g., semiconductor) layer; forming a cap layer (e.g., silicon nitride) on the SOI substrate; forming, on the insulating layer, first and second semiconductor fins with a first cap layer on the first fin and a second cap layer on the second fin; providing a first high-k dielectric layer across the first and the second cap layers and the first and second fins; providing a first metal layer onto the first high-k dielectric layer; providing a first semiconductor layer onto the first metal layer; removing the first semiconductor layer, the first metal layer, and the first high-k dielectric layer from the second cap layer, the second fin and from regions adjacent to the second fin; providing a second high-k dielectric layer onto the second cap layer, the second fin and a portion of the first metal layer; providing a second metal layer onto the second high-k dielectric layer, the second metal layer having a composition different than the first metal layer; providing a second semiconductor layer onto the second metal layer in a region above the second cap layer and into the regions adjacent to the second fin; removing the second semiconductor layer from the second metal layer in the region above the second cap layer, from adjoining regions and from the regions adjacent to the second fin; removing the second metal layer and the second high-k dielectric layer from a region above the first cap layer and from adjoining regions above the first semiconductor layer; removing the first metal layer, the first high-k dielectric layer, the first semiconductor layer, the second metal layer, the second high-k dielectric layer and the second semiconductor layer from regions above a plane containing top surfaces of the first and the second cap layers; forming first and second gates; forming respective source and drain regions within portions of the first and the second fins adjacent to the first and second gates, and then removing portions of the first and the second semiconductor layers, the first and the second high-k dielectric layers and the first and the second metal layers from a medial region between the first and the second fins. | 2009-06-11 |
20090148987 | METHOD FOR FABRICATING PIXEL STRUCTURE - A method for fabricating a pixel structure is disclosed. A substrate is provided. A first conductive layer is formed on the substrate, and a first shadow mask exposing a portion of the first conductive layer is disposed over the first conductive layer. Laser is used to irradiate the first conductive layer for removing the part of the first conductive layer and forming a gate. A gate dielectric layer is formed on the substrate to cover the gate. A channel layer is formed on the gate dielectric layer over the gate. A source and a drain are formed on the channel layer and respectively above both sides of the gate. A patterned passivation layer is formed to cover the channel layer and expose the drain. An electrode material layer is formed to cover the patterned passivation layer and the exposed drain. | 2009-06-11 |
20090148988 | METHOD OF REDUCING EMBEDDED SIGE LOSS IN SEMICONDUCTOR DEVICE MANUFACTURING - Embodiments of the invention provide a method of forming embedded silicon germanium (eSiGe) in source and drain regions of a p-type field-effect-transistor (pFET) through a disposable spacer process; depositing a gap-filling layer directly on the eSiGe in the source and drain regions in a first process; depositing a layer of offset spacer material on top of the gap-filling layer in a second process different from the first process; etching the offset spacer material and the gap-filling layer, thus forming a set of offset spacers and exposing the eSiGe in the source and drain regions of the pFET; and finishing formation of the pFET. | 2009-06-11 |
20090148989 | SEMICONDUCTOR DEVICE COMPRISING CAPACITOR AND METHOD OF FABRICATING THE SAME - A semiconductor device, having a memory cell region and a peripheral circuit region, includes an insulating film, having an upper surface, formed on a major surface of a semiconductor substrate to extend from the memory cell region to the peripheral circuit region. A capacitor lower electrode assembly is formed in the memory cell region to upwardly extend to substantially the same height as the upper surface of the insulating film on the major surface of the semiconductor substrate. Additionally, the lower electrode assembly includes first and second lower electrodes that are adjacent through the insulating film. A capacitor upper electrode is formed on the capacitor lower electrode through a dielectric film, to extend onto the upper surface of the insulating film. The capacitor lower electrode includes a capacitor lower electrode part having a top surface and a bottom surface. A semiconductor device organized as just described, permits implementation having a high density of integration while ensuring the capacitor exhibits high reliability and a constant capacitance. | 2009-06-11 |
20090148990 | Semiconductor devices and methods of forming the same - A method of forming a semiconductor device includes forming line patterns on a substrate, the line patterns defining narrow and wide gap regions, forming spacer patterns in the narrow and wide gap regions on sidewalls of the line patterns, spacer patterns in the wide gap regions exposing an upper surface of the substrate, and spacer patterns in the narrow gap regions contacting each other to fill the narrow gap regions, forming an insulating interlayer to cover the spacer patterns and the line patterns, forming at least one opening through the insulating interlayer, the opening including at least one contact hole selectively exposing the upper surface of the substrate in the wide gap region, the contact hole being formed by using the spacer patterns in the narrow gap region as an etching mask, and forming a conductive pattern to fill the opening. | 2009-06-11 |
20090148991 | Method of fabricating semiconductor device having vertical channel transistor - A method of fabricating a semiconductor device having a vertical channel transistor, the method including forming a hard mask pattern on a substrate, forming a preliminary active pillar by etching the substrate using the hard mask pattern as an etch mask, reducing a width of the preliminary active pillar to form an active pillar having a width less than that of the hard mask pattern, forming a lower source/drain region by implanting impurity ions into the substrate adjacent to the active pillar using the hard mask pattern as an ion implantation mask, and forming an upper source/drain region on the active pillar and vertically separated from the lower source/drain region. | 2009-06-11 |
20090148992 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes: a semiconductor substrate; multiple active regions of a first conductive type isolated from one another by shallow-trench isolation regions provided on one surface of the semiconductor substrate; multiple silicon pillars including channel silicon pillars formed in the active regions; multiple first semiconductor regions of a second conductive type that are respectively formed on bottom ends of the silicon pillars and to be sources or drains; multiple second semiconductor regions of the second conductive type that are formed on top ends of the silicon pillars and to be sources or drains; multiple gate insulating films surrounding the silicon pillars; and multiple gate electrodes surrounding the gate insulating films. At least one of the channel silicon pillars has a height different from that of another one of the channel silicon pillars. | 2009-06-11 |
20090148993 | METHOD OF FABRICATING SEMICONDUCTOR DEVICE HAVING A RECESS CHANNEL STRUCTURE THEREIN - A method of fabricating a semiconductor device having a recess channel structure is provided. A first recess is formed in a substrate. A liner and a filling layer are formed in the first recess. A portion of the substrate adjacent to the first recess and a portion of the liner and the filling layer are removed to form trenches. An insulation layer fills the trenches to form isolation structures. The filling layer is removed, using the liner as an etching stop layer, to expose the insulation layer. A portion of the exposed insulation layer is removed to form a second recess having divots adjacent to the sidewalls of the substrate. The liner is removed. A dielectric layer and a gate are formed over the substrate covering the second recess. Source and drain regions are formed in the substrate adjacent to the second recess. | 2009-06-11 |
20090148994 | Method of manufacturing semiconductor device with recess gate transistor - A method of manufacturing a semiconductor device includes forming a plurality of recesses in a semiconductor substrate, forming a gate insulating film in the plurality of recesses, and a plurality of gate electrodes on the gate insulating film in the plurality of recesses, forming an insulating layer on the semiconductor substrate and the plurality of gate electrodes, forming a plurality of contact holes in the insulating layer, the contact holes being formed between adjacent ones of the plurality of gate electrodes, implanting a first impurity into the semiconductor substrate through the plurality of contact holes to form each of source and drain regions in contact with the gate insulating film. | 2009-06-11 |
20090148995 | Processes for manufacturing MOSFET devices with excessive round-hole shielded gate trench (SGT) - This invention discloses an improved method for manufacturing a trenched metal oxide semiconductor field effect transistor (MOSFET) device. The method includes a step of opening a trench in substrate and covering trench walls of the trench with a linen layer followed by removing a portion of the linen layer from a bottom portion of the trench. The method further includes a step of opening a round hole by applying an isotropic substrate etch on the bottom portion of the trench with the round hole extending laterally from the trench walls. The method further includes a step of filling the trench and the round hole at the bottom of the trench with a gate material followed by applying a time etch to removed the gate material from a top portion of the trench whereby the gate material only filling the round hole up to a lateral expansion point of the round hole. | 2009-06-11 |
20090148996 | METHOD OF MAKING A SEMICONDUCTOR ELEMENT - A method of producing a capacitor that includes producing a first electrode having a first surface; forming a recess in an element, walls of the element and the first surface of the first electrode defining the recess, the element having a first surface exterior of the recess; forming a dielectric layer on the element, the dielectric layer oriented against the first surface of the element and against the walls of the element within the recess; polishing off at least a portion of the dielectric layer oriented against the first surface of the element to electrically isolate the portion of the dielectric layer located in the recess from any portion of the dielectric layer remaining outside the recess; and producing a second electrode, the second electrode oriented at least partially within the recess with the dielectric layer oriented between the first electrode and the second electrode. | 2009-06-11 |
20090148997 | PROCESS FOR MANUFACTURING SEMICONDUCTOR DEVICE - Reduction of damage to a semiconductor device due to a marking process while inhibiting deterioration of a mark can not be achieved in conventional processes for manufacturing semiconductor devices. A process for manufacturing the semiconductor device | 2009-06-11 |
20090148998 | SEMICONDUCTOR STRUCTURE AND METHOD OF MANUFACTURE - In various embodiments, semiconductor structures and methods to manufacture these structures are disclosed. In one embodiment, a method includes removing a portion of a semiconductor material using an orientation-dependent etch to form a first cavity, a second cavity, wherein the first cavity is isolated from the second cavity, a first protrusion is between the first cavity and the second cavity, and the semiconductor material comprises silicon. The method further includes performing a thermal oxidation to convert a portion of the silicon of the semiconductor material to silicon dioxide and forming a first dielectric material over the first cavity, over the second cavity, over at least a portion of the semiconductor material, and over at least a portion of the first protrusion. Other embodiments are described and claimed. | 2009-06-11 |
20090148999 | SEMICONDUCTOR STRUCTURE AND METHOD OF MANUFACTURE - In various embodiments, semiconductor structures and methods to manufacture these structures are disclosed. In one embodiment, a method to manufacture a semiconductor structure includes forming a cavity in a substrate. A portion of the substrate is doped, or a doped material is deposited over a portion of the substrate. At least a portion of the doped substrate or at least a portion of the doped material is converted to a dielectric material to enclose the cavity. The forming of the cavity may occur before or after the doping of the substrate or the depositing of the doped material. Other embodiments are described and claimed. | 2009-06-11 |
20090149000 | Combined semiconductor apparatus with thin semiconductor films - A semiconductor apparatus includes two thin semiconductor films bonded to a substrate, and a thin-film interconnecting line electrically connecting a semiconductor device such as a light-emitting device in the first thin semiconductor film to an integrated circuit in the second thin semiconductor film. Typically, the integrated circuit drives the semiconductor device. The two thin semiconductor films are formed separately from the substrate. The first thin semiconductor film may include an array of semiconductor devices. The first and second thin semiconductor films may be replicated as arrays bonded to the same substrate. Compared with conventional semiconductor apparatus comprising an array chip and a separate driver chip, the invented apparatus is smaller and has a reduced material cost. | 2009-06-11 |
20090149001 | PRODUCING SOI STRUCTURE USING HIGH-PURITY ION SHOWER - Disclosed are methods for making SOI and SOG structures using purified ion shower for implanting ions to the donor substrate. The purified ion shower provides expedient, efficient, low-cost and effective ion implantation while minimizing damage to the exfoliation film. | 2009-06-11 |
20090149002 | METHOD OF FORMING A MODIFIED LAYER IN A SUBSTRATE - First, mapping data storing interrupted areas is obtained. In a first modified-layer forming step, before a stacked article is stacked on a front surface of a substrate, a laser beam is directed to the interrupted areas based on the mapping data to form modified layers only at the interrupted areas. After the stacked articles have been stacked on the substrate, in a second modified-layer forming step, the laser beam is directed at least to the predetermined dividing line formed with no modified layer in the first modified-layer forming step to form a modified layer. | 2009-06-11 |
20090149003 | DICING DIE-BONDING FILM - The invention relates to a dicing die-bonding film having a pressure-sensitive adhesive layer ( | 2009-06-11 |
20090149004 | Micromirror manufacturing method - A micro-mirror manufacturing method for dividing a plurality of micro-mirror devices each having at least one mirror, formed on a semiconductor wafer into individual micro-mirror devices can be provided. The manufacturing method comprises a step of depositing an inorganic protection layer on the mirror before separating the micro-mirror devices from the wafer and a step of removing the inorganic protection layer after separating the micro-mirror devices from the wafer. | 2009-06-11 |
20090149005 | METHOD FOR MAKING A DISMOUNTABLE SUBSTRATE - The invention concerns a method for forming a growth mask on the surface of an initial crystalline substrate, comprising the following steps:
| 2009-06-11 |
20090149006 | Methods of forming a phase-change material layer pattern, methods of manufacturing a phase-change memory device and related slurry compositions - In methods of forming a phase-change material layer pattern, an insulation layer having a recessed portion may be formed on a substrate, and a phase-change material layer may be formed on the insulation layer to fill the recessed portion. A first polishing process may be performed on the phase-change material layer using a first slurry composition to partially remove the phase-change material layer, the first slurry composition having a first polishing selectivity between the insulation layer and the phase-change material layer. A second polishing process may be performed on the phase-change material layer using a second slurry composition to form a phase-change material layer pattern in the recessed portion, the second slurry composition having a second polishing selectivity substantially lower than the first polishing selectivity. | 2009-06-11 |
20090149007 | ELECTRONIC DEVICE AND METHOD OF MANUFACTURING THE SAME - Provided are an electronic device and a method of manufacturing the same. The device includes a plastic substrate, a transparent thermal conductive layer stacked on the plastic substrate, a polysilicon layer stacked on the thermal conductive layer; and a functional device disposed on the polysilicon layer. The functional device is any one of a transistor, a light emitting device, and a memory device. The functional device may be a thin film transistor including a gate stack stacked on the polysilicon layer. | 2009-06-11 |
20090149008 | METHOD FOR DEPOSITING GROUP III/V COMPOUNDS - Embodiments of the invention generally relate to methods for forming Group III-V materials by a hydride vapor phase epitaxy (HVPE) process. In one embodiment, a method for forming a gallium nitride material on a substrate within a processing chamber is provided which includes heating a metallic source to form a heated metallic source, wherein the heated metallic source contains gallium, aluminum, indium, alloys thereof, or combinations thereof, exposing the heated metallic source to chlorine gas while forming a metallic chloride gas, exposing the substrate to the metallic chloride gas and a nitrogen precursor gas while forming a metal nitride layer on the substrate during the HVPE process. The method further provides exposing the substrate to chlorine gas during a pretreatment process prior to forming the metal nitride layer. In one example, the exhaust conduit of the processing chamber is heated to about 200° C. or less during the pretreatment process. | 2009-06-11 |
20090149009 | SEMICONDUCTOR STRUCTURE AND METHOD OF MANUFACTURE - In various embodiments, semiconductor structures and methods to manufacture these structures are disclosed. In one embodiment, a method includes removing a portion of a semiconductor material using an electrochemical etch to form a first cavity, a second cavity, wherein the first cavity is isolated from the second cavity, a first protrusion is between the first cavity and the second cavity, and the semiconductor material comprises silicon. The method further includes performing a thermal oxidation to convert a portion of the silicon of the semiconductor material to silicon dioxide and forming a first dielectric material over the first cavity, over the second cavity, over at least a portion of the semiconductor material, and over at least a portion of the first protrusion. Other embodiments are described and claimed. | 2009-06-11 |
20090149010 | STRUCTURES AND METHODS FOR MANUFACTURING OF DISLOCATION FREE STRESSED CHANNELS IN BULK SILICON AND SOI MOS DEVICES BY GATE STRESS ENGINEERING WITH SiGe AND/OR Si:C - Structures and methods of manufacturing are disclosed of dislocation free stressed channels in bulk silicon and SOI (silicon on insulator) CMOS (complementary metal oxide semiconductor) devices by gate stress engineering with SiGe and/or Si:C. A CMOS device comprises a substrate of either bulk Si or SOI, a gate dielectric layer over the substrate, and a stacked gate structure of SiGe and/or Si:C having stresses produced at the interfaces of SSi (strained Si)/SiGe or SSi/Si:C in the stacked gate structure. The stacked gate structure has a first stressed film layer of large grain size Si or SiGe over the gate dielectric layer, a second stressed film layer of strained SiGe or strained Si:C over the first stressed film layer, and a semiconductor or conductor such as p(poly)-Si over the second stressed film layer. | 2009-06-11 |
20090149011 | NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE AND PROCESS OF MANUFACTURING THE SAME - In device isolation trenches, a first device-isolation insulator film is formed to have recesses thereon and a second device-isolation insulator film is formed in the recesses. The uppermost portions at both ends of the first device-isolation insulator film are located higher than the uppermost portions at both ends of the second device-isolation insulator film. | 2009-06-11 |
20090149012 | METHOD OF FORMING A NONPLANAR TRANSISTOR WITH SIDEWALL SPACERS - A semiconductor device comprising a semiconductor body having a top surface and a first and second laterally opposite sidewalls as formed on an insulating substrate is claimed. A gate dielectric is formed on the top surface of the semiconductor body and on the first and second laterally opposite sidewalls of the semiconductor body. A gate electrode is then formed on the gate dielectric on the top surface of the semiconductor body and adjacent to the gate dielectric on the first and second laterally opposite sidewalls of the semiconductor body. The gate electrode comprises a metal film formed directly adjacent to the gate dielectric layer. A pair of source and drain regions are then formed in the semiconductor body on opposite sides of the gate electrode. | 2009-06-11 |
20090149013 | METHOD OF FORMING A CRACK STOP LASER FUSE WITH FIXED PASSIVATION LAYER COVERAGE - A crack stop void is formed in a low-k dielectric or silicon oxide layer between adjacent fuse structures for preventing propagation of cracks between the adjacent fuse structures during a fuse blow operation. The passivation layer is fixed in place by using an etch stop shape of conducting material which is formed simultaneously with the formation of the interconnect structure. This produces a reliable and repeatable fuse structure that has controllable passivation layer over the fuse structure that is easily manufactured. | 2009-06-11 |
20090149014 | METHOD FOR PRODUCING A SEMICONDUCTOR DEVICE | 2009-06-11 |
20090149015 | MANUFACTURING METHOD OF CONTACT STRUCTURE - A manufacturing method of a contact structure includes first providing a substrate on which a contact pad has already been formed. Afterwards, a polymer bump is formed on the contact pad. Next, a conductive layer is formed on the polymer bump. The conductive layer covers the polymer bump and extends to the outside of the polymer bump. The portion of the conductive layer extending to the outside of the polymer bump serves as a test pad. | 2009-06-11 |
20090149016 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - Provided is a semiconductor device and a method of fabricating the same. The method of fabricating the semiconductor device includes forming a mask pattern having an opening corresponding to an electrode pad formed on a semiconductor substrate; forming a bump by filling the opening with a conductive first material; forming a sidewall film on sidewalls of the bump using a second material; forming a connection member between an upper surface of the bump and a wire substrate using a conductive third material in order to electrically connect the bump and the wire substrate; and forming an underfill resin between the wire substrate and the semiconductor substrate, wherein a wetting angle between the second material and the third material is greater than that between the first material and the third material. | 2009-06-11 |
20090149017 | METHOD OF CLEANING SEMICONDUCTOR SUBSTRATE, AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR SUBSTRATE PROCESSING APPARATUS FOR USE IN THE SAME - A semiconductor substrate processing apparatus is provided with a cleaning process chamber containing a semiconductor substrate for performing a cleaning process on the semiconductor substrate. Connected to the cleaning process chamber is a cleaning liquid feeding pipe for supplying a cleaning liquid to the semiconductor substrate. A gas dissolving unit is provided in the midpoint of the cleaning liquid feeding pipe for dissolving a prescribed gas in ultrapure water. An inert gas or a reducing gas is dissolved as a prescribed gas in ultrapure water. A control unit is provided having a function of supplying the cleaning liquid with the prescribed gas dissolved therein to the semiconductor substrate subjected to the cleaning process before performing a dry process. Therefore, the surface of the semiconductor substrate is free from stains. Moreover, a metal interconnection does not elude. | 2009-06-11 |
20090149018 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE HAVING AN INTERCONNECT STRUCTURE THAT INCREASES IN IMPURITY CONCENTRATION AS WIDTH INCREASES - The present invention provides a semiconductor device capable of suppressing an increase in electrical resistance of a narrow interconnect, while keeping reliability of a wide interconnect from being degraded. A semiconductor device comprises a plurality of interconnect layers, and an interconnect in at least one interconnect layer among the plurality of interconnect layers contains an impurity, and the wider the interconnect in the at least one interconnect layer is, the higher concentration of the impurity the interconnect contains. | 2009-06-11 |
20090149019 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device has a first interlayer insulating film formed on a substrate, having a first interconnection buried therein, and having a depressed portion and an insulating barrier film formed on the first interlayer insulating film. A second interlayer insulating film is formed to fill in the depressed portion, cover the upper surface of the insulating barrier film, and have a second interconnection buried therein. | 2009-06-11 |
20090149020 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE - A technology is provided which allows, in a coupling portion obtained by burying a conductive material within a coupling hole bored in an insulating film, the removal of a natural oxide film on the surface of a silicide layer which is present at the bottom portion of the coupling hole. A coupling hole is bored in an interlayer insulating film (first and second insulating films) to expose the surface of a nickel silicide layer at the bottom portion of the coupling hole. Then, reduction gases including a HF gas and a NH | 2009-06-11 |
20090149021 | SPRAY DISPENSING METHOD FOR APPLYING LIQUID METAL - Embodiments of a method for applying a thermal-interface material are described. During this method, a first surface of a heat-removal device and a second surface of a semiconductor die are prepared. Next, a region on a given surface, which is at least one of the first surface and the second surface, is defined. Then, the thermal-interface material is applied to at least the region, where the thermal-interface material includes a material that is a liquid metal over a range of operating temperatures of the semiconductor die. | 2009-06-11 |
20090149022 | METHOD FOR IMPROVING UNIFORMITY AND ADHESION OF LOW RESISTIVITY TUNGSTEN FILM - Methods of improving the uniformity and adhesion of low resistivity tungsten films are provided. Low resistivity tungsten films are formed by exposing the tungsten nucleation layer to a reducing agent in a series of pulses before depositing the tungsten bulk layer. According to various embodiments, the methods involve reducing agent pulses with different flow rates, different pulse times and different interval times. | 2009-06-11 |
20090149023 | METHOD OF FABRICATING SEMICONDUCTOR DEVICE HAVING THREE-DIMENSIONAL STACKED STRUCTURE - A method of fabricating a semiconductor device having a three-dimensional stacked structure is provided, which realizes easily the electrical interconnection between the stacked semiconductor circuit layers along the stacking direction by using buried interconnections. | 2009-06-11 |
20090149024 | Pattering method for a semiconductor substrate - A patterning method for a semiconductor substrate is disclosed. A substrate is provided and a stack structure is laid thereon. The stack layer includes at least a target layer and a pad layer sequentially formed on the substrate. Follow by a lithography process, wherein photoresists are laid on the stack layer to form a plurality of photoresist elements. Thus, a plurality of pattern is formed on the target layer, and a portion of target layer's surface is exposed. Lastly, ion implanting is provided and defines a doped area as hard mask for the etching process. | 2009-06-11 |
20090149025 | Remover Compositions - A remover composition containing 1,3-propanediamine (a), 1-hydroxyethylidene-1,1-diphosphonic acid (b) and water, wherein the remover composition contains the component (a) in an amount of from 0.2 to 30% by weight, the component (b) in an amount of from 0.05 to 10% by weight, and the water in an amount of from 60 to 99.75% by weight, and wherein the composition has a pH at 20° C. of from 9 to 13; and a remover composition containing an organic amine (A), an organic phosphonic acid (B), a linear sugar alcohol (C) and water, wherein the remover composition contains the component (A) in an amount of from 0.2 to 30% by weight, the component (B) in an amount of from 0.05 to 10% by weight, the component (C) in an amount of from 0.1 to 10% by weight, and the water in an amount of from 50 to 99.65% by weight, and wherein the composition has a pH at 20° C. of from 9 to 13. | 2009-06-11 |
20090149026 | METHOD FOR FORMING HIGH DENSITY PATTERNS - Methods are disclosed, such as those involving increasing the density of isolated features in an integrated circuit. In one or more embodiments, a method is provided for forming an integrated circuit with a pattern of isolated features having a final density of isolated features that is greater than a starting density of isolated features in the integrated circuit by a multiple of two or more. The method can include forming a pattern of pillars having a density X, and forming a pattern of holes amongst the pillars, the holes having a density at least X. The pillars can be selectively removed to form a pattern of holes having a density at least 2X. In some embodiments, plugs can be formed in the pattern of holes, such as by epitaxial deposition on the substrate, in order to provide a pattern of pillars having a density 2X. In other embodiments, the pattern of holes can be transferred to the substrate by etching. | 2009-06-11 |
20090149027 | Method of Fabricating an Integrated Circuit - Embodiments of the invention relate to a method of fabricating an integrated circuit, including etching of a layer that includes a high k material in the form of a metal oxide composition, wherein an etchant is used that includes a silicon halogen composition. | 2009-06-11 |
20090149028 | METHODS AND APPARATUS FOR A HYBRID CAPACITIVELY-COUPLED AND AN INDUCTIVELY-COUPLED PLASMA PROCESSING SYSTEM - A capacitively-coupled plasma (CCP) processing system having a plasma processing chamber for processing a substrate is provided. The capacitively-coupled Plasma (CCP) processing system includes an upper electrode and a lower electrode for processing the substrate, which is disposed on the lower electrode during plasma processing. The capacitively-coupled Plasma (CCP) processing system also includes an array of inductor coils arrangement configured to inductively sustain plasma in a gap between the upper electrode and the lower electrode. | 2009-06-11 |
20090149029 | PRODUCTION METHOD FOR SEMICONDUCTOR DEVICE - An inventive semiconductor device production method is a method for producing a semiconductor device having a metal interconnection by etching a metal film including a lower layer of a first metal material and an upper layer of a second metal material different from the first metal material. In the production method, the upper layer is selectively etched under conditions such that an etching rate for the upper layer is higher than an etching rate for the lower layer. The etching is terminated when the lower layer is exposed. Thereafter, the upper layer is over-etched under conditions such that the etching rate for the upper layer is substantially equal to the etching rate for the lower layer. Then, the lower layer is selectively etched. | 2009-06-11 |
20090149030 | OXIDE ETCHING METHOD - There is provided an etching method of an amorphous oxide layer containing In and at least one of Ga and Zn, which includes etching the amorphous oxide layer using an etchant containing any one of acetic acid, citric acid, hydrochloric acid, and perchloric acid. | 2009-06-11 |
20090149031 | Method of making a semiconductor device with residual amine group free multilayer interconnection - The present invention provides a semiconductor device that can restrict the dissolution hindering phenomenon in a chemically amplified resist film. More specifically, after the formation of a contact pattern on a semiconductor substrate, a wiring pattern is formed on the contact pattern. A SiC film, a first SiOC film, a SiC film, a second SiOC film, a USG film as a diffusion preventing film, and a silicon nitride film as a reflection preventing film, are formed on the wiring pattern. A dual damascene structure is then formed using the chemically amplified resist film and another chemically amplified resist film. In this manner, the N | 2009-06-11 |
20090149032 | Method for manufacturing semiconductor device and substrate processing apparatus - The present invention suppresses metallic contamination in a processing chamber and a breakage of a quartz member, while suppressing decrease in film formation rate in a thin film formation process immediately after dry cleaning of the inside of the processing chamber, and enhances the operation rate of a apparatus. The method according to the invention includes the steps of: removing the thin film on the inside of the processing chamber by supplying a fluorine gas solely or a fluorine gas diluted by an inert gas solely, as the cleaning gas, to the inside of the processing chamber heated to a first temperature; and removing an adhered material remaining on the inside of the processing chamber after removing the thin film by supplying a fluorine gas solely or a fluorine gas diluted by an inert gas solely, as the cleaning gas, to the inside of the processing chamber heated to a second temperature. | 2009-06-11 |
20090149033 | SYSTEMS AND METHODS FOR FORMING METAL OXIDE LAYERS - A method of forming (and apparatus for forming) a metal oxide layer, preferably a dielectric layer, on a substrate, particularly a semiconductor substrate or substrate assembly, using a vapor deposition process and ozone with one or more metal organo-amine precursor compounds. | 2009-06-11 |
20090149034 | SEMICONDUCTOR MODULE AND METHOD OF MANUFACTURING THE SAME - In a semiconductor module, adhesion between an insulating base material and an insulator provided on the insulating base material, for example a sealing resin of the semiconductor element, is to be improved. | 2009-06-11 |
20090149035 | METHOD FOR MANUFACTURING OF A CRYSTAL OSCILLATOR - A method of manufacturing a crystal oscillator, in which method semiconductor components and the crystal or another resonator ( | 2009-06-11 |
20090149036 | INHERENTLY SEALED ELECTRICAL CONNECTOR - An entirely wearable electrical connector for power/data connectivity. The principal element of a modular network is the wearable electrical connector, which is integrated into a personal area network with USB compatibility. An embodiment comprises a non-conductive elastomeric environmental seal. | 2009-06-11 |
20090149037 | SELF-IDENTIFYING ELECTRICAL CONNECTOR - An entirely wearable electrical connector for power/data connectivity. The principal element of a modular network is the wearable electrical connector, which is integrated into a personal area network with USB compatibility. Several wearable connector embodiments are disclosed. An enhancement to the wearable connector includes OSI Layer 2 (and potentially Layer 3) functionality. Data Link layer functionality is supported by including electronic serial numbers at wearable snap-connector points. | 2009-06-11 |
20090149038 | FORMING EDGE METALLIC CONTACTS AND USING COULOMB FORCES TO IMPROVE OHMIC CONTACT - Vertical metallic contacts are provided along the edge of a plurality of substrates. The vertical metallic contact can range in area and large area contacts can be formed by layering metal traces with vias. The traces and vias should be placed near an edge of a substrate. An etch of the edge exposes the vertical metallic contact. Coulomb forces are used to attract the edge of two substrates together to establish a physical connection of the vertical metallic contacts. A shearing force can be applied to the common surface of the physical connection by using lateral Coulomb forces to break through any oxide layer. Finally, a corner substrate provides a metallic connection between an edge of a substrate and the circuitry in a planar surface of the substrate. Coulomb islands are used to generate the Coulomb forces. | 2009-06-11 |
20090149039 | System and method for interconnecting circuit boards - A connector system is provided. The system includes a substantially circular interconnecting hub, and a plurality of circuit board bays configured substantially radially around the substantially circular interconnecting hub. Each circuit board bay has a plurality of aligned connectors configured to receive a circuit board. The interconnecting circuit hub has, for each individual circuit board bay, a direct data pathway connecting the individual circuit board bay to all remaining circuit board bays of the plurality of circuit board bays. Each of the plurality of circuit board bays can directly communicate through the interconnecting hub with each of the remaining circuit boards bays. | 2009-06-11 |
20090149040 | COAXIALLY CONNECTED STRUCTURE FOR OPPOSED WIRING SUBSTRATES AND DEVICE HAVING THE SAME - A coaxially connected structure for opposed wiring substrates of the present invention includes a first substrate equipped with a tab type bracket and a second substrate equipped with a socket type bracket, and further includes first and second ground cases respectively mounted on the first and second substrates to cover them. The first and second ground cases are respectively provided with first and second penetration openings to pass the tab type bracket and the socket type bracket therethrough. Exposed parts of the tab type bracket and the socket type bracket from the openings are mutually engaged and being fully surrounded with at least one conductive tubular member which has a function to determine a distance between the first substrate and the second substrate. | 2009-06-11 |
20090149041 | Orthogonal Backplane Connector - An orthogonal backplane connector systems having midplane footprints that provide for continuity of impedance and signal integrity through the midplane and allow for the same connector to be coupled to either side of the midplane. This design creates an orthogonal interconnect without taking up unnecessary PCB real estate. The midplane circuit board may include a first differential signal pair of electrically conductive vias disposed in a first direction, and a second differential signal pair of electrically conductive vias disposed in a second direction that is generally orthogonal to the first direction. The first and second differential signal pair of electrically conductive vias are electrically connected through the midplane circuit board. Each pair may be associated with and be located in between ground vias. A ground via that is large relative to the signal vias may be provided. The second signal vias may comprise a shared signal via, receiving a contact from respective connectors connected to each side of the midplane circuit board. The second signal vias may comprise partial signal vias, extending from one or more sides partially into the midplane circuit board. The signal pairs may be offset from a via array centerline formed by the ground vias to correspond with mating ends of signal contacts of an electrical connector that likewise jog away from a centerline of a respective contact column of the connector. | 2009-06-11 |
20090149042 | Electrical connector having flexibly and steadily enagagement between metallic shells and grounding terminals - An electrical connector ( | 2009-06-11 |
20090149043 | Electrical connector having improved grounding member - An electrical connector ( | 2009-06-11 |
20090149044 | ELECTRONIC MODULE LOCKING AND EJECTING APPARATUS - A locking and ejecting apparatus includes a carriage for holding an electronic module having a connector therein, a sliding bracket slid in the carriage, a mating connector attached to the sliding bracket for connecting with the connector, a triggering portion formed on the sliding bracket, a push-push switch attached to the carriage, and a resilient member. Two actuated retaining pieces are formed on the push-push switch, and a trigger is set between the retaining pieces. When the sliding bracket is slid relative to the carriage, the resilient member is deformed and the trigger is triggered by the triggering portion, the retaining pieces are actuated to hold the triggering portion, the sliding bracket is locked in the carriage. When the trigger is triggered again, the retaining pieces are actuated to release the triggering portion, the sliding bracket is ejected out of the carriage by a restoring force of the resilient member. | 2009-06-11 |
20090149045 | Electrical connector with improved ground piece - An electrical connector includes an insulative housing, a plurality of first and second contacts retained in the insulative housing and a metallic ground. Each first contact comprises a first contact portion and a first mounting portion. Each second contact comprises a second contact portion and a second mounting portion. The first and second mounting portions are respectively arranged in first and second rows. The second contacts comprise a grounding contact. The ground piece comprises an elastic contact beam for abutting against the grounding contact so that the surface of the grounding contact is expanded. As a result, cross-talk occurred between the contacts can be decreased. | 2009-06-11 |
20090149046 | CONNECTOR - A connector | 2009-06-11 |
20090149047 | Memory card connector with improved switch contacts for stably detection of card insertion or removal - A memory card connector includes an insulative housing and a plurality of contacts retained in the insulative housing and a pair of switch contacts. The insulative housing defines a card receiving cavity for receiving a memory card. The pair of switch contacts are of a first status when the memory card is located in a deepest insertion position of the card receiving cavity, and the pair of switch contacts are of a second status different from the first status when the memory card is located in a final working position. | 2009-06-11 |
20090149048 | Electrical connector - A high voltage electrical connector includes a connector body. A first connector is supported within the connector body. A second connector is supported within the connector body and electrically connected to the first connector. A high voltage circuit protection device is electrically connected between the first connector and the second connector. | 2009-06-11 |
20090149049 | Electrical Connector - An electrical connector, for example a connector that will operate with the Universal Serial Bus, is disclosed. In some embodiments, the connector includes none, one, or several tongue board, tongue tip, electrical contact, housing shell, insulating strip on the inner lining of housing shell, protective edge. A connector integral to a printed circuit board is also disclosed. Other embodiments are disclosed. | 2009-06-11 |
20090149050 | MULTI-CONNECTOR, AND CHARGING CABLE AND DATA CABLE HAVING THE SAME - A multi-connector, and a charging cable and a data cable including the same are disclosed. The multi-connector includes a 24-pin connector and a 20-pin connector that may be used regardless of the type and manufacturer of a portable terminal. The multi-connector includes a first connector body having a first connector installed on a side thereof, a second connector body having a second connector installed on a side thereof, and a hinge shaft to connect the first connector body to the second connector body. The first connector body and/or the second connector body are pivotable about the hinge shaft. | 2009-06-11 |
20090149051 | MOUNTING APPARATUS FOR PLUG OF SIGNAL WIRE - A mounting apparatus for securely fixing a plug to a socket. The socket includes two opposite sidewalls. The mounting apparatus includes a pair of securing means movably mounted to the corresponding sidewalls of the socket for clamping the plug. | 2009-06-11 |
20090149052 | Connector - The connector including the first and second connector housings is provided with means for draining water entered inside. At an end part of the second connector housing, situated at the front of an insertion direction of the first connector housing into the second connector housing, the second connector housing includes: a connecting part which connects a tube part and a body part of the second connector housing to each other; and a through hole which is adjacent to the connecting part and penetrates through the tube part to communicate a first space, which is outside the body part and inside the tube part, and the outside of the tube part to each other, wherein a facing surface of the connecting part facing the first connector housing is provided with an inclined surface gradually inclining toward the insertion direction as the facing surface approaches the through hole. | 2009-06-11 |
20090149053 | IN-LINE CONNECTOR - Connectors are provided herein for connecting two elongated members that are positioned in-line to one another. Advantageously, the connectors not only allow for connection of the two members to permit for mechanical, electrical, EMI, and/or grounding applications, the connectors have provisions for accommodating thermal expansion and offset, which may include angular and/or axial offset. In certain embodiments, one or more collapsible housing pins or collars are provided to permit assembly and disassembly by either extending the housing pin or collapsing the housing pin. | 2009-06-11 |
20090149054 | CONNECTOR | 2009-06-11 |
20090149055 | CONNECTOR HOLDING CLAMP AND CONNECTOR RETAINING STRUCTURE - An upper panel section includes an inserting hole into which a tip of a longitudinal-type equipment-side connector that is mounted on a PCB of an equipment at right angle and includes a spring section formed on its lateral surface is inserted. A foot section supports the upper panel section on the PCB. An inner circumference of the inserting hole has a shape surrounding substantially an entire circumference of the tip of the equipment-side connector. The foot section is provided at a position that opens up the lateral surface of the longitudinal-type equipment-side connector on which the spring section of the equipment-side connector is formed. | 2009-06-11 |
20090149056 | Electrical card connector with an improved guiding member - An electrical card connector ( | 2009-06-11 |
20090149057 | CONNECTOR - A restriction ( | 2009-06-11 |
20090149058 | Card connector for connecting with two cards - A card connector ( | 2009-06-11 |
20090149059 | Electric Wire Coupler - An electrical wire coupler adapted to electrically connect at least two wires, each comprising a conductive core and insulation therearound, is provided. The coupler comprises at least two compartments independently openable. Each of the compartments allows, in an open position, placement therein of at least one wire and, in a closed position, retention therein of the at least one wire. The coupler further comprises conductive portions adapted to contact the conductive core, wherein each compartment comprises at least one of the conductive portions, and at least some of the conductive portions are electrically connected to other portions. | 2009-06-11 |
20090149060 | Electrical connector with improved heat dissipation structure - An electrical connector includes an insulative housing ( | 2009-06-11 |
20090149061 | Electrical connector having improved indicating module - An electrical connector ( | 2009-06-11 |
20090149062 | Hospital grade electrical receptacle - An electrical receptacle includes a housing having a cover or face member coupled to a base, and a mounting bridge extending around and contacting the bottom and the two opposite ends of the base. Each of the end-contacting portions of the mounting bridge has at least one base tab that projects inwardly into engagement with the end of the base, and at least one face tab, preferably barbed, that projects upwardly into the face member. During assembly, the base tabs preferably are bent over an upper edge of the base to firmly clamp the mounting bridge to the base. A line contact assembly extending along each side of the base has at least one line contact tab that projects upwardly into the face member. Mating snap-fit connectors afford additional robustness to the assembly. | 2009-06-11 |
20090149063 | ELECTRICAL COAXIAL CONNECTOR - An electrical coaxial connector comprising a body made of insulator to be put on a circuit board, a signal-joining contacting conductor held by the body, and a grounding contacting conductor formed into a cylindrical shape and held also by the body for surrounding the signal-joining contacting conductor on the circuit board, wherein the grounding contacting conductor has an arm portion extending toward the circuit board from one of ring-shaped ends of the grounding contacting conductor, which is more distant from the circuit board than the other, a grounding terminal portion is formed at an end of the arm portion to be soldered to a ground-potential terminal provided on the circuit board, and each of the grounding contacting conductor and the arm portion is resilient. | 2009-06-11 |
20090149064 | HIGH CURRENT COAXIAL CONNECTION WITH TWO PLUG ELEMENTS, AND GRADIENT COIL CONDUCTOR - A high-current coaxial connection with two plug elements that can be connected with one another, in particular to connect a current-carrying coaxial conductor to a gradient coil of a magnetic resonance apparatus, has a first and second coupling rings provided at the respective plug elements. The first coupling ring with a first thread is screwed onto one plug contact to be fixed to the plug element while the second coupling ring with a second thread that overlaps the first coupling ring, is screwed onto a mating thread section at the other plug element. Both coupling rings are rotationally locked relative to one another and the first thread and the second thread are different. | 2009-06-11 |
20090149065 | Electrical connector having improved shieding means - An electrical connector ( | 2009-06-11 |
20090149066 | Electrical connector with ESD protection - An electrical connector has an insulative housing ( | 2009-06-11 |
20090149067 | ELECTRICAL CONNECTOR RECEPTACLE - An electrical coupler includes a connector receptacle having multiple modules. The modules each include a pair of signal conductors and a ground plane or shield, held together by a dielectric module body. The shields are between the pairs of conductors in adjacent modules, and provide electrical shielding between the pairs of signal contacts of different modules. The signal conductors and the shields may be coupled to a board, such as a circuit board. The receptacle may be an angled receptacle, such as a right angle receptacle. The signal conductors of each pair in the receptacle may have a predetermined amount of skew, having different effective electrical lengths. This may allow signal paths through the receptacle and the board to have a combined electrical path that is substantially the same for the signal conductor pair of one of the modules. | 2009-06-11 |
20090149068 | CONNECTOR WITH FILTER FUNCTION - A connector with a filter function includes a first substrate having a first surface and a second surface opposite to each other; a plurality of first terminal lines formed on the first surface of the first substrate, wherein each of the first terminal lines is further arranged periodically and repeatedly with a predetermined periodic unit pattern; a case connected to one side end of the first substrate; a second substrate having a first surface and a second surface opposite to each other and disposed in the case; and a plurality of second terminal lines having a periodic unit pattern, formed on the first surface of the second substrate, and electrically connected to the first terminal lines on the first substrate. | 2009-06-11 |
20090149069 | ELECTRICAL-CONNECTION DEVICE, PARTICULARLY FOR PHOTOVOLTAIC-CELL SOLAR PANELS - An electrical-connection device, particularly for photovoltaic-cell panels, has: a first electrical terminal, designed to be connected to apparatuses for generation or use of electrical energy and to extend in a fixed position through a wall for support of the connection device; a seal for fluid-tight coupling of the first electrical terminal to the supporting wall; a second electrical terminal connected to the first electrical terminal and to an electrical wiring external to the supporting wall; and an electrically insulated liquid-tight chamber, housing at least partially the first electrical terminal and the second electrical terminal. | 2009-06-11 |
20090149070 | ALL-IN-ONE CARD CONNECTOR - An all-in-one card connector has a insulating case, a first base, a second base, a single card terminal assembly and multiple modular card terminal assemblies. The single card terminal assembly is formed on the first base and is inserted into one end of the insulating case. The modular card terminal assemblies are formed on the second base and are inserted into the other end of the insulating case. After inserting, the bases are cut from the single and modular card terminal assemblies. Because multiple modular card terminal assemblies are all formed on the second base, the material for the base is saved to reduce the cost and the mounting process is also simplified. | 2009-06-11 |
20090149071 | Electrical card connector with improved card restriction structure - An electrical card connector for insertion of a first card and a second card which is wider than the first card, includes an insulative housing defining a front mating port, a card receiving space extending backwardly from the mating port for receiving the first and the second cards, and a plurality of terminals for mating with a first card and a second card wider than the first card. A card restriction mechanism is fixed to the insulative housing and includes a guiding body and an elastic spring located on the guiding body. The guiding body restricts and guides the first card and second cards to be inserted into the receiving space while the cards moving through the mating port. | 2009-06-11 |
20090149072 | Electrical connector with improved contacts retaining mechanism - An electrical connector includes an insulative housing having a front mating face, a base portion, a mating portion protruding forwardly from the base portion and a number of passageways recessed rearward from the front mating face, the housing defining a number of blocks on a rear side thereof, the blocks each having an abutting face on a lower end thereof; a number of first contacts received in the passageways respectively and each including a contacting portion exposed in the passageway to mate with a corresponding mating connector, a level retaining arm fixed in the passageway and defining a front end connecting with the contacting portion and a rear end opposite to the front end, and a vertical mounting portion extending downwardly from a rear end of the retaining arm, the vertical mounting portion including a soldering portion to be soldered onto a printed circuit board and a protrusion tab extending laterally to have a larger width than that of the soldering portion, the protrusion tab abutting against the abutting face to prevent the vertical mounting portion from moving upwardly. | 2009-06-11 |
20090149073 | Electrical connector assembly - An electrical connector assembly ( | 2009-06-11 |
20090149074 | Connecting module - A connecting module ( | 2009-06-11 |