24th week of 2015 patent applcation highlights part 54 |
Patent application number | Title | Published |
20150162251 | DISPLAY DEVICE AND MANUFACTURING METHOD THEREOF - A display device includes a first insulating substrate including a display area, a peripheral area and a test area, a gate conductor including a test element group gate electrode, a gate electrode and a gate line on the first insulating substrate, a gate insulating layer on the gate conductor, a semiconductor layer including a test element group semiconductor layer and a pixel semiconductor layer on the gate insulating layer, a data conductor including a test element group source electrode, a test element group drain electrode, a data line including a source electrode, and a drain electrode on the semiconductor layer, a first passivation layer on the data conductor, a test element group common electrode and a pixel common electrode on the first passivation layer, a second passivation layer on the test element group common electrode and the pixel common electrode, and a pixel electrode on the second passivation layer. | 2015-06-11 |
20150162252 | FAULT TOLERANT DESIGN FOR LARGE AREA NITRIDE SEMICONDUCTOR DEVICES - A fault tolerant design for large area nitride semiconductor devices is provided, which facilitates testing and isolation of defective areas. A transistor comprises an array of a plurality of islands, each island comprising an active region, source and drain electrodes, and a gate electrode. Electrodes of each island are electrically isolated from electrodes of neighboring islands in at least one direction of the array. Source, drain and gate contact pads are provided to enable electrical testing of each island. After electrical testing of islands to identify defective islands, overlying electrical connections are formed to interconnect source electrodes in parallel, drain electrodes in parallel, and to interconnect gate electrodes to form a common gate electrode of large gate width Wg. Interconnections are provided selectively to good islands, while electrically isolating defective islands. This approach makes it economically feasible to fabricate large area GaN devices, including hybrid devices. | 2015-06-11 |
20150162253 | CARRIER AND A METHOD FOR PROCESSING A CARRIER - According to various embodiments, a carrier may be provided, the carrier including: a hollow chamber spaced apart from a surface of the carrier; a trench structure extending from the surface of the carrier to the hollow chamber and laterally surrounding a first region of the carrier, the trench structure including one or more trenches extending from the surface of the carrier to the hollow chamber, and one or more support structures intersecting the one or more trenches and connecting the first region of the carrier with a second region of the carrier outside the trench structure, wherein the one or more support structures including an electrically insulating material. | 2015-06-11 |
20150162254 | CARRIER AND A METHOD FOR PROCESSING A CARRIER - According to various embodiments, a carrier may include: a hollow chamber spaced apart from a surface of the carrier; and at least one support structure within the hollow chamber connecting a first region of the carrier disposed over the hollow chamber with a second region of the carrier disposed below the hollow chamber, wherein at least a part of a surface of the at least one support structure is spaced apart from an inner surface of the hollow chamber, and wherein the at least one support structure includes an electrically insulating material. | 2015-06-11 |
20150162255 | SEMICONDUCTOR MOUNTING DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR MOUNTING DEVICE - A semiconductor mounting device including a first substrate having insulation layers, conductor layers formed on the insulation layers, and via conductors connecting the conductor layers, a second substrate having insulation layers and conductor layers formed on the insulation layers of the second substrate, first bumps connecting the first substrate and the second substrate and formed on an outermost conductor layer of the first substrate formed on an outermost insulation layer of the first substrate, and second bumps positioned to mount a semiconductor element to the second substrate and formed on an outermost conductor layer of the second substrate formed on an outermost insulation layer of the second substrate. The second substrate has a thickness which is greater than a thickness of the first substrate. | 2015-06-11 |
20150162256 | Fan Out Package Structure and Methods of Forming - Packages and methods of forming packages are disclosed. According to an embodiment, a structure comprises a die comprising an electrical pad on an active side, and an encapsulant laterally around the die and extending directly over the active side of the die. A conductive pattern is over the encapsulant, and the conductive pattern comprises a via in an opening through the encapsulant to the electrical pad. The via contacts the electrical pad. In some embodiments, a dielectric layer is over the encapsulant, and the conductive pattern is over the dielectric layer. In other embodiments, the encapsulant is a dielectric-encapsulant, and the conductive pattern adjoins the dielectric-encapsulant. In some embodiments, the encapsulant may be a photo-patternable material, a molding compound, or an Ajinomoto Build-up Film. The structure may further comprise additional dielectric layers and conductive patterns. | 2015-06-11 |
20150162257 | METHOD AND STRUCTURE FOR WAFER LEVEL PACKAGING WITH LARGE CONTACT AREA - A method to provide a wafer level package with increasing contact pad area comprising the steps of forming a first packaging layer on wafer top surface, grinding the wafer back surface and etch through holes, depositing a metal to fill the through holes and covering wafer backside, cutting through the wafer from wafer backside forming a plurality of grooves separating each chip then depositing a second packaging layer filling the grooves and covering the wafer back metal, reducing the first packaging layer thickness to expose the second packaging layer filling the grooves and forming a plurality of contact pads overlaying the first packaging layer thereafter cutting through the second packaging layer in the grooves to form individual package. | 2015-06-11 |
20150162258 | Underfill Pattern with Gap - An embodiment is a structure comprising a package, a substrate, and external electrical connectors mechanically and electrically coupling the package to the substrate. The package contains a die. The external electrical connectors are between the package and the substrate. An underfill material is around a periphery region of the package and between the periphery region and the substrate. A gap is between a central region of the package and the substrate, and does not contain the underfill material. The underfill material may seal the gap. The gap may be an air gap. In some embodiments, the underfill material may fill greater than or equal to 10 percent and no more than 70 percent of a volume between the package and the substrate. | 2015-06-11 |
20150162259 | INTELLIGENT CHIP PLACEMENT WITHIN A THREE-DIMENSIONAL CHIP STACK - An integrated circuit (IC) stack device for thermal management is disclosed. The IC stack device can include a primary IC having a first set of cores with a ratio of first enabled cores and first disabled cores. The IC stack device can also have a supplementary IC interfaced with the primary IC, and having a second set of cores with a second ratio of second enabled cores and second disabled cores, with the second ratio being less than the first ratio. The integrated circuit stack device can also include a cooling element located such that the primary integrated circuit is between the cooling element and the supplementary integrated circuit. The cooling element can be designed to facilitate heat dissipation of the first and second enabled cores of the primary integrated circuit and the supplementary integrated circuit. | 2015-06-11 |
20150162260 | CHIP PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF - A chip package structure including a leadframe, a chip, at least one heat dissipation pillar, and a molding compound is provided. The leadframe includes a die pad and a plurality of leads. The die pad has at least one through hole. The leads surround the die pad. The chip is located on the die pad and electronically connected to the leads. The chip includes an active surface and a back surface opposite to the active surface. The back surface of the chip is adhered to the die pad. The heat dissipation pillar is located on the back surface and passes through the through hole. The molding compound encapsulates the chip, at least parts of the leads, and the die pad. The molding compound includes at least one opening to expose the heat dissipation pillar. A manufacturing method of the chip package structure is also provided. | 2015-06-11 |
20150162261 | Power Semiconductor Package with Integrated Heat Spreader and Partially Etched Conductive Carrier - In one implementation, a power semiconductor package includes a power transistor having a first power electrode and a gate electrode on its bottom surface, and a second power electrode on its top surface. The first power electrode is configured for attachment to a first partially etched conductive carrier segment and the gate electrode is configured for attachment to a second partially etched conductive carrier segment. The power semiconductor package also includes a power electrode heat spreader situated over the second power electrode and configured for attachment to a power electrode conductive carrier segment. | 2015-06-11 |
20150162262 | Interconnect Structure for Semiconductor Devices - An interconnect and a method of forming an interconnect for a semiconductor device is provided. Conductive lines having different widths are formed. Wider conductive lines are used where the design includes an overlying via, and narrower lines are used in which an overlying via is not included. An overlying dielectric layer is formed and trenches and vias are formed extending through the overlying dielectric layer to the wider conductive lines. Voids or air gaps may be formed adjacent select conductive lines, such as the narrower lines. | 2015-06-11 |
20150162263 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - The semiconductor device includes first interlayer insulating layers and first conductive patterns which are alternately stacked; a second interlayer insulating layer formed on the first interlayer insulating layers and the first conductive patterns; and a slit passing through the second interlayer insulating layer, the first interlayer insulating layers and the first conductive patterns to divide the first interlayer insulating layers and the first conductive patterns into stack structures. | 2015-06-11 |
20150162264 | PACKAGE STRUCTURE AND FABRICATION METHOD THEREOF - A package structure is provided, which includes: a wafer having a surface with a groove, a thin film closing an open end of the groove and electrical contacts; a chip having a surface with a conductive layer and an opposite surface with a concave portion and a seal ring located at a periphery of the concave portion, the chip being disposed on the wafer with the seal ring surrounding the thin film and the electrical contacts located outside the seal ring; an encapsulant formed on the wafer for encapsulating the chip and the electrical contacts; a plurality of sub-conductive wires embedded in the encapsulant with one ends exposed from a top surface of the encapsulant and the other ends in electrical connection with the electrical contacts; and a through hole penetrating the wafer and communicating with the concave portion, thereby reducing the fabrication cost and size of the package structure. | 2015-06-11 |
20150162265 | SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME - Semiconductor packages including chips having through silicon vias (TSVs) and methods of manufacturing the same may be provided to provide reliable and thinner semiconductor packages by mitigating or preventing a crack from occurring at an uppermost chip. The semiconductor package including a substrate, a first chip stacked on the substrate, the first chip including a plurality of through silicon vias (TSVs), an uppermost chip stacked on the first chip, the uppermost chip being thicker than the first chip, a first gap fill portion covering at least a portion of a side surface of the uppermost chip while filling a space between the first chip and the uppermost chip, and a sealant for sealing the first chip, the uppermost chip, and the first gap fill portion may be provided. | 2015-06-11 |
20150162266 | SEMICONDUCTOR CHIP WITH POWER GATING THROUGH SILICON VIAS - A semiconductor chip includes a substrate having a frontside and a backside coupled to a ground. The chip includes a circuit in the substrate at the frontside. A through silicon via (TSV) having a front-end, a back-end, and a lateral surface is included. The back-end and lateral surface of the TSV are in the substrate, and the front-end of the TSV is substantially parallel to the frontside of the substrate. The chip also includes an antifuse material deposited between the back-end and lateral surface of the TSV and the substrate. The antifuse material insulates the TSV from the substrate. The chip includes a ground layer insulated from the substrate and coupled with the TSV and the circuit. The ground layer conducts a program voltage to the TSV to cause a portion of the antifuse material to migrate away from the TSV, thereby connecting the circuit to the ground. | 2015-06-11 |
20150162267 | RADIO-FREQUENCY DEVICE PACKAGE AND METHOD FOR FABRICATING THE SAME - An electronic device package has a base and an electronic device chip mounted on the base. The electronic device chip includes a semiconductor substrate having a front side and a back side, a electronic component disposed on the front side of the semiconductor substrate, an interconnect structure disposed on the electronic component, a through hole formed through the semiconductor substrate from the back side of the semiconductor substrate, connecting to the interconnect structure, and a TSV structure disposed in the through hole. The interconnect structure is electrically connected to the RF component, and a thickness of the semiconductor substrate is less than that of the interconnect structure. | 2015-06-11 |
20150162268 | ELECTRONIC DEVICE AND METHOD FOR FABRICATING THE SAME - An electronic device includes a semiconductor memory unit. The semiconductor memory unit includes a plurality of conductive pillars stretching in a direction perpendicular to a substrate, the plurality of conductive pillars arranged in a first direction and a second direction intersecting the first direction, conductive patterns disposed between the conductive pillars, variable resistance layers each of which is disposed between a corresponding one of the conductive pillars and a corresponding one of the conductive patterns, said each of the variable resistance layers contacting the corresponding conductive pattern and the corresponding conductive pillar, first lines disposed between the conductive pillars in the second direction and stretch in the first direction, the first lines contacting the conductive patterns under the conductive patterns, and second lines disposed between the conductive pillars in the first direction and stretch in the second direction, the second lines contacting the conductive patterns over the conductive patterns. | 2015-06-11 |
20150162269 | SEMICONDUCTOR DIE PACKAGE WITH INSULATED WIRES FOR ROUTING POWER SIGNALS - A semiconductor die package has a die mounted to a die pad. The die has data bond pads and power supply bond pads. Lead fingers are spaced from and project outwardly from the die pad. Each of the lead fingers has a proximal end that is near to a respective edge of the die pad, and a distal end farther from the die pad. The lead fingers include power bar lead fingers and data lead fingers. A power bar bridges the proximal ends of two of the power bar lead fingers. The power bar is between the proximal ends of the data lead fingers and the respective edge of the die pad. Insulated bond wires are used to selectively electrically couple the power bar to the die power supply bond pads. | 2015-06-11 |
20150162270 | PACKAGED SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING - In one general aspect, a package can include a semiconductor die having a first terminal on a first side of the semiconductor die and a second terminal on a second side of the semiconductor die, a leadframe portion electrically coupled to the second terminal of the semiconductor die, and a molding compound. The first terminal on the first side of the semiconductor die, a first surface of the leadframe portion, and a first surface of the molding compound can define at least a portion of a first surface of the package. A second surface of the molding compound and a second surface of the leadframe portion can define at least a portion of a second surface of the package parallel to the first surface of the package, and the second surface can be on an opposite side of the package from the first surface of the package. | 2015-06-11 |
20150162271 | LEADFRAME, PACKAGE ASSEMBLY AND METHOD FOR MANUFACTURING THE SAME - A leadframe, a package assembly and methods for manufacturing the same are disclosed. A plurality of electronic devices are stacked in a plurality of levels in the package assembly. The leadframe includes a plurality of leads having interconnect areas. The plurality of leads are grouped so that the interconnect areas of each group of leads have a height corresponding to one level of electronic devices. In the package assembly, the interconnect areas of each group of leads are soldered to one level of electronic devices. The leadframe and the package assembly result in increased packaging density, less usage of bonding wires in the package assembly, and improve reliability. The method for manufacturing the package assembly reduces adverse effects of a reflow process on properties of the electronic devices, and thus further improves reliability of the package assembly. | 2015-06-11 |
20150162272 | SWITCH MODE POWER CONVERTERS USING MAGNETICALLY COUPLED GALVANICALLY ISOLATED LEAD FRAME COMMUNICATION - An integrated circuit package for use in a switch mode power converter includes a portion of a lead frame disposed within an encapsulation. The lead frame includes a first conductor having an inner conductive loop disposed within the encapsulation, and a second conductor galvanically isolated from the first conductor having an outer conductive loop disposed within the encapsulation and magnetically coupled to the first conductive loop to provide a communication link between the first and second conductors. First and second control circuits are coupled to the first and second conductors, respectively. The first control circuit is coupled to control a switching circuit in response to one or more control signals communicated between first and second dice that include the first and second control circuits, respectively, through the communication link to regulate a transfer of energy from an input to an output of the switch mode power converter. | 2015-06-11 |
20150162273 | DEVICE HAVING MULTIPLE-LAYER PINS IN MEMORY MUX1 LAYOUT - An integrated circuit (IC) memory device that includes a first conductive layer, a second conductive layer electrically coupled to the first conductive layer, the second conductive layer formed over the first conductive layer, a third conductive layer separated from the second conductive layer, the third conductive layer formed over the second conductive layer, a fourth conductive layer electrically coupled to the third conductive layer, the fourth conductive layer formed over the third conductive layer, a 2P2E pin box formed in and electrically coupled to the first conductive layer or the second conductive layer and a 1P1E pin box formed in and electrically coupled to the third conductive layer or the fourth conductive layer. | 2015-06-11 |
20150162274 | SEMICONDUCTOR APPARATUS - A semiconductor apparatus is disclosed, which includes a semiconductor element provided on a plane; a sealing resin that seals the semiconductor element; a terminal that is electrically connected to the semiconductor element and includes a part that projects from a predetermined surface of the sealing resin; and a concave portion that is recessed toward a side of the semiconductor element from the predetermined surface, when viewed in a direction perpendicular to the plane. A side of the concave portion on the side of the semiconductor element includes a rounded shape, when viewed in the direction perpendicular to the plane. | 2015-06-11 |
20150162275 | ELECTRONIC PACKAGE, PACKAGE CARRIER, AND METHOD OF MANUFACTURING PACKAGE CARRIER - A method of manufacturing package carrier is provided. In the method, a holding substrate and a conductive layer are provided. The conductive layer is on the holding substrate. Next, an insulating pattern is formed on the conductive layer. The insulating pattern exposes a portion of the conductive layer. A supporting board is provided. Next, the insulating pattern is detachably fixed in the supporting board. After the insulating pattern is detachably fixed in the supporting board, the holding substrate is removed, and the conductive layer remains. After removing the holding substrate, the conductive layer is patterned to form a wiring layer. | 2015-06-11 |
20150162276 | SEMICONDUCTOR DEVICE - A semiconductor device includes: a first semiconductor chip having a first antenna that is formed in a first hole provided in the first semiconductor chip, has an inclined surface inclined with respect to a central line of the first hole, and transmits and receives a radio wave; and a second semiconductor chip stacked over the first semiconductor chip, the second semiconductor chip having a second antenna that is formed in a second hole provided in the second semiconductor chip, has an inclined surface inclined with respect to a central line of the second hole, and transmits and receives a radio wave, wherein the first antenna and the second antenna are disposed so that the inclined surface of the first antenna and the inclined surface of the second antenna face each other. | 2015-06-11 |
20150162277 | ADVANCED INTERCONNECT WITH AIR GAP - Ultra-low-k dielectric materials used as inter-layer dielectrics in high-performance integrated circuits are prone to be structurally unstable. The Young's modulus of such materials is decreased, resulting in porosity, poor film strength, cracking, and voids. An alternative dual damascene interconnect structure incorporates air gaps into a high modulus dielectric material to maintain structural stability while reducing capacitance between adjacent nanowires. Incorporation of an air gap having k=1.0 compensates for the use of a higher modulus film having a dielectric constant greater than the typical ultra-low-k (ULK) dielectric value of about 2.2. The higher modulus film containing the air gap is used as an insulator between adjacent metal lines, while a ULK film is retained to insulate vias. The dielectric layer between two adjacent metal lines thus forms a ULK/high-modulus dielectric bi-layer. | 2015-06-11 |
20150162278 | TRENCH INTERCONNECT HAVING REDUCED FRINGE CAPACITANCE - Ultra-low-k dielectric materials used as inter-layer dielectrics in high-performance integrated circuits are prone to be structurally unstable. The Young's modulus of such materials is decreased, resulting in porosity, poor film strength, cracking, and voids. An alternative dual damascene interconnect structure incorporates deep air gaps into a high modulus dielectric material to maintain structural stability while reducing capacitance between adjacent nanowires. Incorporation of a deep air gap having k=1.0 compensates for the use of a higher modulus film having a dielectric constant greater than the typical ultra-low-k (ULK) dielectric value of about 2.2. The higher modulus film containing the deep air gap is used as an insulator and a means of reducing fringe capacitance between adjacent metal lines. The dielectric layer between two adjacent metal lines thus forms a ULK/high-modulus dielectric bi-layer. | 2015-06-11 |
20150162279 | INTERCONNECT STRUCTURES AND FABRICATION METHOD THEREOF - An interconnect structure is provided. The interconnect structure includes a substrate; and at least a first interconnect component having a first contact region and a second interconnect component having a second contact region. The interconnect structure also includes an interlayer dielectric layer formed on the semiconductor substrate at a same layer as the first interconnect component and the second interconnect component. Further, the interconnect structure includes an interconnect line layer electrically connecting the first contact region and the second contact region formed inside the interlayer dielectric layer. | 2015-06-11 |
20150162280 | Surface Pre-Treatment for Hard Mask Fabrication - A robust metallization profile is formed by pre-treat an anti-reflective coating layer by plasma before forming a hard mask layer. Pre-treatment is helpful especially in small feature size process, for example, 50 nm and below. By changing constitution of a surface layer of the anti-reflective coating, interface of the anti-reflective coating layer and the hard mask layer is smoothed which results in less overhang and better gap-filling performance. | 2015-06-11 |
20150162281 | INTEGRATED CIRCUIT DEVICE AND METHOD FOR MANUFACTURING THE SAME - In general, according to one embodiment, an integrated circuit device includes a first conductive member extending in a first direction, a second conductive member extending in the first direction, a first contact having a lower end connected to the first conductive member, and a second contact having a lower end connected to the second conductive member. A position of the first contact in the first direction is different from a position of the second contact in the first direction. Cross sections of the first contact and the second contact have longitudinal directions in a second direction as viewed from above. The second direction is from the first contact toward the second contact. | 2015-06-11 |
20150162282 | BI-LAYER HARD MASK FOR ROBUST METALLIZATION PROFILE - A robust metallization profile is formed by forming two or more layers of hard mask with different density. Multi-layer metal hard mask is helpful especially in small feature size process, for example, 50 nm and below. Lower layers have higher density. In such ways, enough process window is offered by lower layers and at the same time, round hard mask profile is offered by upper layers. | 2015-06-11 |
20150162283 | INTEGRATED CIRCUIT SHIELDING TECHNIQUE UTILIZING STACKED DIE TECHNOLOGY INCORPORATING TOP AND BOTTOM NICKEL-IRON ALLOY SHIELDS HAVING A LOW COEFFICIENT OF THERMAL EXPANSION - An integrated circuit shielding technique utilizing stacked die technology incorporating top and bottom nickel-iron alloy shields having a low coefficient of thermal expansion of especial utility in conjunction with magnetoresistive random access memory (MRAM) and other devices requiring magnetic shielding. | 2015-06-11 |
20150162284 | SEMICONDUCTOR DEVICE - To improve reliability of a semiconductor device obtained through a dicing step. In a ring region, a first outer ring is provided outside a seal ring, and a second outer ring is provided outside the first outer ring. This can prevent a crack from reaching even the seal ring that exists in the ring region, for example, when a scribe region located outside the ring region is cut off by a dicing blade. | 2015-06-11 |
20150162285 | SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME - Various embodiments provide semiconductor structures and methods for forming the same. In an exemplary structure, a substrate has a device region, a seal ring region surrounding the device region, and a dielectric layer disposed thereon. A first seal ring structure is located within the dielectric layer on the seal ring region, and includes a plurality of first connection layers overlappingly disposed and separated by the dielectric layer. At least one first connection layer is formed by a plurality of discrete sub-connection layers. The first seal ring structure further includes a plurality of first conductive plugs between vertically adjacent first connection layers. A top of each first conductive plug is connected to an upper first connection layer. A bottom of each first conductive plug between at least two vertically adjacent first connection layers extends into the dielectric layer between horizontally adjacent sub-connection layers of a lower first connection layer. | 2015-06-11 |
20150162286 | SEMICONDUCTOR DEVICE FOR ESD PROTECTION - A semiconductor device for electrostatic discharge protection includes a substrate, a first well and a second well formed in the substrate. The first and second wells are formed side by side, meeting at an interface, and have a first conductivity type and a second conductivity type, respectively. A first heavily doped region and a second heavily-doped region are formed in the first well. A third heavily doped region and a fourth heavily-doped region are formed in the second well. The first, second, third, and fourth heavily-doped regions have the first, second, second, and first conductivity types, respectively. Positions of the first and second heavily-doped regions are staggered along a direction parallel to the interface. | 2015-06-11 |
20150162287 | Electronic Device - An electronic device includes multiple semiconductor chips in a single housing. Such semiconductor chips may comprise different semiconductor materials, for example they may comprise GaN. Using bonding clips instead of bonding wires is an efficient way of connecting such semiconductor chips to a substrate. | 2015-06-11 |
20150162288 | SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME - A semiconductor device having a semiconductor substrate is provided. The semiconductor substrate includes an integrated circuit, which includes multi-layer structured metallization and inter-metal dielectric. The integrated circuit is below a passivation, which is over a metal structure. The metal structure includes a metal pad and an under bumper metallurgy, which is over and aligned with the metal pad. The metal pad is electrically connected to the integrated circuit, and the under bumper metallurgy is configured to electrically connect to a conductive component of another semiconductor device. The integrated circuit further includes a conductive trace, which is below and aligned with the metal structure. The conductive trace is connected to a power source such that an electromagnetic field is generated at the conductive trace when an electric current from the power source passes through the conductive trace. | 2015-06-11 |
20150162289 | Protective Layer for Contact Pads in Fan-out Interconnect Structure and Method of Forming Same - In accordance with a method embodiment includes providing a die having a contact pad on a top surface and forming a conductive protective layer over the die and covering the contact pad. A molding compound is formed over the die and the conductive protective layer. The conductive protective layer is exposed using a laser drilling process. A redistribution layer (RDL) is formed over the die. The RDL is electrically connected to the contact pad through the conductive protective layer. | 2015-06-11 |
20150162290 | METHOD FOR HANDLING VERY THIN DEVICE WAFERS - A structure and method of handling a device wafer during through-silicon via (TSV) processing are described in which a device wafer is bonded to a temporary support substrate with a permanent thermosetting material. Upon removal of the temporary support substrate a planar frontside bonding surface including a reflowed solder bump and the permanent thermosetting material is exposed. | 2015-06-11 |
20150162291 | SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME - A semiconductor device having a semiconductor substrate is provided. The semiconductor device has a metal structure over the semiconductor substrate. The metal structure is configured to receive a bump. The semiconductor device further has a conductive trace between the semiconductor substrate and the metal structure. The conductive trace is configured to connect to a power source. When an electric current from the power source passes through the conductive trace, an electromagnetic field is generated at the conductive trace. The position of the bump is adjusted in response to the electromagnetic field. | 2015-06-11 |
20150162292 | SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING SEMICONDUCTOR PACKAGE - A semiconductor package includes a wiring substrate that includes a first conductive member; a semiconductor chip that is mounted on the wiring substrate and includes a second conductive member, the first conductive member and the second conductive member being positioned to face each other; and a bonding member that bonds and electrically connects the first conductive member and the second conductive member, at least one of the first conductive member and the second conductive member being a pillar-shaped terminal, the bonding member being bonded to an end surface of the pillar-shaped terminal and a portion of a side surface of the pillar-shaped terminal, an intermetallic compound layer being formed at an interface of the bonding member and the pillar-shaped terminal. | 2015-06-11 |
20150162293 | Apparatus And Methods For High-Density Chip Connectivity - Self-alignment structures, such as micro-balls and V-grooves, may be formed on chips made by different processes. The self-alignment structures may be aligned to mask layers within an accuracy of one-half the smallest feature size inside a chip. For example, the alignment structures can align an array of pads having a pitch of 0.6 microns, compared to a pitch of 100 microns available with today's Ball Grid Array (BGA) technology. As a result, circuits in the mated chips can communicate via the pads with the same speed or clock frequency as if in a single chip. For example, clock rates between interconnected chips can be increased from 100 MHz to 4 GHz due to low capacitance of the interconnected pads. Because high-density arrays of pads can interconnect chips, chips can be made smaller, thereby reducing cost of chips by order(s) of magnitude. | 2015-06-11 |
20150162294 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - Certain embodiments provide a method for manufacturing a semiconductor device including forming a first interconnection layer having a first conductive layer and a first insulating layer which are exposed from a surface of the first interconnection layer, forming a second interconnection layer having a second conductive layer and a second insulating layer which are exposed from a surface of the second interconnection layer, forming a first non-bonded surface on the surface of the first insulating layer by making a partial area of the surface of the first insulating layer lower than the surface of the first conductive layer, the partial area containing surroundings of the first conductive layer, and connecting the surface of the first conductive layer and the surface of the second conductive layer and bonding the surface of the first insulating layer excluding the first non-bonded surface and the surface of the second insulating layer. | 2015-06-11 |
20150162295 | CONNECTING TECHNIQUES FOR STACKED CMOS DEVICES - A stacked integrated circuit includes multiple tiers vertically connecting together. A multi-layer horizontal connecting structure is fabricated inside a substrate of a tier. Layers of the horizontal connecting structure have different patterns as viewed from above the substrate. | 2015-06-11 |
20150162296 | SEMICONDUCTOR DEVICE - In order to inhibit a crack under a pad opening without increasing a chip size, a protective film ( | 2015-06-11 |
20150162297 | Power Converter Package with an Integrated Output Inductor - In one implementation, a power semiconductor package includes a conductive carrier including a switch node segment and a power output segment. The power semiconductor package also includes an integrated output inductor stacked over the conductive carrier and configured to couple the switch node segment to the power output segment. The power semiconductor package further includes a power stage stacked over the integrated output inductor. | 2015-06-11 |
20150162298 | PACKAGED SEMICONDUCTOR DEVICE WITH INTERIOR POLYGONAL PADS - Embodiments of a packaged semiconductor device with interior polygon pads are disclosed. One embodiment includes a semiconductor chip and a package structure defining a rectangular boundary and having a bottom surface that includes interior polygonal pads exposed at the bottom surface of the package structure and located on a centerline of the bottom surface of the package structure and edge polygonal pads exposed at the bottom surface of the package structure, located at an edge of the rectangular boundary, and including one edge polygonal pad in the vicinity of each corner of the rectangular boundary. The interior polygonal pads are configured such that a line running between at least one vertex of each of the interior polygonal pads is parallel to an edge of the rectangular boundary of the package structure. | 2015-06-11 |
20150162299 | INTEGRATED WIRE BONDER AND 3D MEASUREMENT SYSTEM WITH DEFECT REJECTION - An apparatus comprises a wire bonder system including a wire bonding device, a measuring device and a rejection device. The wire bonding device is configured to attach wire bond type electrical interconnect to an electronic assembly. A wire bond is formed between a first semiconductor device and a second electronic device to form at least a portion of the electronic assembly. The measuring device is configured to perform a three dimensional measurement associated with a wire bond, and the rejection device is configured to identify an electronic assembly for rejection according to the three dimensional wire bond measurement. | 2015-06-11 |
20150162300 | LASER ASHING OF POLYIMIDE FOR SEMICONDUCTOR MANUFACTURING - A system for laser ashing of polyimide for a semiconductor manufacturing process is provided. The system includes: a semiconductor chip, a top chip attached to the semiconductor chip by a connection layer, a supporting material, a polyimide glue layer disposed between the supporting material and semiconductor chip, a plasma asher, and an ashing laser configured to ash the polyimide glue on the semiconductor chip. | 2015-06-11 |
20150162301 | METHOD FOR FABRICATING SEMICONDUCTOR PACKAGE - A method for fabricating a semiconductor package is provided, which includes the steps of: providing a carrier having at least a semiconductor chip disposed thereon, the semiconductor chip having a first surface attached to the carrier, and an opposite second surface having a plurality of first conductive elements thereon; disposing an interposer on the first conductive elements, wherein the interposer has opposite third and fourth surfaces, the interposer is disposed on the first conductive elements via the third surface, and a plurality of conductive posts are embedded in the interposer and electrically connected to the third surface; forming an encapsulant on the carrier for encapsulating the semiconductor chip and the interposer; removing a portion of the encapsulant from the upper surface thereof and a portion of the interposer from the fourth surface thereof to expose ends of the conductive posts; and removing the carrier, thereby improving the connection quality between the semiconductor chip and the interposer. | 2015-06-11 |
20150162302 | METHODS OF FORMING SEMICONDUCTOR DIE ASSEMBLIES - Semiconductor assemblies, structures, and methods of fabrication are disclosed. A coating is formed on an electrically conductive pillar. The coating, which may be formed from at least one of a silane material and an organic solderability protectant material, may bond to a conductive material of the electrically conductive pillar and, optionally, to other metallic materials of the electrically conductive pillar. The coating may also bond to substrate passivation material, if present, or to otherwise-exposed surfaces of a substrate and a bond pad. The coating may be selectively formed on the conductive material. Material may not be removed from the coating after formation thereof and before reflow of the solder for die attach. The coating may isolate at least the conductive material from solder, inhibiting solder wicking or slumping along the conductive material and may enhance adhesion between the resulting bonded conductive element and an underfill material. | 2015-06-11 |
20150162303 | Array Based Fabrication of Power Semiconductor Package with Integrated Heat Spreader - In one implementation, a method of fabricating a power semiconductor package is disclosed. The method includes providing a conductive carrier array including a plurality of power modules held together with connecting bars, where each of the plurality of power modules includes a control transistor, a sync transistor, and a driver IC. The method further includes overlying on the conductive carrier array a heat spreader array including a plurality of power electrode heat spreaders such that each of the plurality of power electrode heat spreaders couples a drain of the sync transistor to a source of the control transistor in each power module. | 2015-06-11 |
20150162304 | Silver-To-Silver Bonded IC Package Having Two Ceramic Substrates Exposed On The Outside Of The Package - A packaged power device involves no soft solder and no wire bonds. The direct-bonded metal layers of two direct metal bonded ceramic substrate assemblies, such as Direct Bonded Aluminum (DBA) substrates, are provided with sintered silver pads. Silver nanoparticle paste is applied to pads on the frontside of a die and the paste is sintered to form silver pads. Silver formed by an evaporative process covers the backside of the die. The die is pressed between the two DBAs such that direct silver-to-silver bonds are formed between sintered silver pads on the frontside of the die and corresponding sintered silver pads of one of the DBAs, and such that a direct silver-to-silver bond is formed between the backside silver of the die and a sintered silver pad of the other DBA. After leadforming, leadtrimming and encapsulation, the finished device has exposed ceramic of both DBAs on outside package surfaces. | 2015-06-11 |
20150162305 | METHOD OF FORMING A SEMICONDUCTOR DEVICE AND STRUCTURE THEREFOR - In one embodiment, a conductor bump is formed on an under bump conductor of a semiconductor device to extend a first distance away from a surface of the under bump conductor including forming a protective layer on an outer surface of the conductor bump wherein the plurality of semiconductor dies are subsequently singulated by etching through the semiconductor substrate with an etchant and wherein the protective layer protects the conductor bump from the etchant. | 2015-06-11 |
20150162306 | ENCAPSULATED WAFER-LEVEL CHIP SCALE (WLSCP) PEDESTAL PACKAGING - Consistent with an example embodiment, there is semiconductor device assembled to resist mechanical damage. The semiconductor device comprises an active circuit defined on a top surface, contact areas providing electrical connection to the active circuit. There is a pedestal structure upon which the active circuit is mounted on an opposite bottom surface; the pedestal structure has an area smaller than the area of the active device. An encapsulation, consisting of a molding compound, surrounds the sides and the underside of the active device and it surrounds the contact areas. The encapsulation provides a resilient surface protecting the active device from mechanical damage. A feature of the embodiment is that the contact areas may have solder bumps defined thereon. | 2015-06-11 |
20150162307 | Packages with Thermal Management Features for Reduced Thermal Crosstalk and Methods of Forming Same - An embodiment package includes a first die stack on a surface of a package component, a second die stack on the surface of the package component, and a contour lid over the first die stack and second die stack. The contour lid includes a first thermal conductive portion over the first die stack, a second thermal conductive portion over the second die stack, and a thermal barrier portion between the first thermal conductive portion and the second thermal conductive portion. The thermal barrier portion includes a low thermal conductivity material. | 2015-06-11 |
20150162308 | INTERPOSER-CHIP-ARRANGEMENT FOR DENSE PACKAGING OF CHIPS - The interposer-chip-arrangement comprises an interposer ( | 2015-06-11 |
20150162309 | DEVICES AND STACKED MICROELECTRONIC PACKAGES WITH PACKAGE SURFACE CONDUCTORS AND METHODS OF THEIR FABRICATION - Embodiments of methods for forming a device include performing an oxidation inhibiting treatment to exposed ends of first and second device-to-edge conductors, and forming a package surface conductor to electrically couple the exposed ends of the first and second device-to-edge conductors. Performing the oxidation inhibiting treatment may include applying an organic solderability protectant coating to the exposed ends, or plating the exposed ends with a conductive plating material. The method may further include applying a conformal protective coating over the package surface conductor. An embodiment of a device formed using such a method includes a package body, the first and second device-to-edge conductors, the package surface conductor on a surface of the package body and extending between the first and second device-to-edge conductors, and the conformal protective coating over the package surface conductor. | 2015-06-11 |
20150162310 | DEVICES AND STACKED MICROELECTRONIC PACKAGES WITH PACKAGE SURFACE CONDUCTORS AND ADJACENT TRENCHES AND METHODS OF THEIR FABRICATION - Embodiments of methods for forming microelectronic device packages include forming a trench on a surface of a package body in an area adjacent to where first and second package surface conductors will be (or have been) formed on both sides of the trench. The method also includes forming the first and second package surface conductors to electrically couple exposed ends of various combinations of device-to-edge conductors. The trench may be formed using laser cutting, drilling, sawing, etching, or another suitable technique. The package surface conductors may be formed by dispensing (e.g., coating, spraying, inkjet printing, aerosol jet printing, stencil printing, or needle dispensing) one or more conductive materials on the package body surface between the exposed ends of the device-to-edge conductors. | 2015-06-11 |
20150162311 | MULTIPLE ACTIVE VERTICALLY ALIGNED CORES FOR THREE-DIMENSIONAL CHIP STACK - An integrated circuit (IC) stack device for multiple active vertically stacked cores is disclosed. The IC stack device can include a primary IC having a first set of cores, and a supplementary IC interfaced with the primary IC having a second set of cores. The IC stack device can also include a peripheral component connection located such that the primary IC is between the peripheral component connection and the supplemental IC. The IC stack device can include control logic configured to route, in a primary mode, signals from a particular core of the first set of cores to a data bus. The control logic can route, in a secondary mode, signals from a particular core of the second set of cores to a data bus. The control logic can route, in a dual mode, signals from both of the particular cores to a data bus. | 2015-06-11 |
20150162312 | ELECTRONIC APPARATUS AND METHOD FOR FABRICATING THE SAME - An electronic apparatus includes a first electronic part with a first terminal, a second electronic part with a second terminal opposite the first terminal, and a joining portion which joins the first terminal and the second terminal. The joining portion contains a pole-like compound extending in a direction in which the first terminal and the second terminal are opposite to each other. The joining portion contains the pole-like compound, so the strength of the joining portion is improved. When the first terminal and the second terminal are joined, the temperature of one of the first electronic part and the second electronic part is made higher than that of the other. A joining material is cooled and solidified in this state. By doing so, the pole-like compound is formed. | 2015-06-11 |
20150162313 | INTERCONNECT STRUCTURES WITH POLYMER CORE - Embodiments of the present disclosure are directed towards techniques and configurations of interconnect structures having a polymer core in integrated circuit (IC) package assemblies. In one embodiment, an apparatus includes a first die having a plurality of transistor devices disposed on an active side of the first die and a plurality of interconnect structures electrically coupled with the first die, wherein individual interconnect structures of the plurality of interconnect structures have a polymer core, and an electrically conductive material disposed on the polymer core, the electrically conductive material being configured to route electrical signals between the transistor devices of the first die and a second die. Other embodiments may be described and/or claimed. | 2015-06-11 |
20150162314 | LIGHT- EMITTING DEVICE - In an aspect of the present invention, a light-emitting device includes a substrate; a first electrode and a second electrode arranged on an upper surface of the substrate with a gap between the first electrode and the second electrode, the gap being positioned at a central portion of the upper surface of the substrate; a first light-emitting diode element electrically mounted on the first electrode; and a second light-emitting diode element electrically mounted on the second electrode, wherein the first electrode includes a first inner portion and a first outer portion that are two equal area portions divided at a center line of the first electrode, and the first light-emitting diode element is mounted on the first outer portion of the first electrode, and wherein the second electrode includes a second inner portion and a second outer portion that are two equal area portions divided at a center line of the second electrode, and the second light-emitting diode element is mounted on the second outer portion of the second electrode. | 2015-06-11 |
20150162315 | DOUBLED SUBSTRATE MULTI-JUNCTION LIGHT EMITTING DIODE ARRAY STRUCTURE - The present disclosure provides one embodiment of a light-emitting structure. The light-emitting structure includes a carrier substrate having first metal features; a transparent substrate having second metal features; a plurality of light-emitting diodes (LEDs) bonded with the carrier substrate and the transparent substrate, sandwiched between the carrier substrate and the transparent substrate; and metal pillars bonded to the carrier substrate and the transparent substrate, each of the metal pillars being disposed between adjacent two of the plurality of LEDs, wherein the first metal features, the second metal features and the metal pillars are configured to electrically connect the plurality of LEDs. | 2015-06-11 |
20150162316 | Packaged Semiconductor Devices and Methods of Packaging Semiconductor Devices - Packaged semiconductor devices and methods of packaging semiconductor devices are disclosed. In some embodiments, a method of packaging a semiconductor device includes forming a mask coating over a carrier, coupling an integrated circuit die over the mask coating, and disposing a molding compound around the integrated circuit die. The method includes forming an interconnect structure over the integrated circuit die and the molding compound. | 2015-06-11 |
20150162317 | Fabricating a Proximity Sensor Having Light-Blocking Structure in Leadframe - A method for fabricating a semiconductor proximity sensor includes providing a flat leadframe with a first and a second surface. The second surface is solderable. The leadframe includes a first and a second pad, a plurality of leads, and fingers framing the first pad. The fingers are spaced from the first pad by a gap which is filled with a clear molding compound. A light-emitting diode (LED) chip is assembled on the first pad and encapsulated by a first volume of the clear compound. The first volume outlined as a first lens. A sensor chip is assembled on the second pad and encapsulated by a second volume of the clear compound. The second volume outlined as a second lens. Opaque molding compound fills the space between the first and second volumes of clear compound, forms shutters for the first and second lenses, and forms walls rising from the frame of fingers to create an enclosed cavity for the LED. The pads, leads, and fingers connected to a board using a layer of solder for attaching the proximity sensor. | 2015-06-11 |
20150162318 | CHIP, CHIP PACKAGE AND DIE - In various embodiments, a chip for a chip package is provided. The chip may include a substrate and an integrated circuit over the substrate. The integrated circuit may include a test circuit, for example a built-in self-test circuit, and an operation circuit, the test circuit including one or more first driver stages each having a first driver performance and the operation circuit including one or more second driver stages each having a second driver performance which is different from the first driver performance, first contacts electrically coupled with the first driver stages, and second contacts electrically coupled with the second driver stages, wherein the test circuit and the first contacts are configured to provide a test mode for testing the integrated circuit and wherein the operation circuit and the second contacts are configured to provide an operating mode of the integrated circuit being different from the test mode. | 2015-06-11 |
20150162319 | Semiconductor Device Including Multiple Semiconductor Chips and a Laminate - A semiconductor device includes a laminate, a first semiconductor chip at least partly embedded in the laminate, a second semiconductor chip mounted on a first main surface of the laminate, and a first electrical contact arranged on the first main surface of the laminate. The second semiconductor chip is electrically coupled to the first electrical contact. | 2015-06-11 |
20150162320 | METHOD AND APPARATUS FOR FLOATING OR APPLYING VOLTAGE TO A WELL OF AN INTEGRATED CIRCUIT - In one well bias arrangement, no well bias voltage is applied to the n-well, and no well bias voltage is applied to the p-well. Because no external well bias voltage is applied, the n-well and the p-well are floating, even during operation of the devices in the n-well and the p-well. In another well bias arrangement, the lowest available voltage is not applied to the p-well, such as a ground voltage, or the voltage applied to the n+-doped source region of the n-type transistor in the p-well. This occurs even during operation of the n-type transistor in the p-well. In yet another well bias arrangement, the highest available voltage is not applied to the n-well, such as a supply voltage, or the voltage applied to the p+-doped source region of the p-type transistor in the n-well. This occurs even during operation of the p-type transistor in the n-well. | 2015-06-11 |
20150162321 | Composite Power Device with ESD Protection Clamp - There are disclosed herein various implementations of a normally off (enhancement mode) composite power device with an ESD protection clamp. Such a normally off composite power device includes a normally on (depletion mode) power transistor providing a composite drain of the normally off composite power device, and a normally off low voltage (LV) transistor cascoded with the normally on power transistor. The normally off LV transistor provides a composite source and a composite gate of the normally off composite power device. The normally off composite power device also includes the ESD protection clamp coupled between the composite source and the composite gate. The ESD protection clamp is configured to provide electrostatic discharge (ESD) protection for the normally off composite power device. | 2015-06-11 |
20150162322 | BIPOLAR JUNCTION TRANSISTOR DEVICE AND METHOD OF MAKING THE SAME - A method is provided of forming a bipolar transistor device. The method comprises depositing a collector dielectric layer over a substrate in a collector active region, depositing a dielectric anti-reflective (DARC) layer over the collector dielectric layer, dry etching away a base opening in the DARC layer, and wet etching away a portion of the collector dielectric layer in the base opening to provide an extended base opening to the substrate. The method further comprises performing a base deposition to form a base epitaxy region in the extended base opening and extending over first and second portions of the DARC layer that remains as a result of the dry etching away the base opening in the DARC layer, and forming an emitter region over the base epitaxy region. | 2015-06-11 |
20150162323 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - In IC chips for display device driving, an operational amplifier is widely used in input and output circuits, and a capacitor in a medium withstanding voltage chip is used as a compensation capacitor. As for this product area, cost competitiveness is very important. Therefore, a MIS capacitor with good area efficiency is widely used. However, unlike a so-called varactor widely used in a VCO circuit, a characteristic of as small a voltage dependence of the capacitor as possible is used. Therefore, an additional process is added to reduce the voltage dependence of the capacitor, but there is a problem of an increase in process cost. A semiconductor substrate side capacitor electrode in a MIS capacitor within a first conduction type medium withstanding voltage chip used in an I/O circuit or the like on a semiconductor integrated circuit device is formed in a first conduction type low withstanding voltage well region. | 2015-06-11 |
20150162324 | HALF-BRIDGE CIRCUIT WITH A LOW-SIDE TRANSISTOR AND A LEVEL SHIFTER TRANSISTOR INTEGRATED IN A COMMON SEMICONDUCTOR BODY - A half-bridge circuit includes a low-side transistor and a high-side transistor each having a load path and a control terminal. The half-bridge circuit further includes a high-side drive circuit having a level shifter with a level shifter transistor. The low-side transistor and the level shifter transistor are integrated in a common semiconductor body. | 2015-06-11 |
20150162325 | SEMICONDUCTOR DIODE - A semiconductor diode with integrated resistor has a semiconductor body with a front surface, a back surface and a diode structure with an anode electrode and a cathode electrode. A resistance layer arranged on the back surface of the semiconductor body provides the integrated resistor | 2015-06-11 |
20150162326 | Semiconductor Package for III-Nitride Transistor Stacked with Diode - One exemplary disclosed embodiment comprises a two-terminal stacked-die package including a diode, such as a silicon diode, stacked atop a III-nitride transistor, such that a cathode of the diode resides on and is electrically coupled to a source of the III-nitride transistor. A first terminal of the package is coupled to a drain of the III-nitride transistor, and a second terminal of the package is coupled to an anode of the diode. In this manner, devices such as cascoded rectifiers may be packaged in a stacked-die form, resulting in reduced parasitic inductance and resistance, improved thermal dissipation, smaller form factor, and lower manufacturing cost compared to conventional packages. | 2015-06-11 |
20150162327 | SEMICONDUCTOR MODULE - A semiconductor module is provided with a plurality of chip-type passive components, a conductive supporting member onto which the plurality of chip-type passive components are mounted, and a resin sealing part covering the plurality of chip-type passive components and at least a portion of the conductive supporting member. The plurality of chip-type passive components each include a semiconductor substrate, a plurality of electrodes formed on the semiconductor substrate, and a passive circuit connected between the plurality of electrodes. | 2015-06-11 |
20150162328 | SEMICONDUCTOR DEVICE AND RELATED FABRICATION METHODS - Semiconductor device structures and related fabrication methods are provided. An exemplary semiconductor device structure ( | 2015-06-11 |
20150162329 | SEMICONDUCTOR ARRANGEMENT AND FORMATION THEREOF - A semiconductor arrangement and method of forming the same are described. A semiconductor arrangement includes a first gate structure on a first side of an active area and a second gate structure on a second side of the active area, where the first gate structure and the second gate structure share the active area. A method of forming the semiconductor arraignment includes forming a deep implant of the active area before forming the first gate structure, and then forming a shallow implant of the active area. Forming the deep implant prior to forming the first gate structure alleviates the need for an etching process that degrades the first gate structure. The first gate structure thus has a desired configuration and is able to be formed closer to other gate structures to enhance device density. | 2015-06-11 |
20150162330 | SEMICONDUCTOR DEVICE WITH CONFORMAL DOPING AND METHOD OF MAKING - A semiconductor arrangement is provided. The semiconductor arrangement includes a first semiconductor device. The first semiconductor device includes a first active region having a first doped region and a second doped region over the first doped region. The second doped region includes a first bottom portion and a first sidewall. The first bottom portion includes a first bottom portion inner surface, a first bottom portion outer surface, a first bottom portion height and a first bottom portion width. The first sidewall includes a first sidewall inner surface, a first sidewall outer surface, a first sidewall width and a first sidewall height, the first sidewall height greater than the first bottom portion height. A method of making a semiconductor device is also provided. | 2015-06-11 |
20150162331 | TEST PATTERN OF SEMICONDUCTOR DEVICE - A test pattern of a semiconductor device is provided, which includes first and second fins formed to project from a substrate and arranged to be spaced apart from each other, first and second gate structures formed to cross the first and second fins, respectively, a first source region and a first drain region arranged on the first fin on one side and the other side of the first gate structure, a second source region and a second drain region arranged on the second fin on one side and the other side of the second gate structure, a first conductive pattern connected to the first and second drain regions to apply a first voltage to the first and second drain regions and a second conductive pattern connecting the first source region and the second gate structure to each other. | 2015-06-11 |
20150162332 | SEMICONDUCTOR DEVICES HAVING COMPOSITE SPACERS CONTAINING DIFFERENT DIELECTRIC MATERIALS - An integrated circuit device includes an electrically conductive pattern on a substrate. This electrically conductive pattern may be a gate pattern of a field effect transistor. A first electrically insulating spacer is provided on a sidewall of the electrically conductive pattern. The first electrically insulating spacer includes a first lower spacer and a first upper spacer, which extends on the first lower spacer and has a side surface vertically aligned with a corresponding side surface of the first lower spacer. The first upper spacer has a greater dielectric constant relative to a dielectric constant of the first lower spacer. A pair of parallel channel regions may also be provided, which protrude from a surface of the substrate. The electrically conductive pattern may surround top and side surfaces of the pair of parallel channel regions. | 2015-06-11 |
20150162333 | Method for Fabricating A Multi-Gate Device - A device includes a wafer substrate including an isolation feature, at least two fin structures embedded in the isolation feature, and at least two gate stacks disposed around the two fin structures respectively. A first inter-layer dielectric (ILD) layer is disposed between the two gate stacks, with a dish-shaped recess formed therebetween, such that a bottom surface of the recess is below the top surface of the adjacent two gate stacks. A second ILD layer is disposed over the first ILD layer, including in the dish-shaped recess. The second ILD includes nitride material; the first ILD includes oxide material. | 2015-06-11 |
20150162334 | MULTI-GATE SEMICONDUCTOR DEVICES - A multi-gate semiconductor device is formed including a semiconductor substrate. The multi-gate semiconductor device also includes a first transistor including a first fin portion extending above the semiconductor substrate. The first transistor has a first channel region formed therein. The first channel region includes a first channel region portion doped at a first concentration of a first dopant type and a second channel region portion doped at a second concentration of the first dopant type. The second concentration is higher than the first concentration. The first transistor further includes a first gate electrode layer formed over the first channel region. The first gate electrode layer may be of a second dopant type. The first dopant type may be N-type and the second dopant type may be P-type. The second channel region portion may be formed over the first channel region portion. | 2015-06-11 |
20150162335 | SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME - A method of manufacturing a semiconductor device includes forming an isolation layer on a substrate, where an active pattern is defined, forming an insulating interlayer on the active pattern of the substrate and the isolation layer, removing portions of the insulating interlayer, the active pattern and the isolation layer to form a first recess, forming a first contact in the first recess on a first region of the active pattern exposed by the first recess, removing portions of the active pattern and the isolation layer in the first recess by performing an isotropic etching process, to form an enlarged first recess, and
| 2015-06-11 |
20150162336 | SELF-ALIGNED LATERALLY EXTENDED STRAP FOR A DYNAMIC RANDOM ACCESS MEMORY CELL - A self-aligned strap structure can be formed by forming trench capacitors and overlying trench top conductive material portions. End portions of fin mask structures overlie portions of the trench top conductive material portions. A dielectric spacer is formed around each end portions of the fin mask structure to cover additional areas of the trench top conductive material portions. An anisotropic etch is performed to recess portions of the trench top conductive material portions that are not covered by the fin mask structures or dielectric spacers. Conductive strap structures that are self-aligned to end portions of semiconductor fins are formed simultaneously with formation of the semiconductor fins. Access fin field effect transistors can be subsequently formed. | 2015-06-11 |
20150162337 | PATTERN FACTOR DEPENDENCY ALLEVIATION FOR EDRAM AND LOGIC DEVICES WITH DISPOSABLE FILL TO EASE DEEP TRENCH INTEGRATION WITH FINS - Dummy deep trenches can be formed within a logic device region in which logic devices are to be formed while deep trench capacitors are formed within a memory device region. Semiconductor fins are formed over a top surface prior to forming trenches, and disposable material is filled around said semiconductor fins. A top surface of said disposable filler material layer can be coplanar with a top surface of said semiconductor fins, which eases deep trench formation. Conductive material portions of the dummy deep trenches can be recessed to avoid electrical contact with semiconductor fins within the logic device region, while an inner electrode of each deep trench can contact a semiconductor fin within the memory device region. A dielectric material portion can be formed above each conductive material portion of a dummy deep trench. | 2015-06-11 |
20150162338 | Methods of Forming Sidewall Gates - A method of forming sidewall gates for vertical transistors includes depositing a gate dielectric layer over polysilicon channel structures, and depositing a gate polysilicon layer over the gate dielectric. The gate polysilicon layer is then etched back to form separated gate electrodes. Filler portions are then formed between gate electrodes, which are then etched from the top down while their sides are protected. | 2015-06-11 |
20150162339 | FINFET CROSSPOINT FLASH MEMORY - A flash memory device in a dual fin single floating gate configuration is provided. Semiconductor fins are formed on a stack of a back gate conductor layer and a back gate dielectric layer. Pairs of semiconductor fins are formed in an array environment such that shallow trench isolation structures can be formed along the lengthwise direction of the semiconductor fins within the array. After formation of tunneling dielectrics on the sidewalls of the semiconductor fins, a floating gate electrode is formed between each pair of proximally located semiconductor fins by deposition of a conformal conductive material layer and an isotropic etch. A control gate dielectric and a control gate electrode are formed by deposition and patterning of a dielectric layer and a conductive material layer. | 2015-06-11 |
20150162340 | NONVOLATILE SEMICONDUCTOR MEMORY HAVING A WORD LINE BENT TOWARDS A SELECT GATE LINE SIDE - A nonvolatile semiconductor memory includes a cell unit having a select gate transistor and a memory cell connected in series, a select gate line connected to the select gate transistor, and a word line connected to the memory cell. One end of the word line is bent to the select gate line side, and a fringe is connected between a bent point and a distal end of the word line. | 2015-06-11 |
20150162341 | NON-VOLATILE MEMORY DEVICE HAVING INCREASED MEMORY CAPACITY - A non-volatile memory device according to an embodiment of the present invention includes a first memory layer including a plurality of memory cells stacked between a first conductive line and a second conductive line over a semiconductor substrate. In addition, a second memory layer including the plurality of memory cells stacked between the second conductive line and a third conductive line. Further, the second memory layer is extended over the page buffer and the peripheral circuit sequentially arranged from the first memory layer. | 2015-06-11 |
20150162342 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a first stacked structure having first conductive layers and first insulating layers formed alternately with each other, first semiconductor patterns passing through the first stacked structure, a coupling pattern coupled to the first semiconductor patterns, and a slit passing through the first stacked structure and the coupling pattern. | 2015-06-11 |
20150162343 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A {111} plane of a substrate having a silicon crystal structure meets a top surface of the substrate to form an interconnection line on the top surface. A first stacked structure and a second stacked structure is formed on the substrate. Each of the first and the second stacked structures includes gate electrodes stacked on the substrate. A transistor is disposed on the substrate and positioned between the first stacked structure and the second stacked structure. The transistor includes a gate electrode extending in a first direction, a source region and a drain region. The source and the drain regions are disposed at both sides of the gate electrode in a second direction crossing the first direction. The interconnection line is extended at an angle with respect to the second direction. | 2015-06-11 |
20150162344 | METHODS OF FABRICATING THREE-DIMENSIONAL SEMICONDUCTOR DEVICES - Three dimensional semiconductor memory devices and methods of fabricating the same are provided. According to the method, sacrificial layers and insulating layers are alternately and repeatedly stacked on a substrate, and a cutting region penetrating an uppermost sacrificial layer of the sacrificial layers is formed. The cutting region is filled with a non sacrificial layer. The insulating layers and the sacrificial layers are patterned to form a mold pattern. The mold pattern includes insulating patterns, sacrificial patterns, and the non sacrificial layer in the cutting region. The sacrificial patterns may be replaced with electrodes. The related semiconductor memory device is also provided. | 2015-06-11 |
20150162345 | SEMICONDUCTOR MEMORY DEVICE INCLUDING A SLIT - A semiconductor device includes a first conductive layer, at least one first slit through the first conductive layer, and configured to divide the first conductive layer in the unit of a memory block, second conductive layers stacked on the first conductive layer, and a second slit through the second conductive layers at a different location from the first slit and configured to divide the second conductive layers in the unit of the memory block. | 2015-06-11 |
20150162346 | Semiconductor Package - Disclosed is a semiconductor package. The semiconductor package includes a substrate formed with transistors, power metal lines formed on the substrate, data metal lines formed on the substrate to transmit and receive data to and from the transistors, and an insulating layer formed on the substrate, the power metal lines, and the data metal lines. Herein, the insulating layer has openings partially exposing the power metal lines. | 2015-06-11 |
20150162347 | ARRAY SUBSTRATE AND FABRICATION METHOD THEREOF, AND DISPLAY DEVICE - Embodiments of the invention provide an array substrate, a fabrication method thereof, and a display device. The array substrate includes a first conductive pattern connecting with a low level potential, a second conductive pattern provided in a same layer as a STV signal line, and an insulating layer provided between the first conductive pattern and the second conductive pattern. The first conductive pattern, the insulating layer and the second conductive pattern have an overlapping region so as to form a storage capacitor. A conductive tip toward the second conductive pattern is formed at a position of the STV signal line that corresponds to the second conductive pattern. | 2015-06-11 |
20150162348 | SEMICONDUCTOR DEVICE AND PRODUCTION METHOD THEREFOR - This semiconductor device ( | 2015-06-11 |
20150162349 | THIN FILM TRANSISTOR ARRAY PANEL AND METHOD OF MANUFACTURING THE SAME - A thin film transistor array panel includes: a substrate; a gate line and a common voltage line on the substrate and electrically separated from each other; a gate insulating layer on the gate line and the common voltage line; a first passivation layer on the gate insulating layer; a common electrode on the first passivation layer; a second passivation layer on the common electrode; and a pixel electrode and a connecting member on the second passivation layer and electrically separated from each other. A first contact hole and a second contact hole are defined in the first and second passivation layers. The pixel electrode and the drain electrode are connected to each other through the second contact hole. The connecting member and the common electrode are connected to each other through the first contact hole. | 2015-06-11 |
20150162350 | ARRAY SUBSTRATE AND PREPARATION METHOD THEREOF, DISPLAY PANEL AND DISPLAY DEVICE - An array substrate is disclosed. The array substrate includes an array of pixel units on a substrate, gate lines, and data lines. The array substrate also includes common electrode lines. Each pixel unit includes a TFT, a pixel electrode, and a common electrode. The TFT is connected with one of the gate lines, one of the common electrode lines, and the common electrode. The pixel electrode is connected with the data line. In addition, the array of pixel units includes a plurality of first pixel units and a plurality of second pixel units with opposite potential polarities, where the first pixel units and the second pixel units are arranged alternatively in same rows/columns. | 2015-06-11 |