24th week of 2015 patent applcation highlights part 60 |
Patent application number | Title | Published |
20150162851 | CAPACITIVE MICROMACHINED ULTRASOUND TRANSDUCER - The patent application discloses a capacitive micromachined ultrasound transducer, comprising a silicon substrate; a cavity; a first electrode, which is arranged between the silicon substrate and the cavity; wherein the first electrode is arranged under the cavity; a membrane, wherein the membrane is arranged above the cavity and opposite to the first electrode; a second electrode, wherein the second electrode is arranged above the cavity and opposite to the first electrode; wherein the second electrode is arranged in or close to the membrane, wherein the first electrode and the second electrode are adapted to be supplied by a voltage; and a first isolation layer, which is arranged between the first electrode and the second electrode, wherein the first isolation layer comprises a dielectric. It is also described a system for generating or detecting ultrasound waves, wherein the system comprises a transducer according to the patent application. Further, it is disclosed a method for manufacturing a transducer according to the patent application, wherein the transducer is manufactured with the help of a CMOS manufacturing process, wherein the transducer can be manufactured as a post-processing feature during a CMOS process. | 2015-06-11 |
20150162852 | CAPACITIVE MICRO-MACHINED TRANSDUCER AND METHOD OF MANUFACTURING THE SAME - The present invention relates to a method of manufacturing a capacitive micro-machined transducer ( | 2015-06-11 |
20150162853 | ACTUATOR FOR AN ULTRASONIC MOTOR AND ULTRASONIC MOTOR COMPRISING AT LEAST ONE SUCH ACTUATOR - An ultrasonic motor comprising a rotor ( | 2015-06-11 |
20150162854 | System and Method for Stimulating Rainfall - For stimulating a rainfall, a plurality of electrically conducting elements are provided, which cover a substantially horizontal area, are supplied with a high voltage and generate in the substantially horizontal area a high voltage electric field providing in the atmosphere ionization of gas molecules which attract water and cause formation of a plurality of water clusters forming a cloud that produce a rainfall. | 2015-06-11 |
20150162855 | OUTPUT CONTROL APPARATUS OF A MOTOR AND METHOD FOR CONTROLLING A CONTROLLER OF THE SAME - An output control apparatus of a motor includes a controller formed by having a power device to bridge a motor and a power supply. The controller incorporating the power device provides voltage control modulation during different motor speeds so as to fix the recharging voltage at the DC bus in a specific range without involvement of any voltage converter. It is unnecessary to use additional complex circuits or other DC/DC converters to reduce the voltage recharged from the motor running at a high speed. In addition, space for the apparatus is reduced, and the specification and function of the original controller can be maintained without trading off work in redesigning the motor system. | 2015-06-11 |
20150162856 | Method and Electronic Device for Improving the Availability of an Electromechanical Actuator - A method for improving the availability of an electromechanical actuator of an electromechanical or electrohydraulic brake system in a motor vehicle, including electronic motor regulation functioning in a non-restricted operating mode (normal operation) for a field-commutated electric motor actuated by pulse width modulation. An electronic device having a setpoint value interface ( | 2015-06-11 |
20150162857 | MOTOR CONTROLLER - A 0-axis current calculator | 2015-06-11 |
20150162858 | MOTOR CONTROL APPARATUS AND MOTOR CONTROL METHOD - A motor control apparatus that controls a plurality of motors each including a plurality of coils, has a plurality of coil current driving signal generation apparatuses each provided for a corresponding one of control-target controlled motors of the plurality of motors to generate, at a first time interval, a plurality of coil current driving signals supplied to the plurality of coils in the controlled motor. Each of the plurality of coil current driving signal generation apparatuses includes: a timing state generation unit that cyclically generates a plurality of timing states at a period of a second time, which is shorter than the first time interval; and a coil current driving signal output unit that outputs the plurality of coil current driving signals to the controlled motor at a timing when the timing state generated by the timing state generation unit matches an assigned timing state assigned to the controlled motor. | 2015-06-11 |
20150162859 | METHODS AND SYSTEMS FOR CONTROLLING AN ELECTRIC MOTOR - Methods and systems for controlling an electric motor are provided. An electric motor controller is configured to be coupled to an electric motor. The controller includes a rectifier, an inverter coupled to the rectifier, and a control unit coupled to the inverter. The rectifier is configured to rectify an alternating current (AC) input voltage to produce a pulsed direct current (DC) voltage that drops to approximately zero during each cycle when the AC input voltage transits zero. Energy is stored on a load coupled to the motor when AC input voltage is available. The inverter is configured to receive the DC voltage and to provide a conditioned output voltage to the motor. The control unit is configured to manage energy transfer between the motor and the load such that the motor generates positive torque when the DC voltage supplied to the inverter has approximately 100% voltage ripple. | 2015-06-11 |
20150162860 | METHOD FOR CONTROLLING THREE-PHASE BRUSHLESS DC MOTOR COMPRISING SINGLE HALL SENSOR - A method for controlling a three-phase brushless DC motor including a single hall sensor, the method including: A) measuring a deviation angle θ of a mounting position of the single hall sensor and storing; B) starting the motor: outputting six-path PWM signals by the microprocessor to control the operation of the inverter and allowing the single hall sensor to continuously and stably measure a position signal; C) obtaining a rotating angular velocity ω=360°/T in the last 360° electric angle cycle by the microprocessor; D) calculating a real-time position angle α=ωt+θ of a present 360° electric angle cycle by the microprocessor; and E) outputting the six-path PWM signals by the microprocessor to control the operation of the inverter so as to simultaneously energize the three-phase winding (U, V, and W); and switching a current direction of each winding. | 2015-06-11 |
20150162861 | DUAL ALTERNATOR SYSTEM - A dual alternator system includes a main alternator controlled by an electronic voltage regulator, a secondary alternator system having a secondary alternator controlled by a LIN controlled alternator voltage regulator and an electronic control unit (“ECU”) coupled to the LIN controller alternator voltage regulator by a LIN bus that that determines whether the secondary alternator should be off or operated to generate current. The ECU when it determines that the secondary alternator should be off sends a voltage setpoint signal to the LIN controlled alternator voltage regulator having a low value that is well below nominal system voltage. The ECU when it determines that the secondary alternator should be operated to provide current sends a voltage setpoint to the LIN controlled alternator voltage regulator having a high value that is well above a nominal system voltage and a MECL setpoint value. | 2015-06-11 |
20150162862 | CONTROL SYSTEM FOR CONTROLLING THE ROTATIONAL SPEED OF A DRIVE MOTOR - The rotational speed of at least one drive motor of a motor vehicle is controlled by an electronic control system, wherein the differential rotational speed between a specified target rotational speed and an actual rotational speed of the drive motor is considered as a system value for determining the control parameters that influence the rotational speed control process. As an additional system value, the magnitude and direction of the differential rotational speed gradient are considered when determining the control parameters. | 2015-06-11 |
20150162863 | EXTENDED-SPEED LOW-RIPPLE TORQUE CONTROL OF SWITCHED RELUCTANCE MOTOR DRIVES - Various embodiments are described herein for an extended-speed low-ripple torque control of a switched reluctance motor (SRM) using online torque sharing function (TSF). Two operational modes of an online TSF are defined during the commutation: In Mode I, absolute value of rate of change of flux linkage (ARCFL) of incoming phase is higher than outgoing phase; in Mode II, ARCFL of outgoing phase is higher than incoming phase. To compensate the torque error produced by imperfect tracking of phase current, a proportional and integral compensator with torque error is added to the torque reference of outgoing phase in Mode I and incoming phase in Mode II. Therefore, the total torque is determined by the phase with lower ARCFL rather than the phase with higher ARCFL as in conventional TSFs. | 2015-06-11 |
20150162864 | Systems and Methods for Limiting Current Inrush in Electric Drive Systems - Systems and methods for controlling potentially damaging inrushes of current to the capacitor bank of an electric drive system when the voltage on the capacitor bank is low. In one embodiment, a variable speed drive has a converter that converts AC power to DC power, a capacitor bank that receives the DC power, and an inverter that converts the DC power stored by the capacitor bank to AC output power. The converter has three sections that rectify the phases of three-phase input power. Each section has at least one controlled rectifier component, and the rectifier components have switches connected to them in parallel. When the voltage on the capacitor bank is low, the controlled rectifiers and switches are controlled to prevent dangerously high inrushes of current to the capacitor bank. | 2015-06-11 |
20150162865 | PHOTOVOLTAIC POWER APPARATUS FOR RAPID DEPLOYMENT - A rapidly deployed photovoltaic (PV) apparatus ( | 2015-06-11 |
20150162866 | SUPPORTING DEVICE FOR SOLAR PANEL - The present disclosure relates to a photovoltaic system and, more particularly, to a supporting device for a solar panel employed in a photovoltaic system. A supporting device for a solar panel includes a buoyant member including an upper body in which a plurality of protrusions are formed upwardly and first and second props are formed on the protrusions to prop a solar panel, respectively, and a lower body in which a wing part is formed to be protruded from the side thereof and a lower surface is formed to be protruded downwardly, and a connector formed to have a box shape and connecting the buoyant members in a vertical direction or horizontal direction, wherein the buoyant members are coupled to the connector as the wing parts are coupled to the connector. | 2015-06-11 |
20150162867 | SOLAR ENERGY SYSTEMS - Improved solar energy system including an improved solar collector mounting assembly, preferably comprises a bi-facial solar active component mounted with its solar active face(s) orthogonal to the ground/horizon, at or near its perimeter frame. According to certain embodiments, the mounting assembly allows the fin to oscillate with respect to a fixed mounting position in response to displacing forces. Additionally, the solar energy system may be utilized to retrofit an existing energy operating system, wherein the solar powered system can interact in a hybrid fashion with the existing energy source of the retrofitted system. | 2015-06-11 |
20150162868 | SOLAR POWER SYSTEM AND SOLAR ENERGY TRACKING METHOD - A solar power system and a solar energy chasing method. Errors may be corrected in the installation area of a solar energy collecting plate with solar cells, particularly, in the installation direction thereof. Therefore, a control angle may be operated and determined, so that the solar cells or the solar energy collecting plate may be rotated precisely in the desired direction. In the case of disposing a plurality of solar energy collecting plates, the solar energy collecting plates may be controlled according to a predetermined rotation angle, thereby increasing solar energy absorbing efficiency. | 2015-06-11 |
20150162869 | SOLAR CELL, MODULE, ARRAY, NETWORK, AND POWER GRID - The present invention teaches a solar cell, a solar module, a solar array, a network of solar arrays, and also a solar power grid suitable for providing power for industrial, residential and transportation use. A solar cell or solar module including a plurality of solar cells can be made in a structure configured to have the appearance of natural foliage. Accordingly, a solar array including a plurality of solar modules each including at least one solar cell can be made to resemble a palm tree, a deciduous tree, an evergreen tree, or other type of natural foliage. A network of solar arrays can be made to resemble a row or grove of palm trees, and thus meet the functional and aesthetic demands of landscape architecture. The network of solar arrays can extend for many miles alongside roads, highways, railways, pipelines, or canals, and can further include means for storing and transmitting electric power. In particular, a network of solar arrays can be in communication with recharging stations for use by electric and hybrid transportation vehicles. Accordingly, a network of solar arrays can form at least a portion of a solar power grid. | 2015-06-11 |
20150162870 | Edge Connector for Photovoltaic Solar Modules - An edge connector for a photovoltaic solar module is provided, comprising: a dielectric edge connector housing with a lateral mounting tab for attachment to an end-face edge of the solar module; a first cable connector disposed at an end of the edge connector housing for releasably connecting a first connection line to the edge connector for establishing an electrical connection between the connection line and the solar module; a second cable connector disposed opposite the first cable connector on the edge connector housing and electrically connected to the first cable connector, for attaching an edge connector line that is limited to the solar module; and a conductor strip connecting element disposed between the cable connectors of the edge connector and electrically connected to the cable connectors, for electrical connection to a conductor strip. | 2015-06-11 |
20150162871 | Method of Cell Isolation in Photovoltaic Solar Module or Solar Array - This disclosure puts the light on the “method of cell isolation” in photovoltaic (PV) solar module and solar array. The present method and device prevent a shaded cell to affect the power of a PV solar module. The device controls every individual cell in the module or in the array. In a standard PV solar module of 60 cells for instance, if one individual cell is shaded the device isolates the shaded cell and allows the power of the 59 remaining cells to be harvested without suffering other losses. In other words, if one cell is shaded only the power of this cell is lost. Consequently, the power lost in a PV solar module or solar array is proportional to the number of cells shaded in that module or array. The device has 3 main parts: the “Command”, the “Check Cell” and the “Relay”. The Command circuit sends in the loop a pulse to the Check Cell circuits which role is to compare the voltage of the cells against a reference voltage. If a “cell k” is shaded, the “Check Cell k” commands the “Relay k” to close allowing the main current to flow through the relay. When the “Check Cell k” receives again a pulse from the Command circuit and the “cell k” is no longer shaded, then it commands the relay to open. | 2015-06-11 |
20150162872 | INSPECTION APPRATUS AND INSPECTION METHOD - An inspection apparatus inspects a solar cell. The inspection apparatus includes: a short-circuiting element that electrically connects an anode as a p-type semiconductor layer and a cathode as an n-type semiconductor layer of the solar cell to short-circuit the solar cell; an irradiation part that irradiates the solar cell short-circuited by the short-circuiting element with pulse light; and a detection part that detects an electromagnetic wave emitted from the solar cell in response to the irradiation of the solar cell with pulse light from the irradiation part. | 2015-06-11 |
20150162873 | IMPULSE-ASSISTED LC TANK OSCILLATOR - An impulse generation circuit for a voltage controlled oscillator includes a zero-crossing detector configured to detect a zero-crossing time of an output signal of the voltage controlled oscillator. The zero-crossing time corresponds to a time that the output signal crosses from a first polarity to a second polarity. A delay circuit is configured to wait for a delay period based on the zero-crossing time and a voltage peak of the output signal. An impulse generation module is configured to generate an impulse subsequent to the delay period. An energy injector is configured to, in response to the impulse, connect a supply voltage to the output signal of the voltage controlled oscillator for a duration of the impulse. | 2015-06-11 |
20150162874 | RESISTANCE CORRECTION CIRCUIT, RESISTANCE CORRECTION METHOD, AND SEMICONDUCTOR DEVICE - Disclosed is a semiconductor device that suppresses stress-induced resistance value changes. The semiconductor device includes a resistance correction circuit. The resistance correction circuit includes a first resistor whose stress-resistance value relationship is a first relationship, a second resistor whose stress-resistance value relationship is a second relationship, and a correction section that controls the resistance value of a correction target resistor. The correction section detects the difference between the resistance value of the first resistor and the resistance value of the second resistor and corrects, in accordance with the result of detection, the resistance value of the correction target resistor. | 2015-06-11 |
20150162875 | REGENERATIVE FREQUENCY MULTIPLIER - A technology is provided for generating an output frequency. An input signal with a defined frequency may be received. The input signal may be split so that a first signal with the defined frequency of the input signal is received at a frequency multiplier and a second signal with the defined frequency of the input signal is received at a frequency mixer. The first signal may be multiplied by N, wherein N is a predefined integer. The first signal may be limited to a predetermined frequency and passed to the frequency mixer. The first signal and the second signal may be mixed to produce at least two mixed signals. A first output signal and a second output signal may be generated based on the at least two mixed signals. | 2015-06-11 |
20150162876 | AMPLIFIER CIRCUIT WITH CROSS WIRING OF DIRECT-CURRENT SIGNALS AND MICROWAVE SIGNALS - Provided is an amplifier circuit with cross wiring of direct-current signals and microwave signals, which includes: two branch sub-circuits being mirrors with each other and a third capacitor The sub-circuit includes a direct-current feeding circuit and a microwave signal circuit. The direct-current feeding circuit further comprising: a transistor core drain power-up port (Vds) of a heterojunction field effect transistor (FET), a first micro-strip inductor, a first capacitor, a pair of third inductors, a pair of branched second inductors. The microwave signal circuit further comprising: A pair of third inductors, a pair of first capacitors, a pair of second capacitors, a pair of ground inductors, a pair of fourth inductors, a serially connected fifth inductor. | 2015-06-11 |
20150162877 | SYSTEMS, CIRCUITS AND METHODS RELATED TO MULTI-MODE POWER AMPLIFIERS HAVING IMPROVED LINEARITY - Multi-mode power amplifiers (PAs) having improved linearity. A PA can include an amplifying bipolar junction transistor (BJT) configured to receive and amplify a radio-frequency (RF) signal. The PA can further include a biasing circuit configured to provide a first bias signal or a second bias signal to the BJT for operation in a first mode or a second mode. Each of the first bias signal and the second bias signal can be routed to the BJT through a path that includes a common node and a ballast. The PA can further include a linearizing circuit implemented between the common node and a node along an input path for the BJT. The linearizing circuit can be configured as a coupling path to improve linearity of the PA operating in the first mode while allowing the ballast to be sufficiently robust for the PA operating in the second mode. | 2015-06-11 |
20150162878 | Harmonics Cancellation Circuit for a Power Amplifier - The present disclosure relates to a circuit that includes an input port for applying a sinusoidal input signal, and a first buffering means for converting the sinusoidal input signal into a square wave signal. A DC level of the square wave signal may be defined by an adjustable threshold voltage level. The circuit also includes an output port for outputting the square wave signal to a power amplifier. Further, the circuit includes a feedback loop having a low pass filtering means arranged for filtering the square wave signal and comparing means arranged for comparing a DC level of a filtered signal received from the low pass filtering means with a pre-set reference level. The reference level may be selected for cancelling a given harmonic component. The comparing means is further arranged for outputting to the first buffering means a correction signal for adjusting the threshold voltage level of the first buffering means. | 2015-06-11 |
20150162879 | WIDEBAND ACTIVE BALUN LNA TOPOLOGY WITH NARROW-BAND FILTERING AND NOISE CANCELLING - The present invention provides a wideband active balun LNA topology with narrow-band filtering and noise cancelling. The amplifier includes three transconductance stages, a feedback network, and a load. The first and second transconductance stages are connected in parallel to receive the input signal. The differential output of the first transconductance stage is fed back to voltage input through a differential-to-single-end-end feedback network, while the output of the first transconductance, passing through the third transconductance, is added to the output of the second transconductance stage in proper phase. The present invention accomplish both wideband low-noise amplification and narrow-band filtering without inserting interface stages, thereby improving the linearity and noise performance of the whole circuit. Noise cancellation technique is implemented in differential way to ensure the low noise figure. The present invention also achieves single-end to differential conversion with balanced output and superior second order linearity performance. | 2015-06-11 |
20150162880 | INTERFERENCE SUPPRESSION FOR SWITCHED MODE POWER SUPPLY WITH ERROR CORRECTION - A switched mode power supply arranged to provide a switched supply at one terminal of an inductor, another terminal of the inductor being connected to a first input of an error amplifier having a reference signal at a second input, the error amplifier generating a corrected switched supply at an output in dependence on the difference between signals at its first and second inputs, there being provided a feedback path between the output of the error amplifier and the first input of the error amplifier, and further comprising circuitry for sensing a switcher interference current in the feedback path of the error amplifier, and for adjusting the corrected switched supply output to reduce the switcher interference current in the output. | 2015-06-11 |
20150162881 | AUGMENTED TWIN NONLINEAR TWO-BOX MODELING AND PREDISTORTION METHOD FOR POWER AMPLIFIERS AND TRANSMITTERS - The augmented twin nonlinear two-box modeling and predistortion method for power amplifiers and transmitters provides power amplifier distortion modeling and predistortion linearization. A memoryless nonlinearity is combined with a memory polynomial function that includes cross-terms. The method can utilize an augmented forward twin-nonlinear two-box model, an augmented reverse twin-nonlinear two-box model, or alternatively, an augmented parallel twin-nonlinear two-box model. The present two-box models are validated in modeling and predistortion applications. Measurement results demonstrate the superiority of the present two-box models with respect to conventional state of the art models. The present two-box models lead to better accuracy with reduced complexity. | 2015-06-11 |
20150162882 | POWER AMPLIFIER WITH WIDE BAND AM-AM FEEDBACK AND DIGITAL PRE-DISTORTION - A system including an amplifier circuit configured to amplify an input and generate an output, a bias circuit configured to bias the amplifier circuit, and a feedback circuit configured to generate feedback based on the input and the output, and to adjust the bias of the amplifier circuit based on the feedback to reduce amplitude nonlinearity in the output. A digital pre-distortion circuit is configured to reduce phase nonlinearity in the output. | 2015-06-11 |
20150162883 | AMPLIFIER CIRCUIT - The present disclosure relates to an amplifier circuit ( | 2015-06-11 |
20150162884 | DYNAMIC RANGE CONTROL GAIN ENCODING - A system and method is provided for converting Dynamic Range Control/Compression (DRC) gain values into a spline representation that is compatible with the current standards. The system and method may: 1) minimize the bitrate for encoding and/or 2) minimize the approximation error between reference gain and interpolation values. A strategy for bitrate minimization may be the reduction of the number of spline nodes since gain and slope information must be transmitted for each node. Accordingly, an efficient heuristics based approach is provided that reduces the number of spline nodes needed to represent a series of DRC gain values using interpolation while accounting for overshoots and other inaccuracies. | 2015-06-11 |
20150162885 | AMPLIFIER CIRCUIT AND METHOD OF AMPLIFYING A SIGNAL IN AN AMPLIFIER CIRCUIT - An amplifier circuit, comprising: an input, for receiving an input signal to be amplified; a power amplifier, for amplifying the input signal; a switched power supply, having a switching frequency, for providing at least one supply voltage to the power amplifier; and a dither block, for dithering the switching frequency of the switched power supply. The dither block is controlled based on the input signal. Another aspect of the invention involves using first and second switches, each having different capacitances and resistances, and using the first or second switch depending on the input signal or volume signal. Another aspect of the invention involves controlling a bias signal provided to one or more components in the signal path based on the input signal or volume signal. | 2015-06-11 |
20150162886 | TRANSMISSION LINE FILTER WITH TUNABLE CAPACITOR - A tunable filter design. The filter is implemented using transmission line sections as inductive and capacitive components. At least one capacitive component is a tunable capacitor. In some implementations, the tunable capacitor may be an interdigitated array of finger elements arranged so that the spacing between fingers may be adjusted. The design has a number of advantages including high capacitance for a given circuit area, small area for a given desired capacitance, mechanical stability, high self resonance frequency, and high quality factor. | 2015-06-11 |
20150162887 | OUTPUT STAGE FOR ADAPTING AN AC VOLTAGE SIGNAL OF AN ULTRASOUND GENERATOR - The present invention relates to an output stage for adapting an AC voltage signal of an ultrasound generator to a converter connectable to the output stage, wherein the output stage has two input terminals for receiving the AC voltage produced by the ultrasound generator and two output terminals for outputting an adapted AC voltage, as well as an output transformer with a primary coil having a number n | 2015-06-11 |
20150162888 | VARIABLE-FREQUENCY RESONANCE CIRCUIT AND VARIABLE-FREQUENCY FILTER - A variable-frequency resonance circuit includes first and second input/output terminals and a resonance circuit portion. The resonance circuit portion includes a first inductor and first and second LC series circuits. The resonance circuit portion is connected between a ground and a transmission line that connects the first and second input/output terminals. The first LC series circuit includes a second inductor and a variable capacitor connected in series with each other. The second LC series circuit includes a third inductor and a fixed capacitor connected in series with each other. The first and second LC series circuits are connected in parallel between the first inductor and a ground. The first and second inductors are configured such that positive-coupling mutual inductance is produced therebetween. | 2015-06-11 |
20150162889 | VARIABLE CAPACITANCE CIRCUIT AND IMPEDANCE MATCHING CIRCUIT - A first variable capacitance section included in a variable capacitance circuit includes a plurality of first variable capacitance elements connected to a signal line and each having a first capacitance value or a second capacitance value greater than the first capacitance value according to driving voltage, and includes a first fixed capacitance element connected in series with the plurality of first variable capacitance elements. A second variable capacitance section included in the variable capacitance circuit includes a second variable capacitance element connected to the signal line and having the first capacitance value or the second capacitance value according to the driving voltage, and includes a second fixed capacitance element connected in series with the second variable capacitance element. | 2015-06-11 |
20150162890 | CIRCUIT MODULE - Isolators are disposed such that DC magnetic fields of permanent magnets intensity with each other, and thus, the input impedance of non-reciprocal circuits | 2015-06-11 |
20150162891 | LUMPED ELEMENT RADIO FREQUENCY TUNING CALIBRATION PROCESS - A preferred method for efficiently tuning RF ports while avoiding conventional labor intensive, step-by-step processes is disclosed. The method may use at least three tuning blocks (comprised of capacitors and inductors) in a series topology and at least three tuning blocks in a shunt topology. These tuning blocks will yield two circles that can be charted on the Smith chart. Those circles may then be centered along the centerline of the Smith chart to adjust for latency, and then expanded to adjust for the losses. Once those circles have been expanded, the circle (either series or shunt) that encompasses one the Smith chart reference circles is used and the traditional Smith chart methodology can be used to tune the RF port. | 2015-06-11 |
20150162892 | COMMUNICATION DEVICE AND METHOD OF ADJUSTING APPLIED VOLTAGE FOR MATCHING CIRCUIT - A communication device changes an applied voltage output from a voltage circuit, and allows a capacitance measuring device to measure the respective capacitance values of a variable capacitance element before and after a change in the applied voltage. The communication device calculates a voltage correction value for correcting an initial variation of the capacitance value of the variable capacitance element using the respective capacitance values of the variable capacitance element before and after the change in the applied voltage, and respective applied voltage values before and after the change, and a correction voltage for canceling the initial variation in the capacitance value of the variable capacitance element, and outputs the correction voltage from the voltage circuit. | 2015-06-11 |
20150162893 | ACOUSTIC WAVE DEVICE AND METHOD FOR MANUFACTURING SAME - An SAW device ( | 2015-06-11 |
20150162894 | SYNCHRONOUS CHARGE SHARING FILTER - A signal processing device has a first discrete time analog signal processing section, which has an input, an output, a plurality of charge storage elements, and plurality of switch elements coupling the charge storage elements. The device has a controller coupled to the first signal processing section configured to couple different subsets of the charge elements of the first signal processing section in successive operating phases to apply a signal processing function to an analog signal presented at the input of the first signal processing section and provide a result of the applying of the signal processing function as an analog signal to the output of first signal processing section. The signal processing function of the first signal processing section comprises a combination of a filtering function operating at a first sampling rate and one or more modulation functions operating at corresponding modulation rates lower than the first sampling rate. | 2015-06-11 |
20150162895 | AREA EFFICIENT BASEBAND FILTER - An area efficient baseband filter is disclosed. In an exemplary embodiment, an apparatus includes a current to voltage (I-V) filter configured to receive an input current signal at an input port and generate a filtered output voltage signal at an output port based on a feedback transconductance. The input current signal comprises an input DC current in addition to a signal current. The apparatus also includes a feedback circuit connected between the output port and the input port, the feedback circuit having at least one transistor configured to couple the input DC current to a signal ground and to provide the feedback transconductance for the I-V filter. | 2015-06-11 |
20150162896 | DIGITAL FILTER CIRCUIT - A digital filter circuit that implements a filtering process for a plurality of channels having different sampling rates with a small circuit complexity includes a delay circuit divided into first to mth groups of delay devices, processing stage division means for selectively supplying first to (m−1)th input delayed signals and output signals of the second to mth taps to the first to (m−1)th groups of delay devices, tap coefficient supply means for supplying first to mth selected tap coefficients, a multiplying circuit for multiplying outputs of the first to mth taps and the first to mth selected tap coefficients, an adding circuit for adding up first to mth multiplication results, an accumulative addition part for accumulatively adding the first to mth multiplication results and addition results of the plurality of adders, and an output data format generation part for generating an output format of a filtering process result of each of processing stages from the plurality of accumulative addition results and outputs of the adding circuit. | 2015-06-11 |
20150162897 | ADAPTIVE SELF-TUNABLE ANTENNA SYSTEM AND METHOD - Adaptive self-tunable antenna systems and methods are provided including a closed-loop system for sensing near-field RF signals of transmitted RF signals and tuning an antenna or switching between multiple antennas, so that the strength of the transmitted RF signals is maximized. A sensing antenna detects the near-field RF signal, which is filtered and converted to an RF strength control signal that can be used to generate an antenna tuning control signal. An antenna tuner uses the antenna tuning control signal to keep the antenna in resonance by dynamically changing the electrical length of the antenna or switching between multiple antennas to maximize the strength of the radiated RF signal. Such antennas may be less prone to detuning due to interaction with human bodies or other objects. Dynamically matching the antennas to an RF power amplifier and low noise amplifier can improve stability, power efficiency, gain, noise figure, and receiver sensitivity. | 2015-06-11 |
20150162898 | EFFICIENT WAKEUP OF POWER GATED DOMAINS THROUGH CHARGE SHARING AND RECYCLING - A mechanism is provided for an integrated circuit with power gating. A power header switch is configured to connect and disconnect any circuits to a common voltage source. A powered off circuit is disconnected from the common voltage source. A first capacitor and a second capacitor are configured to supply wakeup electrical charge to a given circuit of the circuits. The first capacitor and the second capacitor are connectable to the given circuit and the powered off circuit. A controller is configured to controllably connect the first capacitor and/or the second capacitor to the given circuit in order to supply the wakeup electrical charge to the given circuit, when the powered off circuit was previously connected to the first capacitor and/or the second capacitor. | 2015-06-11 |
20150162899 | EFFICIENT WAKEUP OF POWER GATED DOMAINS THROUGH CHARGE SHARING AND RECYCLING - A mechanism is provided for an integrated circuit with power gating. A power header switch is configured to connect and disconnect any circuits to a common voltage source. A powered off circuit is disconnected from the common voltage source. A first capacitor and a second capacitor are configured to supply wakeup electrical charge to a given circuit of the circuits. The first capacitor and the second capacitor are connectable to the given circuit and the powered off circuit. A controller is configured to controllably connect the first capacitor and/or the second capacitor to the given circuit in order to supply the wakeup electrical charge to the given circuit, when the powered off circuit was previously connected to the first capacitor and/or the second capacitor. | 2015-06-11 |
20150162900 | SAMPLE CLOCK GENERATOR FOR OPTICAL TOMOGRAPHIC IMAGING APPARATUS, AND OPTICAL TOMOGRAPHIC IMAGING APPARATUS - A sample clock generator includes a first optical path and a second optical path through which input lights are guided, an optical phase shifter to shift a phase of the input light guided through the first optical path, an interference-light generating unit to combine a phase-shifted input light and the input light guided through the second optical path to thereby generate an interference light for sample clock, a splitting unit to split the interference light for sample clock into two split lights having different phases, one light receiving unit to at least receive one split light from among the two split lights having different phases, the other light receiving unit to at least receive the other split light, a signal generating unit to generate a sample clock signal based on signals outputted from the one light receiving unit and the other light receiving unit. | 2015-06-11 |
20150162901 | Integrated Switch and Limiter Circuit - A fast response time, self-activating, adjustable threshold limiter including a limiting element LE, a first coupling element CE | 2015-06-11 |
20150162902 | METHOD AND APPARATUS FOR BALANCING CURRENTS - A method and apparatus are provided for balancing currents of two or more parallel-connected power semiconductor switches during an on-state of the switches. A control terminal of each switch is driven by a driver unit. The method includes determining ratios between the currents through the switches. For each switch, the method includes controlling the voltage at the control terminal on the basis of the ratios by controlling a level of a supply voltage of the driver unit of the switch, and after a turn-on commutation transient, modulating the output of the driver unit. The duty cycle of the modulation is controlled to minimize the time required for the transition of the voltage at the control terminal from the one voltage level to another. | 2015-06-11 |
20150162903 | EFFICIENT WAKEUP OF POWER GATED DOMAINS THROUGH CHARGE SHARING AND RECYCLING - A mechanism is provided for an integrated circuit with power gating. A power header switch is configured to connect and disconnect any circuits to a common voltage source. A powered off circuit is disconnected from the common voltage source. A first capacitor and a second capacitor are configured to supply wakeup electrical charge to a given circuit of the circuits. The first capacitor and the second capacitor are connectable to the given circuit and the powered off circuit. A controller is configured to controllably connect the first capacitor and/or the second capacitor to the given circuit in order to supply the wakeup electrical charge to the given circuit, when the powered off circuit was previously connected to the first capacitor and/or the second capacitor. | 2015-06-11 |
20150162904 | EFFICIENT WAKEUP OF POWER GATED DOMAINS THROUGH CHARGE SHARING AND RECYCLING - A mechanism is provided for an integrated circuit with power gating. A power header switch is configured to connect and disconnect any circuits to a common voltage source. A powered off circuit is disconnected from the common voltage source. A first capacitor and a second capacitor are configured to supply wakeup electrical charge to a given circuit of the circuits. The first capacitor and the second capacitor are connectable to the given circuit and the powered off circuit. A controller is configured to controllably connect the first capacitor and/or the second capacitor to the given circuit in order to supply the wakeup electrical charge to the given circuit, when the powered off circuit was previously connected to the first capacitor and/or the second capacitor. | 2015-06-11 |
20150162905 | HIGH PERFORMANCE IGBT GATE DRIVE - High performance gate drives and methods for driving semiconductor switching elements, such as insulated gate bipolar transistors (IGBTs), are provided. The gate drive can control the voltage applied to the gate of the IGBT to one or more intermediate voltages near the threshold voltage of the IGBT to control dv/dt of the collector-emitter voltage during and the di/dt of the collector current turn off. For instance, a voltage level between the turn on voltage and the turn off voltage can be applied for a first time period to control dv/dt of the collector-emitter voltage and di/dt of the collector current during turn off. Another voltage level between the turn on voltage and the turn off voltage can be applied for a second time period during reverse recovery of a freewheeling diode coupled in parallel with the IGBT. | 2015-06-11 |
20150162906 | METHODS FOR OVERDRIVING A BASE CURRENT OF AN EMITTER SWITCHED BIPOLAR JUNCTION TRANSISTOR AND CORRESPONDING CIRCUITS - An emitter switched bipolar transistor circuit includes a bipolar junction transistor (BJT) having a collector coupled to an output terminal, a metal oxide semiconductor field effect transistor (MOSFET) coupled to an emitter of the BJT, a bias voltage supply coupled to the base of the BJT, a buffer coupled to the base of the BJT, and a comparator. The comparator includes a first input coupled to the collector of the BJT, a second input coupled to a voltage reference, and an output coupled to an input of the buffer. The comparator is configured to receive a collector voltage of the BJT at the first input of the comparator, compare the received collector voltage with the voltage reference, and cause the buffer to inject a current pulse to the base of the BJT until the collector voltage is less than the voltage reference, indicating the BJT is substantially saturated. | 2015-06-11 |
20150162907 | CONFIGURABLE INTERFACE CIRCUIT - The present invention relates to an interface circuit for intermediate connection between a logic circuit and a power circuit, having a supply connection for connection to a power supply, contains two logic connections, which are configurable as logic input or logic output, and two power connections, which are configurable as power input or power output, and a configuration unit for the corresponding configuration, wherein the power input can be read by the logic output and the power output can be driven by the logic input. | 2015-06-11 |
20150162908 | TOUCH-SENSOR STRUCTURES AND METHODS OF FORMING THE SAME - A touch-sensor structure includes a first conductive layer, a second conductive layer, insulating isolation portions, and an intermediate conductive layer. The first conductive layer includes first conductive units, connection lines and second conductive units. Each connection line connects to two first conductive units. The second conductive layer includes bridge lines. Each bridge line is electrically connected to two second conductive units. The insulating isolation portion is disposed between the connection line and the bridge line. The intermediate conductive layer is at least disposed at an overlapping position between the bridge lines and the second conductive units to isolate the first conductive layer from the second conductive layer. The intermediate conductive layer electrically connects each bridge line to the corresponding second conductive units. | 2015-06-11 |
20150162909 | LOAD IMPEDANCE ADJUSTMENT FOR AN INTERFACE OF A DATA STORAGE DEVICE - A data storage device includes a signal source. A load is responsive to the signal source. A method includes adjusting an impedance of the load to reduce an impedance mismatch between the signal source and the load. | 2015-06-11 |
20150162910 | LOW-POWER INTERNAL CLOCK GATED CELL AND METHOD - A circuit includes a clock trigger block and a logic circuit. The logic circuit is configured to output a signal to the clock trigger block based on a logic level of an enable signal received at the logic circuit. The clock trigger block is configured to output an output signal response to a clock signal received at the clock trigger block and the signal received from the logic circuit. | 2015-06-11 |
20150162911 | OPERATION MODE SETTING CIRCUIT OF SEMICONDUCTOR APPARATUS AND DATA PROCESSING SYSTEM USING THE SAME - An operation mode setting circuit of a semiconductor apparatus includes a mode register set configured to update an operation mode information generated internally at the semiconductor apparatus based on preliminary information data in response to a preliminary information setting signal and a preliminary information providing block configured to provide the preliminary information data selected from a plurality of pre-stored preliminary information data to the mode register setting response to the preliminary information setting signal, the selected preliminary information data corresponding to a detected operation parameter detected in response to the preliminary information setting signal. | 2015-06-11 |
20150162912 | LEVEL SHIFTER - A level shifter includes a first transistor, a second transistor, a third transistor, a fourth transistor, and a switching element. The first transistor is connected to a first node, the input signal and a first power supply voltage. The second transistor is connected to a second node, an inverted input signal and the first power supply voltage. The third transistor is connected to a second power supply voltage, the first node and the second node. The fourth transistor is connected to the second power supply voltage, the second node and the first node. The switching element is connected between the first node and the second node. When a voltage level of the input signal is changed, the switching element is turned on for a time interval according to the enabling signal, so that a voltage level of the output signal is changed. | 2015-06-11 |
20150162913 | FILED PROGRAMMABLE GATE ARRAY DEVICE WITH PROGRAMMABLE INTERCONNECT IN BACK END OF LINE PORTION OF THE DEVICE - A Field-Programmable Gate Array device is provided with programmable interconnect points in the form of interconnect circuits comprising one or more pass transistors, wherein at least some components of the interconnect circuits are implemented in the Back-End-Of-Line part of the Field-Programmable Gate Array device's production process. The memory element in an interconnect point is not produced as a Static Random Access Memory cell, but as a Dynamic Random Access Memory cell, requiring only a single select transistor and a storage capacitor for each memory element. The fabrication of at least the select transistor and the pass transistor involves the use of a thin film semiconductor layer, e.g., Indium Gallium Zinc Oxide, enabling production of transistors with low leakage in the Back-End-Of-Line. | 2015-06-11 |
20150162914 | Resonant Inductor Coupling Clock Distribution - The present disclosure provides for a clock distribution network for distributing clocking signals within a synchronous sequential logic circuit. The clock distribution network distributes the one or more clock signals by inductively and/or capacitively coupling a clocking signal from a primary distribution node to various secondary distribution nodes within the synchronous sequential logic circuit. The various secondary distribution nodes resonate at respective resonant frequencies to generate other clocking signals for use within the synchronous sequential logic circuit in response to receiving the clocking signal. | 2015-06-11 |
20150162915 | SEMICONDUCTOR INTEGRATED CIRCUIT AND POWER-SUPPLY VOLTAGE ADAPTIVE CONTROL SYSTEM - A semiconductor integrated circuit has: N input terminals; N output terminals; a plurality of flip-flops including N flip-flops and R redundant flip-flops; a selector section configured to select N selected flip-flops from the plurality of flip-flops depending on reconfiguration information and to switch data flow such that data input to the N input terminals are respectively output to the N output terminals by the N selected flip-flops; and an error detection section. At a test mode, the N flip-flops form a scan chain and a scan data is input to the scan chain. The error detection section detects an error flip-flop included in the N flip-flops based on scan input/output data respectively input/output to/from the N flip-flops at the test mode and further generates the reconfiguration information such that the detected error flip-flop is excluded from the N selected flip-flops. | 2015-06-11 |
20150162916 | FRACTIONAL-N SYNTHESIZER - One embodiment of the present invention provides a synthesizer. The synthesizer includes one or more tunable oscillators, a frequency-dividing circuit coupled to the tunable oscillators, and a multiplexer coupled to the frequency-dividing circuit. The frequency-dividing circuit includes a number of frequency dividers, and is configured to generate a number of frequency-dividing outputs. At least one frequency-dividing output has a different frequency division factor. The multiplexer is configured to select a frequency-dividing output | 2015-06-11 |
20150162917 | CLOCK GENERATION CIRCUIT - The present technique relates to a clock generation circuit including a phase difference comparison circuit configured to compare a phase of each of an input clock signal and a feedback signal, and provides a phase difference signal indicating a phase difference between the input clock signal and the feedback signal, a filter circuit configured to suppress a high frequency component in the phase difference signal, an output circuit configured to modulate the phase difference signal in such a manner as to decrease a noise component of a low frequency band and increase a noise component of a high frequency band, and generate and output an output clock signal from the modulated phase difference signal and a reference clock signal, and a frequency dividing circuit configured to divide a frequency of the output clock signal, at a predetermined frequency dividing ratio, and feed it back to the phase comparison circuit. | 2015-06-11 |
20150162918 | DIGITAL OUTPUT CLOCK GENERATION - An on-chip clock signal generation apparatus is provided which is configured to generate an output clock signal to be passed off-chip in association with an output data signal. The apparatus comprises: an input configured to receive an input clock signal and clock phase generation circuitry configured to generate a plurality of candidate clock signals in dependence on the input clock signal. The candidate clock signals are phase-shifted with respect to one another. Selection circuitry is configured to select and output one of the candidate clock signals as the output clock signal in dependence on at least one selection signal. All components of the apparatus are embodied as digital components. | 2015-06-11 |
20150162919 | APPARATUSES AND METHODS FOR COMPENSATING FOR POWER SUPPLY SENSITIVITIES OF A CIRCUIT IN A CLOCK PATH - Apparatuses and methods for compensating for differing power supply sensitivities of a circuit in a clock path. One such method includes altering signal timing of at least one of reference and feedback clock signals differently according to variations in power supply voltage to compensate for differences in delay power supply sensitivities of delays of a forward clock path and of a feedback clock path. Another example method includes providing an output clock signal in phase with an input clock signal and compensating for delay error between delays used in providing at least some of the delay of the output clock signal relative to the input clock signal by providing delays having power supply sensitivities resulting in a combined power supply sensitivity that is inverse to the delay error. | 2015-06-11 |
20150162920 | MULTI-FREQUENCY CLOCK SKEW CONTROL FOR INTER-CHIP COMMUNICATION IN SYNCHRONOUS DIGITAL SYSTEMS - Embodiments are disclosed of an apparatus capable of performing multi-rate synchronous communication between component chips. Each chip may receive a common clock reference signal, and may generate an internal clock signal dependent on the clock reference signal. A clock distribution tree and phase-locked loop may be used to minimize internal clock skew at I/O circuitry at the chip perimeter. Each chip may also generate an internal synchronizing signal that is phase-aligned to the received clock reference signal. Each chip may use its respective synchronizing signal to synchronize multiple clock dividers that provide software-selectable adjusted-frequency clock signals to the I/O cells of the chip. In this way, the adjusted-frequency clock signals of the multiple chips are edge-aligned to the low-skew internal clock signals, and phase-aligned to the common clock reference signal, allowing the I/O cells of the multiple chips to perform synchronous communication at multiple rates with low clock skew. | 2015-06-11 |
20150162921 | CIRCUIT AND OPERATING METHOD OF PLL - A phase locked loop (PLL) includes a voltage controlled oscillator (VCO), a loop filter, and a feedback control unit. The VCO is configured to generate a first oscillating signal and a second oscillating signal according to a VCO control signal. The loop filter is configured to output the VCO control signal by low-pass filtering a signal at an input node of the loop filter. The feedback control unit has an output node coupled to the input node of the loop filter, the feedback control unit is configured to apply a first predetermined amount of current, along a first current direction, to the first feedback control output node during a variable period of time; and to apply one of K second predetermined amounts of current, along a second current direction opposite the first current direction, to the first feedback control output node during a predetermined period of time. | 2015-06-11 |
20150162922 | BIMODAL SERIAL LINK CDR ARCHITECTURE - A system for generating a local clock, configurable to utilize a forwarded clock and a data stream, or a data stream only, as frequency and phase references. In one embodiment, the system includes a phase locked loop that may be referenced to a forwarded clock, or to a phase reference formed from received data, utilizing a sampler, a crossing sampler, and a bang-bang phase detector. The system includes a local phase recovery loop which may utilize the bang-bang phase detector as part of a phase detector for controlling a phase interpolator, the output of the phase interpolator serving as the local clock for clocking received data. | 2015-06-11 |
20150162923 | CIRCUITS AND METHODS OF SYNCHRONIZING DIFFERENTIAL RING-TYPE OSCILLATORS - A circuit includes a first differential ring-type oscillator, a second differential ring-type oscillator, and a coupling structure. The coupling structure capacitively couples the first and second differential ring-type oscillators. A method of synchronizing the first and second differential ring-type oscillators is also disclosed. | 2015-06-11 |
20150162924 | SIGNAL PROCESSING APPARATUS, SIGNAL PROCESSING METHOD, AND NON-TRANSITORY COMPUTER-READABLE STORAGE MEDIUM STORING PROGRAM - To enable processing of a signal at an appropriate level. | 2015-06-11 |
20150162925 | IMAGE SENSOR INCLUDING HETEROGENEOUS ANALOG TO DIGITAL CONVERTOR - An image sensor in accordance with exemplary embodiments of the inventive concept may include a pixel sensor array which includes an active pixel sensor and an optical black pixel sensor; a first analog to digital converter configured to convert a first sensing signal, which is provided from the active pixel sensor, to a first digital signal; a second analog to digital converter configured to convert a second sensing signal, which is provided from the optical black pixel sensor, to a second digital signal; and an output buffer configured to temporarily store and output the first digital signal and the second digital signal, wherein a plurality of noise characteristics of the second analog to digital converter is different from a plurality of noise characteristics of the first analog to digital converter. | 2015-06-11 |
20150162926 | SUCCESSIVE APPROXIMATION REGISTER ANALOG-TO-DIGITAL CONVERTER - A successive approximation register (SAR-ADC) including a digital-to-analog conversion (DAC) circuit, a sample-and-hold circuit, a comparison circuit and a SAR logic control circuit is provided. The DAC circuit is configured to convert an N-bits digital logic signal into a comparison signal, where N is a positive integer. The sample-and-hold circuit is configured to sample and hold an analog input signal. The comparison circuit is configured to use the analog input signal held by the sample-and-hold circuit as a basis for comparing with the comparison signal and thereby generates a comparison result signal. The SAR logic control circuit is configured to provide the N-bits digital logic signal and determine a logic state of each of bits of the digital logic signal one by one according to the comparison result signal, and thus generate a digital output signal related to the analog input signal. | 2015-06-11 |
20150162927 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND DATA PROCESSING SYSTEM - The semiconductor integrated circuit device has: more than one analog port; an A/D conversion part operable to execute an A/D conversion process for converting an analog signal taken in through each analog port into a digital signal for each preset virtual channel; and an A/D conversion control part operable to control an action of the A/D conversion part. The A/D conversion control part includes: virtual channel registers on which correspondence between the virtual channel and the analog port can be set; and a scan-group-forming register on which a start position of a scan group and an end position thereof can be set. The A/D conversion control part controls the A/D conversion part to successively execute an A/D conversion process on a plurality of virtual channels from a virtual channel associated with the start pointer to a virtual channel associated with the end pointer. | 2015-06-11 |
20150162928 | METHOD AND SYSTEM FOR ASYNCHRONOUS SUCCESSIVE APPROXIMATION REGISTER (SAR) ANALOG-TO-DIGITAL CONVERTERS (ADCS) - An asynchronous successive approximation register analog-to-digital converter (SAR ADC), which utilizes one or more overlapping redundant bits in each digital-to-analog converter (DAC) code word, is operable to generate an indication signal that indicates completion of each comparison step and indicates that an output decision for each comparison step is valid. A timer may be initiated based on the generated indication signal. A timeout signal may be generated that preempts the indication signal and forces a preemptive decision, where the preemptive decision sets one or more remaining bits up to, but not including, the one or more overlapping redundant bits in a corresponding digital-to-analog converter code word for a current comparison step to a particular value. For example, the one or more remaining bits may be set to a value that is derived from a value of a bit that was determined in an immediately preceding decision. | 2015-06-11 |
20150162929 | ANALOG-TO-DIGITAL CONVERTER AND IMAGE SENSOR - An analog-to-digital converter has a comparator to compare, within a predetermined period, an input signal with a ramp signal or with a triangle wave signal, a first counter to count up or down in accordance with a logic of a signal that indicates a comparison result of the comparator within the predetermined period, a count value storage to sequentially store count values of the first counter whenever the logic of the signal that indicates a comparison result of the comparator changes within the predetermined period, a second counter to count the number of times the logic of the signal that indicates a comparison result of the comparator changes, and an arithmetic module to output a value obtained by adding up the count values stored in the count value storage and dividing the added-up value by a count value of the second counter. | 2015-06-11 |
20150162930 | MULTI-ZONE DATA CONVERTERS - Aspects of a method and system for data converters having a transfer function with multiple operating zones. In some embodiments, an operating zone of the multiple operating zones is characterized by more stringent performance criteria than the other operating zones. Thus, such data converters may receive an input signal and generate an output signal from the input signal per the transfer function and the more stringent performance criteria in the appropriate operating zone. | 2015-06-11 |
20150162931 | ANALOG TO DIGITAL CONVERTER CIRCUIT - An analog-digital converter circuit is disclosed. Voltage control means is configured to control a voltage. Comparing means is configured to send a resulting comparative signal to the voltage control means. A first DAC is connected to the comparing means and to the voltage control means. Switching means connects an input means to the comparing means during a sampling phase. A second DAC is connected to the comparing means and to the voltage control means. A switching means connects input to the second DAC during a sampling phase, and connects voltage control means to DAC during a conversion phase. Switching means connects a second input to comparing means during a sampling phase. | 2015-06-11 |
20150162932 | Tunable Baseline Compensation Scheme for Touchscreen Controllers - A method for compensating for panel capacitance the associated current is proposed, wherein the mutual capacitances of a capacitance sensing array are selectively coupled to drive voltages and to a self capacitance under test. | 2015-06-11 |
20150162933 | METHOD FOR DIGITAL ERROR CORRECTION FOR BINARY SUCCESSIVE APPROXIMATION ANALOG-TO-DIGITAL CONVERTER (ADC) - An analog input voltage is converted to a digital code by, generating a first set of confirmed bits based on a first series of comparisons of an output of a digital-to-analog converter with the analog input voltage and generating a second set of confirmed bits based on a second series of comparisons of the output of the digital-to-analog converter with the analog input voltage. The first set of confirmed bits is independent of the second series of comparisons. The bits of the digital output code corresponding to the analog input voltage are generated based on the first set of confirmed bits, the second set of confirmed bits and a constant value representative of a voltage shift introduced in the digital-to-analog converter between the first series of comparisons and the second series of comparisons. | 2015-06-11 |
20150162934 | DIGITAL-TO-ANALOG CONVERSION APPARATUSES AND METHODS - A digital-to-analog conversion apparatus to convert a digital signal to an output analog voltage signal includes an analog-to-digital conversion processing circuit and an analog voltage signal output circuit. The analog-to-digital conversion processing circuit is configured to increase a resolution of the digital-to-analog conversion apparatus without increasing a frequency of an input clock signal. The analog voltage signal output circuit is configured to generate the output analog voltage signal based on the input clock signal at the increased resolution of the digital-to-analog conversion apparatus. | 2015-06-11 |
20150162935 | DELTA-SIGMA ANALOG-TO-DIGITAL CONVERTER - A delta-sigma analog-to-digital converter for use with multiplexed input channels. The delta-sigma analog-to-digital converter comprising at least one integrator that includes an operational amplifier, a memory element with a leakage preventing switch structure for each input channel and a reset switch element adapted to reset the operational amplifier between the input channels. The specific switch design prevents effectively channel to channel cross talk between multiplexed channels. | 2015-06-11 |
20150162936 | Method for Coding a Data Stream - The invention relates to a method for coding a data stream (DS), wherein the data stream (DS) comprises a multiplicity of characters which are symbols (S) from an alphabet, wherein the characters of the data stream (DS) are combined to form a plurality of blocks (B), and the blocks (B) are entropy-coded on the basis of a code table (CT) valid for the respective block (B). The method according to the invention is characterized by the fact that the blocks (B), by means of iteration (IT), are associated with a plurality of clusters (CL) on the basis of a clearance (d) which is defined such that the clearance (d) between a block (B) and a cluster (CL) is smaller the less pronounced the change in the entropy (ET) of the cluster (CL) when adding the block (B) to the cluster (CL). In a respective iteration step, of the iteration (IT), reassignment of the blocks (B) to the clusters (CL) takes place by virtue of the blocks (B) being assigned in each case to the cluster (CL) with the smallest clearance (d) between the block (B) and the cluster (CL). Then, in each case one code table (CT) is assigned to the clusters (CL) determined by the iteration (IT), which code table is determined on the basis of the frequency distribution of the symbols (S) in at least some of the blocks (B) contained in the respective cluster (CL) and is valid for all blocks (B) of the respective cluster (CL). | 2015-06-11 |
20150162937 | Adaptive Coded-Modulation for Intelligent Optical Transport Networks - A computer implemented method for dynamic data rate adjustment within a cascaded forward error correction FEC for optical communications includes subjecting data communicated over an optical network to a forward error correction in an encoding or decoding of the data, the encoding or decoding employing a codeword, re-encoding part of the codeword for generating a subsequent codeword where an actual code rate is tuned by adjusting a size of data encoded to provide re-encoded data, and dynamically changing the re-encoded data size to achieve cascaded rate adaptive FEC for communication of the data over the optical network. | 2015-06-11 |
20150162938 | DIGITAL RADIO TAGGING USING AN RF TUNER ACCESSORY - An accessory having an RF tuner for digital radio, such as HD radio, can be in communication with a media player such as a portable media device (“PMD”). The user can be given the ability to command the accessory to provide raw digital data, the ability to scan only for stations having digital audio content (or for all available stations), the ability to provide station lists of stations having digital audio content (or all available stations), and the ability to request and store metadata beyond that for stations actually being listened to provide enhanced search capabilities. Enhanced metadata and searching can provide the listener the ability to refine station choices without having to listen at length to any particular station, and further can facilitate tagging broadcast tracks for subsequent access and/or purchase. | 2015-06-11 |
20150162939 | SYSTEM AND METHOD FOR SIMULTANEOUS VOICE AND DATA COMMUNICATIONS - An antenna configuration for an electronic device routes a receive communication path. The antenna configuration includes a main antenna coupled to a transmit communication path, a diversity antenna, and a switch controller. The switch controller operates to route the receive communication path to a main receiving component of a transceiver from the main antenna when the electronic device is operating in a first operational mode and route the receive communication path to the main receiving component of the transceiver from the diversity antenna when the electronic device is operating in a second operational mode. | 2015-06-11 |
20150162940 | TIA-TO-ADC INTERFACE WITH LOW-NOISE AND A WIDE-RANGE OF PASSIVE GAIN CONTROL - A circuit for a low-noise interface between an amplifier and an analog-to-digital converter (ADC) may comprise a capacitor element having a capacitance of C coupled between a first and second output node of the amplifier. A resistor circuit coupled between the capacitor element and input nodes of the ADC. A desired value R | 2015-06-11 |
20150162941 | APPARATUS AND METHOD FOR UTILIZING A SMART RECEIVER SWITCH FOR IMPROVING IDLE MODE PERFORMANCE - An apparatus, a method, and a computer program are disclosed, which can enable a wireless user equipment (UE) to reduce or avoid system losses, such as decode failures and the unavailability of page messages, which might otherwise result in a poor user experience. By way of example and not limitation, a UE may be configured to switch from a low-sensitivity receiver to a high-sensitivity receiver, or to a receive diversity configuration, when operating under poor channel conditions. | 2015-06-11 |
20150162942 | POWER CONTROL SCHEME FOR DEVICE TO DEVICE NETWORKS - The invention is directed to systems, methods and computer program products for managing device-to-device (D2D) traffic associated with a terminal. An exemplary method comprises: first determining whether the terminal is handling D2D traffic; second determining whether a human body is located either less than or equal to a predetermined distance from the terminal; third determining whether the terminal is receiving power from an external power source; and fourth determining whether to continue handling D2D traffic based on at least one of the second and third determining steps. | 2015-06-11 |
20150162943 | Proximity Detection Using an Antenna and Directional Coupler Switch - Detection of an increase in a mismatch of an antenna of a radio frequency (RF) device and/or a change in a capacitance value of the antenna indicates proximity of a body to the antenna. Upon detection of proximity of a body to the antenna, reduction of transmit power of the RF device may be done to meet Specific Absorption Rate (SAR) level regulations. | 2015-06-11 |
20150162944 | Proximity Detection Using an Antenna and Directional Coupler Switch - Detection of an increase in a mismatch of an antenna of a radio frequency (RF) device and/or a change in a capacitance value of the antenna indicates proximity of a body to the antenna. Upon detection of proximity of a body to the antenna, reduction of transmit power of the RF device may be done to meet Specific Absorption Rate (SAR) level regulations. | 2015-06-11 |
20150162945 | DOCKING SYSTEM FOR A WIRELESS COMMUNICATION DEVICE - There is provided a docking system comprising a mobile communication device comprising an accelerometer, a first docking station configured to hold the communication device at a first tilt angle; and a second docking station configured to hold the communication device at a second tilt angle, the second angle being different from the first angle, wherein the communication device further comprises processing circuitry configured to, when the communication device is placed in the docking station: detect an electrical connection between the mobile device and docking station; enable the accelerometer and detect a tilt angle of the communication device; and based on the detected tilt angle, identify a docking station and set charging properties of the communication device. There is also provided a method for setting properties of a mobile device based on a measured tilt angle. | 2015-06-11 |
20150162946 | GLASS SUBSTRATE FOR DISPLAY AND MANUFACTURING METHOD THEREOF - The present disclosure relates to the field of liquid crystal display, and particularly to a glass substrate for a display. The glass substrate is treated through a vapor deposition apparatus, and includes an optical compensation film. The optical compensation film has a relatively higher transmittance in a compensation area than in other areas, and the shape and position of the compensation area are configured to be consistent with a non-uniform heated area caused by the vapor deposition apparatus on the glass substrate. The present disclosure further relates to a corresponding method for manufacturing the glass substrate. According to the present disclosure, the defects of the glass substrate can be accurately overcome and the mura phenomenon of the display panel can be reduced. | 2015-06-11 |
20150162947 | DATA COMMUNICATION DEVICE FOR A TRANSPORT MEANS - A simplified mobile data communication device ( | 2015-06-11 |
20150162948 | Electronic Device Cover - An electronic device cover is provided having an elongated first surface, a first and second sidewall surface, and a first and second inward lip member forming a sleeve-like configuration to accept a handheld electronic device therein. The first end of the cover comprises an inwardly flaring surface adapted to prevent an electronic device from sliding therethrough. The second end of the cover comprises an outwardly flaring surface adapted to facilitate insertion of an electronic device therethrough. The device is adapted to be sized such that the first surface and sidewall surfaces are coextensive with a rectangular smartphone or tablet device. The inward lip members extend partially over the outer surface of the electronic device to retain the same within the cover interior volume. Overall, the cover dissipates impact energy and improves acoustics of the electronic device when secured thereto. | 2015-06-11 |
20150162949 | Independent Control of Branch FETs for RF Performance Improvement - A FET-based RF switch architecture and method that provides for independent control of FETs within component branches of a switching circuit. With independent control of branch FETs, every RF FET in an inactive branch that is in an “open” (capacitive) state can be shunted to RF ground and thus mitigate impedance mismatch effects. Providing a sufficiently low impedance to RF ground diminishes such negative effects and reduces the sensitivity of the switch circuit to non-matched impedances. | 2015-06-11 |
20150162950 | METHOD AND DECODER FOR DESPREADING DATA SIGNALS SPREAD USING WALSH SEQUENCES - According to the invention, a data stream with continuous, periodic transmitted, spread data signals of N chips each is split into two data streams of N chips each, which are shifted by N chips; for each of these data streams the correlation functions are calculated within every chip clock time and, in relation to their maxima, evaluated in order to separate user signals from extraneous signals and disturbing signals. | 2015-06-11 |