24th week of 2020 patent applcation highlights part 77 |
Patent application number | Title | Published |
20200186079 | PHOTOVOLTAIC ELEMENT AND MOUNTED SURFACE COMPRISING SUCH PHOTOVOLTAIC ELEMENTS - A photovoltaic element is provided that comprises a photovoltaic converter panel and at least one mounting arrangement. The photovoltaic converter panel defines a front surface adapted to receive solar impinging light and defines a back surface opposing the front surface. The at least one mounting arrangement is mounted to the back surface of the photovoltaic converter panel by a glue. Furthermore, a mounted surface is provided that comprises at least two such photovoltaic elements. | 2020-06-11 |
20200186080 | Robot for Cleaning Photovoltaic Panel and Method for Controlling the Same - A robot for cleaning a photovoltaic panel and a method for controlling the robot. The robot is driven by a motor to travel along a left boarder and a right boarder of the photovoltaic panel, and the robot is provided with a first control unit and a distance sensor. The distance sensor is installed on a sidewall of the robot, faces a sidewall of the photovoltaic panel, and is configured to measure a distance between the distance sensor and the sidewall of the photovoltaic panel. The sidewalls are left sidewalls or right sidewalls. The first control unit is configured to determine that a measurement for the distance that is fed back by the distance sensor exceeds a first preset range, and determine that the robot deviates. Thereby, it is detected in real time whether the robot deviates, facilitating timely correcting deviation. | 2020-06-11 |
20200186081 | VERTICAL SOLAR APPARATUS - Disclosed is a vertical solar apparatus, comprising a vertical light guide device ( | 2020-06-11 |
20200186082 | JUNCTION BOX FOR A PHOTOVOLTAIC MODULE - A junction box for an electrical connection of a photovoltaic module, comprising a plug-in module and a housing module. The plug-in module comprises a plug element and a connection element, wherein the plug element enables a plug-in connection with an external electrical connection line, and the connection element provides a connection option for an internal electrical supply line into the photovoltaic module. The housing module can be connected to, and detached from, the plug-in module and can also be attached to the photovoltaic module in order to offer protection of a connection area of the photovoltaic module against outer influences. | 2020-06-11 |
20200186083 | METHOD AND DEVICE FOR DETECTING A MAXIMUM SYSTEM POWER OUTPUT OF A PHOTOVOLTAIC SYSTEM - A method for determining a system power, which is maximally possible at a point in time, of a photovoltaic system, comprising a plurality of photovoltaic generators, wherein the photovoltaic system is not operated at the maximally possible system power at the point in time, and wherein at least some of the photovoltaic generators of the plurality of photovoltaic generators are operated at different operating points at the point in time, is disclosed. The method and associated apparatus includes defining a mapping between the different operating points of the individual photovoltaic generators and virtual operating points of a standard generator, determining virtual operating points of a standard generator corresponding to the different operating points of the individual photovoltaic generators based on the mapping, determining a characteristic curve of the standard generator from the virtual operating points of the standard generator, determining a maximum of the characteristic curve, and determining the maximally possible system power at the point in time from the maximum of the characteristic curve of the standard generator. | 2020-06-11 |
20200186084 | OVENIZED MEMS - One or more heating elements are provided to heat a MEMS component (such as a resonator) to a temperature higher than an ambient temperature range in which the MEMS component is intended to operate—in effect, heating the MEMS component and optionally related circuitry to a steady-state “oven” temperature above that which would occur naturally during component operation and thereby avoiding temperature-dependent performance variance/instability (frequency, voltage, propagation delay, etc.). In a number of embodiments, an IC package is implemented with distinct temperature-isolated and temperature-interfaced regions, the former bearing or housing the MEMS component and subject to heating (i.e., to oven temperature) by the one or more heating elements while the latter is provided with (e.g., disposed adjacent) one or more heat dissipation paths to discharge heat generated by transistor circuitry (i.e., expel heat from the integrated circuit package). | 2020-06-11 |
20200186085 | RELAXATION OSCILLATORS WITH DELAY COMPENSATION - Relaxation oscillators with delay compensation are provided herein. In certain embodiments, a relaxation oscillator includes a capacitor, a current source that outputs a charging current, and control circuitry that operates to selectively charge the capacitor with the charging current. The control circuitry includes a primary or main comparator operable to compare a charging voltage of the capacitor to a threshold voltage. The relaxation oscillator further includes delay compensation circuitry coupled to the capacitor and operable to adjust the threshold voltage to provide compensation for a delay of the control circuitry. | 2020-06-11 |
20200186086 | Self-Biased Amplifier for Use with a Low-Power Crystal Oscillator - A self-biased amplifier includes a capacitor, a bias generation circuit and a common source amplifier. The capacitor is used to receive an input voltage and output an alternating component of the input voltage. The bias generation circuit is coupled to the capacitor, and used to generate a first bias voltage according to the alternating component. The common source amplifier is coupled to the bias generation circuit, and used to generate an amplified voltage according to the first bias voltage. | 2020-06-11 |
20200186087 | INJECTION-LOCKED OSCILLATOR WITH VARIABLE IMPEDANCE - Injection-locked oscillator comprising:
| 2020-06-11 |
20200186088 | MIXER MODULE - A mixer module includes a mixer, at least one DC offset circuit, a filter and a controller. The mixer mixes an input signal to generate a first signal. The at least one DC offset circuit generates a second signal based on the first signal. The filter filters out an AC portion of the second signal and generates a third signal according to a DC portion of the second signal. The controller controls the at least one DC offset circuit based on the third signal to reduce a DC portion of the first signal. | 2020-06-11 |
20200186089 | FREQUENCY DETECTOR - A frequency detector is used for detecting a frequency difference of a signal to be tested from a first time point to a second time point. The frequency detector includes: an alternating current coupled capacitor configured to receive the signal to be tested; a rectifying circuit electrically connected to the alternating current coupled capacitor; an analog-to-digital converter electrically connected to the rectifying circuit; a control unit electrically connected to the analog-to-digital converter; and a counter electrically connected to the rectifying circuit and the control unit, wherein the control unit is configured to calculate the frequency difference of the signal to be tested from the first time point to the second time point according to outputs of the analog-to-digital converter and outputs of the counter. | 2020-06-11 |
20200186090 | METHOD FOR ADJUSTING OUTPUT OF AMPLIFIER BY USING SENSING CIRCUIT CONFIGURED TO SENSE POWER SUPPLIED TO AMPLIFIER AND ELECTRONIC DEVICE THEREFOR - An electronic device is provided. The electronic device includes an antenna, an amplification circuit configured to amplify a signal to be transmitted through the antenna, a first sensing circuit configured to sense first information corresponding to a voltage value of power supplied to the amplification circuit, a second sensing circuit configured to sense second information corresponding to a current value of the power, and a protective circuit. The protective circuit may be configured to summate the first information and the second information into a single parameter, to determine whether a summation value corresponding to the single parameter deviates from an operating area determined by characteristics of the amplification circuit, and to adjust an output of the amplification circuit if the summation value deviates from the operating area. | 2020-06-11 |
20200186091 | COMPLEMENTARY CURRENT FIELD-EFFECT TRANSISTOR DEVICES AND AMPLIFIERS - The present invention relates to a novel and inventive compound device structure, enabling a charge-based approach that takes advantage of sub-threshold operation, for designing analog CMOS circuits. In particular, the present invention relates to a solid state device based on a complementary pair of n-type and p-type current field-effect transistors, each of which has two control ports, namely a low impedance port and gate control port, while a conventional solid state device has one control port, namely gate control port. This novel solid state device provides various improvement over the conventional devices. | 2020-06-11 |
20200186092 | High Efficiency Switching Power Amplifier - A power amplifier and method for operating the same is disclosed. The amplifier includes a number of transistors coupled in series between a power node and a ground node. These transistors include a first transistor having a source terminal coupled to the power node, and a second transistor having its source terminal coupled to a ground node. A subset of transistors is also coupled in series between the first and second transistors. During operation in a first mode, the first and second transistors act as switching transistors, switching according to data received thereby. The subset of transistors, during the first mode, act as cascode transistors. During a second mode of operation, the transistors of the subset act as switching transistors, switching in accordance with the received data. | 2020-06-11 |
20200186093 | BIAS CIRCUIT AND AMPLIFIER - A bias circuit includes a bias current circuit varying a resistance value according to a mode voltage determined according to a magnitude of an input radio frequency signal, and generating a bias current that is controlled according to the variation of the resistance value; a bias voltage circuit generating a bias voltage that is adjusted according to a change in a power source voltage and supplying the bias voltage to an amplifying circuit; and a bias transfer circuit supplying the bias current to a base node of the amplifying circuit and blocking an input of the radio frequency signal from the base node. | 2020-06-11 |
20200186094 | POWER AMPLIFIER MODULE - A power amplifier module includes an amplifier transistor and a bias circuit. A first power supply voltage based on a first operation mode or a second power supply voltage based on a second operation mode is supplied to the amplifier transistor. The amplifier transistor receives a first signal and outputs a second signal obtained by amplifying the first signal. The bias circuit supplies a bias current to the amplifier transistor. The bias circuit includes first and second resistors and first and second transistors. The first transistor is connected in series with the first resistor and is turned ON by a first bias control voltage which is supplied when the first operation mode is used. The second transistor is connected in series with the second resistor and is turned ON by a second bias control voltage which is supplied when the second operation mode is used. | 2020-06-11 |
20200186095 | DUAL-DOMAIN POWER DISTRIBUTION SYSTEM IN A MOBILE DEVICE - A mobile device may include a power supply configured to generate a supply voltage, a power converter configured to generate a converted voltage from the supply voltage wherein the converted voltage is significantly different than the supply voltage, and a plurality of power domains. The plurality of power domains may include a first power domain global to the mobile device and comprising a first plurality of electronic components powered from the supply voltage and a second power domain global to the mobile device and comprising a second plurality of electronic components powered from the converted voltage, wherein power requirements of each of the second plurality of electronic components are significantly higher than power requirements of each of the first plurality of electronic components. | 2020-06-11 |
20200186096 | POWER AMPLIFIER WITH INTEGRATED BIAS CIRCUIT HAVING MULTI-POINT INPUT - A power amplifier includes a semiconductor die, and an amplifier and bias circuit integrally formed with the semiconductor die. The die has opposed first and second sides, and a device bisection line extends between the first and second sides. The bias circuit includes a multi-point input terminal with first and second terminals that are electrically connected through a conductive path that extends across the device bisection line, and one or more bias circuit components connected between the multi-point input terminal and the amplifier. The amplifier may include a field effect transistor (FET) with gate and drain terminals, and the bias circuit component(s) are electrically connected between the multi-point input terminal and the gate terminal. In addition or alternatively, the bias circuit component(s) are electrically connected between a multi-point input terminal and the drain terminal. The one or more components may include a resistor-divider circuit. | 2020-06-11 |
20200186097 | INTEGRALLY-FORMED MULTIPLE-PATH POWER AMPLIFIER WITH ON-DIE COMBINING NODE STRUCTURE - A multiple-path amplifier (e.g., a Doherty amplifier) includes a semiconductor die, a radio frequency (RF) signal input terminal, a combining node structure integrally formed with the semiconductor die, and first and second amplifiers (e.g., main and peaking amplifiers) integrally formed with the die. Inputs of the first and second amplifiers are electrically coupled to the RF signal input terminal. A plurality of wirebonds is connected between an output of the first amplifier and the combining node structure. An output of the second amplifier is electrically coupled to the combining node structure (e.g., through a conductive path with a negligible phase delay). A phase delay between the outputs of the first and second amplifiers is substantially equal to 90 degrees. The second amplifier may be divided into two amplifier portions that are physically located on opposite sides of the first amplifier. | 2020-06-11 |
20200186098 | TRANSIMPEDANCE AMPLIFIERS WITH FEEDFORWARD CURRENT - Transimpedance amplifiers with feedforward current are provided herein. In certain embodiments, an amplifier system includes a transimpedance amplifier that amplifies an input current received at an input to generate an output voltage at an output. The amplifier system further includes a controllable current source that is coupled to the output of the transimpedance amplifier, and operable to provide a feedforward current that changes in relation to the input current of the transimpedance amplifier. By providing a feedforward current in this manner, gain and speed performance of the transimpedance amplifier is enhanced. | 2020-06-11 |
20200186099 | RADIO FREQUENCY POWER AMPLIFIER FOR INHIBITING HARMONIC WAVE AND STRAY, CHIP AND COMMUNICATION TERMINAL - Disclosed are a radio frequency power amplifier for inhibiting a harmonic wave and stray, a chip and a communication terminal. The radio frequency power amplifier comprises a power source, an LDO circuit, a harmonic inhibition unit, a stray inhibition unit, an amplifying unit, and a low-pass matching network. On the one hand, by means of the power source being connected to the harmonic inhibition unit, harmonic waves and stray of the power source at a resonant frequency are inhibited. Additionally, by means of the stray inhibition unit reducing the gain of the amplifying unit at a resonant frequency, output of stray is reduced. On the other hand, by means of the low-pass matching network being embedded at an output end of the radio frequency power amplifier, harmonic waves and the stray of a radio frequency signal amplified by the amplifying unit at different frequencies is effectively inhibited. | 2020-06-11 |
20200186100 | CIRCUITS AND METHODS FOR PROVIDING A TRIMMABLE REFERENCE IMPEDANCE - Briefly, embodiments of claimed subject matter relate to determination of a high-impedance state or a low-impedance state of a resistive memory element over a wide range of temperature, such as temperatures approaching −40.0° C. to temperatures approaching +125.0° C. Such determination may be brought about by implementing a circuit which, according to various embodiments described herein, emulates a reference impedance having a negative temperature coefficient. | 2020-06-11 |
20200186101 | AMPLIFICATION CIRCUIT - An amplification circuit includes an input terminal, an output terminal, a capacitor, a bias unit, an amplification unit, and an impedance unit. The input terminal receives a radio frequency signal. The capacitor is coupled to the input terminal and the bias unit. The bias unit includes a transistor for controlling the bias current. The transistor has a first terminal for receiving a system voltage, and a control terminal coupled to the reference voltage terminal. The amplification unit has an input terminal coupled to the capacitor and the bias unit, and an output terminal coupled to the output terminal of the amplification circuit. The impedance unit has a first terminal coupled to the bias unit, and a second terminal coupled to the input terminal of the amplification circuit and the capacitor. The impedance unit adjusts the amplifying linearity of the amplification circuit according to a selection signal. | 2020-06-11 |
20200186102 | DYNAMIC DIFFERENTIAL AMPLIFIER WITH ENHANCED GAIN - A dynamic differential amplifier includes: gain transistors to drive with differential input voltage levels; sample capacitors having first terminals to ramp from an initial voltage level to differential amplified voltage levels of the input voltage levels in response to the driven gain transistors; and adjustment circuits to adjust the amplified voltage levels in the direction of the initial voltage level by an offset voltage level. In some cases, second terminals of the sample capacitors are a common-mode node to maintain a common-mode voltage level midway between the ramping voltage levels of the first terminals. In some cases, the dynamic differential amplifier further includes a comparison circuit to compare the maintained common-mode voltage level to a threshold voltage level, wherein the first terminals of the sample capacitors stop ramping and the adjustment circuits adjust the amplified voltage levels in response to the compared common-mode voltage level reaching the threshold voltage level. | 2020-06-11 |
20200186103 | POLYPHASE DIGITAL SIGNAL PREDISTORTION IN RADIO TRANSMITTER - A method comprises obtaining a transmission signal to be power-amplified in a power amplifier ( | 2020-06-11 |
20200186104 | POWER AMPLIFIER CIRCUIT - A power amplifier circuit includes an amplifier transistor having a base, a collector, a bias circuit, and a first resistance element connected between the base of the amplifier transistor and the bias circuit. The bias circuit includes a voltage generation circuit, a first transistor having a base to which a first direct-current voltage is supplied, and an emitter from which the bias current or voltage is supplied, a second transistor having a base to which a second direct-current voltage is supplied, and an emitter connected to the emitter of the first transistor, a signal supply circuit disposed between the base of the amplifier transistor and the base of the second transistor, and an impedance circuit disposed between the base of the first transistor and the base of the second transistor. | 2020-06-11 |
20200186105 | AMPLIFIER ARRANGEMENT AND SENSOR ARRANGEMENT WITH SUCH AMPLIFIER ARRANGEMENT - An amplifier arrangement comprises a sensor input and a first and a second amplifier. The first amplifier has a first amplifier output and a first input connected to a first reference potential terminal and a second input connected to the sensor input in a direct fashion and to the first amplifier output via a feedback path having a switched integration capacitor that is charged by the feedback path during a first switching phase and discharged during a second switching phase. The second amplifier has a second amplifier output, a first input connected to a second reference potential terminal and a second input. A first feedback capacitor is connected in-between two pairs of feedback switches. A second feedback capacitor is connected between the second amplifier output and the second input of the second amplifier. An impedance element is coupled between the second amplifier output and the sensor input. | 2020-06-11 |
20200186106 | INVERTER STACKING AMPLIFIER - The exemplified disclosure presents a highly power efficient amplifier (e.g., front-end inverter and/or amplifier) that achieves significant current reuse (e.g., 6-time for a 3-stack embodiments) by stacking inverters and splitting the capacitor feedback network. In some embodiments, the exemplified technology facilitates N-time current reuse to substantially reduced power consumption. It is observed that the exemplified disclosure facilitates significant current-reuse operation that significantly boost gain gm while providing low noise performance without increasing power usage. In addition, the exemplified technology is implemented such that current reuse and number of transistor has a generally linear relationship and using fewer transistors as compared to known circuits of similar topology. | 2020-06-11 |
20200186107 | POWER AMPLIFIER INTEGRATED CIRCUIT WITH INTEGRATED SHUNT-L CIRCUIT AT AMPLIFIER OUTPUT - A multiple-path (e.g., Doherty) amplifier includes a semiconductor die, a radio frequency (RF) signal input terminal, a combining node structure integrally formed with the semiconductor die, first and second amplifiers (e.g., main and peaking amplifiers, or vice versa) integrally formed with the semiconductor die, and a shunt circuit electrically connected between an output of the first amplifier and a ground reference node. Inputs of the first and second amplifier are electrically coupled to the RF signal input terminal, and outputs of the first and second amplifier are electrically coupled to the combining node structure. The shunt circuit includes a shunt inductance and a shunt capacitance coupled in series between the output of the first amplifier and the ground reference node, and the shunt capacitance has a first terminal coupled to the shunt inductance, and a second terminal coupled to the ground reference node. | 2020-06-11 |
20200186108 | MULTISTAGE AMPLIFIER - A multistage amplifier includes: N amplifiers (N≥2), a (k+1) | 2020-06-11 |
20200186109 | BIAS SWITCH CIRCUIT FOR COMPENSATING FRONTEND OFFSET OF HIGH ACCURACY MEASUREMENT CIRCUIT - Disclosed is a high accurate measurement circuit, and the feature is using bias switching circuit for compensating front end offset, and the back end offset of amplifier is also cancelled. In the real measurement environment, offset exists in the amplifier of the measurement circuit has, and non-ideal effects also exist in the interface between measurement terminal and the measurement circuit, such as leakage current of chip package pins or mismatch of the circuit. The above non-ideal effects belong to front end offset and cannot be compensated by the prior arts. The disclosed structure uses the bias switch circuit and uses different switching method in the two measurement timings. By subtracting the measurement results for the two measurement timings, the front end offset is compensated, and the back end offset of the amplifier is also cancelled. | 2020-06-11 |
20200186110 | METHODS AND APPARATUS FOR A DUAL MODE OPERATIONAL AMPLIFIER - Various embodiments of the present technology comprise a method and apparatus for a dual mode operational amplifier. According to various embodiments, the operational amplifier functions as both a fully-differential amplifier and a single-ended amplifier. The operational amplifier may comprise additional transistors that function as switches, which can be selectively operated according to a desired mode. | 2020-06-11 |
20200186111 | COMBING POWER AMPLIFERS AT MILIMETER WAVE FREQUENCIES - A system having a set of power amplifiers each having a primary inductive structure configured to provide an output signal. A secondary inductive structure is configured to inductively couple to each of the primary inductive structures. A transmission line is provided with a signal trace and a ground trace. The signal trace of the transmission line is connected to a first end of the secondary inductive structure. A return path from a second end of the secondary inductive structure is coupled via a resonant network to the ground trace of the transmission line, in which the return path is spaced away from the secondary inductive structure to minimize inductive coupling to the primary structures. | 2020-06-11 |
20200186112 | Playback Device Group Volume Control - Embodiments are provided for satellite volume control. An example method includes receiving an input at a playback device to adjust a volume for a plurality of playback devices that are grouped for synchronous playback of audio content, wherein the plurality of playback devices includes the playback device. The method also includes sending a first message over a network from the playback device to a device associated with the plurality of playback devices, the first message including information based on the input, wherein the information is used to adjust the volume of the plurality of playback devices. The method also includes receiving a second message at the playback device over the network, the second message including information for the volume of the playback device, wherein the volume is based on the adjusted volume of the plurality of playback devices. | 2020-06-11 |
20200186113 | VOLUME ADJUSTING METHOD AND MOBILE TERMINAL - The embodiment of the disclosure provides a volume adjusting method and device, a mobile terminal and a storage medium. The method includes: acquiring first audio information corresponding to an audio source when detecting that the audio source of a terminal device is playing; determining a first audio amplitude of the first audio information; determining a second audio amplitude of second audio information when the first audio amplitude meets a preset query condition, wherein the second audio information is played after the first audio information; determining corresponding adjustment information when the second audio amplitude meets a preset adjustment condition; and adjusting a volume of the terminal device according to the adjustment information. The disclosure improves the volume adjustment efficiency and reduces the energy consumption of the terminal device. | 2020-06-11 |
20200186114 | Audio Signal Adjustment Method, Storage Medium, and Terminal - An audio signal adjustment method, a storage medium, and a terminal are provided. The method may include: when it is detected that a pre-set event is triggered, controlling a microphone to acquire an audio signal, the pre-set event comprising a pre-set call event and/or a pre-set voice recording event; analyzing the sound loudness corresponding to the audio signal; dynamically adjusting, according to the analysis result and a pre-set adjustment policy, the sound loudness corresponding to the audio signal; and performing, according to the type of the pre-set event, corresponding output processing on the adjusted audio signal. | 2020-06-11 |
20200186115 | Noise Estimation Using Coherence - The technology described herein can be embodied in a method for estimating a power spectral density of noise, the method including receiving an input signal representing audio captured using a microphone. The input signal includes a first portion that represents acoustic outputs from two or more audio sources, and a second portion that represents a noise component. The method also includes iteratively modifying a frequency domain representation of the input signal, such that the modified frequency domain representation represents a portion of the input signal in which effects due to the first portion are substantially reduced. The method further includes determining, from the modified frequency domain representation, an estimate of a power spectral density of the noise, and generating a control signal configured to adjust one or more gains of an acoustic transducer. The control signal is generated based on the estimate of the power spectral density of the noise. | 2020-06-11 |
20200186116 | METHOD FOR MANUFACTURING PIEZOELECTRIC VIBRATION ELEMENT AND METHOD FOR MANUFACTURING PIEZOELECTRIC VIBRATOR - A method for manufacturing a piezoelectric vibration element that includes preparing a piezoelectric substrate; providing a first electrode layer on a first main surface of the piezoelectric substrate; arranging a mask on a side of the first main surface of the piezoelectric substrate, the mask including a center region and a peripheral region located along a periphery of the center region; and irradiating a radiation beam through the mask toward the first main surface of the piezoelectric substrate such that a larger amount of the radiation beam passes through the peripheral region than the center region of the mask so as to remove a part of the first electrode layer to form a first excitation electrode that decreases in thickness from the center region to the peripheral region of the mask on the first main surface of the piezoelectric substrate. | 2020-06-11 |
20200186117 | PROCESS FOR TRANSFERRING A THIN LAYER TO A SUPPORT SUBSTRATE THAT HAVE DIFFERENT THERMAL EXPANSION COEFFICIENTS - A process for transferring a thin layer consisting of a first material to a support substrate consisting of a second material having a different thermal expansion coefficient, comprises providing a donor substrate composed of an assembly of a thick layer formed of the first material and of a handle substrate having a thermal expansion coefficient similar to that of the support substrate, and the donor substrate having a main face on the side of the thick layer introducing light species into the thick layer to generate a plane of weakness therein and to define the thin layer between the plane of weakness and the main face of the donor substrate; assembling the main face of the donor substrate with a face of the support substrate; and detachment of the thin layer at the plane of weakness, the detachment comprising application of a heat treatment. | 2020-06-11 |
20200186118 | Attenuator De-Qing Loss Improvement and Phase Balance - The de-Qing loss and phase imbalance caused by the inherent capacitance of a switched resistance, such as a MOSFET with a resistor, can be reduced by using a shunting switch across the resistor that is in series with the resistor's switch. The shunting switch shorts across the resistor when the resistor's switch is open and in reference mode, thereby significantly reducing the resistance in series with the inherent capacitance of the open resistor's switch. | 2020-06-11 |
20200186119 | ACOUSTIC WAVE DEVICE, RADIO-FREQUENCY FRONT-END CIRCUIT, AND COMMUNICATION APPARATUS - An acoustic wave device includes a high-acoustic-velocity film, a piezoelectric layer provided directly or indirectly on the high-acoustic-velocity film, an IDT electrode provided on the piezoelectric layer, and a dielectric film provided on the piezoelectric layer to cover the IDT electrode. An acoustic velocity of bulk waves propagating through the high-acoustic-velocity film is higher than an acoustic velocity of acoustic waves propagating through the piezoelectric layer. The dielectric film includes a material including hydrogen atoms. | 2020-06-11 |
20200186120 | LAMB WAVE RESONATOR-BASED TORQUE SENSOR - A torque sensor chip including a semiconductor substrate, an acoustic reflector formed on the semiconductor substrate, and first and second Lamb wave resonators (LWRs). The first LWR is formed on a side of the acoustic reflector opposite the semiconductor substrate. The first LWR is at a first angle with respect to an axis of the IC. The second LWR also is formed on the side of the acoustic reflector opposite the semiconductor substrate. The second LWR is at a second angle, different than the first angle, with respect to the axis of the IC. | 2020-06-11 |
20200186121 | ACOUSTIC WAVE DEVICE AND ACOUSTIC WAVE MODULE INCLUDING THE SAME - An acoustic wave device includes a piezoelectric substrate, functional elements, an outer peripheral support layer, a cover portion, and a protective layer covering the cover portion. A hollow space is defined by the piezoelectric substrate, the outer peripheral support layer, and the cover portion, and the functional elements are disposed in the hollow space. The acoustic wave device further includes an under bump metal layer, a wiring pattern, and a through-electrode that connects these elements. In the protective layer, a through-hole to be filled with a conductor to electrically connect a solder ball and the under bump metal layer is provided. The outer peripheral support layer includes a protruding portion protruding to the hollow space. When the acoustic wave device is seen in plan view, at least a portion of the through-hole overlaps the hollow space, and an end portion of the protruding portion overlaps an inner region of the through-hole. | 2020-06-11 |
20200186122 | ACOUSTIC WAVE DEVICE, METHOD OF FABRICATING THE SAME, FILTER, AND MULTIPLEXER - An acoustic wave device includes: a piezoelectric substrate; and a pair of comb-shaped electrodes located on the piezoelectric substrate, each of the comb-shaped electrodes being formed mainly of a monocrystalline metal film, each of the comb-shaped electrodes including electrode fingers. | 2020-06-11 |
20200186123 | ACOUSTIC WAVE DEVICE, FILTER, AND MULTIPLEXER - An acoustic wave device includes: a piezoelectric substrate; and a pair of comb-shaped electrodes located on the piezoelectric substrate, each of the comb-shaped electrodes including a plurality of electrode fingers, side surfaces facing each other of the electrode fingers having a plurality of protrusion portions and a plurality of recessed portions arranged in an extension direction of the electrode fingers, ends of the protrusion portions and the recessed portions narrowing. | 2020-06-11 |
20200186124 | ACOUSTIC WAVE ELEMENT, FILTER ELEMENT, AND COMMUNICATION APPARATUS - An acoustic wave element | 2020-06-11 |
20200186125 | BULK-ACOUSTIC WAVE RESONATOR - A bulk-acoustic wave resonator includes: a first substrate formed of a first material; an insulating layer or a piezoelectric layer disposed on a first side of the first substrate; and a second substrate formed of a second material and disposed on a second side of the first substrate, wherein the second material has thermal conductivity that is higher than a thermal conductivity of the first material. | 2020-06-11 |
20200186126 | RADIO FREQUENCY MODULE, FRONT END MODULE, AND COMMUNICATION DEVICE - A radio frequency module includes a switch circuit that includes selection terminals, a filter that allows the signal in the first frequency band to pass therethrough, a filter that allows the signal in the second frequency band to pass therethrough, a phase adjustment circuit that is connected to the selection terminal and the filter, and a phase adjustment circuit that is connected to the selection terminal and the filter. The filter includes an acoustic wave resonator that is formed on a substrate that has piezoelectricity. The filter includes an acoustic wave resonator that is formed on a substrate that has piezoelectricity. At least one of circuit elements that are included in the phase adjustment circuit is formed on the substrate. At least one of circuit elements that are included in the phase adjustment circuit is formed on the substrate. | 2020-06-11 |
20200186127 | FILTER DEVICE AND METHOD FOR MANUFACTURING THE SAME - A filter device includes a substrate having piezoelectricity, a first filter including an IDT electrode disposed on the substrate, a terminal electrode disposed on the substrate, a first wiring electrode disposed on the substrate and connecting the first filter and a terminal electrode, and a dielectric film disposed above the substrate to cover the IDT electrode. At least a portion of the first wiring electrode is not covered with the dielectric film. | 2020-06-11 |
20200186128 | ACOUSTIC WAVE DEVICE, RADIO-FREQUENCY FRONT-END CIRCUIT, AND COMMUNICATION APPARATUS - An acoustic wave device includes a high-acoustic-velocity film, a low-acoustic-velocity film provided on the high-acoustic-velocity film, a piezoelectric layer provided on the low-acoustic-velocity film, and an IDT electrode provided on the piezoelectric layer. An acoustic velocity of bulk waves propagating through the high-acoustic-velocity film is higher than an acoustic velocity of acoustic waves propagating through the piezoelectric layer. An acoustic velocity of bulk waves propagating through the low-acoustic-velocity film is lower than an acoustic velocity of bulk waves propagating through the piezoelectric layer. The low-acoustic-velocity film includes a material including hydrogen atoms. | 2020-06-11 |
20200186129 | CAPACITOR CIRCUIT AND CAPACITIVE MULTIPLE FILTER - A capacitor circuit includes a first terminal, a first to a third transistor and a first capacitor. The first transistor includes a first terminal configured to be coupled to a first current source and the first terminal of the capacitor circuit, and a second terminal coupled to a reference voltage terminal. The second transistor includes a first terminal configured to be coupled to a second current source, a second terminal coupled to the reference voltage terminal, and a control terminal coupled to the first terminal of the second transistor and a control terminal of the first transistor. The third transistor includes a first terminal configured to be coupled to a third current source and the first terminal of the first transistor, a second terminal coupled to the reference voltage terminal, and a control terminal coupled to the control terminal of the second transistor. The first capacitor includes a first terminal coupled to the first terminal of the capacitor circuit, and a second terminal coupled to the control terminal of the first transistor. | 2020-06-11 |
20200186130 | METHODS AND APPARATUS TO MEASURE RESONANT SENSORS BASED ON DETECTION OF GROUP DELAY - Methods, apparatus, systems and articles of manufacture are disclosed to measure a resonant sensor based on detection of group delay. An example apparatus includes a modulation manager configured to query the resonant sensor with a modulated signal including a frequency; and a resonance determiner configured to determine a resonance frequency of the resonant sensor based on a group delay associated with the resonant sensor and the frequency. | 2020-06-11 |
20200186131 | LOW-POWER SCAN FLIP-FLOP - Disclosed are scan flip-flops (SFFs) that reduce the dynamic power consumption of a system-on-chip (SOC) that incorporates them. Each SFF includes a master latch and a slave latch, each having a driver, a feed-forward path and a feedback path. Each SFF further includes at least one shared clock-gated power supply transistor, which is controlled by either a clock signal or an inverted clock signal to selectively and simultaneously connect a voltage rail to both the driver from one latch and the feedback path of the other latch. The different SFF embodiments have different numbers of shared clock-gated power supply transistors and various other different features designed for optimal power and/or performance. For example, the different SFF embodiments have different types of slave latch drivers; different types of transistors; and/or different types of master latch drivers (e.g., a single-stage, multiple clock phase-dependent driver or a multi-stage, single clock phase-dependent driver). | 2020-06-11 |
20200186132 | SUPERCONDUCTING CIRCUIT AND METHOD FOR DETECTING A RISING EDGE OF AN INPUT SIGNAL - Superconducting circuits and methods for detecting a rising edge of an input signal are described. An example superconducting circuit includes an input terminal for receiving an input signal comprising both positive pulses and negative pulses. The superconducting circuit further includes a first stage, coupled to the input terminal and a first node, configured to suppress both any backward propagating negative pulses and any forward propagating negative pulses, and allow propagation of any forward propagating positive pulses. The superconducting circuit further includes a second stage, coupled to the first node, configured to store a forward propagating positive pulse and reflect a stored positive pulse back to the first node as a negative pulse such that in response to each rising edge of the input signal a return-to-zero signal comprising both a rising edge and a falling edge is provided as an output at the first node. | 2020-06-11 |
20200186133 | TIME-DELAY CIRCUIT - A circuit for generating a time delay, including a capacitive element for integrating a first current supplied by a first current source, in which the first current source includes a switched-capacitor circuit. | 2020-06-11 |
20200186134 | PVT-INDEPENDENT FIXED DELAY CIRCUIT - A PVT-independent fixed delay circuit includes a circuit structure that has a current generator and a multi-level inverter-based time delay unit. The inverter-based time delay unit has at least two NMOS transistors M | 2020-06-11 |
20200186135 | CALIBRATION OF A DELAY CIRCUIT - A method of calibrating a delay generation circuit and the corresponding circuit. | 2020-06-11 |
20200186136 | Clock adjustment circuit and clock adjustment method - Clock adjustment circuits and clock adjustment methods are provided. The clock adjustment circuit is configured to generate an output clock and includes a phase interpolator, a logic circuit, and an integrator. The phase interpolator is configured to generate by interpolation an intermediate clock according to a first reference clock, a second reference clock, and a control signal. The frequencies of the first reference clock, the second reference clock and the intermediate clock are substantially the same. The logic circuit is coupled to the phase interpolator and configured to generate the output clock according to the intermediate clock and one of the first reference clock and the second reference clock. The integrator is coupled to the phase interpolator and the logic circuit and configured to generate the control signal according to the output clock. The control signal varies with an average based on a duty cycle of the output clock. | 2020-06-11 |
20200186137 | PHASE ERROR CORRECTION FOR CLOCK SIGNALS - A multi-phase clock generator circuit includes a phase reference generator circuit configured to generate a phase reference signal in response to a phase selection signal and a peak ramp signal. A phase error correction circuit is configured to provide an error signal based on a synchronization clock signal and a multi-phase clock signal. The error signal is applied to the phase reference signal to correct for phase errors in the multi-phase clock signal. A comparator is configured to compare a ramp signal and the phase reference signal to produce the multi-phase clock signal. | 2020-06-11 |
20200186138 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR SYSTEM FOR DETECTING VOLTAGE-DROP LEVEL - A semiconductor device includes a voltage adjust circuit suitable for generating an adjusting voltage according to a counting signal; an oscillating circuit operable by an oscillating control signal, and suitable for outputting an operational clock signal whose frequency is controlled by the adjusting voltage; a pumping circuit suitable for generating an internal voltage by pumping a source voltage according to the operational clock signal; and a counting circuit suitable for generating the counting signal by counting the operational clock signal according to the oscillating control signal. | 2020-06-11 |
20200186139 | High-Speed Switch with Accelerated Switching Time - A method and apparatus is disclosed for maintaining a stable power supply to a circuit when activating/deactivating a switch in order to accelerate the switching time of the switch. The gate of a FET is coupled to a switch driver. The switch driver is powered by a positive power supply and a negative power supply. When the switch is to be activated/deactivated, the gate is first coupled to a reference potential (i.e., ground) for a “reset period” to reduce any positive/negative charge that has been accumulated in the FET. At the end of the reset period, the gate is then released from the reference potential and the switch driver drives the gate to the desired voltage level to either activate or deactivate the switch. | 2020-06-11 |
20200186140 | CONTROL CIRCUIT AND POWER CONVERSION DEVICE - The present invention relates to a control circuit controlling a switching device. The control circuit is a control circuit controlling first and second switching devices which are serially connected between first potential and second potential lower than the first potential and operate in a complementary manner. The control circuit includes a first control circuit controlling the first switching device and a second control circuit controlling the second switching device, and performs variable control of a circuit constant of each of the first and second control circuits based on a temperature of one of the first and second switching devices. | 2020-06-11 |
20200186141 | POWER TRANSISTOR DEVICE AND METHOD OF CONTROLLING THE SAME - A power device includes a first transistor circuit configured to operate in response to a first control signal, a control circuit configured to generate a second control signal in response to the first control signal, and a second transistor circuit configured to operate in response to the second control signal. The second transistor circuit has an active area that is larger than an active area of the first transistor circuit. | 2020-06-11 |
20200186142 | METHODS AND APPARATUS TO IMPLEMENT CURRENT LIMIT TEST MODE - Methods, apparatus, systems and articles of manufacture are disclosed. An example apparatus includes a gate controller coupled between an input terminal and an intermediate node, the gate controller including a first transistor coupled between the input terminal and a first node; a second transistor coupled between the first node and the intermediate node; a third transistor coupled between the input terminal and the intermediate node; and a charge pump coupled to the intermediate node; a switching network coupled between the intermediate node and an output terminal, the switching network including a high-side drive (HSD) transistor having a HSD gate terminal coupled to the intermediate node, the HSD transistor coupled between an input voltage and a switch node. | 2020-06-11 |
20200186143 | METHOD FOR ACTUATING AT LEAST ONE SEMICONDUCTOR SWITCH, IN PARTICULAR IN A COMPONENT OF A MOTOR VEHICLE - The invention relates to a method for actuating at least one semiconductor switch, in particular in a component of a motor vehicle. The at least one semiconductor switch can be switched with a control voltage ( | 2020-06-11 |
20200186144 | HIGH-SIDE SWITCH AND LOW-SIDE SWITCH LOSS EQUALIZATION IN A MULTIPHASE SWITCHING CONVERTER - An electrical system includes a motor and a plurality of switch pairs, each switch pair having a high-side switch, a low-side switch, and a switch node coupled to the motor. The electrical system also includes gate driver circuitry coupled to each switch of the plurality of switch pairs. The electrical system also includes a controller coupled to the gate driver circuitry. The controller is configured to direct the gate driver circuitry to provide a first set of gate drive signals together with (i.e., overlapping pulses) a second set of gate drive signals, wherein the first set of gate drive signals is phase-shifted relative to the second set of gate drive signals. | 2020-06-11 |
20200186145 | GATE DRIVING CIRCUIT AND POWER SWITCHING SYSTEM - A gate driving circuit that controls a switching element includes: a startup switch which is provided between a gate voltage source and an output terminal; a termination switch which is provided between the output terminal and an output ground terminal; a startup resistor provided between a gate and a source of the startup switch; and a termination resistor provided between a gate and a source of the termination switch. At least one of the startup resistor or the termination resistor is configured to adjust a resistance value. | 2020-06-11 |
20200186146 | SAMPLING CIRCUIT AND SAMPLING METHOD - Sampling circuits and methods for sampling are provided. In a first operating phase, sampling capacitors are coupled to inputs, and in a second operating phase, to a common-mode signal. | 2020-06-11 |
20200186147 | AC SWITCH, AND UNINTERRUPTIBLE POWER SUPPLY AND VOLTAGE SAG COMPENSATOR INCLUDING AC SWITCH - An AC switch ( | 2020-06-11 |
20200186148 | BIDIRECTIONAL LEVEL TRANSLATOR HAVING NOISE REDUCTION AND IMPROVED DATA RATE - A level translator translates signals between first and second voltage domains. An output buffer thereof includes a plurality of PFETs coupled in parallel between a second domain's output supply voltage and an output signal and a plurality of NFETs coupled in parallel between the output signal and the ground rail. Each gate of the plurality of PFETs is coupled to a respective first resistor; the first resistors are coupled in series and receive a first gate control signal. Each gate of the plurality of NFETs is coupled to a respective second resistor; the second resistors are coupled in series and receive a second gate control signal. A first booster NFET is coupled between the output supply voltage and the output signal and a second booster NFET is coupled between the output signal and the ground rail. The booster NFETs receive control signals that operate in the first voltage domain. | 2020-06-11 |
20200186149 | PROGRAMMABLE LOGIC DEVICE WITH FINE-GRAINED DISAGGREGATION - A programmable device may have logic circuitry formed in a top die and memory and specialized processing blocks formed in a bottom die, where the top die is stacked directly on top of the bottom die in a face-to-face configuration. The logic circuitry may include logic sectors, logic array blocks, logic elements, and other types of logic regions. The memory blocks may include large banks of multiport memory for storing data. The specialized processing blocks may include multipliers, adders, and other arithmetic components. The logic circuitry may access the memory and specialized processing blocks via an address encoded scheme. Configured in this way, the maximum operating frequency of the programmable device can be optimized such that critical paths will no longer need to traverse any unused memory and specialized processing blocks. | 2020-06-11 |
20200186150 | LOGIC DRIVE BASED ON STANDARD COMMODITY FPGA IC CHIPS USING NON-VOLATILE MEMORY CELLS - A field-programmable-gate-array (FPGA) IC chip includes multiple first non-volatile memory cells in the FPGA IC chip, wherein the first non-volatile memory cells are configured to save multiple resulting values for a look-up table (LUT) of a programmable logic block of the FPGA IC chip, wherein the programmable logic block is configured to select, in accordance with its inputs, one from the resulting values into its output; and multiple second non-volatile memory cells in the FPGA IC chip, wherein the second non-volatile memory cells are configured to save multiple programming codes configured to control a switch of the FPGA IC chip. | 2020-06-11 |
20200186151 | LOGIC DRIVE WITH BRAIN-LIKE ELASTICITY AND INTEGRALITY BASED ON STANDARD COMMODITY FPGA IC CHIPS USING NON-VOLATILE MEMORY CELLS - A chip package comprises an interposer; an FPGA IC chip over the interposer, wherein the FPGA IC chip comprises a programmable logic block configured to perform a logic operation on its inputs, wherein the programmable logic block comprises a look-up table configured to be provided with multiple resulting values of the logic operation on multiple combinations of the inputs of the programmable logic block respectively, wherein the programmable logic block is configured to select, in accordance with one of the combinations of its inputs, one from the resulting values into its output, and multiple non-volatile memory cells configured to save the resulting values respectively; multiple first metal bumps between the interposer and the FPGA IC chip; and an underfill between the interposer and the FPGA IC chip, wherein the underfill encloses the first metal bumps. | 2020-06-11 |
20200186152 | PHASE LOCKED LOOP - A phase locked loop includes a phase adjustment circuit configured to detect a phase difference of an input signal and a feedback signal, and generate a pre-phase locked clock signal corresponding to the detected phase difference; and a multiple output synchronization circuit configured to generate a first phase locked clock signal by using the pre-phase locked clock signal, and generate a second phase locked clock signal which is synchronized with the first phase locked clock signal, by delaying the pre-phase locked clock signal by a signal processing time for generating the first phase locked clock signal. | 2020-06-11 |
20200186153 | SIGNAL SOURCE - Conventional signal sources each have a disadvantage that the noise in a control voltage of a VCO increases, thereby deteriorating the phase noise of an output signal of the signal source. | 2020-06-11 |
20200186154 | CLOCK GENERATOR - A clock generator receives first and second clock signals, and input representing a desired frequency ratio. A comparison is made between frequencies of an output clock signal and the first clock signal, and a first error signal represents the difference between the desired frequency ratio and this comparison result. The first error signal is filtered. A comparison is made between frequencies of the output clock signal and the second clock signal, and a second error signal represents the difference between the filtered first error signal and this comparison result. The second error signal is filtered. A numerically controlled oscillator receives the filtered second error signal and generates an output clock signal. As a result, the output clock signal has the jitter characteristics of the first input clock signal over a useful range of jitter frequencies and the frequency accuracy of the second input clock signal. | 2020-06-11 |
20200186155 | FREQUENCY SYNTHESIZER WITH DYNAMICALLY SELECTED LEVEL SHIFTING OF THE OSCILLATING OUTPUT SIGNAL - An oscillator circuit powered by a source voltage generates an oscillating output signal. The oscillating output signal is level shifted and applied to a first input of a multiplexer. A second input of the multiplexer receives the oscillating output signal. The multiplexer selects one of the oscillating output signal and the level shifted oscillating output signal for output as a selected oscillating output signal in response to a select signal. A locked loop circuit generates controls a frequency of the oscillating output signal as a function of the selected oscillating output signal and a reference oscillating signal. The select signal further selects one of a reference voltage and the source voltage of the oscillator circuit as an error amplifier reference voltage for a voltage regulator circuit that generates the first power supply voltage. | 2020-06-11 |
20200186156 | Adaptive Non-linearity Identification and Compensation Using Orthogonal Functions in a Mixed Signal Circuit - A feedback divider in a mixed-signal circuit is modulated by a frequency control word controlling a delta-sigma modulator. An accumulated quantization error from the delta-sigma modulator is compared to a residual error in the circuit by a Least-Mean Square (LMS) correlator for gain calibration to adjust for linear errors. Upper bits of the accumulated quantization error access a lookup table to find two outputs of the compensation function that are interpolated between using lower bits of the accumulated quantization error. The interpolated result is an adjustment subtracted from the loop to compensate for non-linear errors. A set of orthogonal kernels is generated from the accumulated quantization error and calibrated using another LMS correlator and inverse transformed to generate updates to the non-linear compensation function in the lookup table. The kernels can be Walsh Hadamard (WH) and the inverse transformer an inverse WH transformer. | 2020-06-11 |
20200186157 | ANALOG-TO-DIGITAL CONVERTER AND MICROPHONE INCLUDING THE SAME - An analog-to-digital converter (ADC) includes a first operator configured to subtract an analog value from an analog signal; an amplifier configured to amplify an output of the first selector; a filter configured to filter an output of the amplifier; a quantizer configured to generate a digital bit stream from an output of the filter; and a digital-to-analog converter (DAC) configured to output the analog value according to the digital bit stream. | 2020-06-11 |
20200186158 | Method and Circuit for Compensating for the Offset Voltage of Electronic Circuits - The present invention corresponds to a method and a circuit for compensating the offset voltage of electronic circuits, where the circuit implementing the method comprises: a dynamic comparator ( | 2020-06-11 |
20200186159 | AD CONVERTER - There provided an AD converter that includes an analog processing part configured to select one of the measurement target voltages and a plurality of reference voltages for each channel, to output an analog voltage signal; a first selection part configured to select one of a plurality of analog voltage signals; a first AD conversion part configured to perform AD conversion on the analog voltage signal to generate a first original digital signal; a second selection part configured to select one of the plurality of analog voltage signals; a second AD conversion part configured to perform AD conversion on the analog voltage signal to generate a second original digital signal; a digital processing part configured to receive the first original digital signal and the second original digital signal; and a controller configured to control contents selected in the analog processing part, the first selection part, and the second selection part. | 2020-06-11 |
20200186160 | INTEGRATED SELF-TEST MECHANISM FOR AN ANALOG-TO-DIGITAL CONVERTER, A REFERENCE VOLTAGE SOURCE, A LOW DROPOUT REGULATOR, OR A POWER SUPPLY - An integrated self-test mechanism for monitoring an analog-to-digital converter (ADC), a reference voltage (V | 2020-06-11 |
20200186161 | Frequency DAC for Radar - A frequency digital-to-analog converter (FDAC) for generating an analog frequency modulating signal from a digital frequency modulating signal includes a Least Significant Bit (LSB) DAC section and a Most Significant Bit (MSB) DAC section. The LSB DAC section comprises a plurality of LSB DACs and is configured to switch between the LSB DACs for mitigating mismatch. The MSB DAC section comprises a plurality of MSB DAC cells and is configured to switch the MSB DAC cells according to a predefined sequence during a period of the digital frequency modulating signal. | 2020-06-11 |
20200186162 | CLOCK JITTER MEASUREMENT USING SIGNAL-TO-NOISE RATIO DEGRADATION IN A CONTINUOUS TIME DELTA-SIGMA MODULATOR - A continuous time Delta-Sigma (CT-ΔΣ) modulator has an input node configured to receive an input signal and an output node configured to output a digital output signal. The CT-ΔΣ modulator includes a feedback loop with a summation circuit configured to sum the digital output signal with a jitter perturbed test signal to generate a signal supplied to an input of a digital to analog converter circuit. A single tone signal is injected with a jitter error of a clock signal to generate the jitter perturbed test signal. A processing circuit processes the digital output signal to detect a signal to noise ratio of the CT-ΔΣ modulator. The detected signal to noise ratio is indicative of presence of jitter in the clock signal. | 2020-06-11 |
20200186163 | SYSTEM AND METHODS FOR VIRTUALIZING DELTA SIGMA DIGITIZATION - A method for virtually performing delta-sigma digitization is provided. The method is performed on a series of digital samples output from a communication stack of a communication network. The method includes steps of obtaining a delta-sigma digitization sampling frequency for the output series of digital samples, calculating an oversampling ratio for the output series of digital samples, interpolating the output series of digital samples at a rate equivalent to the oversampling ratio, and quantizing the interpolated series of digital samples to plurality of discrete predetermined levels. | 2020-06-11 |
20200186164 | ENTROPY ENCODING AND DECODING SCHEME - Decomposing a value range of the respective syntax elements into a sequence of n partitions with coding the components of z laying within the respective partitions separately with at least one by VLC coding and with at least one by PIPE or entropy coding is used to greatly increase the compression efficiency at a moderate coding overhead since the coding scheme used may be better adapted to the syntax element statistics. Accordingly, syntax elements are decomposed into a respective number n of source symbols s | 2020-06-11 |
20200186165 | HARDWARE FRIENDLY DATA COMPRESSION - Systems, apparatus and methods are provided for compressing data. An exemplary method may comprise interleaving one or more literal length fields with one or more literal fields to an output. The literal fields may contain a first data segment literally copied to the output, and each of the one or more literal length fields may contain a value representing a length of a succeeding literal field. The method may further comprise determining a second data segment being matched to a previously literally copied sequence of data and a match position and writing to the output one or more match length fields and a match position field containing the match position. The literal length fields may contain a total length of the first data segment and the match length fields may contain a total length of the second data segment. | 2020-06-11 |
20200186166 | ENERGY EFFICIENT ADAPTIVE DATA ENCODING METHOD AND CIRCUIT - Various energy efficient data encoding schemes and computing devices are disclosed. In one aspect, a method of transmitting data from a transmitter to a receiver connected by plural wires is provided. The method includes sending from the transmitter on at least one but not all of the wires a first wave form that has first and second signal transitions. The receiver receives the first waveform and measures a first duration between the first and second signal transitions using a locally generated clock signal not received from the transmitter. The first duration is indicative of a first particular data value. | 2020-06-11 |
20200186167 | METHOD FOR DIVIDING CARRYING BLOCK OF LDPC CODE AND APPARATUS THEREFOR - Disclosed are a method for dividing a carrying block of a Low Density Parity Check (LDPC) code and an apparatus therefor. The method for dividing a LDPC code of the present disclosure can obtain a high throughput by using a limited size of shifting network. Moreover, it is possible to prevent degradation in performance due to a minimum size of code block by performing shortening for a large size of code block while minimizing the number of code blocks. Furthermore, in selection of a minimum size of code block, since a minimum size of code block is selected on the basis of shortening for a relatively large size of code block, it is possible to increase the size of the minimum size of code block. | 2020-06-11 |
20200186168 | METHOD AND DEVICE FOR DETERMINING CHECK MATRIX, AND COMPUTER STORAGE MEDIUM - Disclosed in the present application are a method and device for determining a check matrix, as well as a computer storage medium, which are configured to provide a structural solution for a high-throughput low-delay low-density parity check (LDPC) check matrix suitable for a 5G system. A method for determining a check matrix as provided in an embodiment of the present application comprises: determining a base graph of a low-density parity check code LDPC matrix, and according to the base graph of the LDPC matrix, determining a check matrix of the LDPC. | 2020-06-11 |
20200186169 | PERFORMANCE OF A DATA CHANNEL USING POLAR CODES FOR A WIRELESS COMMUNICATION SYSTEM - Various embodiments provide for encoding and decoding data channel information with polar codes where the frozen bits of the information block can be set to a scrambling identifier based on the device ID, cell ID, or some other unique identifier instead of being set to null. The frozen bits can be identified based on the type of polar code being used, and while the non-frozen bits can be coded with the data link data, the frozen bits can be coded with the scrambling identifier. In an example where there are more frozen bits than bits in the scrambling identifier, the most reliable of the frozen bits can be coded with the scrambling identifier. In another example, the frozen bits can be set to the CRC bits, which can then be masked by the scrambling identifier. | 2020-06-11 |
20200186170 | Distributed CRC-Assisted Polar Code Construction - According to some embodiments, a method in a wireless device comprises obtaining a set of information bits for wireless transmission and dividing the set of information bits into one or more subsets of information bits. For each subset, generating extra cyclic redundancy check (CRC) bits using a CRC polynomial capable of generating N CRC bits. The extra CRC bits for each subset comprise less than N CRC bits. The method further comprises: generating a final set of N or less CRC bits for the set of information bits using the CRC polynomial; generating a set of coded bits by encoding the set of information bits for wireless transmission, together with the extra CRC bits and the final set of CRC bits, using a polar encoder; and transmitting the set of coded bits using a wireless transmitter. | 2020-06-11 |
20200186171 | DATA WRITING METHOD, MEMORY CONTROLLING CIRCUIT UNIT AND MEMORY STORAGE DEVICE - A data writing method, a memory controlling circuit unit and a memory storage device are provided. The method includes: obtaining a data; encoding a plurality of sub-data in the data to obtain a plurality of first error checking and correction codes respectively corresponding to the plurality of sub-data; writing the plurality of sub-data and the plurality of first error checking and correction codes into a first physical programming unit; encoding the plurality of sub-data to obtain a second error checking and correction code; and writing the second error checking and correction code into a second physical programming unit. | 2020-06-11 |
20200186172 | Decoding Signals By Guessing Noise - Devices and methods described herein decode a sequence of coded symbols by guessing noise. In various embodiments, noise sequences are ordered, either during system initialization or on a periodic basis. Then, determining a codeword includes iteratively guessing a new noise sequence, removing its effect from received data symbols (e.g. by subtracting or using some other method of operational inversion), and checking whether the resulting data are a codeword using a codebook membership function. This process is deterministic, has bounded complexity, asymptotically achieves channel capacity as in convolutional codes, but has the decoding speed of a block code. In some embodiments, the decoder tests a bounded number of noise sequences, abandoning the search and declaring an erasure after these sequences are exhausted. Abandonment decoding nevertheless approximates maximum likelihood decoding within a tolerable bound and achieves channel capacity when the abandonment threshold is chosen appropriately. | 2020-06-11 |
20200186173 | LTE FREQUENCY BAND SWITCHING DEVICE AND METHOD, AND MOBILE TERMINAL - An LTE frequency band switching device and method, and a mobile terminal are provided. The device includes a power amplification module, a switching module, a duplexer, an antenna switch and an antenna. An output signal is outputted to the switching module after being amplified by the power amplification module; the switching module divides same into a plurality of frequency band signals, and selects a current working frequency band according to a switching instruction; the duplexer controls the transceiving of a working frequency band signal; and when the antenna switch is turned on, the current working frequency band signal is transceived by the antenna. | 2020-06-11 |
20200186174 | WIRELESS RADIO SYSTEM OPTIMIZATION BY PERSISTENT SPECTRUM ANALYSIS - Apparatuses and methods for simultaneously operating as a wireless radio and monitoring the local frequency spectrum. For example, described herein are wireless radio devices that use a secondary receiver to monitor frequencies within the operating band and prevent or avoid interferers, including in particular half-IF interferers. The systems, devices, and methods described herein may adjust the intermediate frequency in a superheterodyne receiver to select an intermediate frequency that minimizes interference. In particular, described herein are apparatuses and methods that use a second receiver which is independent of the first receiver and may be connected to the same receiving antenna to monitor the geographically local frequency spectrum and may detect spurious interferers, allowing the primary receiver to adjust the intermediate frequency and avoid spurious interferes. | 2020-06-11 |
20200186175 | DUAL-MODE FREQUENCY MULTIPLIER - One illustrative dual mode frequency multiplier embodiment includes: a first and a second nonlinear element, a summation node, and a switchable phase shifter. The first and second nonlinear elements are driven by a differential signal to produce a first and a second branch signal each having even and odd harmonics, the even harmonics being in-phase and the odd harmonics being out of phase. The first and second branch signals combine at the summation node to form a combined signal. The switchable phase shifter couples the first nonlinear element to the summation node, providing the first branch signal with a phase shift switchable between 0 and 180° to suppress either the odd or the even harmonics from the combined signal. | 2020-06-11 |
20200186176 | METHOD FOR CHARACTERIZING NONLINEAR DISTORTION OF TRANSMITTER, ASSOCIATED TRANSMITTER AND CHARACTERIZATION CIRCUIT THEREOF - A method for characterizing nonlinear distortion of a transmitter, an associated transmitter and a characterization circuit thereof are provided. The method includes: utilizing a transmitting chain circuit within the transmitter to generate an output signal according to a test signal; utilizing a loop back circuit within the transmitter to generate a loop back signal according to the output signal; calculating a plurality of distorted indices respectively corresponding to a plurality of test samples of the test signal according to a plurality of loop back samples of the loop back signal, wherein the plurality of test samples correspond to the plurality of loop back samples, respectively; dividing the plurality of distortion indices into multiple groups according to power of the plurality of test samples; calculating an average value of distortion indices within each group of the multiple groups; and characterizing the nonlinear distortion of the transmitter according to the average value. | 2020-06-11 |
20200186177 | Receiver Architectures with Parametric Circuits - An RF receiver circuit configuration and design is limited by conditions and frequencies to simultaneously provide steady state low-noise signal amplification, frequency down-conversion, and image signal rejection. The RF receiver circuit may be implemented as one of a CMOS single chip device or as part of an integrated system of CMOS components. | 2020-06-11 |
20200186178 | Method and Apparatus for IIP2 Calibration - Aspects include an apparatus and a method for performing Second Order Input Intercept Point (IIP2) calibration of a Digital-to-Analog (DAC) during a full-duplex mode receive operation. In some aspects, a plurality of correlation values are obtained, indicating an amount of IMD energy of an RF signal, wherein the correlation values are associated with IIP2DAC values of a DAC. In some aspects, the apparatus can calculate a mixer bias value, based on the correlation values, and adjust a bias value of a mixer according to the determined bias value. The apparatus can obtain the correlation values, calculate the bias value, and adjust the bias value of the mixer during the full-duplex mode receive operation. In some aspects, the apparatus can thus improve IIP2 of the mixer and reduce IMD energy in a receive signal, during the receive operation, without the need of standby or factory calibration. | 2020-06-11 |