24th week of 2014 patent applcation highlights part 74 |
Patent application number | Title | Published |
20140164786 | COMMUNICATION BETWEEN KEY MANAGER AND STORAGE SUBSYSTEM KERNEL VIA MANAGEMENT CONSOLE - System, computer program product, and method embodiments for communication between a kernel operational on a storage subsystem and a key manager (KM) through a hardware management console (HMC) to provide encryption support are provided. In one embodiment, an event request is initiated by the kernel to the KM to execute an event flow. Pursuant to a communication request by the kernel to the HMC, a socket of the HMC is opened along a communication path between the KM and the kernel according to an event flow type selected by the KM for the event flow. Data including a data payload is sent by the KM to the kernel, the data payload corresponding to the selected event flow type. | 2014-06-12 |
20140164787 | CONTROL METHOD AND INFORMATION PROCESSING APPARATUS - A control method is executed by an information processing apparatus that includes a first processor; a second processor that executes a program to be protected; first memory that is shared between the first and the second processors; and non-volatile second memory that stores the program to be protected. The control method includes reading the program that is to be protected and stored in the second memory, when the information processing apparatus is started up; encrypting the read program only once after start up of the information processing apparatus; writing the encrypted program into the first memory; and decrypting the encrypted program that is written in the first memory, and causing the second processor to execute the decrypted program. | 2014-06-12 |
20140164788 | Secure Switch Between Modes - A state sensitive device is described, the device including a state register which stores a record of the effective-state of the device, a mask field having a value which varies according to a value of the state register, and a processor which changes the value of the mask field to a new value of the mask field when there is a change in the value of the state register, wherein, the processor performs a state dependent calculation requiring the value of the mask field as an operand in the state dependent calculation which will yield an incorrect result if the value of the mask field does not properly correspond to the value of the state register. Related methods, systems and apparatus are also described. | 2014-06-12 |
20140164789 | AUTHENTICATING MICROCODE PATCHES WITH EXTERNAL ENCRYPTION ENGINE - A single or multicore processor having a separate hardware cryptographic engine (HCE) for microcode patch updates is presented. Microcode in each core is modified to utilize the HCE for patch updates. Various arrangements are presented. Memory for HCE processing can include shared L2 or L3 memory or a separate DRAM configured in the address space of each core or set of cores and the HCE. In some embodiments, the HCE may be located on a circuit card attached to an extension bus, such as a PCIe or LPC bus. | 2014-06-12 |
20140164790 | STORAGE SECURITY USING CRYPTOGRAPHIC SPLITTING - Methods and systems for administrative management of a secure data storage network are disclosed. One system includes a secure storage appliance configured to host a plurality of volumes, each volume associated with a plurality of shares stored on a corresponding plurality of physical storage devices and having a plurality of volume management settings, wherein each volume is accessible by a group of one or more users, each user assigned an administrative access level, the volume management settings are editable by a first user from the group of one or more users associated with the volume and assigned an administrative access level sufficient to edit the volume management settings, and the volume management settings are inaccessible by a second user from outside the group of one or more users associated with the volume and assigned an administrative access level at least equal to that of the first user. | 2014-06-12 |
20140164791 | SECURE VIRTUAL MACHINE MEMORY - Apparatus, systems, and methods may operate to restore an operational state of an associated virtual machine (VM) using encrypted information stored in encrypted memory locations. A single hypervisor may be used to encrypt and decrypt the information. Access may be permitted to a designated number of the encrypted memory locations only to a single application executed by the associated VM subject to the hypervisor. Access may be denied to any other application executed by the associated VM, or any other VM. | 2014-06-12 |
20140164792 | Securing Encrypted Virtual Hard Disks - Securing encrypted virtual hard disks may include a variety of processes. In one example, a virtual hard disk is created for a user and encrypted with a volume key, and the volume key placed in an administrator header. The administrator header may be encrypted with a protection key, the protection key created from a user identifier corresponding to the user, a volume identifier corresponding to the virtual hard disk, and two cryptographic secrets. The protection key may then destroyed after encrypting the administrator header and therefore, might never leave the encryption engine. The two cryptographic secrets may be stored in separate storage locations, one accessible to the user and the other accessible to administrators. Accordingly, the protection key might never transmitted or can be intercepted, and no single entity may be compromised to gain access to all of the information needed to recreate the protection key. | 2014-06-12 |
20140164793 | CRYPTOGRAPHIC INFORMATION ASSOCIATION TO MEMORY REGIONS - Embodiments herein relate to cryptographic operations, such as encrypting and/or decrypting information to read from or written to first and second memory regions. The first cryptographic information is related to the first memory region and the second cryptographic information is related to the second memory region. | 2014-06-12 |
20140164794 | SEQUENTIAL POWER UP OF DEVICES IN A COMPUTING CLUSTER BASED ON RELATIVE COMMONALITY - A computer program product includes computer usable program code for: identifying a plurality of power distribution units (PDUs) disposed in a rack, wherein each PDU receives power from a main power source and includes a circuit breaker; identifying a plurality of devices disposed in the rack, wherein each device receives power from one of the PDUs, and wherein the plurality of devices are selected from server nodes, network switches and external data storage devices; obtaining vital product data from a service processor in each device, wherein the vital product data identifies the device by a model identification code; and powering on, for each of the PDUs, the plurality of devices that are connected to the PDU in a sequence to prevent an inrush current from tripping the circuit breaker within the PDU, wherein the sequence powers on devices in order of ascending commonality of the model identification code. | 2014-06-12 |
20140164795 | BRIDGE CIRCUIT FOR ETHERNET POWERED DEVICE - A network powered device includes field effect transistors connected as bridge circuit. The bridge circuit includes control circuitry to enable the FETs based on completion of a powered device detection sequence performed by power sourcing equipment coupled to the device via an Ethernet link. | 2014-06-12 |
20140164796 | SYSTEMS AND METHODS FOR PROVIDING IMPROVED POWER BACKUP FOR DESKTOP COMPUTERS - The present disclosure relates to systems and methods for providing power from a secondary power source upon an interruption of a primary power source. In certain embodiments, the secondary power source may supply power without use of a power inverter that converts direct current into alternating current or a current rectifier that provides a second conversion of alternating current into a direct current. Embodiments in accordance with the present disclosure may also employ a time delay to improve operation of the secondary power source. | 2014-06-12 |
20140164797 | PORTABLE ELECTRICAL DEVICE CHARGING SYSTEM AND METHOD USING THERMAL ENERGY - A portable electrical device charging system and method for using thermal energy, especially for use in the field or as part of military operations, is disclosed. The inventive electrical device charging system has one or more thermal electric generators attached, physically connected to, or incorporated within a container or pouch that is used to heat packaged meals-ready-to-eat (“MRE”). With the generation of heat to cook the MRE, the heat transfer through the container or pouch activates the thermal electric generators which generates electricity, in the form of an electric current, that can be used to charge any electrical device including an electrical storage device. More particularly, the generated electrical current may be used to charge radios, batteries, cell phones, personal data assistant devices, tablets, cameras, flashlights, or any other similar device. | 2014-06-12 |
20140164798 | METHOD AND APPARATUS FOR CONTROLLING POWER-OFF OF TERMINAL - A method and an apparatus for controlling power-off of a terminal are disclosed in embodiments of the present invention, where the method includes: acquiring usage state information of the terminal after the terminal is powered on; and controlling the terminal to power off if it is determined, according to the usage state information, that the terminal is abnormally powered on. | 2014-06-12 |
20140164799 | OPTIMIZING POWER USAGE BY FACTORING PROCESSOR ARCHITECTURAL EVENTS TO PMU - A method and apparatus to monitor architecture events is disclosed. The architecture events are linked together via a push bus mechanism with each architectural event having a designated time slot. There is at least one branch of the push bus in each core. Each branch of the push bus may monitor one core with all the architectural events. All the data collected from the events by the push bus is then sent to a power control unit. | 2014-06-12 |
20140164800 | ELECTRONIC DEVICE WITH OPERATING FREQUENCY ADJUTING FUNCTION AND METHOD FOR ADJUSTING OPERATING FREQUENCY - The present invention provides an electronic device with operating frequency adjusting function. The electronic device detects the inner temperature value T0 of the electronic device and the power consumption W0 of an electronic component of the electronic device. The electronic device determines whether a trigger condition is met according to the detected inner temperature value T0 and the detected power consumption W0 of the electronic component, determines the adjusting schedule corresponding to the trigger condition determined to be met, and adjusts the operating frequency of the electronic component according to the determined adjusting schedule. | 2014-06-12 |
20140164801 | SWITCHED-MODE POWER SUPPLY UNIT, METHOD OF OPERATION AND USE OF A SWITCHED-MODE POWER SUPPLY UNIT IN A COMPUTER - A switched-mode power supply unit for a computer includes at least one switching element that switches a charging current to charge a storage element, at least one secondary output circuit that provides an output voltage (Vout+), at least one controllable oscillator circuit that provides a switching clock, and at least one control circuit that determines a switch-off time for the at least one switching element, wherein, in operation of the switched-mode power supply unit, a mean oscillator clock of the oscillator circuit is controlled in dependence on a controlled variable (Vcontrol) specifying the output voltage or power of the secondary output circuit such that the mean oscillator clock rises monotonously with the output power and a switch-on time for the at least one switching element is determined in dependence on the mean oscillator clock and a random deviation. | 2014-06-12 |
20140164802 | Frequency And Voltage Scaling Architecture - A method and apparatus for scaling frequency and operating voltage of at least one clock domain of a microprocessor. More particularly, embodiments of the invention relate to techniques to divide a microprocessor into clock domains and control the frequency and operating voltage of each clock domain independently of the others. | 2014-06-12 |
20140164803 | Power Management Integrated Circuit Having A Configurable Total Hibernate Mode - A Multi-Tile Power Management Integrated Circuit (MTPMIC) includes tiles including an MCU/ADC tile and a power manager tile. The power manager tile includes a hibernate circuit and a set of Configurable Switching Power Supply Pulse Width Modulator (CSPSPWM) components. The CSPSPWM, in combination with other circuitry external to the integrated circuit, form a switching power supply. The hibernate circuit is operable in a hibernate mode where the CSPSPWM is disabled and the switching power supply no longer generates a supply voltage. A processor in the MCU/ADC tile writes across a standardized bus to configure the hibernate circuit to wake up after a timer determines a configurable amount of time has lapsed, or to wake up in response to a signal present on a terminal of MTPMIC. The processor enables the hibernate mode causing the switching power supply to no longer provide power to the processor and other circuitry of MTPMIC. | 2014-06-12 |
20140164804 | SYSTEM AND METHODS FOR DIMM-TARGETED POWER SAVING FOR HYPERVISOR SYSTEMS - A method of saving power in a computing system having a plurality of dual in-line memory modules (DIMMs) and employing a suspend-to-RAM sleep mode includes, when entering suspend-to-RAM sleep mode, consolidating selected information into a subset of DIMMs, and turning off power to all other DIMMs. A DIMM power rail may be coupled to each of the DIMMs, the DIMM power rail being configured to selectively have power being supplied to respective DIMMs turned off in response to enable/disable logic signals. | 2014-06-12 |
20140164805 | DATA PROCESSING APPARATUS, METHOD FOR CONTROLLING DATA PROCESSING APPARATUS, AND PROGRAM - A data processing apparatus operating in a first power mode and a second power mode in which power consumption is lower than that of the first power mode includes a plurality of USB interfaces, a selection unit configured to select at least one of the USB interfaces which is to be used when the second power mode is entered, and a control unit configured to perform control so that, in the second power mode, electric power is supplied to a device connected to the at least one of the USB interfaces selected by the selection unit through the at least one of the USB interfaces. | 2014-06-12 |
20140164806 | INTEGRATED CIRCUIT DEVICE INCLUDING A PLURALITY OF INTEGRATED CIRCUITS AND ITS APPLICATION TO PANEL DISPLAY DEVICE - An integrated circuit device includes first and second integrated circuits and a power supply line. The first integrated circuit includes a first power supply circuit, a timing generation circuit generating a synchronization signal, and a first power supply control section. The second integrated circuit includes a second power supply circuit and a second power supply control section. The power supply line electrically connects the outputs of the first and second power supply circuit. The first and second power supply control sections are each configured to start the operations of the first and second power supply circuits, respectively, in response to a start of a supply of the synchronization signal after a sleep-out command is supplied thereto. The timing generation circuit starts supplying the synchronization signal after a predetermined waiting time elapses after the sleep-out command is supplied to the first integrated circuit. | 2014-06-12 |
20140164807 | INFORMATION PROCESSING APPARATUS, CONTROL METHOD OF INFORMATION PROCESSING APPARATUS, AND STORAGE MEDIUM - Whether to enable a packet discarding mode is designated and, if an information processing apparatus operates in a power saving mode and the packet discarding mode is enabled, the information processing apparatus determines processing for a received packet based on a proxy response pattern, a WOL pattern, and a discard pattern, and, if the information processing apparatus operates in the power saving mode and the packet discarding mode is disabled, the information processing apparatus determines processing for the received packet based on the proxy response pattern and the WOL pattern without using the discard pattern. | 2014-06-12 |
20140164808 | METHOD AND APPARATUS FOR PREVENTING OVERHEATING OF A COMPUTER - A computer implemented method and apparatus for preventing overheating of a computer comprising sensing a disengagement action for the computer, detecting a power setting associated with the disengagement action, and performing, when the power setting is detected to be set to a preset mode, at least one of alerting the user regarding the power setting and forcing the computer into a low power state. | 2014-06-12 |
20140164809 | METHODS AND DEVICES FOR REGULATING POWER IN WIRELESS RECEIVER CIRCUITS - Access terminals are adapted to regulate power in wireless receiver circuits. In one example, access terminals include a communications interface with at least one wireless receiver circuit. A processing circuit coupled with the communications interface can determine that data is not expected to be received by the access terminal for a period of time while operating in a connected mode. One or more components of the wireless receiver circuit, including a low noise amplifier (LNA) of the wireless receiver circuit, can subsequently be powered down (e.g., set to a passive state) in response to such a determination. Other aspects, embodiments, and features are also claimed and described. | 2014-06-12 |
20140164810 | SYSTEM AND METHODS FOR DIMM-TARGETED POWER SAVING FOR HYPERVISOR SYSTEMS - A method of saving power in a computing system having a plurality of dial in-line memory modules (DIMMs) and employing a suspend-to-RAM sleep mode includes, when entering suspend-to-RAM sleep mode, consolidating selected information into a subset of DIMMs, and turning off power to all other DIMMs. A DIMM power rail may be coupled to each of the DIMMs, the DIMM power rail being configured to selectively have power being supplied to respective DIMMs turned off in response to enable/disable logic signals. | 2014-06-12 |
20140164811 | SEQUENTIAL POWER UP OF DEVICES IN A COMPUTING CLUSTER BASED ON DEVICE FUNCTION - A computer program product includes computer usable program code embodied on a tangible computer usable storage medium for: identifying a plurality of power distribution units (PDUs) disposed in a rack, wherein each PDU receives power from a main power source, and wherein each PDU includes a circuit breaker; identifying a plurality of devices disposed in the rack, wherein each device receives power from one of the PDUs, and wherein the plurality of devices are selected from server nodes, network switches and external data storage devices; and powering on, for each of the PDU, the plurality of devices that are connected to the PDU in a sequence to prevent an inrush current from tripping the circuit breaker within the PDU, wherein the sequence powers on the devices identified as network switches and external data storage devices prior to powering on the devices identified as server nodes. | 2014-06-12 |
20140164812 | SEQUENTIAL POWER UP OF DEVICES IN A COMPUTING CLUSTER BASED ON DEVICE FUNCTION - A method of powering on a plurality of devices includes identifying a plurality of power distribution units disposed in a rack, wherein each power distribution units is connected to receive power from a main power source, and wherein each power distribution unit includes a circuit breaker. The method further includes identifying a plurality of devices disposed in the rack, wherein each device is connected to receive power from one of the power distribution units, and wherein the plurality of devices are selected from server nodes, network switches and external data storage devices. For each of the power distribution units, the plurality of devices that are connected to the power distribution unit are powered on in a sequence to prevent an inrush current from tripping the circuit breaker within the power distribution unit. The sequence powers on the devices identified as network switches and external data storage devices prior to powering on the devices identified as server nodes. | 2014-06-12 |
20140164813 | SEQUENTIAL POWER UP OF DEVICES IN A COMPUTING CLUSTER BASED ON RELATIVE COMMONALITY - A method of powering on a plurality of devices includes identifying a plurality of power distribution units (PDUs) disposed in a rack, wherein each PDU receives power from a main power source and includes a circuit breaker. A plurality of devices disposed in the rack are identified, wherein each device receives power from one of the PDUs, and wherein the plurality of devices are server nodes, network switches or external data storage devices. Vital product data (VPD) is obtained from a service processor in each device, wherein the VPD identifies the device by a model identification code. For each PDU, the plurality of devices connected to the PDU are powered on in a sequence to prevent an inrush current from tripping the circuit breaker within the PDU, wherein the sequence powers on devices in order of ascending commonality of the model identification code. | 2014-06-12 |
20140164814 | IDENTIFICATION OF POWER SOURCE ELECTRICAL CONNECTIVITY - A computer determines a characteristic corresponding to each of a first power source and a second power source. The first and second power sources are connected to one or more power distribution units and are configured to provide power in a datacenter. The characteristic includes at least one of a current, a resistance, a voltage, a frequency, a phase, and a magnetic field. The computer generates a comparison of the characteristic corresponding to the first power source and the second power source, to a threshold value of the characteristic. The computer determines if the comparison violates the threshold value of the characteristic. In response to determining the comparison does not violate the threshold value of the characteristic, the computer determines that the first power source and the second power source are connected to a given power distribution unit included in the one or more power distribution units. | 2014-06-12 |
20140164815 | SERVER ANALYZING SYSTEM - A system analyzing system includes a field programmable gate array, a complex programmable logic device electrically connected to the field programmable gate array, a micro control unit electrically connected to the field programmable gate array and a display module electrically connected to micro control unit. The complex programmable logic device and the micro control unit control the field programmable gate array to be powered on/powered off and the field programmable gate array saves the sequence of times when the field programmable gate array is powered on/powered off and displaying the time sequence on the display module, and the micro control unit is capable of receiving a command and sending the command to the field programmable gate array to execute from the display module. | 2014-06-12 |
20140164816 | DISTRIBUTED MANAGEMENT OF A SHARED CLOCK SOURCE TO A MULTI-CORE MICROPROCESSOR - Microprocessors are provided with decentralized logic and associated methods for indicating power related operating states, such as desired voltages and frequency ratios, to shared microprocessor power resources such as a voltage regulator module (VRM) and phase locked loops (PLLs). Each core is configured to generate a value to indicate a desired operating state of the core. Each core is also configured to receive a corresponding value from each other core sharing the applicable resource, and to calculate a composite value compatible with the minimal needs of each core sharing the applicable resource. Each core is further configured to conditionally drive the composite value off core to the applicable resource based on whether the core is designated as a master core for purposes of controlling or coordinating the applicable resource. The composite value is supplied to the applicable shared resource without using any active logic outside the plurality of cores. | 2014-06-12 |
20140164817 | DISASTER RECOVER INTERNET PROTOCOL ADDRESS FAILOVER - An approach is provided for internet protocol (IP) address failover. An application on a primary site is assigned a private IP address. This private IP address is accessible within a local network. This private IP address is mapped to a public IP address, which is accessible to users outside the local network. The application is then replicated to a backup site with the same private IP address used to access it on the primary site. In case of a disaster recover event on the primary site, the replicated application can be accessed on the backup site by way of the public IP address. | 2014-06-12 |
20140164818 | Automatic Failover of Nodes of a Middle-Tier Layer - Method and system are provided for automatic failover between multiple nodes in a middle-tier layer between client applications and a back-end service. The method at a first node includes: receiving a request from a client application; determining that the first node cannot service the request successfully; forwarding the request from the first node to a second peer node; receiving a response at the first node on completion of the request by the second peer node; and forwarding the response from the first node to the client application. An original path of communication between the client application and the first node is maintained. The failover of the request from the first node to the second peer node is transparent to the client application. Nodes may be registered in a group, wherein a node in a group has awareness of other nodes in the group. | 2014-06-12 |
20140164819 | MEMORY OPERATION OF PAIRED MEMORY DEVICES - A method and apparatus for operation of a memory module for storage of a data word is provided. The apparatus includes a memory module having a set of paired memory devices including a first memory device to store a first section of a data word and a second memory device to store a second section of the data word when used in failure free operation. The apparatus may further include a first logic module to perform a write operation by writing the first and second sections of the data word to both the first memory device and the second memory device upon the determination of certain types of failure. The determination may include that a failure exists in the word section storage of either the first or second memory devices but that no failures exist in equivalent locations of word section storage in the two memory devices. | 2014-06-12 |
20140164820 | MANAGING ERRORS IN A DRAM BY WEAK CELL ENCODING - This disclosure includes a method for preventing errors in a DRAM (dynamic random access memory) due to weak cells that includes determining the location of a weak cell in a DRAM row, receiving data to write to the DRAM, and encoding the data into a bit vector to be written to memory. For each weak cell location, the corresponding bit from the bit vector is equal to the reliable logic state of the weak cell and the bit vector is longer than the data. | 2014-06-12 |
20140164821 | Techniques For Encoding and Decoding Using a Combinatorial Number System - A data storage system includes a memory circuit having memory cells and a control circuit. The control circuit is operable to receive data bits provided for storage in the memory cells. A subset of the memory cells have predetermined stuck-at faults. The control circuit is operable to compute a binomial coefficient for each of the predetermined stuck-at faults based on a bit position of a corresponding one of the predetermined stuck-at faults within the memory cells. The control circuit is operable to add together the binomial coefficients to generate an encoded number using a combinatorial number system. The control circuit is operable to generate a first set of redundant bits that indicate the encoded number. The first set of redundant bits are used to decode bits read from the memory cells to regenerate the data bits. | 2014-06-12 |
20140164822 | HOST COMPUTER AND METHOD FOR MANAGING SAS EXPANDERS OF SAS EXPANDER STORAGE SYSTEM - In a method for managing serial attached small computer system interface (SAS) expanders using a host computer, the host computer connects to an SAS expander storage system through a redundant array of independent disks (RAID) card. The SAS expander storage system includes a first switch device, a first SAS expander, a second SAS expander, a second switch, a flash memory, and hard disk drives. The method controls the first switch device to switch the RAID card from the first SAS expander to the second SAS expander when the first SAS expander fails to function, controls the second switch device to switch the flash memory from the first SAS expander to the second SAS expander, and controls the first switch device to connect each of the hard disk drives to the second SAS expander. | 2014-06-12 |
20140164823 | Memory Disturbance Recovery Mechanism - Components of a memory system, such as a memory controller and memory device, which detect accumulated memory read disturbances and correct such disturbances before they reach a level that causes errors. The memory device includes a memory array and a disturbance control circuit. The memory array includes a plurality of memory rows. Each memory row is associated with a disturbance warning circuit having a state that corresponds to an accumulated disturbance in the memory row. The disturbance control circuit determines, responsive to an activation of a memory row of the plurality of memory rows specified by a row access command, whether the disturbance condition is present in the memory row based on the state of the disturbance warning circuit associated with the memory row. If a disturbance condition is present, the disturbance control circuit causes a recovery operation to be performed on the memory row to reduce the accumulated disturbances. | 2014-06-12 |
20140164824 | ERROR DETECTION/CORRECTION BASED MEMORY MANAGEMENT - The present disclosure includes methods, devices, and systems for error detection/correction based memory management. One embodiment includes performing a read operation with respect to a particular group of memory cells of a memory device and, if the read operation results in an uncorrectable error, determining whether to retire the particular group of memory cells in response to a status of an indicator corresponding to the particular group of memory cells, wherein the status of the indicator indicates whether the particular group of memory cells has a previous uncorrectable error associated therewith. | 2014-06-12 |
20140164825 | IDENTIFYING LOST WRITE ERRORS IN A RAID ARRAY - A data access request is received specifying a data block stored in a stripe of a parity group that includes a plurality of data storage devices to store data blocks and a parity storage device to store parity information for the data. The stripe includes a data block from each of the plurality of data storage devices and the stripe includes a parity block from the parity storage device. An error is detected in the data block specified by the data access request. The error is identified as a lost write error for the data block or a lost write error for the parity block. Identifying the error includes comparing a first storage device signature stored in a metadata field associated with the data block to a second storage device signature stored in a label block identifying a data storage device where the data block is stored. | 2014-06-12 |
20140164826 | In-Vehicle Electronic Control Device - An in-vehicle electronic control device for diagnosing the details of an abnormality of a microcomputer appropriately is provided. A monitoring function for detecting a malfunction by monitoring input/output of a main function of a hardware part and a monitoring function for detecting an abnormality by monitoring the calculating result of a main function in a software part are provided in a microcomputer. The main function to be monitored is implemented with a different structure than the malfunction/abnormality monitoring function. Furthermore, a malfunction processing circuit for monitoring an abnormality of the microcomputer is provided outside the microcomputer. | 2014-06-12 |
20140164827 | METHOD AND DEVICE FOR MANAGING HARDWARE ERRORS IN A MULTI-CORE ENVIRONMENT - A method and device for managing hardware errors in a multi-core environment includes allocating processor cores to a main set and a spare set of processor cores. The main set of processor cores are used by an operating system, and the spare set of processor cores are dedicated to software applications. Should a processor core error occur, a processor core swap may be performed to swap a spare processor core for a failing main processor core without interrupting the execution of the operating system. | 2014-06-12 |
20140164828 | CONSISTENCY OF DATA IN PERSISTENT MEMORY - Consistency of data stored in persistent memory is maintained using separate commit and harden operations for a transaction. A transaction is committed with a processing device, the committing including marking an end of an atomic operation on a modified object from the transaction, creating a new copy of the modified object, and storing a mapping of the modified object to the new copy of the modified object in a recorded log. A checksum identifying the modified object is created and stored in the recorded log. The transaction is hardened by storing the modified object and the recorded log from cache into persistent memory. | 2014-06-12 |
20140164829 | RECOVERY FOR LONG RUNNING MULTITHREADED PROCESSES - In response to receiving a checkpoint request from a first task for a process executing in parallel with at least a second task for the process, checkpoint data from the first task is stored to establish a restart point for the first task, wherein the checkpoint data records a current state of the first task, and the checkpoint data from the first task is merged with previously received checkpoint data for the at least second task to create a checkpoint file. In response to restarting the process, the first task and the at least second task are restarted using the checkpoint data in the checkpoint file. | 2014-06-12 |
20140164830 | USING A VIRTUAL BOOT DEVICE TO ACCESS A SYSTEM RECOVERY IMAGE - A technique that includes presenting a virtual cartridge including a system recovery image to a computer system. The technique includes using a virtual boot device to access the system recovery image. | 2014-06-12 |
20140164831 | METHOD AND APPARATUS FOR MAINTAINING REPLICA SETS - Provided are systems and methods for managing asynchronous replication in a distributed database environment, wherein a cluster of nodes are assigned roles for processing database requests. In one embodiment, the system provides a node with a primary role to process write operations against its database, generate an operation log reflecting the processed operations, and permit asynchronous replication of the operations to at least one secondary node. In another embodiment, the primary node is the only node configured to accept write operations. Both primary and secondary nodes can process read operations. Although in some to settings read requests can be restricted to secondary nodes or the primary node. In one embodiment, the systems and methods provide for automatic failover of the primary node role, can include a consensus election protocol for identifying the next primary node. Further, the systems and methods can be configured to automatically reintegrate a failed primary node. | 2014-06-12 |
20140164832 | TEST CIRCUIT AND METHOD FOR PROCESSING A TEST ROUTINE - According to one embodiment, a test circuit is provided comprising a tester configured to perform a test routine comprising a plurality of test commands for testing an electronic circuit, wherein the tester comprises a checker configured to, if a test command of the plurality of test commands is to be performed, check, whether there is currently a state in which performing the test command could lead to a damage of the electronic circuit and configured to, in case it determines that there is currently a state in which performing the test routine could lead to a damage of the electronic circuit, output a signal indicating that performing the test routine could lead to a damage of the electronic circuit. | 2014-06-12 |
20140164833 | BUILT-IN SELF-TEST FOR STACKED MEMORY ARCHITECTURE - A built-in self-test for stacked memory architecture. An embodiment of a memory device includes a memory stack including one or more DRAM (dynamic random access memory) elements; and a system element for control of the memory stack. The system element includes a built-in self-test (BIST) engine to generate a write test event or a read test event for the memory stack, a test interface to receive test data for write test event or the read test events from the BIST engine, and a memory controller, the memory control to receive at least a portion of the test data from the test interface and to implement the write test event or read test event at the DRAM elements of the memory stack. | 2014-06-12 |
20140164834 | APPARATUS AND A METHOD FOR MEMORY TESTING BY A PROGRAMMABLE CIRCUIT IN A SAFETY CRITICAL SYSTEM - The invention relates to a method and apparatus. In the method, a programmable random access memory testing circuit detects a signal to initiate testing of at least one random access memory circuit, the testing circuit being connected to a bus to which a processor and the at least one memory circuit is connected, the at least one memory circuit comprising at least a first memory block. The testing circuit determines that the bus is not reserved and reserves the bus. The testing circuit reads application data in a first memory block to a temporary memory of the testing circuit. The testing circuit executes marching test for the first memory block in a memory circuit. The testing circuit returns the application data back to the first memory block in the memory circuit. The testing circuit releases the bus. | 2014-06-12 |
20140164835 | SYSTEMS AND METHODS FOR ERROR SIMULATION AND CODE TESTING - A method for error simulation in a data storage subsystem providing abstractions of one or more storage devices. The method includes dividing the data storage subsystem into two or more hierarchically organized subsystems, wherein the subsystems interact using IO Request Packets (IORPs), such that relatively higher level subsystems create and populate IORPs and pass them to relatively lower level subsystems for corresponding processing. The method further includes defining an IORP modifier configured to attach to matching IORPs based on one or more attributes of the IORP modifier and to modify at least one of the processing and one or more attributes of the IORP in order to simulate errors in the data storage subsystem. | 2014-06-12 |
20140164836 | TECHNIQUES FOR TEST AUTOMATION IN EMERGENT SYSTEMS - Certain example embodiments described herein relate to techniques for test automations in emergent systems. More particularly, certain example embodiments provide a mechanism for dynamic recognition of combinations of services/components, monitoring of their real-time usage, and automatic generation and running of tests for the combinations at appropriate times (e.g. when part of a combination is updated). The tests for individual (and, if available, combinations of) services are associated with the services using a registry. A taxonomy or ontology can be used to denote the semantics of the services, providing an array of options for assessing how and when to run tests and actions. It also is possible to detect similar combinations of services automatically. It therefore becomes possible to automate the detection and running of tests for a combination of services/components, even in emergent systems where such combinations cannot always be predicted in advance and where services/components are addable/modifiable over time. | 2014-06-12 |
20140164837 | MULTI-CORE PROCESSOR, DEVICE HAVING THE SAME, AND METHOD OF OPERATING THE MULTI-CORE PROCESSOR - A multi-core processor includes a plurality of cores, each core configured to output an scan output pattern in response to an input of an scan input pattern, a multiplexing circuit configured to be responsive to a selection signal to output one of the scan output patterns output by the plurality of cores, and a comparison circuit configured to compare the scan output patterns with one another in units of bits, and to generate a plurality of comparison signals corresponding to comparison results. | 2014-06-12 |
20140164838 | AT-SPEED TEST ACCESS PORT OPERATIONS - This disclosure describes different ways to improve the operation of a device's 1149.1 TAP to where the TAP can perform at-speed Update & Capture, Shift & Capture and Back to Back Capture & Shift operations. In a first embodiment of the disclosure the at-speed operations are achieved by time division multiplexing CMD signals onto the TMS input to the TAP. The CMD signals are input to a CMD circuit that operates in conjunction with a Dual Port Router to execute the at-speed operations of a circuit. In a second embodiment of the disclosure the at-speed operations are achieved by detecting the TAP's Exit1DR state as a CMD signal that is input to the CMD circuit that operates in conjunction with a Dual Port Router to execute the at-speed operations of a circuit. In a third embodiment of the disclosure the at-speed operations are achieved by detecting the TAP's Exit1DR and PauseDR states and in response producing Capture and Update signals that are input to a Programmable Switch that operates in conjunction with a Dual Port Router to execute the at-speed operations of a circuit. In a fourth embodiment of the disclosure the at-speed operations are achieved by detecting the TAP's Exit1DR and PauseDR states and inputting these states to a Dual Port Router to control the at-speed operations of a circuit. Each of the embodiments may be augmented to include externally accessible Update and Capture input signals that can be selected to allow a tester to directly control the at-speed operations of a circuit. The improvements of the disclosure are achieved without requiring any additional IC pins beyond the 4 required TAP pins, except for examples showing use of additional data input pins (TDI or WPI signals), additional data output pins (TDO or WPO signals) or examples showing use of additional control input pins (Capture and Update signals). Devices including the TAP improvements can be operated compliantly in a daisy-chain arrangement with devices that don't include the TAP improvements. | 2014-06-12 |
20140164839 | PROGRAMMABLE DEVICE, METHOD FOR RECONFIGURING PROGRAMMABLE DEVICE, AND ELECTRONIC DEVICE - In the event of a software error, operations of a programmable device must be suspended while a configuration memory is being rewritten; however, with a system such as a communication device that will be significantly affected if the device is shut down, the system needs to be restored without suspending the operations. This programmable device is provided with: multiple control circuits; a comparison unit that compares outputs of the multiple control circuits so as to inspect for an occurrence of an error; a storage unit that stores internal states of error-free control circuits among the multiple control circuits when an occurrence of an error is determined by the comparison unit; a reconfiguration unit that reconfigures the control circuit in which the occurrence of the error has been determined by the comparison unit; and a control unit that inputs the internal states of the error-free control circuits, which are stored in the storage unit, to the control circuit in which the occurrence of the error has been determined by the comparison unit. | 2014-06-12 |
20140164840 | METHOD AND SYSTEM FOR MONITORING TRANSACTION EXECUTION ON A COMPUTER NETWORK AND COMPUTER STORAGE MEDIUM - A presentation control method for an interaction interface comprises the following steps: acquiring a contact list and a message of a friend in the contact list; generating an image block corresponding to the friend in the contact list; and presenting the message of the friend in the image block. The aforementioned presentation control method for an interaction interface as well as a real-time communications tool and a computer storage medium generate a corresponding image block for every friend in the contact list, so as to further present the message of the friend in the image block. A user can directly view a message of a friend through an image block in an interface, so that the operation is simplified and the convenience of operations is enhanced. | 2014-06-12 |
20140164841 | ROLE-ORIENTED TESTBED ENVIRONMENTS FOR USE IN TEST AUTOMATION - In managing testing on a testbed environment a test automator executes an operation specified in a test script to be performed on a testbed environment, wherein the operation refers to a particular role identifier identifying one of a plurality of roles hosted within the testbed environment by at least one host in the testbed environment, wherein the operation does not refer to any of the at least one host. The test automator performs the operation on a particular host of the at least one host of the testbed environment using at least one value from a host description file for calling the particular host assigned to the particular role identifier in a configuration file. | 2014-06-12 |
20140164842 | ROLE-ORIENTED TESTBED ENVIRONMENTS FOR USE IN TEST AUTOMATION - In managing testing on a testbed environment a test automator executes an operation specified in a test script to be performed on a testbed environment, wherein the operation refers to a particular role identifier identifying one of a plurality of roles hosted within the testbed environment by at least one host in the testbed environment, wherein the operation does not refer to any of the at least one host. The test automator performs the operation on a particular host of the at least one host of the testbed environment using at least one value from a host description file for calling the particular host assigned to the particular role identifier in a configuration file. | 2014-06-12 |
20140164843 | SYSTEM, METHOD AND COMPUTER PROGRAM PRODUCT FOR DEBUGGING AN ASSERTION - In accordance with embodiments, there are provided mechanisms and methods for debugging an assertion. These mechanisms and methods for debugging an assertion can enable improved interpretation and analysis of data validation results, more efficient development associated with data validation, etc. | 2014-06-12 |
20140164844 | pBIST ENGINE WITH DISTRIBUTED DATA LOGGING - A programmable Built In Self Test (pBIST) system used to test embedded memories where the memories under test are incorporated in a plurality of sub chips not integrated with the pBIST module. A distributed Data Logger is incorporated into each sub chip, communicating with the pBIST over serial and a compressed parallel data paths. | 2014-06-12 |
20140164845 | HOST COMPUTER AND METHOD FOR TESTING SAS EXPANDERS - In a method for testing serial attached small computer system interface (SAS) expanders using a host computer, the host computer connects to a master SAS expander through a first serial port, and connects to slave SAS expanders through a second serial port. The host computer sends a test command to the master SAS expander to test the master SAS expander, and stores the test result of the master SAS expander into a flash memory of the master SAS expander. The host computer controls the master SAS expander to transfer the test command to each of the slave SAS expanders to test each of the slave SAS expanders, and stores the test result of each of the slave SAS expanders into the flash memory. The host computer displays all the test results on a display device of the host computer obtained from the flash memory. | 2014-06-12 |
20140164846 | Master-Slave Expander Logging - The invention provides a data storage topology that includes a master logging node where the event logs for all of the nodes may be stored on a consolidated basis. The master logging node is configured with a sufficient amount of reserved or additional data storage to accommodate the event logging requirement for the entire data storage topology. The other expanders in the topology may remain at a baseline model. The master logging medium may be an inexpensive persistent storage, such as a flash chip or USB key. The master logging expander may pull the event logs and other information from the remote expanders or, alternatively, the remote expanders may push their event logs and other information to the master logging node. In particular embodiments, the pull or push configuration may be implemented through preexisting SAS protocols. | 2014-06-12 |
20140164847 | Internal Logic Analyzer with Programmable Window Capture - One embodiment includes receiving a data signal transmitted to the processing unit, analyzing the data signal and generating feedback information related to the data signal, and capturing the data signal via a write enable during a plurality of clock cycles specified by a programmable controller included within the processing unit. One advantage of the disclosed technique is that the programmable controller can be used to set the capture window for one or more hardwired triggers included within the processing unit. Further, the programmable controller is able to set up additional triggers that separate and apart from the hardwired triggers included within the processing unit and set the capture window for those triggers. Thus, the disclosed technique provides a highly flexible and adaptive approach for capturing and storing on-chip data and feedback information that can be analyzed later when performing diagnostic and debugging operations. | 2014-06-12 |
20140164848 | TRACING INSTRUCTION POINTERS AND DATA ACCESSES - A system for tracing instruction pointers and data accesses in a plurality of processor cores includes a plurality of trace units. The plurality of trace units include at least one first trace unit configured to perform an instruction pointer trace and at least one second trace unit configured to perform a data trace. The system includes a multiplexer coupled between the plurality of processor cores and the plurality of trace units. The multiplexer is configured to selectively connect one trace unit of the plurality of trace units to one processor core of the plurality of processor cores. The multiplexer is configured during run time based on one of hardware triggers and software. | 2014-06-12 |
20140164849 | RAID SURVEYOR - A method for surveying a data storage subsystem for latent errors before a failing disk drive of the data storage subsystem fails and recovering unreadable data usable to reconstruct data of the failing disk drive. The method includes determining that a disk drive of a plurality of disk drives of the data storage subsystem meets a threshold for being identified as a failing disk drive, and prior to failure of the failing disk drive, surveying at least a portion of the data on the remaining plurality of disk drives to identify data storage areas with latent errors. The identified data storage areas may be reconstructed utilizing, at least in part, data stored on the failing disk drive. | 2014-06-12 |
20140164850 | AVOIDING PROCESSING FLAWS IN A COMPUTER PROCESSOR TRIGGERED BY A PREDETERMINED SEQUENCE OF HARDWARE EVENTS - A system, method and computer program product for avoiding a processing flaw in a computer processor triggered by a predetermined sequence of hardware events. The system may include a detecting unit and a power-on reset unit. The detecting unit detects that the predetermined sequence of hardware events is going to occur at the computer processor. The power-on reset unit initializes the computer processor to a state stored in computer memory in response to detecting the sequence of hardware events. | 2014-06-12 |
20140164851 | Fault Processing in a System - A status indication regarding operation of a first subsystem is provided. A fault of the first subsystem is detected. In response to detecting the fault, a status indication is updated, and a resource used by the first subsystem is freed up. | 2014-06-12 |
20140164852 | INFORMATION PROCESSING APPARATUS, INFORMATION PROCESSING METHOD, AND INFORMATION PROCESSING SYSTEM - An information processing apparatus includes a receiving unit receiving data input to one or more apparatuses; a data storage unit storing the data with a determined display position thereof in a display screen; a log storage unit storing a data change as a log; an association unit monitoring a communication status of a communication with the one or more apparatuses, and associating information indicating an apparatus where a communication error occurs and a timing when the communication occurs with the log; a recording unit recording video of the data change displayed in the display screen from when the communication error occurs until when the communication is recovered for an apparatus; and a transmission unit transmitting the video from an event when the communication error occurs until an event when the communication is recovered and the log to the apparatus. | 2014-06-12 |
20140164853 | MEMORY OPERATION OF PAIRED MEMORY DEVICES - A method and apparatus for operation of a memory module for storage of a data word is provided. The apparatus includes a memory module having a set of paired memory devices including a first memory device to store a first section of a data word and a second memory device to store a second section of the data word when used in failure free operation. The apparatus may further include a first logic module to perform a write operation by writing the first and second sections of the data word to both the first memory device and the second memory device upon the determination of certain types of failure. The determination may include that a failure exists in the word section storage of either the first or second memory devices but that no failures exist in equivalent locations of word section storage in the two memory devices. | 2014-06-12 |
20140164854 | pBIST ARCHITECTURE WITH MULTIPLE ASYNCHRONOUS SUB CHIPS OPERATING IN DIFFERRING VOLTAGE DOMAINS - A programmable Built In Self Test (pBIST) system used to test embedded memories where the memories may be operating at a voltage domain different from the voltage domain of the pBIST. A plurality of buffer and synchronizing registers are used to avoid meta stable conditions caused by the time delays introduced by the voltage shifters required to bridge the various voltage domains. | 2014-06-12 |
20140164855 | pBIST READ ONLY MEMORY IMAGE COMPRESSION - A programmable Built In Self Test (pBIST) system used to test embedded memories where a plurality of memories requiring different testing conditions are incorporated in an SOC. The pBIST Read Only Memory storing the test setup data is organized to eliminate multiple instances of test setup data for similar embedded memories. | 2014-06-12 |
20140164856 | pBIST ENGINE WITH REDUCED SRAM TESTING BUS WIDTH - A programmable Built In Self Test (pBIST) system used to test embedded memories where the memories under test are incorporated in a plurality of sub chips not integrated with the pBIST module. Test data comparison is performed in a distributed data logging architecture to minimize the number of interconnections between the distributed data loggers and the pBIST. | 2014-06-12 |
20140164857 | Testing Disk Drives Shared by Multiple Processors in a Supercomputer Complex - According to one embodiment of the present disclosure, an approach is provided in which an interface node selects a logical block address that corresponds to a contiguous memory location located on a storage device that is accessible by multiple interface nodes. The interface node retrieves a logical block address status indicator from a shared memory area and determines, based upon the logical block status indicator, whether the logical block address is utilized by a different interface node. If the logical block address is not utilized by a different interface node, the interface node tests the corresponding contiguous memory location. | 2014-06-12 |
20140164858 | TESTING APPARATUS AND TESTING METHOD OF ELECTRONIC DEVICE - A testing apparatus and a testing method of an electronic device are provided. The testing apparatus includes at least two device transfer plates and a testing circuit. The device transfer plates are electrically and respectively connected to corresponding electronic devices and at least two sockets corresponding to the electronic devices. The testing circuit is electrically connected to the device transfer plates respectively through at least two sets of serial signal wire pairs. According to types of the electronic devices, the testing circuit provides a serial signal to one of the device transfer plates through the corresponding serial signal wire pair and receives a response from another one of the device transfer plates through the corresponding serial signal wire pair, so as to test whether an open circuit is occurred to a bus between the electronic devices respectively corresponding to the device transfer plates. | 2014-06-12 |
20140164859 | Dynamic Design Partitioning For Scan Chain Diagnosis - Aspects of the invention relate to techniques for chain fault diagnosis based on dynamic circuit design partitioning. Fan-out cones for scan cells of one or more faulty scan chains of a circuit design are determined and combined to derive a forward-tracing cone. Fan-in cones for scan cells of the one or more faulty scan chains and for failing observation points of the circuit design are determined and combined to derive a backward-tracing cone. By determining intersection of the forward-tracing cone and the backward-tracing cone, a chain diagnosis sub-circuit for the test failure file is generated. Using the process, a plurality of chain diagnosis sub-circuits may be generated for a plurality of test failure files. Scan chain fault diagnosis may then be performed on the plurality of chain diagnosis sub-circuits with a plurality of computers. | 2014-06-12 |
20140164860 | ON-CHIP CONTROLLER AND A SYSTEM-ON-CHIP - An on-chip clock controller includes a clock-control chain configured to shift first clock-control bits in serial and output the first clock-control bits to a first clock domain in parallel in response to a clock-control scan clock provided from outside of a chip, and a first domain clock generator, the first domain clock generator configured, during a test mode, to generate a first internal clock by selectively outputting a first data scan clock provided from outside of the chip or a first functional clock generated from inside of the chip. | 2014-06-12 |
20140164861 | APPARATUS AND METHOD FOR SELF-TESTING A COMPONENT FOR SIGNAL RECOVERY - A circuit having a component for signal recovery, such as an adaptive equalizer, may be tested in order to ensure that the component operates properly. Unfortunately, external test equipment may be expensive and prone to being damaged. According to an aspect of the disclosure, there is provided a circuit including BIST (Built-in Self-Test) circuitry for testing a component for signal recovery with a stress signal that simulates an imperfect signal received over a communication channel. The circuit also has a detector for determining whether the component is operating properly with the stress signal. Thus, no external test equipment is needed for testing the component. In some implementations, the BIST circuitry includes a low-pass filter for filtering a transmit signal into the stress signal. Thus, the amount of circuitry involved in generating the stress signal can be reduced. | 2014-06-12 |
20140164862 | ELECTRONIC DEVICE TESTING SYSTEM AND METHOD - An electronic device testing system is configured to test an electronic device which generates a plurality of signals while running. The electronic device testing system includes a programmable logic device (PLD) configured to monitor and control the electronic device and a computer connected to the PLD. The PLD includes a read/write control module connected to the electronic device and a controller connected to the read/write control module. The read/write control module reads the plurality of signals generated by the electronic device. The controller determines whether the plurality of signals has errors and sends error signals to the computer. The computer analyzes the error signals and displays problems associated with the error signals. The present disclosure further discloses an electronic device testing method based upon the above testing system. | 2014-06-12 |
20140164863 | ADAPTIVE MOVING READ REFERENCES FOR MEMORY CELLS - Examples are disclosed for generating or providing a moving read reference (MRR) table for recovering from a read error of one or more memory cells of a non-volatile memory included in a storage device. Priorities may be adaptively assigned to entries included in the MRR table and the entries may be ordered for use based on the assigned priorities. Other examples are described and claimed. | 2014-06-12 |
20140164864 | WIRELESS COMMUNICATIONS TERMINAL, BASE STATION DEVICE, AND RESOURCE ALLOCATION METHOD - The purpose of the present invention is to avoid ACK/NACK collision in a system in which E-PDCCH control information is transmitted, increase the utilization efficiency of ACK/NACK resources, and suppress unnecessary PUSCH band reduction. A wireless communications terminal having a configuration comprising: a reception unit that receives control signals including ACK/NACK indexes, via an expanded physical downlink control channel; a control unit that determines, on the basis of the ACK/NACK indexes, whether to use a dynamically allocated dynamic ACK/NACK resource or a specified resource specified beforehand, to send downlink data ACK/NACK signals; and a transmission unit that sends the ACK/NACK signals using the dynamic ACK/NACK resource or the specified resource, as determined. | 2014-06-12 |
20140164865 | ERROR-CORRECTION DECODING WITH REDUCED MEMORY AND POWER REQUIREMENTS - An example method is provided that includes receiving a representation of a codeword that includes a plurality of bits, and associating the bits with a respective plurality of one-bit hard-bit values representing the bits and multiple-bit soft-bit values representing measures of reliability of respective hard-bit values. The method includes for each of a plurality of iterations, updating a hard-bit/soft-bit value of one or more bits of a respective subset of the bits as a function of current hard-bit values of the subset's bits, and the current hard-bit and soft-bit values of the respective bit. For two iterations in which the current hard-bit and soft-bit values for each bit of a subset for both iterations is the same, the hard-bit/soft-bit value updated for any bit of the subset during one of the two iterations is the same as that computed for the respective bit during the other of the two iterations. | 2014-06-12 |
20140164866 | Low Density Parity Check Decoder With Miscorrection Handling - A data processing system is disclosed including a decoder circuit, syndrome calculation circuit and hash calculation circuit. The decoder circuit is operable to apply a decoding algorithm to a decoder input based on a first portion of a composite matrix to yield a codeword. The syndrome calculation circuit is operable to calculate a syndrome based on the codeword and on the first portion of the composite matrix. The hash calculation circuit is operable to calculate a hash based on a second portion of the composite matrix. The decoder circuit is also operable to correct the codeword on the hash when the syndrome indicates that the codeword based on the first portion of the composite matrix is correct but a second test indicates that the codeword is miscorrected. | 2014-06-12 |
20140164867 | STOPPING CRITERIA FOR LAYERED ITERATIVE ERROR CORRECTION - The present disclosure includes apparatuses and methods related to stopping criteria for layered iterative error correction. A number of methods can include receiving a codeword with an error correction circuit, iteratively error correcting the codeword with the error correction circuit including parity checking the codeword on a layer-by-layer basis and updating the codeword after each layer. Methods can include stopping the iterative error correction in response to a parity check being correct for a particular layer. | 2014-06-12 |
20140164868 | FLASH MEMORY READ ERROR RECOVERY WITH SOFT-DECISION DECODE - An apparatus having a circuit and one or more processor is disclosed. The circuit is configured to receive a codeword from a memory. The memory is nonvolatile. The codeword generally has one or more errors. The processors are configured to generate read data by decoding the codeword repeatedly. The decoding includes a soft-decision decoding that uses a plurality of parameters calculated by (i) a first procedure, (ii) a second procedure in response to a plurality of failures of the decoding to converge using the first procedure and (iii) a third procedure in response to another failure of the decoding to converge using the second procedure. | 2014-06-12 |
20140164869 | EFFICIENT DATA-STORAGE DEVICES THAT INCLUDE MEMORY ELEMENTS CHARACTERIZED BY POTENTIALLY LARGE SWITCHING LATENCIES - One example disclosed in the application is an electronic data-storage device comprising one or more arrays of memory elements that each includes a data-storage medium that is switched between two different states by application of a switching-inducing force or gradient to the data-storage medium, a top control element and a bottom control element through which the switching-inducing force or gradient is applied, and a feedback signal. The data-storage device also includes an error-control-coding encoder that encodes received data and a READ/WRITE controller that writes encoded data received from the error-control-coding encoder to a number of memory elements by applying the switching-inducing force to the one or mare arrays of memory elements until feedback signals indicate that the WRITE operation has completed or until the switching-inducing force or gradient has been applied for a maximum application time. | 2014-06-12 |
20140164870 | SYSTEM AND METHOD FOR LOWER PAGE DATA RECOVERY IN A SOLID STATE DRIVE - In some embodiments of the present invention, a data storage system includes a controller and a non-volatile memory array having a plurality of memory pages. The controller performs a method that efficiently resolves the lower page corruption problem. In one embodiment, the method selects programmed lower page(s) for which paired upper page(s) have not been programmed, reads data from those selected lower page(s), corrects the read data, and reprograms the read data into those lower page(s). Since the number of lower pages in this condition is typically low (e.g., several pages in a block with hundreds or thousands of pages), this is a much more efficient method than reprogramming the entire block. In another embodiment, a similar reprogramming method is applied as a data recovery scheme in situations in which only lower pages are programmed (e.g., SLC memory, MLC memory in SLC mode, etc.). | 2014-06-12 |
20140164871 | DRAM ERROR DETECTION, EVALUATION, AND CORRECTION - This disclosure includes a method for correcting errors on a DRAM having an ECC which includes writing data to a DRAM row, reading data from the DRAM row, detecting errors in the data that cannot be corrected by the DRAM's ECC, determining erasure information for the row, evaluating the errors using the erasure information, and correcting the errors in the data. | 2014-06-12 |
20140164872 | ERROR CORRECTED PRE-READ FOR UPPER PAGE WRITE IN A MULTI-LEVEL CELL MEMORY - Methods, apparatuses and articles of manufacture may receive a first page of data and correct one or more errors in the first page of data to generate a page of corrected data. A program command may then be sent with a second page of data and the page of corrected data, to program a page of memory to store the second page of data. | 2014-06-12 |
20140164873 | Techniques For Storing Bits in Memory Cells Having Stuck-at Faults - A data storage system includes a memory circuit comprising memory cells and a control circuit. The control circuit generates a first set of redundant bits indicating bit positions of the memory cells having stuck-at faults in response to a first write operation if a first rate of the stuck-at faults in the memory cells is greater than a first threshold. The control circuit is operable to encode data bits to generate encoded data bits and a second set of redundant bits that indicate a transformation performed on the data bits to generate the encoded data bits in response to a second write operation if a second rate of stuck-at faults in the memory cells is greater than a second threshold. The encoded data bits stored in the memory cells having the stuck-at faults match digital values of corresponding ones of the stuck-at faults. | 2014-06-12 |
20140164874 | DRAM ERROR DETECTION, EVALUATION, AND CORRECTION - This disclosure includes a method for correcting errors on a DRAM having an ECC which includes writing data to a DRAM row, reading data from the DRAM row, detecting errors in the data that cannot be corrected by the DRAM's ECC, determining erasure information for the row, evaluating the errors using the erasure information, and correcting the errors in the data. | 2014-06-12 |
20140164875 | MEMORY CONTROLLER AND METHOD OF OPERATING THE SAME - A memory controller includes a register configured to store a parity check matrix, and an error correcting code (ECC) decoder configured to perform error bit correction on data supplied from a non-volatile memory device using the parity check matrix. The parity check matrix includes N column matrices, where N is a natural number. Each of the N column matrices includes multiple sub-matrices, and a last sub-matrix of the multiple sub-matrices of each column matrix, which is a non-zero valued matrix that comes last in an decoding sequence of the ECC decoder, is an identity matrix. | 2014-06-12 |
20140164876 | MODULATION CODING OF PARITY BITS GENERATED USING AN ERROR-CORRECTION CODE - A communication system, such as a magnetic recording channel, configured to apply modulation coding to parity bits of a block error-correction code. An embodiment of the communication system may have a transmitter having two different modulation encoders, one configured to apply a first modulation code to information bits and the other configured to apply a second modulation code to the parity bits that have been generated from the information bits using a block error-correction code. Alternatively or in addition, an embodiment of the communication system may have a receiver that incorporates a soft modulation codec configured to use the second modulation code in the log-likelihood-ratio space to enable decoding iterations between a sequence detector and a parity-check decoder. | 2014-06-12 |
20140164877 | STORING PORTIONS OF DATA IN A DISPERSED STORAGE NETWORK - A method begins, in accordance with a segmentation approach, dividing large data to be stored into regions and dividing a region into segments. The method continues by generating preliminary DSN storage information for one or more regions. The method continues by identifying other large data stored in the DSN that has a relationship with the large data to be stored in the DSN and retrieving DSN storage information for the other large data. The method continues by comparing, at a region level, the preliminary DSN storage information with the retrieved DSN storage information. When a region of the large data to be stored has substantially similar DSN storage information as a region of the other large data, the method continues by utilizing the DSN storage information for the region of the other large data for the DSN storage information of the region of the large data. | 2014-06-12 |
20140164878 | Data Recovery on Cluster Failures and ECC Enhancements with Code Word Interleaving - Techniques are presented for dealing with errors that arise from cluster fails, where a number of memory cells in the same area fail. An ECC code word can tolerate a given total amount of error while still being able to still be decoded, so that if error due to clusters can be identified and removed or lessened, it may be possible to still decode the word not otherwise decodable. After identifying possible error bit cluster locations, one or more bits in the cluster locations are flipped to see if the data content of the code word can be extracted. For embodiments using LDPC ECC code, uncertainty can be added for the bits of a suspected cluster location. To reduce the effects of cluster failures, code words can be interleaved within a page and the difference code words can have differing levels of ECC capability. | 2014-06-12 |
20140164879 | Data Recovery on Cluster Failures and ECC Enhancements with Code Word Interleaving - Techniques are presented for dealing with errors that arise from cluster fails, where a number of memory cells in the same area fail. An ECC code word can tolerate a given total amount of error while still being able to still be decoded, so that if error due to clusters can be identified and removed or lessened, it may be possible to still decode the word not otherwise decodable. After identifying possible error bit cluster locations, one or more bits in the cluster locations are flipped to see if the data content of the code word can be extracted. For embodiments using LDPC ECC code, uncertainty can be added for the bits of a suspected cluster location. To reduce the effects of cluster failures, code words can be interleaved within a page and the difference code words can have differing levels of ECC capability. | 2014-06-12 |
20140164880 | ERROR CORRECTION CODE RATE MANAGEMENT FOR NONVOLATILE MEMORY - An apparatus having an interface and a circuit is shown. The interface is coupled to a memory that is nonvolatile. The circuit is configured to (i) read a plurality of codewords from a block in the memory based on a program/erase count associated with the block, (ii) count a number of iterations used to decode the codewords and (iii) decrease a code rate of an error correction coding used to program the block in response to the number of iterations exceeding a threshold. | 2014-06-12 |
20140164881 | POLICY FOR READ OPERATIONS ADDRESSING ON-THE-FLY DECODING FAILURE IN NON-VOLATILE MEMORY - An apparatus includes a non-volatile memory and a controller. The controller is operatively coupled to the non-volatile memory and configured to perform read and write operations on the non-volatile memory using codewords as a unit of read access. The controller includes an error correction engine configured to perform an error correction on codewords read from the non-volatile memory, and, if the error correction fails, to perform one or more retry procedures. The controller is further configured to perform one or more background procedures as a result of the error correction or one or more of the retry procedures not being successful and send an error message as a result of all of the retry procedures not being successful. The one or more background procedures are directed to determining a cause of the error correction failure. | 2014-06-12 |
20140164882 | DTV TRANSMITTING SYSTEM AND METHOD OF PROCESSING BROADCAST DATA - A DTV transmitting system includes an encoder, a randomizer, a block processor, a group formatter, a deinterleaver, and a packet formatter. The encoder codes enhanced data for error correction, permutes the coded data, and further codes the permuted data for error detection. The randomizer randomizes the coded enhanced data, and the block processor codes the randomized data at an effective coding rate of 1/H. The group formatter forms a group of enhanced data having data regions, and inserts the coded enhanced data into at least one of the data regions. The deinterleaver deinterleaves the group of enhanced data, and the packet formatter formats the deinterleaved data into corresponding data bytes. | 2014-06-12 |
20140164883 | OPTICAL TRANSMISSION MODULE AND OPTICAL SIGNAL TRANSMISSION APPARATUS - Embodiments of the present invention provide an optical sending module, an optical receiving module, an apparatus for sending an optical signal, and an apparatus for receiving an optical signal, and relate to the field of optical communications. The optical sending module includes: an FEC coding module and an optical sending interface. The apparatus for sending an optical signal includes: a protocol processing module and the optical sending module. The optical receiving module includes: an FEC decoding module and an optical receiving interface. The apparatus for receiving an optical signal includes: a protocol processing module and the optical receiving module. The present invention can reduce the scale, power consumption, and cost of the protocol processing module and reduce the network expansion cost. | 2014-06-12 |
20140164884 | HIGH-PERFORMANCE ECC DECODER - Methods for Error Correction Code (ECC) decoding include producing syndromes from a set of bits, which represent data that has been encoded with the ECC. An Error Locator Polynomial (ELP) is generated based on the syndromes. At least some of the ELP roots are identified, and the errors indicated by these roots are corrected. Each syndrome may be produced by applying to the bits vector operations in a vector space. Each syndrome is produced by applying vector operations using a different basis of the vector space. The ELP may be evaluated on a given field element by operating on ELP coefficients using serial multipliers, wherein each serial multiplier performs a sequence of multiplication cycles and produces an interim result in each cycle. Responsively to detecting at least one interim result indicating that the given element is not an ELP root, the multiplication cycles are terminated before completion of the sequence. | 2014-06-12 |
20140164885 | TIME INFORMATION OBTAINING DEVICE AND RADIO-CONTROLLED TIMEPIECE - A time information obtaining device and a radio-controlled timepiece are shown. According to one implementation, the time information obtaining device includes the following. A code identifying section identifies each code of a code string in a radio wave. A first portion parity calculating section calculates a portion parity where a parity bit of a variable code is subtracted from a parity code showing a parity bit for a code string portion. A first portion parity deciding section decides a portion parity based on a calculated number of portion parities. A second portion parity deciding section obtains a portion parity from an invariable code other than the variable code. A parity confirming section confirms a match between the portion parities decided by the first portion parity deciding section and the second portion parity deciding section. | 2014-06-12 |