24th week of 2012 patent applcation highlights part 32 |
Patent application number | Title | Published |
20120147645 | THREE DIMENSIONAL NON-VOLATILE STORAGE WITH DUAL GATED VERTICAL SELECT DEVICES - A three-dimensional array adapted for memory elements that reversibly change a level of electrical conductance in response to a voltage difference being applied across them. Memory elements are formed across a plurality of planes positioned different distances above a semiconductor substrate. Bit lines to which the memory elements of all planes are connected are oriented vertically from the substrate and through the plurality of planes. | 2012-06-14 |
20120147646 | THREE DIMENSIONAL NON-VOLATILE STORAGE WITH CONNECTED WORD LINES - A three-dimensional array adapted for memory elements that reversibly change a level of electrical conductance in response to a voltage difference being applied across them. Memory elements are formed across a plurality of planes positioned different distances above a semiconductor substrate. Bit lines to which the memory elements of all planes are connected are oriented vertically from the substrate and through the plurality of planes. | 2012-06-14 |
20120147647 | THREE DIMENSIONAL NON-VOLATILE STORAGE WITH THREE DEVICE DRIVER FOR ROW SELECT - A three-dimensional array adapted for memory elements that reversibly change a level of electrical conductance in response to a voltage difference being applied across them. Memory elements are formed across a plurality of planes positioned different distances above a semiconductor substrate. Bit lines to which the memory elements of all planes are connected are oriented vertically from the substrate and through the plurality of planes. | 2012-06-14 |
20120147648 | THREE DIMENSIONAL NON-VOLATILE STORAGE WITH DUAL GATE SELECTION OF VERTICAL BIT LINES - A three-dimensional array adapted for memory elements that reversibly change a level of electrical conductance in response to a voltage difference being applied across them. Memory elements are formed across a plurality of planes positioned different distances above a semiconductor substrate. Bit lines to which the memory elements of all planes are connected are oriented vertically from the substrate and through the plurality of planes. | 2012-06-14 |
20120147649 | Non-Volatile Memory Having 3d Array of Read/Write Elements with Low Current Structures and Methods Thereof - A three-dimensional array read/write (R/W) memory elements is formed across multiple layers of planes positioned at different distances above a semiconductor substrate. It is preferable to operate the R/W elements with low current and high resistive states. The resistance of these resistive states depends also on the dimension of the R/W elements and is predetermined by the process technology. A sheet electrode in series with the R/W element and a method of forming it provide another degree of freedom to adjust the resistance of the R/W memory element. The thickness of the sheet electrode is adjusted to obtain a reduced cross-sectional contact in the circuit path from the word line to the bit line. This allows the R/W memory element to have a much increased resistance and therefore to operate with much reduced currents. The sheet electrode is formed with little increase in cell size. | 2012-06-14 |
20120147650 | Non-Volatile Memory Having 3D Array of Read/Write Elements with Vertical Bit Lines and Select Devices and Methods Thereof - A three-dimensional memory is formed as an array of memory elements that are formed across multiple layers of planes positioned at different distances above a semiconductor substrate. The memory elements reversibly change a level of electrical conductance in response to a voltage difference being applied across them. The three-dimensional array includes a two-dimensional array of pillar lines acting as local vertical bit lines through the multiple layers of planes which together with arrays of word lines on each plane are used to access the memory elements. The three-dimensional memory is formed over a CMOS substrate with an intermediate pillar select layer. The pillar select layer is formed with a plurality of pillar select devices which are switching transistors formed outside the CMOS and serve to switch selected rows of pillar lines to corresponding metal lines on the substrate. | 2012-06-14 |
20120147651 | THREE DIMENSIONAL NON-VOLATILE STORAGE WITH DUAL LAYERS OF SELECT DEVICES - A three-dimensional array adapted for memory elements that reversibly change a level of electrical conductance in response to a voltage difference being applied across them. Memory elements are formed across a plurality of planes positioned different distances above a semiconductor substrate. Bit lines to which the memory elements of all planes are connected are oriented vertically from the substrate and through the plurality of planes. | 2012-06-14 |
20120147652 | THREE DIMENSIONAL NON-VOLATILE STORAGE WITH ASYMMETRICAL VERTICAL SELECT DEVICES - A three-dimensional array adapted for memory elements that reversibly change a level of electrical conductance in response to a voltage difference being applied across them. Memory elements are formed across a plurality of planes positioned different distances above a semiconductor substrate. Bit lines to which the memory elements of all planes are connected are oriented vertically from the substrate and through the plurality of planes. | 2012-06-14 |
20120147653 | CIRCUIT AND SYSTEM OF A HIGH DENSITY ANTI-FUSE - A high density anti-fuse cell can be built at the cross points of two perpendicular interconnect lines, such as active region lines, active and polysilicon lines, active and metal lines, or polysilicon and metal lines. The cell size can be very small. At least one of the anti-fuse cells have a thin oxide fabricated before, after, or between a diode in at least one contact holes at the cross points of the interconnect lines. The thin oxide of the anti-fuse cells at the cross points can be selected for rupture by applying supply voltages in the two perpendicular lines. In some embodiments, a diode can be created after thin oxide is ruptured so that explicitly fabricating a diode or opening a contact hole at the cross-point may not be necessary. | 2012-06-14 |
20120147654 | Ferroelectric Random Access Memory with Single Plate Line Pulse During Read - A ferroelectric random access memory (FRAM) with reduced cycle time. During a read cycle, plate line voltages are boosted to a voltage to both transfer charge from the selected row of FRAM cells to corresponding bit lines, and to fully polarize a data state in the selected FRAM cells. In one embodiment of the invention, the fully polarized data states is present in those cells that previously stored that data state; for those cells storing the opposite state, a write-back pulse is executed. In another embodiment of the invention, the fully polarized data state results for each of the selected memory cells, by applying a plate line boost voltage of a higher magnitude. Those cells that are to store the opposite data state, as may be determined following error correction, are written back with that data state. | 2012-06-14 |
20120147655 | NON-VOLATILE MEMORY DEVICE AND METHOD FOR PROGRAMMING THE SAME - A non-volatile memory device and a method for programming the same are disclosed. The method for programming the non-volatile memory device includes generating a simultaneous write current based on a program address in such a manner that bit line write cells corresponding to memory cells coupled to the same bit line from among memory cells to be programmed can be simultaneously programmed, and providing the simultaneous write current to the bit line write cells by simultaneously enabling the bit line write cells. | 2012-06-14 |
20120147656 | MEMORY ELEMENT AND MEMORY DEVICE - A memory element and a memory device having the stable switching characteristics with the characteristics of data retention remaining favorable are provided. The memory element includes a first electrode, a memory layer, and a second electrode in this order. The memory layer includes an ion source layer provided on the second electrode side, a resistance change layer provided between the ion source layer and the first electrode, and a barrier layer provided between the resistance change layer and the first electrode, and having conductivity higher than that of the resistance change layer. | 2012-06-14 |
20120147657 | PROGRAMMING REVERSIBLE RESISTANCE SWITCHING ELEMENTS - A storage system and method for operating the storage system that uses reversible resistance-switching elements is described. Techniques are disclosed herein for varying programming conditions to account for different resistances that memory cells have. These techniques can program memory cells in fewer attempts, which can save time and/or power. Techniques are disclosed herein for achieving a high programming bandwidth while reducing the worst case current and/or power consumption. | 2012-06-14 |
20120147658 | SYSTEM OF MEASURING A RESISTANCE OF A RESISTIVE MEMORY DEVICE - A system for measuring a resistance of a memory cell in a resistive memory device can include a pulse generator configured to apply a data write pulse and a resistance read pulse to the resistive memory device with a delay time. A connecting member can be connected between the pulse generator and the resistive memory device. A test measurement device can be connected to the resistive memory device outputting a pulse waveform and a data-processing member can be configured to determine the resistance of the resistive memory device using the pulse waveform and an internal resistance of the test measurement device. | 2012-06-14 |
20120147659 | Bidirectional Non-Volatile Memory Array Architecture - Method and apparatus for transferring data in a memory. A semiconductor memory includes a plurality of memory cells each having a resistive sense element (RSE) in series with a switching device. A conductive word line extends in a first direction adjacent the memory cells and is connected to a gate structure of each of the switching devices. A plurality of conductive bit lines extend in a second direction adjacent the memory cells, each bit line providing a connection node that interconnects a respective pair of the memory cells. A control circuit senses a programmed state of a selected memory cell by setting each of the bit lines on a first side of the selected memory cell to a first voltage level, setting each of the remaining bit lines on an opposing second side of the selected memory cell to a second voltage level, and setting the word line to a third voltage level. | 2012-06-14 |
20120147660 | Preservation Circuit And Methods To Maintain Values Representing Data In One Or More Layers Of Memory - Circuitry and methods for restoring data in memory are disclosed. The memory may include at least one layer of a non-volatile two-terminal cross-point array that includes a plurality of two-terminal memory elements that store data as a plurality of conductivity profiles and retain stored data in the absence of power. Over a period of time, logic values indicative of the stored data may drift such that if the logic values are not restored, the stored data may become corrupted. At least a portion of each memory may have data rewritten or restored by circuitry electrically coupled with the memory. Other circuitry may be used to determine a schedule for performing restore operations to the memory and the restore operations may be triggered by an internal or an external signal or event. The circuitry may be positioned in a logic layer and the memory may be fabricated over the logic layer. | 2012-06-14 |
20120147661 | DATA SECURITY FOR DYNAMIC RANDOM ACCESS MEMORY AT POWER-UP - A circuit and method erase at power-up all data stored in a DRAM chip for increased data security. All the DRAM memory cells are erased by turning on the transistors for the DRAM storage cells simultaneously by driving the wordlines of all the cells to an activated state. With all the devices turned on, the data stored in the memory cells is erased as the voltage of all the cells connected to a common bitline coalesce to a single value. In a preferred embodiment, the wordlines are all turned on simultaneously during a power on reset period. Preferably a power on reset signal is used to drive each logic gate of the pre-decoder portion of the address decoder in order to assert all the wordlines. | 2012-06-14 |
20120147662 | Semiconductor Integrated Circuit and Manufacturing Method Thereof - High manufacturing yield is realized and variation in threshold voltage of each MOS transistor in a CMOS·SRAM is compensated. Body bias voltages are applied to wells for MOS transistors of each SRAM memory cell in any active mode of an information holding operation, a write operation and a read operation of an SRAM. Threshold voltages of PMOS and NMOS transistors of the SRAM are first measured. Control information is programmed into control memories according to results of determination. Levels of the body bias voltages are adjusted based on the programs so that variations in the threshold voltages of the MOS transistors of the CMOS·SRAM are controlled to a predetermined error span. Body bias voltage corresponding to a reverse body bias or an extremely shallow forward body bias is applied to a substrate for the MOS transistors with an operating voltage applied to the source of each MOS transistor. | 2012-06-14 |
20120147663 | NONVOLATILE MEMORY WITH ENHANCED EFFICIENCY TO ADDRESS ASYMETRIC NVM CELLS - This application describes embodiments of MRAM cells that utilize a PMOS transistor as an access transistor. The MRAM cells are configured to mitigate the effects of applying asymmetric current loads to transition a Magnetic-Tunnel Junction of the MRAM cell between magnetoresistive states. | 2012-06-14 |
20120147664 | NON-VOLATILE MEMORY DEVICE AND METHOD FOR CONTROLLING THE SAME - A non-volatile memory and method for controlling the same prevents a faulty operation from being generated in a read operation, resulting in increase in operation reliability. The non-volatile memory device includes a cell array configured to include a plurality of unit cells in which a read or write operation of data is achieved in a unit cell in response to a variation of resistance, a reference cell array configured to include a plurality of reference cells, each of which has the same structure as that of the unit cell, a global reference current generation circuit configured to generate a global reference current corresponding to a position of the reference cell so as to verify data stored in the reference cell array, and a sense-amplifier configured to compare a current flowing in the reference cell array with the global reference current during a write verification operation of the reference cell array, and thus sense data. | 2012-06-14 |
20120147665 | Predictive Thermal Preconditioning and Timing Control for Non-Volatile Memory Cells - Method and apparatus for using thermal preconditioning to write data to a non-volatile memory cell. In accordance with some embodiments, a semiconductor memory has an array of non-volatile memory cells, and a control circuit which stores a first write command from a host to write data to said array. A write circuit flows a write current through an unconditioned first selected cell having a first block address associated with the first write command to write the first selected cell to a selected data state, and concurrently passes a thermal preconditioning current through a second selected cell having a second block address associated with the first block address. The write circuit further passes a thermal preconditioning current through a third selected cell having a third block address associated with the second block address in response to receipt by the control circuit of a second write command from the host associated with the second block address. | 2012-06-14 |
20120147666 | PHASE CHANGE MATERIAL CELL WITH STRESS INDUCER LINER - An example embodiment disclosed is a phase change memory cell. The memory cell includes a phase change material and a transducer positioned proximate the phase change material. The phase change material is switchable between at least an amorphous state and a crystalline state. The transducer is configured to activate when the phase change material is changed from the amorphous state to the crystalline state. In a particular embodiment, the transducer is ferroelectric material. | 2012-06-14 |
20120147667 | VARIABLE RESISTANCE MEMORY PROGRAMMING - Some embodiments include a device having memory elements and methods of storing information into the memory elements. Such methods can include increasing a temperature of a portion of a memory element for a time interval during an operation to change a resistance state of the memory element. After the time interval, the methods can include decreasing the temperature of the portion of the memory element. Decreasing the temperature can be performed using a signal having a first negative slope and a second negative slope. Other embodiments are described. | 2012-06-14 |
20120147668 | Diode and Memory Device Having a Diode - A diode and a memory device having a diode are provided. The diode includes a semiconductor layer and phase change material layer. The semiconductor layer and the phase change material layer have different energy bandgaps and different carrier concentrations such that an isotype heterojunction is formed at a boundary interface between the semiconductor layer and the phase change material layer. | 2012-06-14 |
20120147669 | NON-VOLATILE MEMORY DEVICE AND A METHOD FOR OPERATING THE DEVICE - A method for operating a non-volatile memory device includes programming a memory cell and not programming a flag cell during first to n | 2012-06-14 |
20120147670 | SEMICONDUCTOR STORAGE DEVICE ADAPTED TO PREVENT ERRONEOUS WRITING TO NON-SELECTED MEMORY CELLS - A memory cell array has a number of memory cells which are connected to word lines and bit lines and are arranged in a matrix form, each of the memory cells storing one of n levels (n is a natural number of 2 or more). A control circuit controls the potentials on the word lines and the bit lines in accordance with input data to write data to the memory cells. The control circuit is adapted to, at the write time, first apply a first potential to a well region or substrate in which the memory cells are formed, then set the well region or substrate to a second potential lower than the first potential, and next apply a predetermined voltage to the word lines to thereby perform a write operation. | 2012-06-14 |
20120147671 | OVER-SAMPLING READ OPERATION FOR A FLASH MEMORY DEVICE - A flash memory device and a reading method are provided where memory cells are divided into at least two groups. Memory cells are selected according to a threshold voltage distribution. Data stored in the selected memory cells are detected and the data is latched corresponding to one of the at least two groups according to a first read operation. A second read operation detects and latches data of the memory cells corresponding to another one of the at least two groups. The data is processed through a soft decision algorithm during the second read operation. | 2012-06-14 |
20120147672 | FRACTIONAL BITS IN MEMORY CELLS - Methods, devices, modules, and systems for programming memory cells can include storing charges corresponding to a data state that represents an integer number of bits in a set of memory cells. Programming memory cells can include storing a charge in a cell of the set, where the charge corresponds to a programmed state, where the programmed state represents a fractional number of bits, and where the programmed state denotes a digit of the data state as expressed by a number in base N, where N is equal to 2 | 2012-06-14 |
20120147673 | SEMICONDUCTOR MEMORY DEVICE USING ONLY SINGLE-CHANNEL TRANSISTOR TO APPLY VOLTAGE TO SELECTED WORD LINE - A semiconductor memory device has a memory cell array, a first transistor of a first conductivity type, a second transistor of a second conductivity type and a third transistor of the first conductivity type. A source or drain of the first transistor is connected to each of word lines. A drain of the second transistor is connected to a gate of the first transistor. A source of the third transistor is connected to the gate of the first transistor. The gates of the second transistor and the third transistor are not connected, a source of the second transistor is not connected to a drain of the third transistor, and the gate of the second transistor and the drain of the third transistor have different voltage levels corresponding to opposite logic levels each other. | 2012-06-14 |
20120147674 | Nonvolatile Memory Devices that Utilize Dummy Word Line Segments to Inhibit Dishing During Fabrication - A NAND flash memory device includes a plurality of continuous conductors disposed on a common level of a multilayer substrate, the plurality of continuous conductors including respective conductive lines extending in parallel along a first direction, respective contact pads disposed at ends of the respective conductive lines and respective conductive dummy lines extending in parallel from the contact pads along a second direction | 2012-06-14 |
20120147675 | Nonvolatile Stacked Nand Memory - A NAND string of memory cells has stacks of split word lines (gates), with resulting increased bit density. Variants add a top assist gate to the NAND string, a bottom assist gate to the NAND string, or both a top assist gate and a bottom assist gate to the NAND string. | 2012-06-14 |
20120147676 | NON-VOLATILE STORAGE SYSTEM WITH SHARED BIT LINES CONNECTED TO SINGLE SELECTION DEVICE - A non-volatile storage system is disclosed that includes pairs of NAND strings (or other groupings of memory cells) in the same block being connected to and sharing a common bit line. To operate the system, two selection lines are used so that the NAND strings (or other groupings of memory cells) sharing a bit line can be selected at the block level. Both selection lines are connected to a selection gate for each of the NAND strings (or other groupings of memory cells) sharing the bit line. | 2012-06-14 |
20120147677 | BIASING SYSTEM AND METHOD - Embodiments are provided that include a memory system that includes a memory system, having an access device coupled between a global line and a local line and a voltage source coupled to the global line and configured to output a bias voltage on the global line when the memory system is in a non-operation state. The access device is selected when the memory system is in the non-operation state, and the access device is deselected when the memory system is in an other state. Further embodiments provide, for example, a method that includes coupling a global access line to a local access line, biasing the local access line to a voltage other than a negative supply voltage while a memory device is in a first state and uncoupling the global access line from the local access line while the memory device is in an other state. | 2012-06-14 |
20120147678 | Buffering Systems For Accessing Multiple Layers Of Memory In Integrated Circuits - Embodiments of the invention relate generally to data storage and computer memory, and more particularly, to systems, integrated circuits and methods for accessing memory in multiple layers of memory implementing, for example, third dimension memory technology. In a specific embodiment, an integrated circuit is configured to implement write buffers to access multiple layers of memory. For example, the integrated circuit can include memory cells disposed in multiple layers of memory. In one embodiment, the memory cells can be third dimension memory cells. The integrated circuit can also include read buffers that can be sized differently than the write buffers. In at least one embodiment, write buffers can be sized as a function of a write cycle. Each layer of memory can include a plurality of two-terminal memory elements that retain stored data in the absence of power and store data as a plurality of conductivity profiles. | 2012-06-14 |
20120147679 | METHOD FOR CONDUCTING REFERENCE VOLTAGE TRAINING - A method for conducting reference voltage training includes setting levels of a reference voltage in response to code signals and receiving and storing data for the respective levels of the reference voltage, and simultaneously outputting the stored data. | 2012-06-14 |
20120147680 | SEMICONDUCTOR MEMORY DEVICE - A power supply control circuit which can cut off a power supply independently is provided for each column in a memory cell array. The power supply control circuit is controlled by a circuit which is provided for each column and determines whether or not it is necessary to hold information, whereby a power supply for a memory cell which does not need to hold information is cut off. | 2012-06-14 |
20120147681 | METHODS, DEVICES, AND SYSTEMS RELATING TO A MEMORY CELL HAVING A FLOATING BODY - Methods, devices, and systems are disclosed for a memory cell having a floating body. A memory cell may include a transistor over an insulation layer, the transistor including a source, and a drain. The memory cell may also include a floating body including a first region positioned between the source and the drain, a second region positioned remote from each of the source and drain, and a passage extending through the insulation layer and coupling the first region to the second region. Additionally, the memory cell may include a bias gate at least partially surrounding the second region and configured for operably coupling to a bias voltage. Furthermore, the memory cell may include a plurality of dielectric layers, wherein each outer vertical surface of the second region has a dielectric layer of the plurality adjacent thereto. | 2012-06-14 |
20120147682 | MEMORY ELEMENTS HAVING CONFIGURABLE ACCESS DUTY CYCLES AND RELATED OPERATING METHODS - Apparatus and methods are provided for accessing memory elements. An exemplary memory element includes an array of memory cells and a control module. Each memory cell of the array is coupled to an access line, wherein the control module is configured to assert a first signal for a write duty cycle on the access line to enable writing to a first memory cell of the array of memory cells, and the control module is configured to assert a second signal for a read duty cycle on the access line to enable reading from the first memory cell. The write duty cycle and the read duty cycle are each selected from a plurality of possible duty cycles. In an exemplary embodiment, the read duty cycle and the write duty cycle are chosen to optimize a performance parameter for the memory element. | 2012-06-14 |
20120147683 | SEMICONDUCTOR MEMORY DEVICE - A memory cell is provided at an intersection of a word line and a bit line, and a dummy cell is provided at an intersection of a dummy word line and a dummy bit line. A delay circuit delays a signal read into the dummy bit line to generate a sense amplifier activating signal. A sense amplifier circuit starts an operation based on a change in the sense amplifier activating signal, and detects/amplifies a signal read out from the memory cell into the bit line. The delay circuit is configured having a first logical gate circuit and a second logical gate circuit alternately cascade-connected. A second delay time is longer than a first delay time, the second delay time being a time required for an output signal of the second logical gate circuit to switch from a first logical state to a second logical state, and a first delay time being a time required for an output signal of the first logical gate circuit to switch from a first logical state to a second logical state. | 2012-06-14 |
20120147684 | MEMORY REFRESH APPARATUS AND METHOD - A memory refresh apparatus and method are operable such that in response to the receipt of a refresh control signal, a plurality of refresh control signals is sent to the memory circuits at different times. | 2012-06-14 |
20120147685 | SEMICONDUCTOR STORAGE DEVICE - A semiconductor storage device including an open bit line core architecture includes a plurality of array areas, wherein each of the array areas includes two redundant array blocks, a plurality of real array blocks, and a power supply capacity control unit. The two redundant array blocks contain only redundant word lines and located in edge portions at both ends of the array area, and the plurality of real array blocks contain only real word lines and arranged between the two redundant array blocks by interposing a sense amplifier in alternating fashion. The power supply capacity control unit is configured to increase power supply capacity for a first array area when word line redundancy switching is performed in the first array area to replace any one of the real word lines with a corresponding one of the redundant word lines. | 2012-06-14 |
20120147686 | SEMICONDUCTOR DEVICE HAVING HIERARCHICAL BIT LINE STRUCTURE AND CONTROL METHOD THEREOF - Disclosed herein is a semiconductor device comprising a global bit line and a local bit line, and a switch coupled therebetween. Upon performing a precharge operation, a precharge voltage is supplied to the global bit line with turning the switch ON, so that the local bit line receives the precharge voltage through the global bit line and the switch, and after a lapse of a predetermined time, a precharge voltage is further supplied to the local bit line without an intervention of the global bit line and the switch. | 2012-06-14 |
20120147687 | SEMICONDUCTOR MEMORY DEVICE - A row decoder is disposed on a side of a memory cell array in a column direction and supplies one of word lines with a first drive signal for selecting one of memory cells. A dummy word line is formed extending in the column direction. A dummy bit line is formed extending in a row direction. At least one of the dummy word line and the dummy bit line is disposed outside of the memory cell array. The row decoder outputs a second drive signal toward a sense amplifier circuit via the dummy bit line and the dummy word line. | 2012-06-14 |
20120147688 | INTEGRATED CIRCUITS, SYSTEMS, AND METHODS FOR REDUCING LEAKAGE CURRENTS IN A RETENTION MODE - An integrated circuit includes at least one memory array for storing data. A first switch is coupled with the memory array. A first power line is coupled with the first switch. The first power line is operable to supply a first power voltage. A second switch is coupled with the memory array. A second power line is coupled with the second switch. The second power line is operable to supply a second power voltage for retaining the data during a retention mode. A third power line is coupled with the memory array. The third power line is capable of providing a third power voltage. | 2012-06-14 |
20120147689 | THREE DIMENSIONAL NON-VOLATILE STORAGE WITH MULTI BLOCK ROW SELECTION - A three-dimensional array adapted for memory elements that reversibly change a level of electrical conductance in response to a voltage difference being applied across them. Memory elements are formed across a plurality of planes positioned different distances above a semiconductor substrate. Bit lines to which the memory elements of all planes are connected are oriented vertically from the substrate and through the plurality of planes. | 2012-06-14 |
20120147690 | MEMORY ACCESSING DEVICE - A memory accessing device includes a generator which generates K (K: an integer equal to or more than two) of address coefficients corresponding to a first mode whereas generates L (L: an integer more than K) of address coefficients corresponding to a second mode. A first converter converts each value of the address coefficients generated by the generator into a value of 1/M (M: an integer equal to or more than two). A creator creates address information based on the address coefficients generated by the generator corresponding to the first mode whereas creates address information based on address coefficients converted by the first converter corresponding to the second mode. An outputter outputs the address information created by the creator in order to access a memory provided with a plurality of addresses each of which has a bit width equivalent to any one of N bits and N/M bits. | 2012-06-14 |
20120147691 | SEMICONDUCTOR STORAGE DEVICE AND MEMORY SYSTEM - A semiconductor storage device includes an external terminal to which a first signal is supplied, a core circuit, and an access operation control circuit that generates a signal indicating an access operation mode to the core circuit for subsequent cycles based on a pulse width of the first signal. | 2012-06-14 |
20120147692 | SEMICONDUCTOR DEVICE OUTPUTTING READ DATA IN SYNCHRONIZATION WITH CLOCK SIGNAL - A semiconductor device is provided with a clock output control circuit which supplies a long-period clock signal having a period longer than an internal clock signal within an active period and supplies the internal clock signal within a read period subsequent to the active period, a clock transfer circuit which transfers the internal clock signal and the long-period clock signal outputted from the clock output control circuit, a data input/output terminal, and an input/output circuit which outputs read data to the data input/output terminal in synchronization with the internal clock signal having been transferred by the clock transfer circuit. | 2012-06-14 |
20120147693 | ICE-SHAVING COCKTAIL SHAKER - Ice-shaving cocktail shaker. In at least one exemplary embodiment of a cocktail shaker of the present disclosure, the cocktail shaker comprises a container sized and shaped to receive a quantity of ice and optionally a quantity of liquid, and at least one shaver insert positioned within the container, the at least one shaver insert configured to shave some or all of the quantity of ice when the ice is shaken within the container. In another embodiment, the at least one shaver insert defines at least one cutter portion configured to shave some or all of the quantity of ice when the ice is shaken within the container. In yet another embodiment, the at least one cutter portion is relatively sharp. | 2012-06-14 |
20120147694 | MIXER FOR A BEVERAGE FILLING PLANT - A mixer for mixing and conveying different fluids for a beverage filling plant, with at least one first container section for receiving a first starting fluid, with a second container section for receiving a second starting fluid. A first pump is disposed in a first conduit leading out of the first container section for supplying the first starting fluid to a mixing area, and a second pump is disposed in a second conduit leading out of the second container section for supplying the second starting fluid to the mixing area. The first pump and the second pump are driven by one synchronous motor each and each synchronous motor is connected to a frequency converter, and the first and the second container sections are in one common container. Also, a beverage filling plant with such a mixer and a method of operating such a beverage filling plant are disclosed. | 2012-06-14 |
20120147695 | FEEDER WITH VARIABLE RHOMBOIDAL WALL - A feeder with variable rhomboidal walls includes a base housing, a soft hopper, a plurality of extrusion mechanisms, a pusher screw pole, a motor, and a decelerator. The extrusion mechanisms are respectively provided at four appropriate positions of the soft hopper, and are activated by protruding wheels with the aid of the motor in conjunction with the decelerator, so that the four extrusion mechanisms operate in pairs to squeeze the soft hopper while rendering a rhomboidal space change. Accordingly, a bridge effect associated with the prior art is eliminated to allow a raw material to fall and then to be dispensed by the pusher screw rod for further processing. | 2012-06-14 |
20120147696 | AUTOMATIC POT STIRRER - An automatic pot stirrer is provided that has a mount assembly. The mount assembly is mounted on a pot plate having slider clamps. The slider clamps engage the rim of the pot and are designed to accommodate differently dimensioned pots. The mount assembly supports a shaft that is operatively coupled to a motor at one end and threaded to a block at the other end. The block has opposed first and second block end walls and opposed first and second block paddle walls to which are connected paddles. The first and second block paddle walls may be disposed at about a forty-five degree angle to a second block end wall. The paddles are disposed at about a forty-five degree angle to the second block end wall such that the paddles lift food product from the bottom of the pot during operation of the automatic pot stirrer. | 2012-06-14 |
20120147697 | STIRRING MECHANISM WITH MAGNET FORCE - The present invention provides a stirring mechanism with magnetic force. It has a central rotary arm with permanent magnet, as well as a plurality of lever arms each having one permanent magnet respectively. A track disk rotates synchronously with the central rotary arm. | 2012-06-14 |
20120147698 | LARGE-AREA ULTRASOUND CONTACT IMAGING - An embodiment is a method and apparatus for ultrasonic contact imaging. A thin-film transistor (TFT) array is deposited on a substrate. A receiver having a plurality of receiver elements is deposited on the TFT array to receive a received signal. A transmitter adjacent to the receiver generates a transmit signal at an ultrasonic frequency. The transmit signal is reflected from a surface to produce a reflected signal. The received signal is a superposition of the transmit signal and the reflected signal as result of interference. The received signal is representative of differences in acoustic impedances across the surface. | 2012-06-14 |
20120147699 | DISTANCE- AND FREQUENCY-SEPARATED SWEPT-FREQUENCY SEISMIC SOURCES - There is provided a method of seismic acquisition that utilizes a bank of restricted-bandwidth swept-frequency sub-band sources as a seismic source. Each seismic source will cover a restricted sub-band of frequencies, with all the sources taken together covering the full frequency range. Adjacent frequency bands may partially overlap, but non-adjacent frequency bands should not. The sources may be divided into two or more groups, with no sources covering adjacent frequency bands being placed in the same group. The sources within a group can then be separated by bandpass filtering or by conventional simultaneous source-separation techniques. The source groups may be operated simultaneously but separated in space, and the individual sources themselves may each operate independently, on a sweep schedule customized for that particular source. | 2012-06-14 |
20120147700 | Determining Streamer Depth and Sea Surface Profile - A technique includes receiving data indicative of acoustic measurements acquired by receivers disposed on a seismic receiver spread including at least one streamer. The technique includes processing the data in a machine to determine a depth and/or shaped of the spread. | 2012-06-14 |
20120147701 | SEISMIC ACQUISITION METHOD AND SYSTEM - The maximum output of a seismic source array may be reduced by activating the individual seismic sources within these seismic source array in a pattern that is extended in time rather than by the presently employed conventional simultaneous activation of a large number of individual seismic sources. Methods are disclosed which take data shot with patterned sources and may use a sparse inversion method to create data with the about same image quality as that of conventional sources. In this manner the output of the maximum impulse of a seismic source array may be reduced by an amplitude factor of about 10 in the examples shown here, corresponding to a reduction of about 20 dB while maintaining virtually the same seismic image quality. The disclosed methods may be used in combination with any simultaneous sourcing technique. In addition, the disclosed methods may be used with a plurality of source arrays. | 2012-06-14 |
20120147702 | FILTERING ACOUSTIC WAVEFORMS IN DOWNHOLE ENVIRONMENTS - Methods and apparatus to filter acoustic waveforms in downhole environments are described. An example method involves receiving acoustic waveform data representing acoustic signals traversing at least a portion of a borehole adjacent a subterranean formation and performing a direct transform operation on the acoustic waveform data to generate wavelet map data. The wavelet map data comprises a time-frequency representation of the acoustic waveform data. The example method also involves identifying a waveform of interest via the wavelet map data, extracting data associated with the waveform of interest from the wavelet map data, generating filtered wavelet map data based on the extracted data, and performing an inverse transform operation on the filtered wavelet map data to generate filtered acoustic waveform data | 2012-06-14 |
20120147703 | METHODS AND APPARATUS FOR IMPROVED ACOUSTIC DATA ACQUISITION - A technique is designed to facilitate obtaining of acoustic data. The technique comprises traversing a tool through a subterranean formation from a first depth to subsequent depths. The tool receives a seismic signal during pre-determined time windows. The seismic signal is generated by a seismic source which is activated at varying times relative to the predetermined time windows based on the depth of the tool. | 2012-06-14 |
20120147704 | Integrated Formation Modeling Systems and Methods - Integrated formation modeling systems and methods are described. An example method of performing seismic analysis of a subterranean formation includes obtaining seismic data of the formation, obtaining fluid from the formation and analyzing at least some of the fluid to determine a fluid parameter. The example method additionally includes generating a model of the formation based at least on the seismic data and modifying the model based on the fluid parameter. | 2012-06-14 |
20120147705 | Occupancy Sensing With Selective Emission - An occupancy sensing system includes a driver to emit energy in a space, and a sensor to detect energy reflected within the space. An electrical load for the space is controlled in response to an occupancy condition determined in response to the detected energy. The driver may be selectively de-energized. In some embodiments, the driver may be de-energized during all or a portion of an unoccupied period. In other embodiments, the driver may be de-energized during all or a portion of an occupied period. In some further embodiments, the driver may be de-energized in response to detecting other sources of the type of energy emitted by the driver. | 2012-06-14 |
20120147706 | METHOD FOR MEASURING SEA WAVES BY MEANS OF ULTRASONIC WAVES, AS WELL AS SEA WAVE MEASURING SYSTEM - A method for measuring sea waves includes: transmitting ultrasonic waves from an ultrasonic transmitter | 2012-06-14 |
20120147707 | PARAMETRIC TRANSDUCER SYSTEMS AND RELATED METHODS - A method of optimizing a parametric emitter system having a pot core transformer coupled between an amplifier and an emitter, the method comprising: selecting a number of turns required in a primary winding of the pot core transformer to achieve an optimal level of load impedance experienced by the amplifier; and selecting a number of turns required in a secondary winding of the pot core transformer to achieve electrical resonance between the secondary winding and the emitter. | 2012-06-14 |
20120147708 | PROXIMITY SENSOR USED BY AN OPERATION ROBOT AND METHOD OF OPERATING THE PROXIMITY SENSOR - Described is a proximity sensor used by an operation robot that may measure a proximity distance to an object using an ultrasonic wave in a device such as an operation robot, an endoscope, and the like, and a method of operating the proximity sensor which may be used by an operation robot. The proximity sensor used by the operation robot may include an inner wall provided in a circular structure to secure a cavity within the circular structure, a piezoelectric polymer film disposed outside the inner wall to generate an ultrasonic signal, and to sense the ultrasonic signal, and an outer wall disposed outside the piezoelectric polymer film to propagate the ultrasonic signal via an open window, thereby preventing a collision between devices or an unnecessary contact, and providing a more stable operation environment. | 2012-06-14 |
20120147709 | ELECTROMAGNETIC SEISMIC VIBRATOR ARCHITECTURE - Aspects described herein relate to an electromagnetic seismic vibrator (EMSV) architecture that provide wide frequency range operation, ground force application with high fidelity, and low environmental impact. The EMSV architecture can include a base member that can support a force coil and mitigate electrical heating due, at least in part, to spurious currents. The EMSV architecture can include means for restricting movement of a reaction member included in the EMSV architecture relative to the base member. Such means can permit mitigation of damage of the EMSV architecture in scenarios in which control of the EMSV architecture may fail. | 2012-06-14 |
20120147710 | CIPHER WATCH - A watch able to be used as a cryptographic system to encrypt plaintext to ciphertext or decrypt ciphertext to plaintext includes a watch face and a plurality of concentric rings. Each of the plurality of concentric rings is rotatable with respect to the watch face and includes a number of symbols, the number of symbols corresponding to the number of hours represented on the watch face, at least some of the symbols corresponding to letters of an alphabet, characters in a writing system and/or numbers. At least one of the plurality of concentric rings is rotatable in a direction opposite to a direction of at least one other of the plurality of concentric rings. | 2012-06-14 |
20120147711 | TIME INDICATION DEVICE - A time indication device includes a time display body, a controller, an hour hand module, a minute hand module, and a second hand module. The hour hand module includes an hour hand ring placed around the time display body. An hour hand driving unit connected to the controller, and controlled by the controller to drive the hour hand ring to rotate around the time display body. An hour hand projecting unit, fixed to the hour hand ring, for projecting an hour hand on the time display body. Thus, when the hour hand ring is driven by the hour hand driving unit to rotate around the time display body, it is shown that the hour hand moves on the time display body. The minute hand module and the second hand module have nearly the same structure as the hour hand module. | 2012-06-14 |
20120147712 | Monitoring apparatus - A timing apparatus on a container cap which is associated with a standard push pump. The timer is activated by pushing down on the standard pump that then moves a fluid that is held within a chamber having a first compartment and a second compartment The compartments are in fluid communication with each other. The fluid is moved from one compartment to the other compartment when the pump is pushed and the timer works because the fluid returns to the first compartment over some known range of time when the pump is no longer being pushed. | 2012-06-14 |
20120147713 | FLUID INDICATOR - A visual indicator display device includes a bracelet, a transparent capillary chamber, and a displacement member. The transparent capillary chamber is matched to an indicia and has a primary length and a width less than the primary length. The displacement member is functionally disposed at one end of the capillary chamber and is responsive to a measureable input for moving a fluid contained therein a defined amount. | 2012-06-14 |
20120147714 | GEOMETRICAL-FIGURE TIME DISPLAY - A clock configured to display time as a cumulative sum of time display areas of various shapes arranged in various arrangements. The clock is also configured to display complete and fractional hours in any single display area capable of being activated in a random order. | 2012-06-14 |
20120147715 | STRIKING MECHANISM FOR A WATCH OR A MUSIC BOX - The striking mechanism ( | 2012-06-14 |
20120147716 | THERMALLY-ASSISTED MAGNETIC HEAD - A thermally-assisted magnetic head that has an air bearing surface (ABS) facing a recording medium and that performs magnetic recording while heating the recording medium includes: a magnetic recording element that includes a pole of which an edge part is positioned on the ABS and which generates magnetic flux traveling to the recording medium; a waveguide that is configured with a core through which light propagates and a cladding, surrounding a periphery of the core, at least one part of which extends to the ABS; a plasmon generator that faces a part of the core and that extends toward the ABS side; and a bank layer that is positioned between the plasmon generator and the pole, and of which an edge part on the ABS side protrudes relative to the plasmon generator. | 2012-06-14 |
20120147717 | METHOD OF BURN-IN TESTING FOR THERMALLY ASSISTED HEAD - A plurality of laser diode units is tested in a bar state, each of the laser diode units in which a laser diode that includes a first electrode and a second electrode formed on surfaces facing each other and that is mounted on a mounting surface of a submount such that the first electrode faces the mounting surface of the submount. The method includes preparing a bar in which mounting areas each of which includes the laser diode unit formed thereon and dicing margins for separating the bar into the separate laser diode units are alternatively aligned along a longitudinal direction wherein a first pad electrically connected with the first electrode of the laser diode is disposed on the mounting surface of each of the mounting areas of the submounts and a second pad electrically connected to the first pad of either one of the mounting areas that are adjacent to the dicing margin is disposed on the mounting surface of each of the dicing margins of the submounts: contacting sheet-shaped probes to the second electrode and the second pad at a slantwise angle with respect to the second electrode and the second pad, and pressing the probes to the second electrode and the second pad while deforming the probes; and providing a potential difference between the second electrode and the second pad through the probes so that the laser diode emits laser light. | 2012-06-14 |
20120147718 | PATTERNED PERPENDICULAR MAGNETIC RECORDING MEDIUM WITH EXCHANGE-COUPLED COMPOSITE RECORDING STRUCTURE OF A FePt LAYER AND A Co/X MULTILAYER - A bit-patterned media (BPM) magnetic recording disk has discrete data islands with an exchange-coupled composite (ECC) recording layer (RL) formed of a high-anisotropy chemically-ordered FePt alloy lower layer, a lower-anisotropy Co/X laminate or multilayer (ML) upper layer with perpendicular magnetic anisotropy, wherein X is Pt, Pd or Ni, and an optional nonmagnetic separation layer or coupling layer (CL) between the FePt layer and the ML. The FePt alloy layer is sputter deposited onto a seed layer structure, like a CrRu/Pt bilayer, while the disk substrate is maintained at an elevated temperature to assure the high anisotropy field H | 2012-06-14 |
20120147719 | INFORMATION RECORDING APPARATUS AND INFORMATION RECORDING METHOD - An information recording apparatus for recording additional content on a medium on which a title including one or more files is already recorded, includes means for designating a title to be added on the medium; means for transmitting disc package information, the disc package information and unique IDs; means for receiving and additionally recording on the medium the title to be added generated in the content server, file names of files so as not to be the same as the file names of the files constituting the titles already recorded on the medium; means for receiving and additionally recording a new title for display of a menu screen on the medium, which is generated in the content server, so that the title to be added can be selected, on the basis of the disc package information; and means for receiving and additionally recording new disc package information on the medium. | 2012-06-14 |
20120147720 | CIRCUIT FOR GENERATING A SIGNAL FOR CONTROLLING REPRODUCTION OF DATA RECORDED ON AN OPTICAL DISC - According to one embodiment, a circuit for generating a signal has an amplifier, first and second detection circuits, first and second A/D converters, and a digital signal processing circuit. The amplifier amplifies an electric signal corresponding to an intensity of a reflected light from an optical disc. The first detection circuit detects an upper envelope of an output signal from the amplifier, and outputs an upper envelope signal. The second detection circuit detects a lower envelope of an output signal from the amplifier, and outputs a lower envelope signal. The first A/D converter converts the upper envelope signal into a first digital signal. The second A/D converter converts the lower envelope signal into a first digital signal. The digital signal processing circuit performs calculation processing of the first and the second digital signals, and outputs a signal for controlling reproduction of data recorded on the optical disc. | 2012-06-14 |
20120147721 | METHOD FOR IDENTIFYING DISC - A method for identifying a disc is provided. The method comprising steps of: controlling an optical reader to fetch content stored at a selected position and counting time period; stopping counting and acquiring an access time after receiving the error message; determining if the access time is greater than a reference time; identifying the disc as a legitimate disc when the access time is greater than the reference time; and identifying the disc as a pirate disc when the access time is less than the reference time. | 2012-06-14 |
20120147722 | Nanometer Scale Instrument for Biochemically, Chemically, or Catalytically Interacting with a Sample Material - A data storage system that includes a positioning system for positioning the write/read mechanism and the storage medium of the data storage device with respect to each other in first and second predefined directions. In several embodiments, the read/write mechanism is used to mechanically write data to and electrically read data from the storage medium. In still another embodiment, the read/write mechanism is used to optically write data to and electrically read data from the storage medium. In yet another embodiment, the read/write mechanism is acoustically aided in electrically writing data to and reading data from the storage medium. | 2012-06-14 |
20120147723 | INFORMATION RECORDING DEVICE, INFORMATION REPRODUCING DEVICE, RECORDING MEDIUM MANUFACTURING DEVICE, INFORMATION RECORDING MEDIUM, METHOD, AND PROGRAM - An information recording processing constitution realizing both readout difficulty and high-precision readout is provided. Superimposition recording of highly secret additional information such as a cryptographic key in a groove signal recorded on a disk, which superimposition recording realizes both readout difficulty and high-precision readout, can be performed. The groove signal to which a phase error corresponding to a bit value is set is recorded at a time of recording of the additional information, and at a time of readout of the additional information, the phase error of the groove signal in a predetermined section is subjected to an integrating process and the direction of the phase error of the groove signal within each section is determined. The recording and reproduction of the additional information for increasing readout difficulty and realizing high-precision readout is realized by such processes. | 2012-06-14 |
20120147724 | OPTICAL DATA STORAGE MEDIA AND METHODS FOR USING THE SAME - An optical data storage medium is provided. The optical data storage medium includes a polymer matrix; a reactant capable of undergoing a change upon triplet excitation, thereby causing a refractive index change; and a non-linear sensitizer capable of absorbing actinic radiation to cause upper triplet energy transfer to said reactant. The refractive index change capacity of the medium is at least about 0.005. The non-linear sensitizer comprises a triarylmethane dye. | 2012-06-14 |
20120147725 | REPRODUCING APPARATUS AND REPRODUCING METHOD - A reproducing apparatus includes: a first laser irradiation section irradiating an optical recording medium having a bulk recording layer and recording marks formed by focusing a laser beam on each predetermined layer position in the recording layer, with a first laser beam through an objective lens; a focus position adjusting section adjusting a focus position of the first laser beam; a beam receiving section receiving a reflected beam of the first laser beam from the marks and generating a light receiving signal; a reproducing section reproducing information recorded with the marks based on the light receiving signal; and a control section performing control to allow the focus position in reproduction of the information to correspond to a position shifted by a certain distance to an upper layer side from a focus position of the laser beam in forming the mark at the layer positions as a reproducing object. | 2012-06-14 |
20120147726 | OPTICAL HEAD AND OPTICAL INFORMATION DEVICE - Provided are an optical head and an optical information device capable of inhibiting the temperature rise of a photodetector. An optical head ( | 2012-06-14 |
20120147727 | VERTICAL CAVITY SURFACE EMITTING LASER, VERTICAL-CAVITY-SURFACE-EMITTING-LASER DEVICE, OPTICAL TRANSMISSION APPARATUS, AND INFORMATION PROCESSING APPARATUS - A vertical cavity surface emitting laser includes a semiconductor substrate, a first semiconductor multilayer film reflector of a first conductivity type laminated on the semiconductor substrate, a resonator, and a second semiconductor multilayer film reflector of a second conductivity type laminated on the resonator. In each of the first and second semiconductor multilayer film reflectors, a pair of a high-refractive-index layer and a low-refractive-index layer is stacked. The resonator includes an active layer laminated on the first semiconductor multilayer film reflector. The resonator includes a pair of spacer layers and a resonator extending region. A composition of at least a layer included in the resonator extending region is different from any of compositions of the semiconductor substrate, the first semiconductor multilayer film reflector, and the second semiconductor multilayer film reflector. | 2012-06-14 |
20120147728 | HIGH DENSITY DATA STORAGE MEDIUM, METHOD AND DEVICE - A composition of matter for the recording medium of nanometer scale thermo-mechanical information storage devices and a nanometer scale thermo-mechanical information storage device. The composition includes: one or more polyaryletherketone copolymers, each of the one or more polyaryletherketone copolymers comprising (a) a first monomer including an aryl ether ketone and (b) a second monomer including an aryl ether ketone and a first phenylethynyl moiety, each of the one or more polyaryletherketone copolymers having two terminal ends, each terminal end having a phenylethynyl moiety the same as or different from the first phenylethynyl moiety. The one or more polyaryletherketone copolymers are thermally cured and the resulting cross-linked polyaryletherketone resin used as the recording layer in an atomic force data storage device. | 2012-06-14 |
20120147729 | PORTABLE ELECTRONIC DEVICE WITH DISC DRIVE - A portable electronic device includes a first main body and a disc drive. The disc drive is received in the first main body. The disc drive includes a second main body, a driving element, and a laser assembly. The second main body is rotatably received in the first main body. The driving element is arranged on the second main body for driving a disc. The laser assembly includes a laser slidably received in the first main body. The disc drive is in a use state when the second main body is rotated to cause the driving element to face the laser. | 2012-06-14 |
20120147730 | WIRELESS COMMUNICATIONS SYSTEM WITH SECONDARY SYNCHRONIZATION CODE BASED ON VALUES IN PRIMARY SYNCHRONIZATION CODE - A wireless communication system. The system comprises transmitter circuitry (BST | 2012-06-14 |
20120147731 | APPARATUS OF MULTIPLEXING DATA TRANSMISSION PATH FOR WIRELESS SENSOR NETWORK - The present invention is to provide a method and apparatus for multiplexing a sync node and a gateway of a wireless sensor network, which is capable of allowing communication of the wireless sensor network to be normally performed by multiplexing paths of the sync node and the gateway of the wireless sensor network even in the case where any one of the sync node and the gateway abnormally operates and by transmitting upstream data and downstream data through a path selected among the duplexed paths according to characteristics of the wireless sensor network. | 2012-06-14 |
20120147732 | METHOD AND SYSTEM FOR HANDLING ERROR IN LPP MESSAGES EXCHANGE - A system and method for handling an error in a LTE Positioning Protocol (LPP) transaction is provided. The method includes the steps of: receiving, by a receiver, at least one of a plurality of LPP messages from a sender, wherein each of the LPP messages has a sequence number; returning, by the receiver, an acknowledgment to the sender for each of the at least one received LPP message; returning, by the receiver, an error indication to the sender when the receiver detects an error in the at least one received LPP message; and receiving, by the receiver, at least one of the at least one received LPP message retransmitted by the sender. | 2012-06-14 |
20120147733 | Processing Method after Configuration Update Failure and Network Element Device Thereof - The present invention provides a processing method after configuration update failure and a network element device. The method comprises: after a configuration of a first network element device changes, the first network element device sending a configuration update message to all its adjacent network element devices; if the first network element device receives a configuration update failure message returned by any of its adjacent network element devices, and the configuration update failure message does not contain information instructing the first network element device to perform subsequent processing, the first network element device rolling its configuration back to the one prior to configuration update; and the first network element device resending the configuration update message to all its adjacent network element devices in the rolled-back configuration. The method and network element device ensure continuous optimization of the network and enhancing robustness and stability of the system. | 2012-06-14 |
20120147734 | APPARATUS AND METHOD FOR RETRANSMITTING DATA BASED ON HARQ SCHEME IN WIRELESS COMMUNICATION SYSTEM - A method for retransmitting data using an HARQ method and a mobile station using the same in a wireless telecommunications system are disclosed herein. When all bits of a resource index field in an uplink basic assignment A-MAP received from a base station through a specific frame are set to 1, the mobile station may not retransmit an HARQ sub-packet from an uplink subframe within the specific frame. In this case, the mobile station may retransmit an HARQ sub-packet from an uplink subframe within a frame subsequent to the specific frame. At this point, the uplink subframe and resource index of the subsequent frame respectively correspond to the subframe and resource index having the same index and resource index of an uplink subframe predetermined in association with the retransmission of the mobile station in a previous frame. The resource index corresponds to information indicating where the assigned resource is positioned within the corresponding subframe and how large the size of the assigned resource is. Alternatively, the mobile station may receive once again the uplink basic assignment A-MAP, so as to retransmit the HARQ sub-packet from an uplink subframe designated by the uplink basic assignment A-MAP. | 2012-06-14 |
20120147735 | Method and Apparatus for a Ring Network Node to Acquire Protocol Messages - The present invention provides a method and an apparatus for acquiring protocol messages by a ring-network node, including: using dual fields to identify different protocol messages; if a node supporting G.8032v1 receives a Force Switch (FS) or Manual Switch (MS) protocol message, determining that message is a Signal Fail (SF) protocol message according to an identifier; a node supporting G.8032v2 determining that the received protocol message is an SF or MS or FS protocol message according to the identifier. The method of the present invention enables the nodes in a ring network to accurately control the state of their own ports, thereby avoiding the case that multiple blocking points appear in the ring network and improving the network performance. | 2012-06-14 |
20120147736 | Minimizing the Number of Not-Via Addresses - In an embodiment, a method comprises determining a set of protected components that are associated with a notifying node; determining a single network repair address for the set of protected components, wherein the single network repair address is for use in response to unavailability of any of the protected components when transmitting network traffic to the notifying node; assigning the single network repair address to each of the protected components; wherein the notifying node is an internetworking device and wherein the method is performed by one or more processors. | 2012-06-14 |
20120147737 | SYSTEM AND METHOD FOR PROVIDING IMPROVED FAILOVER PERFORMANCE FOR PSEUDOWIRES - Grouping pseudowires based on hardware interfaces and configured control paths enables improved pseudowire failover performance. Signaling status changes (e.g., from standby to active status) is facilitated by using group IDs for the pseudowire groups, thereby enabling improved failover performance when there is disruption in the network. | 2012-06-14 |
20120147738 | COMMUNICATING INFORMATION IN AN INFORMATION HANDLING SYSTEM - A node communicates with a first network through a link aggregation of at least one primary port and at least one backup port. The link aggregation is for rerouting a communication with the first network to occur through the backup port in response to a malfunction in the communication through the primary port. In response to a malfunction in the communication through the backup port, the node communicates with a second network. | 2012-06-14 |
20120147739 | System and method for assisting user in troubleshouting network connection problems - The present invention is to provide a system for assisting a user in troubleshooting network connection problems, which includes a main terminal device (e.g., a computer) and a mediation device (e.g., a router) connected to the main terminal device and storing an assisting web page. Upon receiving a web page request instruction from the main terminal device, the mediation device redirects the web page request instruction to a website address. When the mediation device determines that itself is not connected to the Internet (i.e., a network connection problem occurs), the mediation device will send the assisting web page to the main terminal device. The assisting web page is displayed by the main terminal device through a browser thereof, so as for the user to troubleshoot the network connection problem according to the steps specified in the assisting web page (e.g., to perform a line inspection, a light signal check, etc.). | 2012-06-14 |
20120147740 | TECHNIQUE FOR DUAL HOMING INTERCONNECTION BETWEEN COMMUNICATION NETWORKS - A dynamically self-configuring and re-configuring dual homing connection (DH) for loop-free data communication between a first communication network and a second communication network, the DH acquiring either a Symmetrical configuration or an Asymmetrical configuration. | 2012-06-14 |
20120147741 | Method and system for ethernet path protection switching - A switching method for Ethernet path protection is provided in the disclosure. The method includes: setting a group of Traffic Engineering Service Instances (TESIs) protected by a protection group; detecting statuses of a working entity and a protection entity; implementing the path protection switching according to an outbound port configured for Ethernet Switching Path (ESP) of the TESI at the endpoint of the protection group and in conjunction with a corresponding protection switching mechanism selected in current status detection. A switching system for Ethernet path protection is also provided in the disclosure, wherein a switching unit is configured to implement the path protection switching according to the outbound port configured for the ESP of the TESI at the endpoint of the protection group and in conjunction with the corresponding protection switching mechanism selected in current status detection. The method and system of the disclosure can enhance the speed of fault recovery, reduce nodes for the protection switching, be beneficial to network optimization, and ensure the reliability of end-to-end traffic. | 2012-06-14 |
20120147742 | APPARATUS AND METHOD FOR PACKET FORWARDING - A method for packet forwarding, including receiving packets; extracting a test packet containing information indicating a path to be verified from the received packets; and forwarding the test packet to the path to be verified, rather than to a first path to which the received packets are forwarded, based on the information indicating the path to be verified contained in the test packet. | 2012-06-14 |
20120147743 | DYNAMIC CONNECTION ADMISSION CONTROL TO ENFORCE SERVICE LEVEL AGREEMENTS IN MULTICAST NETWORKS - A method for networked communications includes determining a group identifier associated with a received request for multicast data, determining an available upstream bandwidth and an available downstream bandwidth, adding an entry for the identified group into a multicast forwarding table, allocating bandwidth from the available upstream bandwidth and available downstream bandwidth, the allocated bandwidth corresponding to bandwidth required by the requested multicast data, and forwarding the received request to an upstream network destination. The method includes, if no response is received in response to the received request within a designated timeout period, removing the entry for the identified group in the multicast forwarding table, and restoring the allocated bandwidth to the available upstream bandwidth and available downstream bandwidth. | 2012-06-14 |
20120147744 | TIME AND DATA RATE POLICING - A non-transitory computer-readable medium includes instructions for receiving a message associated with a session with a user device; determining that a quantity of tokens, to be used to process the message, is less than another quantity of tokens stored in a memory; determining that a session time is less than a threshold based on the determination that the quantity of tokens is less than the other quantity of tokens; determining that a violation has occurred when a time interval is greater than an interval threshold based on the determination that the session time is less than the threshold, where the time interval is from a prior time when another message, associated with the session, was received to a time that the message was received, and where the determining includes incrementing a quantity of violations associated with the session; outputting the message when the quantity of violations is not greater than a violation threshold; and dropping the message when the quantity of violations is greater than the violation threshold. | 2012-06-14 |