24th week of 2017 patent applcation highlights part 55 |
Patent application number | Title | Published |
20170169975 | TRIMMING APPARATUS - A trimming apparatus for adjusting an electric property of a trimming object circuit. The trimming apparatus includes a data input pad that receives an input of serial data, a shift register that outputs parallel setting data by shifting the received serial data, a trimming data generating circuit, and a cutting control circuit that controls application of an electric signal to the trimming data generating circuit. The trimming data generating circuit includes a plurality of trimming elements, each having a conductive part cuttable by a flow of the electric signal, a plurality of pull-up resistors respectively connected to high potential sides of the trimming elements, and a plurality of switches respectively connected to low potential sides of the trimming elements. The trimming data generating circuit is configured to generate trimming data for the trimming object circuit by switching the plurality of switches in accordance with a level of the setting data. | 2017-06-15 |
20170169976 | SEAMLESS SWITCHOVER SYSTEM AND METHOD - A system and method provide seamless control switchover through an input coupled to a power line and a safety apparatus that actuates if the input remains de-energized for a first time interval. Each of a plurality of subsystems has a control unit that controls a power source to energize the power line and is capable of transitioning between master and slave states. A first switch or second and third switches in series couple the power source to the power line. The first switch is closed during master state operation. The second switch is closed during slave operation and the third switch is open if any subsystem control unit is in master state. The system is configured to open or close the first switch, the second switch, or the third switch responsive to a transition of a control unit to or from master state within the first time interval. | 2017-06-15 |
20170169977 | POWER BREAKING APPARATUS AND MOBILE PHONE - Disclosed relates to a power breaking apparatus and a mobile phone. The power breaking apparatus includes: a power source PCB electrically connected with an anode and a cathode of a power source; a breaker electrically connected with the power source PCB, wherein the breaker is arranged with a feeding device comprising a first jack socket and a second jack socket, and when the first jack socket is connected with the second jack socket, then a power supply line of the power source PCB is cut off; and a short-circuit plug arranged with a first plug and a second plug, both of which are electrically connected. The mobile phone includes the power breaking apparatus according to the embodiment of the disclosure. | 2017-06-15 |
20170169978 | METHOD OF MANUFACTURING A CIRCUIT BREAKER AND METHOD OF MANUFACTURING A BATTERY PACK INCLUDING THE CIRCUIT BREAKER - The circuit breaker is fabricated by an assembly step that makes a circuit breaker assembly with a moving contact metal plate, stationary contact metal plate, and bimetallic strip disposed in prescribed locations in an external case; and an anneal step that introduces the circuit breaker assembly made in the assembly step into an anneal oven, heats the circuit breaker assembly in the anneal oven and then cools it to anneal both the moving contact metal plate and the bimetallic strip and produce a heat-treated circuit breaker. | 2017-06-15 |
20170169979 | RETROFIT CAFI/GFI REMOTE CONTROL MODULE - A retrofit CAFI/GFI remote control module may provide dual function protection for simple thermal-magnetic circuit breakers in a residential load center with arc fault and ground fault protection. The module provides line sensors and electronic processing to detect ground faults or arc faults, or both, and operates a bistable relay between the branch breaker and the load to open the circuit, which can then be remotely or manually reset. | 2017-06-15 |
20170169980 | DEVICE FOR MONITORING A CURRENT OF A PRIMARY CONDUCTOR WITH RESPECT TO A PREDETERMINED CURRENT THRESHOLD, AND RELATED TRIP ASSEMBLY AND SWITCHING DEVICE - A device for monitoring a current in a primary conductor with respect to a predetermined current threshold, comprising:
| 2017-06-15 |
20170169981 | THERMIONIC EMISSION FILAMENT, QUADRUPOLE MASS SPECTROMETER AND RESIDUAL GAS ANALYZING METHOD - In order to provide a thermionic emission filament capable of ensuring a long life and improving an analysis accuracy of a mass spectrometer using the thermionic emission filament, in the thermionic emission filament including a core member through which electric current flows and an electron emitting layer which is formed so as to cover a surface of the core member, the electron emitting layer is configured to have denseness for substantial gas-tight integrity. | 2017-06-15 |
20170169982 | AXIAL STRAPPING OF A MULTI-CORE (CASCADED) MAGNETRON - The present disclosure is directed to axial strapping of a multi-core (cascaded) magnetron. The multi-core (cascaded) magnetron includes a cathode and a plurality of cores (anodes) arranged in an axial direction along the cathode. Each of the cores may have a plurality of vanes arranged periodically in an azimuthal direction along a circumference of the cathode and forming by such a way a plurality of resonant cavities. The multi-core (cascaded) magnetron further includes groups of axial straps coupling each of the cores together in the axial direction along the cathode. For example, a first group of axial straps couple the first plurality of vanes of a first core to the second plurality of vanes of a second core. In an embodiment, the axial straps are configured to provide phase synchronization of electromagnetic oscillations induced inside each of the plurality of cores. | 2017-06-15 |
20170169983 | EMITTER AND X-RAY TUBE DEVICE - An emitter for an X-ray tube device is configured to irradiate an anode with electrons for X-ray emission. The emitter includes an electron emission portion to be heated by an electric current, a current application leg for supplying the electric current to the electron emission portion, a support leg, a current application leg fixing portion for supporting the current application leg and supplying the electric current to the current application leg, and a support leg fixing portion for supporting the support leg. At least one of materials and shapes are different between the current application leg fixing portion and the support leg fixing portion so that a difference in an amount of thermal deformation between the current application leg and the support leg in a direction vertical to the electron emission portion is reduced when the electron emission portion is heated. | 2017-06-15 |
20170169984 | ANTIWETTING COATING FOR LIQUID METAL - Technology is described for an antiwetting coating attached to a substrate (e.g., metal substate) on a liquid metal container. In one example, the liquid metal container includes a first enclosure member, a second enclosure member, liquid metal, and an antiwetting coating. The first enclosure member includes a first substrate with a first surface. The second enclosure member includes a second substrate with a second surface. The first enclosure member is positioned proximate to the second enclosure member such that a gap is formed between the first surface and the second surface. The liquid metal positioned within the gap. An antiwetting coating attached to the first surface and/or the second surface. The antiwetting coating includes chromium nitride (CrN), dichromium nitride (Cr | 2017-06-15 |
20170169985 | ROTATING ANODE AND METHOD FOR PRODUCING A ROTATING ANODE - The present invention relates to a rotating anode ( | 2017-06-15 |
20170169986 | SELF-CLEANING LINEAR IONIZING BAR AND METHODS THEREFOR - A self-cleaning linear ionizer with at least one ionizing electrode, at least one electrode-cleaner, and at least two spool assemblies is disclosed. The electrode has opposing ends and defines an axial working length with a surface that produces an ion cloud and develops degradation products with use. Although the working length of the electrode is stationary, the electrode is movable. The electrode-cleaner is also stationary and selectively engages the electrode along its working length. The opposing ends of the electrode are fixed to the opposing spool assemblies which selectively move the ionizing electrode such that the electrode-cleaner removes at least some of the surface degradation products from the electrode during movement. Methods of using the disclosed ionizer have self-cleaning and ionization modes of operation, which may occur cyclically, alternately, or simultaneously, are also disclosed. | 2017-06-15 |
20170169987 | PARALLELIZING ELECTROSTATIC ACCELERATION/DECELERATION OPTICAL ELEMENT - Provided herein are approaches for controlling a charged particle beam using a series of electrodes including a plurality of different shapes. In one approach, an electrostatic optical element includes a first set of electrodes having a first electrode shape for parallelizing and deflecting the charged particle beam using a first set of electrodes having a first electrode shape, such as a concave or convex profile. The electrostatic optical element further includes a second set of electrodes adjacent the first set of electrodes for accelerating or decelerating the charged particle beam along a beamline, wherein the second set of electrodes include a cylindrical shape. In one approach, a power supply is electrically connected to the first and second sets of electrodes, the power supply arranged to enable independent voltage/current control. | 2017-06-15 |
20170169988 | CHARGED PARTICLE BEAM DEVICE AND INSTALLATION METHOD - Provided is a charged particle beam device that is small, high performance, and easy to transport. A charged particle beam device ( | 2017-06-15 |
20170169989 | SAMPLE HOLDER FOR SCANNING ELECTRON MICROSCOPY (SEM) AND ATOMIC FORCE MICROSCOPY (AFM) - The present invention refers to a two-systems compact specimen holder (SH) easy to use which enables to analyse the same sample by employing either an atomic force microscope (AFM) or a scanning electron microscope (SEM), by preserving the setting reference of the details for both microscopies, so that it satisfies the requirements of size, conductivity, magnetization, tidiness, reference and adaptability. | 2017-06-15 |
20170169990 | SCANNING ELECTRON MICROSCOPE - The present invention relates to a scanning electron microscope realized to observe a test sample by detecting back-scattered electrons scattered and emitted from a surface of the test sample in the air without a vacuum chamber which is allowed to observe the test sample in a vacuum state the scanning electron microscope can be useful in minimizing dispersion of electrons of the electron beam passing through the shielding film caused due to electron scattering by focusing the electron beam passing through the shielding film on a top surface of the first back-scattered electron detector disposed between the electron gun and the shielding film to pass an electron beam and configured to detect back-scattered electrons scattered from the test sample since the first back-scattered electron detector is provided with the first planar coil having a magnetic field formed thereon. | 2017-06-15 |
20170169991 | PREPARATION OF CRYOGENIC SAMPLE FOR CHARGED-PARTICLE MICROSCOPY - A method of preparing a sample for study in a charged-particle microscope, whereby the sample is subjected to rapid cooling using a cryogen, comprising the following steps:
| 2017-06-15 |
20170169992 | ELECTRON MICROSCOPE DEVICE AND IMAGING METHOD USING SAME - In order to enable high-speed imaging of a wide-field image, the imaging method using the electron microscope comprises: irradiating and scanning a wide-field region of the sample with a low-dose amount of electron beam, and acquiring a wide-field image of the sample; setting, from this wide-field image, a narrow-field region; irradiating and scanning this narrow-field region with a high-dose amount of the electron beam, and acquiring a narrow-field image of the sample; determining the noise-removal parameters for the acquired wide-field image and narrow-field image; performing image quality improvement processing on the wide-field image and the narrow-field image; performing drift correction on the narrow-field image undergone the image quality improvement processing; and combining the narrow-field image undergone this drift correction and the wide-field image in such a manner that the visibility of each is at the same level throughout the entirety of the combined image. | 2017-06-15 |
20170169993 | MULTI CHARGED PARTICLE BEAM APPARATUS, AND SHAPE ADJUSTMENT METHOD OF MULTI CHARGED PARTICLE BEAM IMAGE - A multi charged particle beam apparatus includes a forming aperture array substrate, where there are formed a plurality of first openings and a plurality of second openings on the periphery of the whole plurality of first openings, each being larger than each of the plurality of first openings, to form multi-beams by the plurality of first openings, and to be able to form a plurality of calibration beams by the plurality of second openings, a shutter to select, one by one, one of the plurality of calibration beams formed by passing through the plurality of second openings, in accordance with a slide position, and a detector to detect a secondary electron including a reflected electron generated by scanning a mark by deflecting the selected calibration beam, in the state of all the multi-beams controlled to be OFF. | 2017-06-15 |
20170169994 | DATA PROCESSING METHOD, CHARGED PARTICLE BEAM WRITING METHOD, AND CHARGED PARTICLE BEAM WRITING APPARATUS - In one embodiment, a data processing method is for creating write data from design data, and registering the write data into a writing apparatus. The method includes applying, to a plurality of pieces of first frame data into which first chip data of the design data is divided, a plurality of conversion processes to create the write data, and applying a plurality of pre-processes to a plurality of pieces of second frame data into which second chip data of the write data is divided, and registering the second chip data into the writing apparatus. The plurality of conversion processes and the plurality of pre-processes are each performed in a pipeline processing on a per-frame basis. The write data is registered into the writing apparatus on a per-chip basis, on a per-virtual chip basis, or on a per-frame basis. The virtual chip includes a plurality of chips combined together. | 2017-06-15 |
20170169995 | Apparatuses And Methods For Avoiding Electrical Breakdown From RF Terminal To Adjacent Non-RF Terminal - An isolation system includes an input junction coupled to one or more RF power supplies via a match network for receiving radio frequency (RF) power. The isolation system further includes a plurality of channel paths connected to the input junction for distributing the RF power among the channel paths. The isolation system includes an output junction connected between each of the channel paths and to an electrode of a plasma chamber for receiving portions of the distributed RF power to output combined power and providing the combined RF power to the electrode. Each of the channel paths includes bottom and top capacitors for blocking a signal of the different type than that of the RF power. The isolation system avoids a risk of electrical arcing created by a voltage difference between an RF terminal and a non-RF terminal when the terminals are placed proximate to each other. | 2017-06-15 |
20170169996 | PLASMA PROCESSING APPARATUS AND PLASMA PROCESSING METHDO - In one embodiment, a plasma processing apparatus includes: a chamber; an introducing part; a counter electrode; a high-frequency power source; and a plurality of low-frequency power sources. A substrate electrode is disposed in the chamber, a substrate is directly or indirectly placed on the substrate electrode, and the substrate electrode has a plurality of electrode element groups. The introducing part introduces process gas into the chamber. The high-frequency power source outputs a high-frequency voltage for ionizing the process gas to generate plasma. The plurality of low-frequency power sources apply a plurality of low-frequency voltages of 20 MHz or less with mutually different phases for introducing ions from the plasma, to each of the plurality of electrode element groups. | 2017-06-15 |
20170169997 | PLASMA ETCHING METHOD, PLASMA ETCHING DEVICE, PLASMA PROCESSING METHOD, AND PLASMA PROCESSING DEVICE - A plasma etching method includes a first step of attracting a substrate onto a monopolar electrostatic chuck in a first plasma, which is a plasma of a noble gas, and stopping generation of the first plasma after the attracting of the substrate, and a second step of etching the substrate in a second plasma, which is a plasma of a halogen-based etching gas, and stopping generation of the second plasma after the etching of the substrate. In the first step, the generation of the first plasma is stopped when a positive voltage is applied from the monopolar electrostatic chuck to the substrate. In the second step, the generation of the second plasma is stopped when a negative voltage is applied from the monopolar electrostatic chuck to the substrate. | 2017-06-15 |
20170169998 | In-Cu Alloy Sputtering Target And Method For Producing The Same - The purpose of the present invention is to provide an In—Cu alloy sputtering target member having high compositional homogeneity in the thickness direction. The present invention provides a sputtering target member having a composition containing from 1 to 70 at. % of Cu relative to a total number of atoms of In and Cu, the balance being In and inevitable impurities, wherein the target member fulfills 0.95≦A/B≦1, where A represents a Cu atomic concentration relative to the total number of atoms of In and Cu in one half of a thickness direction; B represents a Cu atomic concentration relative to the total number of atoms of In and Cu in the other half of the thickness direction; and B≧A; and wherein a number of pores having a size of 100 μm or more is less than 10/cm | 2017-06-15 |
20170169999 | Compact Mass Spectrometer - A miniature mass spectrometer is disclosed comprising an atmospheric pressure ionisation source and a first vacuum chamber having an atmospheric pressure sampling orifice or capillary, a second vacuum chamber located downstream of the first vacuum chamber and a third vacuum chamber located downstream of the second vacuum chamber. An ion detector is located in the third vacuum chamber. A first RF ion guide is located within the first vacuum chamber and a second RF ion guide is located within the second vacuum chamber. The ion path length from the atmospheric pressure sampling orifice or capillary to an ion detecting surface of the ion detector is ≦400 mm. The mass spectrometer further comprises a tandem quadrupole mass analyser, a 3D ion trap mass analyser, a 2D or linear ion trap mass analyser, a Time of Flight mass analyser, a quadrupole-Time of Flight mass analyser or an electrostatic mass analyser arranged in the third vacuum chamber. The product of the pressure P | 2017-06-15 |
20170170000 | ION SOURCE, QUADRUPOLE MASS SPECTROMETER AND RESIDUAL GAS ANALYZING METHOD - In order to attain a main objective of the present invention to provide an ion source capable of efficiently extracting ions, the ion source is configured to include: a conductive tubular body having an ion emitting aperture in a tip surface thereof and a penetration portion in a side wall thereof allowing thermo-electrons to pass through from an outside toward an inside; a mesh surrounding an outer periphery of the penetration portion; and a thermionic emission filament surrounding an outer periphery of the mesh, such that the thermo-electrons emitted from the thermionic emission filament pass through the mesh and reach the inside of the conductive tubular body through the penetration portion. | 2017-06-15 |
20170170001 | MICROSCALE MASS SPECTROMETRY SYSTEMS, DEVICES AND RELATED METHODS - Mass spectrometry systems or assemblies therefore include an ionizer that includes at least one planar conductor, a mass analyzer with a planar electrode assembly, and a detector comprising at least one planar conductor. The ionizer, the mass analyzer and the detector are attached together in a compact stack assembly. The stack assembly has a perimeter that bounds an area that is between about 0.01 mm | 2017-06-15 |
20170170002 | ELECTRODELESS LAMP - An electrodeless lamp driven by a microwave generator is disclosed. The electrodeless lamp includes a first infill composed of mercury-free metal halide and provides a continuous full spectrum radiation including ultraviolet ray, visible light, and infrared ray. Thereby, the electrodeless lamp, which meets the standard of AM 1.5 G, has advantages of environmental friendliness, high efficacy lighting, long service life, and low light decay, and therefore, have become applicable in the field of solar simulators. | 2017-06-15 |
20170170003 | SACRIFICIAL LAYER FOR POST-LASER DEBRIS REMOVAL SYSTEMS AND METHODS - A method of removing post-laser debris from a wafer includes, for an embodiment, forming a sacrificial layer over a layer to be patterned, patterning the sacrificial layer and the layer to be patterned using laser ablation, and removing the sacrificial layer and debris deposited on the sacrificial layer with water. The sacrificial layer includes a water soluble binder and a water soluble ultraviolet (UV) absorbent. Systems for removing the post-laser debris are also described. | 2017-06-15 |
20170170004 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, SUBSTRATE PROCESSING APPARATUS, AND RECORDING MEDIUM - There is provided a method of manufacturing a semiconductor device, including forming a film on a substrate by performing a cycle a predetermined number of times, the cycle including non-simultaneously performing supplying a precursor gas to the substrate; and supplying a first oxygen-containing gas to the substrate. Further, the act of supplying the precursor gas includes a time period in which the precursor gas and a second oxygen-containing gas are simultaneously supplied to the substrate. | 2017-06-15 |
20170170005 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device includes a semiconductor region forming process, a cleaning process, a surface roughness uniformizing process, and an electrode forming process. As the semiconductor region forming process, semiconductor regions are formed such that a plurality of semiconductor regions with different ion injection amounts are exposed on one principal surface of a semiconductor substrate. As the cleaning process, after the semiconductor region forming process, a cleaning using hydrofluoric acid is performed on the one principal surface of the semiconductor substrate. As the surface roughness uniformizing process, after the cleaning process, the surface roughness of the one principal surface of the semiconductor substrate is uniformized. As the electrode forming process, after the surface roughness uniformizing process, electrodes are formed on the one principal surface of the semiconductor substrate. | 2017-06-15 |
20170170006 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - Methods for manufacturing semiconductor devices are disclosed. A photoresist layer is formed over a substrate. A cryogenic process is performed on the photoresist layer. After the cryogenic process, a cleaning process is performed on the photoresist layer to remove the photoresist layer. | 2017-06-15 |
20170170007 | Method for Pattern Formation on a Substrate, Associated Semiconductor Devices, and Uses of the Method - The present disclosure relates to a method for pattern formation on a substrate. An example embodiment includes a method for pattern formation. The method includes providing a photoresist layer on a composite substrate. The method also includes patterning the photoresist layer by lithography to define a plurality of parallel stripe photoresist structures. The method further includes providing a block copolymer on and along the composite substrate, in between the parallel stripe photoresist structures. The block copolymer includes a first component and a second component. The method additionally includes subjecting the block copolymer to predetermined conditions to cause phase separation of the first component and the second component. In addition, the method includes performing a sequential infiltration synthesis process. Still further, the method includes selectively removing the parallel stripe photoresist structures. Additionally, the method includes defining a core stripe structure. Even further, the method includes performing a self-aligned multiple patterning process. | 2017-06-15 |
20170170008 | PATTERN TREATMENT METHODS - Pattern treatment methods comprise: (a) providing a semiconductor substrate comprising a patterned feature on a surface thereof; (b) applying a pattern treatment composition to the patterned feature, wherein the pattern treatment composition comprises a polymer comprising a surface attachment group for forming a bond with a surface of the patterned feature and a solvent, and wherein the pattern treatment composition is free of crosslinkers; (c) removing residual pattern treatment composition from the substrate with a first rinse agent, leaving a coating of the polymer over and bonded to the surface of the patterned feature; and (d) rinsing the polymer-coated patterned feature with a second rinse agent that is different from the first rinse agent, wherein the polymer has a solubility that is greater in the first rinse agent than in the second rinse agent. The methods find particular applicability in the manufacture of semiconductor devices for providing high resolution patterns. | 2017-06-15 |
20170170009 | In-Situ Film Annealing With Spatial Atomic Layer Deposition - Methods for filling the gap of a semiconductor feature comprising exposure of a substrate surface to a precursor and reactant and an anneal environment to decrease the wet etch rate ratio of the deposited film and fill the gap. | 2017-06-15 |
20170170010 | METHOD FOR MANUFACTURING INSULATING FILM LAMINATED STRUCTURE - A method for manufacturing an insulating film laminated structure includes a step of forming a first high-k film on a semiconductor substrate, a step of processing the semiconductor substrate in a processing chamber of a plasma processing apparatus by using a plasma to form an oxide film on an interface between the semiconductor substrate and the first high-k film, and a step of forming a second high-k film on the first high-k film. A plasma oxidation process is performed by using a plasma of an oxygen-containing gas at a processing temperature of the semiconductor substrate in a range from 20° C. to 145° C. while setting a power density of a total power of microwaves to be within a range from 0.035 kW/m | 2017-06-15 |
20170170011 | NAND FLASH MEMORY AND FABRICATION METHODS THEREOF - A method for fabricating an NAND flash memory includes providing a semiconductor substrate with a core region and a peripheral region, forming a plurality of discrete gate stack structures in the core region with neighboring gate stack structures separated by a first dielectric layer. The method further includes forming a flowable dielectric layer on the first dielectric layer and the gate stack structures, and forming a solid dielectric layer through a solidification treatment process performed on the flowable dielectric layer. Voids and seams formed in the top portion of the first dielectric layer are filled by the solid dielectric layer. The method also includes removing the solid dielectric layer and a portion of the first dielectric layer to expose a top portion of the gate stack structures, and forming a metal silicide layer on each gate stack structure. | 2017-06-15 |
20170170012 | METHOD OF INTERCALATING INSULATING LAYER BETWEEN METAL CATALYST LAYER AND GRAPHENE LAYER AND METHOD OF FABRICATING SEMICONDUCTOR DEVICE USING THE SAME - Methods of intercalating an insulating layer between a metal catalyst layer and a graphene layer and methods of fabricating a semiconductor device using the intercalating method are provided. The method of intercalating the insulating layer includes forming the graphene layer on the metal catalyst substrate, intercalating nitrogen ions between the metal catalyst substrate and the graphene layer, and forming the insulating layer between the metal catalyst substrate and the graphene layer by heating the metal catalyst substrate to chemically combine the nitrogen ions with the metal catalyst substrate. | 2017-06-15 |
20170170013 | Display Panel and Method for Fabricating the Same - A display panel and a method for fabricating the display panel are proposed. The method includes steps of forming an amorphous silicon (a-Si) film on a substrate, the a-Si film comprising at least two a-Si layers, and densities of dice of the two adjacent a-Si layers being different; and transforming the a-Si film into a polycrystalline silicon film. The poly-silicon layer have less grain boundaries and larger dice, thereby increasing carrier mobility of the poly-silicon film and correspondingly improving the performance of the display panel. | 2017-06-15 |
20170170014 | LOCALIZED ELASTIC STRAIN RELAXED BUFFER - A strain relaxed buffer layer is fabricated by melting an underlying layer beneath a strained semiconductor layer, which allows the strained semiconductor layer to elastically relax. Upon recrystallization of the underlying layer, crystalline defects are trapped in the underlying layer. Semiconductor layers having different melting points, such as silicon germanium layers having different atomic percentages of germanium, are formed on a semiconductor substrate. An annealing process causes melting of only the silicon germanium layer that has the higher germanium content and therefore the lower melting point. The silicon germanium layer having the lower germanium content is elastically relaxed upon melting of the adjoining silicon germanium layer and can be used as a substrate for growing strained semiconductor layers such as channel layers of field-effect transistors. | 2017-06-15 |
20170170015 | CONFORMAL AMORPHOUS CARBON FOR SPACER AND SPACER PROTECTION APPLICATIONS - A method of forming a nitrogen-doped amorphous carbon layer on a substrate in a processing chamber is provided. The method generally includes depositing a predetermined thickness of a sacrificial dielectric layer over a substrate, forming patterned features on the substrate by removing portions of the sacrificial dielectric layer to expose an upper surface of the substrate, depositing conformally a predetermined thickness of a nitrogen-doped amorphous carbon layer on the patterned features and the exposed upper surface of the substrate, selectively removing the nitrogen-doped amorphous carbon layer from an upper surface of the patterned features and the upper surface of the substrate using an anisotropic etching process to provide the patterned features filled within sidewall spacers formed from the nitrogen-doped amorphous carbon layer, and removing the patterned features from the substrate. | 2017-06-15 |
20170170016 | MULTIPLE PATTERNING METHOD FOR SUBSTRATE - Methods for multiple patterning a substrate may include: forming a hard mask including a carbonaceous layer and an oxynitride layer over the carbonaceous layer on a substrate; and forming a first pattern into the oxynitride layer and partially into the carbonaceous layer using a first soft mask positioned over the hard mask. A wet etching removes a portion of the first soft mask from the first pattern in the oxynitride layer without damaging the carbonaceous layer. Subsequently, a second pattern and a third pattern are formed into the hard mask, creating a multiple pattern in the hard mask. The multiple pattern may be etched into the substrate, followed by removing any remaining portion of the hard mask. | 2017-06-15 |
20170170017 | Method for Patterning a Substrate Involving Directed Self-Assembly - A method for patterning a substrate is disclosed. The method includes applying a first directed self-assembly (DSA) patterning process that defines a first patterned layer on top of the substrate. The pattern of the first patterned layer is to be transferred into the substrate. The method also includes applying a planarizing layer on top of the first patterned layer. The method further includes applying a second DSA patterning process that defines a second patterned layer on top of the planarizing layer, thereby not patterning the planarizing layer. A pattern of the second patterned layer is to be transferred into the substrate. Projections of the pattern of the second patterned layer and the pattern of the first patterned layer on the substrate have no overlap. Additionally, the method includes transferring the patterns defined by the first patterned layer and the second patterned layer into the substrate. | 2017-06-15 |
20170170018 | CONFORMAL DOPING USING DOPANT GAS ON HYDROGEN PLASMA TREATED SURFACE - Well-controlled, conformal doping of semiconductor substrates may be achieved by low temperature hydrogen-containing plasma treatment prior to gas phase doping. Substrates doped in this manner may be capped and annealed for thermal drive-in of the dopant. The technique is particularly applicable to the formation of ultrashallow junctions (USJs) in three-dimensional ( | 2017-06-15 |
20170170019 | MATERIAL REMOVAL PROCESS FOR SELF-ALIGNED CONTACTS - A method is disclosed of removing a first material disposed over a second material adjacent to a field effect transistor gate having a gate sidewall layer that comprises an etch-resistant material on a gate sidewall. The method includes subjecting the first material to a gas cluster ion beam etch process to remove first material adjacent to the gate, and detecting exposure of the second material during the gas cluster ion beam (GCIB) etch process. | 2017-06-15 |
20170170020 | ION IMPLANTATION METHOD AND ION IMPLANTATION APPARATUS - An ion implantation method for scanning an ion beam reciprocally in an x direction and moving a wafer reciprocally in a y direction to implant ions into the wafer is provided. The method includes: irradiating a first wafer arranged to meet a predetermined plane channeling condition with the ion beam and measuring resistance of the first wafer irradiated with the ion beam; irradiating a second wafer arranged to meet a predetermined axial channeling condition with the ion beam and measuring resistance of the second wafer irradiated with the ion beam; and adjusting an implant angle distribution of the ion beam by using results of measuring the resistance of the first and second wafers. | 2017-06-15 |
20170170021 | SUBSTRATE PROCESSING APPARATUS, SUBSTRATE PROCESSING METHOD AND RECORDING MEDIUM - In a substrate processing apparatus | 2017-06-15 |
20170170022 | SYSTEM AND METHOD FOR MITIGATING OXIDE GROWTH IN A GATE DIELECTRIC - Oxide growth of a gate dielectric layer that occurs between processes used in the fabrication of a gate dielectric structure can be reduced. The reduction in oxide growth can be achieved by maintaining the gate dielectric layer in an ambient effective to mitigate oxide growth of the gate dielectric layer between at least two sequential process steps used in the fabrication the gate dielectric structure. Maintaining the gate dielectric layer in an ambient effective to mitigate oxide growth also improves the uniformity of nitrogen implanted in the gate dielectric. | 2017-06-15 |
20170170023 | METHOD OF FABRICATING A SEMICONDUCTOR DEVICE - There is provides a method of fabricating a semiconductor device to decrease contact resistance of source/drain regions and gate electrodes and thereby improve operation performance. The method includes providing an exposed silicon region, forming a rare earth metal silicide film on the exposed silicon region, the rare earth metal silicide film contacting the silicon region, and forming a contact on the rare earth metal silicide film, the contact being electrically connected to the exposed silicon region, wherein the rare earth metal silicide film is formed by simultaneously supplying a rare earth metal and silicon to the exposed silicon region using physical vapor deposition. | 2017-06-15 |
20170170024 | METHOD FOR FORMING SEMICONDUCTOR DEVICE STRUCTURE - A method for forming a semiconductor device structure is provided. The semiconductor device structure includes forming a film over a substrate. The semiconductor device structure includes forming a first mask layer over the film. The semiconductor device structure includes forming a second mask layer over the first mask layer. The second mask layer exposes a first portion of the first mask layer. The semiconductor device structure includes performing a plasma etching and deposition process to remove the first portion of the first mask layer and to form a protection layer over a first sidewall of the second mask layer. The first mask layer exposes a second portion of the film after the plasma etching and deposition process. The semiconductor device structure includes removing the second portion using the first mask layer and the second mask layer as an etching mask. | 2017-06-15 |
20170170025 | SELECTIVE, ELECTROCHEMICAL ETCHING OF A SEMICONDUCTOR - Methods for facilitating fabricating semiconductor structures are provided which include: providing a multilayer structure including a semiconductor layer, the semiconductor layer including a dopant and having an increased conductivity; selectively increasing, using electrochemical processing, porosity of the semiconductor layer, at least in part, the selectively increasing porosity utilizing the increased conductivity of the semiconductor layer; and removing, at least in part, the semiconductor layer with the selectively increased porosity from the multilayer structure. By way of example, the selectively increasing porosity may include selectively, anodically oxidizing, at least in part, the semiconductor layer of the multilayer structure. | 2017-06-15 |
20170170026 | TECHNIQUE TO DEPOSIT METAL-CONTAINING SIDEWALL PASSIVATION FOR HIGH ASPECT RATIO CYLINDER ETCH - Various embodiments herein relate to methods, apparatus and systems for forming a recessed feature in a dielectric-containing stack on a semiconductor substrate. Separate etching and deposition operations are employed in a cyclic manner. Each etching operation partially etches the feature. Each deposition operation forms a protective coating (e.g., a metal-containing coating) on the sidewalls of the feature to prevent lateral etch of the dielectric material during the etching operations. The protective coating may be deposited using methods that result in formation of the protective coating along substantially the entire length of the sidewalls. The protective coating may be deposited using particular reaction mechanisms that result in substantially complete sidewall coating. Metal-containing coatings have been shown to provide particularly good resistance to lateral etch during the etching operation. In some cases, a bilayer approach may be used to deposit the protective coating on sidewalls of partially etched features. | 2017-06-15 |
20170170027 | FINFET DOPING METHODS AND STRUCTURES THEREOF - A method and structure for providing conformal doping of FinFET fin structures, for example by way of a thermal treatment process, includes forming a gate stack at least partially over a fin extending from a substrate. In various embodiments, a barrier metal layer is deposited over the gate stack. By way of example, a thermal fluorine treatment is performed, where the thermal fluorine treatment forms a fluorinated layer within the barrier metal layer, and where the fluorinated layer includes a plurality of fluorine atoms. In some embodiments, after forming the fluorinated layer, an anneal is performed to drive at least some of the plurality of fluorine atoms into the gate stack (e.g., into the interfacial layer and the high-K dielectric layer), thereby conformally doping the gate stack with the at least some of the plurality of fluorine atoms. | 2017-06-15 |
20170170028 | Method for Processing a Silicon Wafer - Disclosed is a method for processing a semiconductor wafer. The method includes forming an oxygen containing region in the semiconductor wafer, wherein forming the oxygen containing region includes introducing oxygen via a first surface into the semiconductor wafer. The method further includes creating vacancies at least in the oxygen containing region and annealing at least the oxygen containing region in an annealing process so as to form oxygen precipitates. | 2017-06-15 |
20170170029 | THIN FILM TRANSISTOR - This thin film transistor has a gate electrode, a gate insulating film, an oxide semiconductor thin film, an etch stop layer for protecting the oxide semiconductor thin film, a source and drain electrodes, and a passivation film in this order on a substrate. The oxide semiconductor thin film is formed of an oxide configured from In, Ga and Sn as metal elements, and O, and has an amorphous structure, and the etch stop layer and/or the passivation film includes SiNx. The thin film transistor has an extremely high mobility of approximately 40 cm | 2017-06-15 |
20170170030 | LID ATTACH OPTIMIZATION TO LIMIT ELECTRONIC PACKAGE WARPAGE - An electronic package includes a carrier and a semiconductor chip. In a first aspect a lid is attached to the chip and subsequently the gap between the lid and the carrier is filled by a seal band that includes seal band material and a plurality of shim members. In another aspect, an interleaved seal band includes a pattern of a first type of seal band material and a second type of seal band material. In another aspect, the lid includes a plurality of surfaces at different topographies to reduce the thickness of the seal band between the topographic lid and the carrier. In yet another aspect the electronic package further includes a frame concentric with the chip. The lid is attached to the frame with a solder, epoxy or elastomer and placed on the chip with a thermal interface material. The seal band material is dispensed on the chip carrier and the frame is then moved towards the chip carrier allowing a minimum seal band thickness. | 2017-06-15 |
20170170031 | Fan-Out Wafer-Level Packaging Using Metal Foil Lamination - Fan-out wafer-level packaging (WLP) using metal foil lamination is provided. An example wafer-level package incorporates a metal foil, such as copper (Cu), to relocate bonding pads in lieu of a conventional deposited or plated RDL. A polymer such as an epoxy layer adheres the metal foil to the package creating conductive contacts between the metal foil and metal pillars of a die. The metal foil may be patterned at different stages of a fabrication process. An example wafer-level package with metal foil provides relatively inexpensive electroplating-free traces that replace expensive RDL processes. Example techniques can reduce interfacial stress at fan-out areas to enhance package reliability, and enable smaller chips to be used. The metal foil provides improved fidelity of high frequency signals. The metal foil can be bonded to metallic pillar bumps before molding, resulting in less impact on the mold material. | 2017-06-15 |
20170170032 | SUBSTRATE PROCESSING DEVICE AND SUBSTRATE PROCESSING METHOD FOR CARRYING OUT CHEMICAL TREATMENT FOR SUBSTRATE - It is an object to reduce a chemical treating width in a peripheral edge part of a substrate while suppressing deterioration in each of uniformity of the chemical treating width and processing efficiency. In order to achieve the object, a substrate processing device for carrying out a chemical treatment for a substrate using a processing liquid having a reaction rate increased with a rise in temperature includes a substrate holding portion, a rotating portion for rotating the substrate held in the substrate holding portion in a substantially horizontal plane, a heating portion for injecting heating steam to a central part of a lower surface of the substrate to entirely heat the substrate, and a peripheral edge processing portion for supplying the processing liquid from above to a peripheral edge part of the substrate heated by the heating portion, thereby carrying out a chemical treatment for the peripheral edge part. | 2017-06-15 |
20170170033 | MINI-ENVIRONMENT APPARATUS - A mini-environment apparatus includes a wafer transportation machine transporting a wafer, a wafer transportation room having the machine and passed by the wafer transported to a processing room, a circulating passage where a gas detoured from the transportation room flows, a blowing means forming a circulating current falling in the transportation room and rising in the passage, a current member arranged in a ceiling part of the transportation room and laminarizing the current and introducing this laminarized current into the transportation room, a particle removal filter arranged in either the ceiling part of the transportation room or the passage, and a chemical filter arranged in the passage detachably and separately from the removal filter. The chemical filter is arranged at a position lower than a lowest position where the wafer may pass through in the transportation room. | 2017-06-15 |
20170170034 | CLEANING DEVICE AND ROLL CLEANING MEMBER - The present invention prevents or alleviates cleaning unevenness in cleaning of a substrate with the use of a roll cleaning member having protruding members. The roll cleaning device includes: a substrate support member that supports and rotates a substrate W; and an upper roll cleaning member ( | 2017-06-15 |
20170170035 | CLEANING DEVICE FOR ATOMIZING AND SPRAYING LIQUID IN TWO-PHASE FLOW - A cleaning device for atomizing and spraying liquid in two-phase flow comprising a nozzle provided with multiple liquid bypass pipelines each having liquid guiding outlets inclined at a predetermined angle and an exhaust mesh plate having vertical gas guiding outlets, which makes the high speed liquid flow and high speed gas flow sprayed out therefrom collide against each other sufficiently to form ultra-micro atomized particles with uniform and adjustable size. The ultra-micro atomized particles are sprayed out downwardly to the wafer surface under the acceleration and vertical orientation effects of an atomized particle guiding outlet to perform a reciprocating cleaning for the wafer. Other components such as an ultrasonic or megasonic generation unit, a gas shielding unit, a self-cleaning unit or a rotating unit can also be provided to perform the multifunction of the nozzle. | 2017-06-15 |
20170170036 | ADJUSTMENT OF VUV EMISSION OF A PLASMA VIA COLLISIONAL RESONANT ENERGY TRANSFER TO AN ENERGY ABSORBER GAS - Disclosed are methods of adjusting the emission of vacuum ultraviolet (VUV) radiation from a plasma in a semiconductor processing chamber. The methods may include generating a plasma in the processing chamber which includes a VUV-emitter gas and a collisional energy absorber gas, and adjusting the emission of VUV radiation from the plasma by altering the concentration ratio of the VUV-emitter gas to collisional energy absorber gas in the plasma. In some embodiments, the VUV-emitter gas may be helium and the collisional energy absorber gas may be neon, and in certain such embodiments, adjusting VUV emission may include flowing helium and/or neon into the processing chamber in a proportion so as to alter the concentration ratio of helium to neon in the plasma. Also disclosed are apparatuses which implement the foregoing methods. | 2017-06-15 |
20170170037 | AMBIDEXTROUS CASSETTE AND METHODS OF USING SAME - Devices and methods for transferring solar cells while maintaining a controlled environment are provided. Such devices include a solar cell carrying cassette adapted to support a stack of solar cells within a solar cell carrying pod that maintains a sealed micro-environment of inert gas and allows for automated transfer of solar cells between the pod and a fabrication line. The solar cell carrying cassette includes a pair of end plates and a plurality of rods extending therebetween that are configured to support a stack of solar cells. An identifier, such as an RFID chip, is included in each of the pair of end plates so as to allow for ready identification of the cassette from a single location relative the pod, while the cassette is coupled within the pod, regardless of the orientation of the cassette within the pod. | 2017-06-15 |
20170170038 | MICRO-ENVIRONMENT CONTAINER FOR PHOTOVOLTAIC CELLS - Devices and methods for transferring solar cells while maintaining a controlled environment are provided. Such devices can include a solar cell carrying pod adapted to support and maintain a stack of solar cells within a sealed micro-environment of inert gas. The solar cell carrying pod can further allow for ready removal of a solar cell carrier to facilitate automated transport of solar cells. The solar cell carrying pod can include a cover adapted to receive a solar cell carrier cassette securely mounted on a base that is sealably coupled with the cover to maintain solar cells within the carrier cassette in a sealed micro-environment for an extended period of time. The base can include a collet-operated gear train to facilitate unlocking and removal of the base from the cover in an automated process to facilitate large-scale solar cell fabrication. | 2017-06-15 |
20170170039 | LIGHT IRRADIATION TYPE HEAT TREATMENT APPARATUS - An oxygen concentration measuring chamber is provided on a wall surface of a chamber in which flash lamp annealing is performed, and a zirconia type oxygen analyzer is provided in the oxygen concentration measuring chamber. An opening for bringing the interior space of the oxygen concentration measuring chamber and a heat treatment space of the chamber into communication with each other therethrough is opened and closed by a gate valve. The opening is closed when the pressure in the chamber is reduced during the treatment. When the pressure in the chamber is reduced to a predetermined pressure to enter a stable state, the gate valve opens the opening, so that gas molecules in the chamber are diffused into the oxygen concentration measuring chamber, and the oxygen analyzer measures the concentration of oxygen in the atmosphere in the chamber. A reference gas for use in the measurement has an oxygen concentration of 1 to 100 ppm. | 2017-06-15 |
20170170040 | SUBSTRATE PROCESSING APPARATUS AND METHOD OF ADJUSTING SUBSTRATE PROCESSING APPARATUS - A substrate processing apparatus includes plural heating modules each including a table on which a substrate is placed to be heated, the substrate having plural heated zones. The table has plural heaters each assigned to heat respective ones of the heated zones. Heat generation of the heaters is controlled independently. A control unit controls the heaters such that integrated quantities of heat of the respective heated zones given by the corresponding heaters from first to second time point are substantially identical to each other in each of the heating modules, and are substantially identical to each other among the heating modules. The first time point is set when a temperature transition profile of the substrate is rising toward a process temperature after placing the substrate on the table under a condition where heat generation of the heaters is stable. The second time point is set after the temperature transition profile reaches the process temperature. | 2017-06-15 |
20170170041 | HIGH SPEED ROTARY SORTER - Embodiments of the present disclosure generally relate to expandable substrate inspection systems. The inspection system includes multiple metrology units adapted to inspect, detect, or measure one or more characteristics of a substrate, including thickness, resistivity, saw marks, geometry, stains, chips, micro cracks, and crystal fraction. The inspection systems may be utilized to identify defects on substrates and estimate cell efficiency prior to processing a substrate. Substrates may be transferred through the inspection system and/or between metrology units on a track or conveyor, and then sorted via at least one gripper coupled with the high speed rotatory sorting apparatus into respective bins based upon the inspection data. The rotary sorting apparatus maintains a sorting capability of at least 5,400 substrates per hour. Each bin may optionally have a gas support cushion for supporting the substrate as it falls from the rotary sorting apparatus into the respective bin. | 2017-06-15 |
20170170042 | EFEM - An EFEM includes a wafer transportation part having a wafer transportation room passed by a wafer transported to a processing room and a load port part airtightly connecting a main opening formed on a container housing the wafer to the room. The transportation part includes a downward current forming device for forming a downward current in the room and a current plate arranged in the room and partly introducing the current into the container connected to the room via the opening. The load port part includes an installation stand for installing the container, a bottom nozzle for communicating with a bottom hole formed at a position distant from the opening more than a bottom surface middle on a bottom surface of the container, and a gas discharge passage for discharging a gas in the container to an outside thereof via the nozzle. | 2017-06-15 |
20170170043 | PURGE MODULE AND LOAD PORT HAVING THE SAME - A purge module which can provide a conventional load port without a gas purging function with the gas purging function, and a load port having the purge module are disclosed. The purge module comprises a jig, a gas control box and pipes. The jig is detachably attached to an upper side of a stage of a load port. The jig comprises a gas inlet for providing a wafer carrier with gas and a gas outlet for receiving gas from the wafer carrier. The gas control box is detachably attached to the load port to control gas flow. The pipes connect the jig and the gas control box. | 2017-06-15 |
20170170044 | CONTROLING METHOD FOR A WAFER TRANSPORTATION PART AND A LOAD PORT PART ON AN EFEM - A controlling method for a wafer transportation part and a load port part on an EFEM includes a fixing step of fixing a container on an installation stand of the load port part, a first cleaning step of connecting a bottom nozzle of the load port part to multiple bottom holes formed on a bottom surface of the container and introducing a cleaning gas into the container and discharging a gas from the container via the nozzle, a connection step of connecting the container and the transportation room, and a wafer transportation step of transporting the wafer from the container to a processing room via the opening and the transportation room and transporting the wafer from the processing room to the container via the transportation room and the opening. | 2017-06-15 |
20170170045 | LOAD PORT DEVICE AND CLEANING GAS INTRODUCING METHOD INTO A CONTAINER ON A LOAD PORT - A load port device includes an installation stand, an opening and closing part, a gas introduction part, and a gas discharge part. The installation stand installs a container whose side surface has a main opening for taking in and out a wafer. The opening and closing part opens and closes the main opening. The gas introduction part introduces a cleaning gas from the main opening into the container. The gas discharge part has a bottom nozzle capable of communicating with a bottom hole formed at a position distant from the main opening more than a bottom surface middle on a bottom surface of the container. The gas discharge part is capable of discharging a gas in the container to an outside of the container. | 2017-06-15 |
20170170046 | PIN STRUCTURE AND VACUUM APPARATUS - The present invention discloses a pin structure and a vacuum apparatus, and the pin structure comprises a machine, and the machine comprises outer pins and inner pins, the outer pins are located at edges of the machine, and the inner pins are movably located in a middle area of the machine, and an amount of the inner pins is three, which are aligned with spaces corresponding to a cutting area of a glass substrate, and tops of the inner pins and the outer pins comprise metal heads; the amount of the pins is merely three to reduce the cost, and the possibility of generating electrostatic induction can be decreased in a certain level to promote the reliability of the products. | 2017-06-15 |
20170170047 | PLASMA TREATMENT DEVICE AND WAFER TRANSFER TRAY - A plasma treatment apparatus includes a wafer transfer tray having a first surface and a second surface opposite to the first surface and configured to hold a wafer on the first surface, a cooling unit configured to cool the wafer transfer tray, a conductive supporter configured to support the second surface of the wafer transfer tray, and a double-surface electrostatic attractor configured to electrostatically attract the wafer to the first surface of the wafer transfer tray and electrostatically attract the supporter to the second surface of the wafer transfer tray. | 2017-06-15 |
20170170048 | WAFER HANDLER FOR INFRARED LASER RELEASE - A wafer handler includes a substrate having a front surface and a back surface, an antireflective layer formed over the back surface, a silicon nitride compensation layer formed over the front surface, and a release layer formed over the compensation layer. The wafer handler can be bonded to a device wafer for processing of the device wafer, and debonded from the device wafer using infrared radiation without damaging the device wafer or devices formed thereon. | 2017-06-15 |
20170170049 | MICRO DEVICE STABILIZATION POST - A method and structure for stabilizing an array of micro devices is disclosed. The array of micro devices is formed on an array of stabilization posts formed from a thermoset material. Each micro device includes a bottom surface that is wider than a corresponding stabilization post directly underneath the bottom surface. | 2017-06-15 |
20170170050 | SUBSTRATE CONVEYANCE ROBOT AND OPERATING METHOD THEREOF - A substrate conveyance robot has an end effector provided to a robot arm and including a substrate holding unit configured to hold a substrate, arm drive unit configured to drive the robot arm, a robot control unit configured to control the arm drive unit, and a holding force detection unit configured to detect a substrate holding force exerted by the substrate holding unit. The robot control unit controls the arm drive unit based on an upper limit value of at least one of acceleration and speed of the end effector which are determined in accordance with the substrate holding force detected by the holding force detection unit. | 2017-06-15 |
20170170051 | WAFER SUPPORT PEDESTAL WITH WAFER ANTI-SLIP AND ANTI-ROTATION FEATURES - An apparatus for semiconductor processing that includes a pedestal that includes a wafer support surface that includes a plurality of mesas and a pattern of grooves is provided. Each mesa may be bracketed between two or more grooves, each mesa may include a plurality of mesa side walls that intersect, at least in part, with one of the grooves and with a mesa top surface that is a substantially planar surface, the mesa top surfaces may be substantially coplanar with each other, and the mesa top surfaces may be configured to support a wafer during semiconductor operations. | 2017-06-15 |
20170170052 | SHAFT-END MOUNTING STRUCTURE - A shaft-end mounting structure according to the present invention is a structure to mount an end of a hollow ceramic shaft | 2017-06-15 |
20170170053 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device is provided in which a zener diode having a desired breakdown voltage and a capacitor in which voltage dependence of capacitance is reduced are mounted together, and various circuits are realized. The semiconductor device includes: a semiconductor layer; a first conductivity type well that is arranged in a first region of the semiconductor layer; a first conductivity type first impurity diffusion region that is arranged in the well; a first conductivity type second impurity diffusion region that is arranged in a second region of the semiconductor layer; an insulating film that is arranged on the second impurity diffusion region; an electrode that is arranged on the insulating film; and a second conductivity type third impurity diffusion region that is arranged at least on the first impurity diffusion region. | 2017-06-15 |
20170170054 | SEMICONDUCTOR DEVICE - A semiconductor device includes a fin protruding from a substrate and extending in a first direction, first and second gate structures intersecting the fin, a recess formed in the fin between the first and second gate structures, a device isolation layer which fills the recess, and which has an upper surface protruded outwardly from the fin and disposed to be coplanar with upper surfaces of the first and second gate structures, a liner formed along a side walls of the device isolation layer protruded outwardly from the fin and a source/drain region disposed at both sides of the recess and spaced apart from the device isolation layer. | 2017-06-15 |
20170170055 | NOVEL CHANNEL SILICON GERMANIUM FORMATION METHOD - A method of making a channel region in a semiconductor device includes providing a substrate having a first transistor area arranged adjacent to a second transistor area; growing an epitaxial layer on the second transistor area of the substrate; forming a trench in the substrate between the first transistor area and the second transistor area; performing a condensation technique to thermally mix materials of the epitaxial layer and the substrate; and filling the trench with a dielectric material to form a shallow trench isolation region between a first channel region of the first transistor and a second channel region of the second transistor; wherein performing the condensation technique is performed after forming the trench. | 2017-06-15 |
20170170056 | SEMICONDUCTOR STRUCTURE WITH AIRGAP - A field effect transistor (FET) with an underlying airgap and methods of manufacture are disclosed. The method includes forming an amorphous layer at a predetermined depth of a substrate. The method further includes forming an airgap in the substrate under the amorphous layer. The method further includes forming a completely isolated transistor in an active region of the substrate, above the amorphous layer and the airgap. | 2017-06-15 |
20170170057 | METHOD OF MANUFACTURING 3-D SEMICONDUCTOR DEVICE - A method of manufacturing three-dimensional semiconductor device, comprising the steps of: a) forming a device unit on a substrate, the said device includes a plurality of stack structures composed of the first material layer and the second material layer stacked along a direction perpendicular to the substrate surface; b) forming a contact lead-out region around the said device unit, the contact lead-out region comprises a plurality of sub-partitions, each of the sub-partitions respectively exposes a different second material layer; c) forming a photoresist on said substrate, covering said plurality of sub-partitions, exposing a portion of said second material layer; d) using the photoresist as a mask, simultaneously etching the portion of the second material layer exposed by said plurality of sub-partitions, until another second material layer beneath said second material layer is exposed; e) slimming the size of the photoresist to expose a portion of said another second material layer; f) repeating said steps d and step e, until all of the second material layers are exposed; g) forming contact leads, connecting each of the plurality of the second material layers. In accordance with the method of the present invention, the total number of etching process steps is reduced dramatically and the area utilization is improved effectively by selectively etching each of the sub-partitions. | 2017-06-15 |
20170170058 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a substrate, a first metal interconnection provided on a first region of the substrate, and a second metal interconnection provided on a second region of the substrate. A width of the second metal interconnection is greater than a width of the first metal interconnection. The first metal interconnection includes a metal pattern. The second metal interconnection includes a lower metal pattern having a concave surface at its top, an upper metal pattern disposed on the concave surface at the top of the lower metal pattern, and a first barrier pattern interposed between the lower metal pattern and the upper metal pattern. The metal interconnections are formed by a damascene process including deposition, reflow, metal implantation, and planarization processes. | 2017-06-15 |
20170170059 | MEMS GRID FOR MANIPULATING STRUCTURAL PARAMETERS OF MEMS DEVICES - A system and method for manipulating the structural characteristics of a MEMS device include etching a plurality of holes into the surface of a MEMS device, wherein the plurality of holes comprise one or more geometric shapes determined to provide specific structural characteristics desired in the MEMS device. | 2017-06-15 |
20170170060 | ETCH STOP IN A DEP-ETCH-DEP PROCESS - Described herein is a method of forming semiconductor devices. The method comprises depositing an etch stop layer of titanium aluminum carbide in a cavity of a semiconductor device; depositing a first layer of metal on the etch stop layer; etching the first layer of metal to create an etch-modified surface of the first layer of metal; and depositing a second layer of metal on the etch- modified surface of the first layer of metal. | 2017-06-15 |
20170170061 | FinFet Low Resistivity Contact Formation Method - A contact structure of a semiconductor device is provided. The contact structure for a semiconductor device comprises a substrate comprising a major surface and a trench below the major surface; a strained material filling the trench, wherein a lattice constant of the strained material is different from a lattice constant of the substrate, and wherein a surface of the strained material has received a passivation treatment; an inter-layer dielectric (ILD) layer having an opening over the strained material, wherein the opening comprises dielectric sidewalls and a strained material bottom; a dielectric layer coating the sidewalls and bottom of the opening, wherein the dielectric layer has a thickness ranging from 1 nm to 10 nm; a metal barrier coating an opening of the dielectric layer; and a metal layer filling a coated opening of the dielectric layer. | 2017-06-15 |
20170170062 | SEMICONDUCTOR DEVICE INTERCONNECT STRUCTURES FORMED BY METAL REFLOW PROCESS - Methods are devices are provided in which interconnection structures are formed using metal reflow techniques. For example, a method to fabricate a semiconductor device includes forming an opening in an ILD (inter-level dielectric) layer. The opening includes a via hole and a trench. A layer of diffusion barrier material is deposited to cover the ILD layer and to line the opening with the diffusion barrier material. A layer of first metallic material is deposited on the layer of diffusion barrier material to cover the ILD layer and to line the opening with the first metallic material. A reflow process is performed to allow the layer of first metallic material to reflow into the opening and at least partially fill the via hole with the first metallic material. A layer of second metallic material is deposited to at least partially fill a remaining portion of the opening in the ILD layer. | 2017-06-15 |
20170170063 | MODULATING MICROSTRUCTURE IN INTERCONNECTS - Recrystallization and grain growth of an interconnect metal, such as Cu, is achieved at higher anneal temperatures of 150° C. to 600° C., for example, for short anneal times of five to 180 minutes by forming a metal stress locking layer on the interconnect metal before anneal and chemical-mechanical polishing. The stress locking layer extends the elastic region of the interconnect metal by suppressing atom diffusion to the free surface, resulting in near zero tensile stress at room temperature after anneal. Stress voiding, which creates reliability problems, is thereby avoided. Improved grain size and texture are also achieved. The stress locking layer is removed after anneal by chemical-mechanical polishing or wet etching leaving the metal interconnect with low stress and improved grain size and texture. Annealing can be done in a forming gas or nitrogen gas atmosphere. | 2017-06-15 |
20170170064 | VOIDLESS CONTACT METAL STRUCTURES - Voidless contact metal structures are provided. In one embodiment, a voidless contact metal structure is provided by first providing a first contact metal that contains a void within a contact opening. The void is then opened to provide a divot in the first contact metal. After forming a dielectric spacer atop a portion of first contact metal, a second contact metal is then formed that lacks any void. The second contact metal fills the entirety of the divot within the first contact metal. In another embodiment, two diffusion barrier structures are provided within a contact opening, followed by the formation of a contact metal structure that lacks any void. | 2017-06-15 |
20170170065 | CARBON FILM FORMING METHOD, CARBON FILM FORMING APPARATUS, AND STORAGE MEDIUM - A carbon film forming method including: forming a first carbon film so that the first carbon film is embedded in the step shape portion by supplying a film forming gas including a hydrocarbon-based carbon source gas to the process target object; etching the first carbon film so that a V-shaped etching region, which is wide in a frontage portion of the step shape portion and becomes narrow as going to a bottom portion of the step shape portion, is formed in the first carbon film existing within the step shape portion, by supplying an etching gas to the process target object; and forming a second carbon film so that the second carbon film is embedded in the etching region by supplying a film forming gas including a hydrocarbon-based carbon source gas to the process target object, in a state where the process target object is heated. | 2017-06-15 |
20170170066 | Method of Semiconductor Integrated Circuit Fabrication - A method of fabricating a semiconductor integrated circuit (IC) is disclosed. The method includes providing a substrate and depositing a conductive layer on the substrate. A patterned hard mask and a catalyst layer are formed on the conductive layer. The method further includes growing a plurality of carbon nanotubes (CNTs) from the catalyst layer and etching the conductive layer by using the CNTs and the patterned hard mask as an etching mask to form metal features. | 2017-06-15 |
20170170067 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - Provided is a semiconductor device including a substrate, a gate structure, a dielectric layer, an etch stop layer, and an adhesion layer. The gate structure is formed over the substrate. The dielectric layer is formed aside the gate structure. The adhesion layer overlays a top surface of the gate structure and extends to a first top surface of the dielectric layer. The etch stop layer is over the adhesion layer and in contact with a second top surface of the dielectric layer. | 2017-06-15 |
20170170068 | SELF-ALIGNED LOW DIELECTRIC CONSTANT GATE CAP AND A METHOD OF FORMING THE SAME - According to an embodiment of the present invention, self-aligned gate cap, comprises a gate located on a substrate; a gate cap surrounding a side of the gate; a contact region self-aligned to the gate; and a low dielectric constant oxide having a dielectric constant of less than 3.9 located on top of the gate. According to an embodiment of the present invention, a method of forming a self-aligned contact comprises removing at least a portion of an interlayer dielectric layer to expose a top surface of a gate cap located on a substrate; recessing the gate cap to form a recessed area; depositing a low dielectric constant oxide having a dielectric constant of less than 3.9 in the recessed area; and polishing a surface of the low dielectric constant oxide to expose a contact area. | 2017-06-15 |
20170170069 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - According to one embodiment, a method for manufacturing a semiconductor device includes forming a silicon film on an upper surface side, a lower surface side, and a side surface side of an air gap, while leaving part of the air gap between the silicon film formed on the upper surface side and the silicon film formed on the lower surface side. The method includes forming a metal film on a side surface of the slit. The method includes forming a plurality of metal silicide layers between the second layers by causing reaction between the metal film and the silicon film. The method includes removing unreacted part of the metal film formed on the side surface of the slit. | 2017-06-15 |
20170170070 | GATE TIE-DOWN ENABLEMENT WITH INNER SPACER - A method for forming a gate tie-down includes opening up a cap layer and recessing gate spacers on a gate structure to expose a gate conductor; forming inner spacers on the gate spacers; etching contact openings adjacent to sides of the gate structure down to a substrate below the gate structures; and forming trench contacts on sides of the gate structure. An interlevel dielectric (ILD) is deposited on the gate conductor and the trench contacts and over the gate structure. The ILD is opened up to expose the trench contact on one side of the gate structure and the gate conductor. A second conductive material provides a self-aligned contact down to the trench contact on the one side and to form a gate contact down to the gate conductor and a horizontal connection within the ILD over an active area between the gate conductor and the self-aligned contact. | 2017-06-15 |
20170170071 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor device is provided as follows. Active fins protrude from a substrate, extending in a first direction. A first device isolation layer is disposed at a first side of the active fins. A second device isolation layer is disposed at a second side of the active fins. A top surface of the second device isolation layer is higher than a top surface of the first device isolation layer and the second side is opposite to the first side. A normal gate extends across the active fins in a second direction crossing the first direction. A first dummy gate extends across the active fins and the first device isolation layer in the second direction. A second dummy gate extends across the second device isolation layer in the second direction. | 2017-06-15 |
20170170072 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device according to one or more exemplary embodiments of the present inventive concept includes forming a plurality of dummy gates on a substrate. Each of the dummy gates includes a gate mask disposed on an upper surface of each of the dummy gates. A spacer is disposed on at least two sides of the dummy gates. An insulating interlayer is formed on the gate mask and the spacer. A first polishing including chemical mechanical polishing is performed on portions of the gate mask and the insulating interlayer by using a slurry composite having a first mixing ratio. A second polishing including chemical mechanical polishing is formed on remaining portions of the gate mask and the insulating interlayer to expose upper surfaces of the plurality of dummy gates, by using a slurry composite having a second mixing ratio. | 2017-06-15 |
20170170073 | Method and Structure to Fabricate Closely Packed Hybrid Nanowires at Scaled Pitch - Techniques for forming closely packed hybrid nanowires are provided. In one aspect, a method for forming hybrid nanowires includes: forming alternating layers of a first and a second material in a stack on a substrate; forming a first trench(es) and a second trench(es) in the stack; laterally etching the layer of the second material selectively within the first trench(es) to form first cavities in the layer; growing a first epitaxial material within the first trench(es) filling the first cavities; laterally etching the layer of the second material selectively within the second trench(es) to form second cavities in the layer; growing a second epitaxial material within the second trench(es) filling the second cavities, wherein the first epitaxial material in the first cavities and the second epitaxial material in the second cavities are the hybrid nanowires. A nanowire FET device and method for formation thereof are also provided. | 2017-06-15 |
20170170074 | METHOD FOR REDUCING LOSS OF SILICON CAP LAYER OVER SIGE SOURCE/DRAIN IN A CMOS DEVICE - A method for forming a semiconductor device includes providing a semiconductor substrate including a PMOS region and an NMOS region. A spacer material layer is deposited. Then, a first photo masking and etch process is used to form first sidewall spacers on the sidewalls of the gate structures in the NMOS region. A sacrificial surface layer is formed. Next, a second photo masking and etch process is used to form second sidewall spacers on the sidewalls of the gate structures in the PMOS region. After the second photoresist layer is removed, with the sacrificial layer masking the NMOS region, stress layers are formed in source/drain regions in the PMOS region, and a cover layer is formed on the stress layers. The method further includes removing the sacrificial material layer, the first sidewall spacers, and the second sidewall spacer. | 2017-06-15 |