24th week of 2017 patent applcation highlights part 57 |
Patent application number | Title | Published |
20170170175 | FIN-TYPE FIELD EFFECT TRANSISTOR STRUCTURE AND MANUFACTURING METHOD THEREOF - A fin-type field effect transistor comprising a substrate, at least one gate structure, spacers and source and drain regions is described. The substrate has a plurality of fins and a plurality of insulators disposed between the fins. The source and drain regions are disposed on two opposite sides of the at least one gate structure. The gate structure is disposed over the plurality of fins and disposed on the plurality of insulators. The gate structure includes a stacked strip disposed on the substrate and a gate electrode stack disposed on the stacked strip. The spacers are disposed on opposite sidewalls of the gate structure, and the gate electrode stack contacts with sidewalls of the opposite spacers. | 2017-06-15 |
20170170176 | METHOD OF CUTTING FINS TO CREATE DIFFUSION BREAKS FOR FINFETS - A method is provided for forming an integrated circuit with FinFETs. Initially, a fin is received with a dummy gate passing thereover. The dummy gate is removed to form a space over the fin. A temporary layer is subsequently placed in the space, and an element from the temporary layer is caused to pass into a portion of the fin to form a modified fin portion. After the temporary layer is removed, at least part of the modified fin portion is etched away to form a gap in the fin. | 2017-06-15 |
20170170177 | S-Contact for SOI - Systems, methods, and apparatus for an improved protection from charge injection into layers of a device using resistive structures are described. Such resistive structures, named s-contacts, can be made using simpler fabrication methods and less fabrication steps. In a case of metal-oxide-semiconductor (MOS) field effect transistors (FETs), s-contacts can be made with direct connection, or resistive connection, to all regions of the transistors, including the source region, the drain region and the gate. | 2017-06-15 |
20170170178 | NOVEL CHANNEL SILICON GERMANIUM FORMATION METHOD - A method of making a channel region in a semiconductor device includes providing a substrate having a first transistor area arranged adjacent to a second transistor area; growing an epitaxial layer on the second transistor area of the substrate; forming a trench in the substrate between the first transistor area and the second transistor area; performing a condensation technique to thermally mix materials of the epitaxial layer and the substrate; and filling the trench with a dielectric material to form a shallow trench isolation region between a first channel region of the first transistor and a second channel region of the second transistor; wherein performing the condensation technique is performed after forming the trench. | 2017-06-15 |
20170170179 | SPACER FOR DUAL EPI CMOS DEVICES - Aspects of the disclosure include a method for making a semiconductor, including patterning a first transistor having one or more gate stacks on a first source-drain area and second transistor comprising one or more gate stacks on a second source-drain area, forming dielectric spacers on gate stack side walls, depositing a first nitride liner on the first and second transistors. The method also includes masking the second transistor and etching to remove the first nitride material and the spacer from the first source-drain area and growing a first epitaxial layer on the first source-drain area by an epitaxial growth process. The method also includes depositing a second nitride liner on the first and second transistors. The method also includes masking the first transistor. The method also includes etching to remove the second nitride material from the second source-drain area and growing a second epitaxial layer on the second source-drain area by an epitaxial growth process. | 2017-06-15 |
20170170180 | FINFET CMOS WITH Si NFET AND SiGe PFET - A method for forming a complementary metal oxide semiconductor (CMOS) device includes growing a SiGe layer on a Si semiconductor layer, and etching fins through the SiGe layer and the Si semiconductor layer down to a buried dielectric layer. Spacers are formed on sidewalls of the fins, and a dielectric material is formed on top of the buried dielectric layer between the fins. The SiGe layer is replaced with a dielectric cap for an n-type device to form a Si fin. The Si semiconductor layer is converted to a SiGe fin for a p-type device by oxidizing the SiGe layer to condense Ge. The dielectric material is recessed to below the spacers, and the dielectric cap and the spacers are removed to expose the Si fin and the SiGe fin. | 2017-06-15 |
20170170181 | SPACER FOR DUAL EPI CMOS DEVICES - Aspects of the disclosure include a method for making a semiconductor, including patterning a first transistor having one or more gate stacks on a first source-drain area and second transistor comprising one or more gate stacks on a second source-drain area, forming dielectric spacers on gate stack side walls, depositing a first nitride liner on the first and second transistors. The method also includes masking the second transistor and etching to remove the first nitride material and the spacer from the first source-drain area and growing a first epitaxial layer on the first source-drain area by an epitaxial growth process. The method also includes depositing a second nitride liner on the first and second transistors. The method also includes masking the first transistor. The method also includes etching to remove the second nitride material from the second source-drain area and growing a second epitaxial layer on the second source-drain area by an epitaxial growth process. | 2017-06-15 |
20170170182 | TALL STRAINED HIGH PERCENTAGE SILICON GERMANIUM FINS FOR CMOS - A silicon germanium alloy (SiGe) fin having a first germanium content is provided within first and second device regions. Each SiGe fin is located on a sacrificial material stack and an oxide material surrounds each SiGe fin. A germanium layer is formed atop each SiGe fin within one of the device regions, while a SiGe layer having a second germanium content less than the first germanium content is formed atop each SiGe fin within the other device region. An exposed surface of each of the germanium layer and the SiGe layer is then bonded to a base substrate. The sacrificial material stack is removed and thereafter the oxide material is recessed to expose a portion of each SiGe fin in the first and second device regions. Each SiGe fin contacting the germanium layer compressively strained, and each SiGe fin contacting the SiGe layer is tensely strained. | 2017-06-15 |
20170170183 | SEMICONDUCTOR DEVICE - A semiconductor device aims to prevent a leak current from flowing between a well and a corner of an active region formed on an upper surface of another well in an SRAM. In a memory cell of the SRAM, a load MOSFET is formed. An end of an active region extending in y-direction is arranged to gradually go away from a p-well as it goes from a gate electrode G | 2017-06-15 |
20170170184 | PLANARIZED INTERLAYER DIELECTRIC WITH AIR GAP ISOLATION - A semiconductor device includes an interlayer insulating layer including a first insulating layer on a substrate, and a plurality of interconnections in the first insulating layer. The interlayer insulating layer includes a first region, and a second region including an air gap. The air gap is defined between a pair of the interconnections in the second region. A top surface of the first insulating layer of the first region is lower than a top surface of at least one of the interconnections in the first region. | 2017-06-15 |
20170170185 | METHOD OF FABRICATING A SEMICONDUCTOR DEVICE - A method of fabricating a semiconductor device includes forming a mold structure including a lower support layer and an upper support layer sequentially stacked on a substrate, doping portions of the upper and lower support layers with impurities to divide each of the upper and lower support layers into first portions doped with the impurities and a second portion surrounding the first portions in a plan view, and removing the first portions of the upper and lower support layers to form an upper support pattern having first openings and a lower support pattern having second openings. | 2017-06-15 |
20170170186 | ROM SEGMENTED BITLINE CIRCUIT - A bitline structure for use in a memory device may be connected to a plurality of bit memory cells. The bitline may be segmented into segments connected to one-third of the plurality of bit memory cells and two-thirds of the bit memory cells, respectively. The segments may be electrically coupled to each other to provide an overall bitline output. | 2017-06-15 |
20170170187 | GATE FRINGING EFFECT BASED CHANNEL FORMATION FOR SEMICONDUCTOR DEVICE - A memory device is described. Generally, the device includes a string of memory transistors, a source select transistor coupled to a first end of the string of memory transistor and a drain select transistor coupled to a second end of the string of memory transistor. Each memory transistor includes a gate electrode formed adjacent to a charge trapping layer and there is neither a source nor a drain junction between adjacent pairs of memory transistors or between the memory transistors and source select transistor or drain select transistor. In one embodiment, the memory transistors are spaced apart from adjacent memory transistors and the source select transistor and drain select transistor, such that channels are formed therebetween based on a gate fringing effect associated with the memory transistors. Other embodiments are also described. | 2017-06-15 |
20170170188 | EMBEDDED HKMG NON-VOLATILE MEMORY - The present disclosure relates to an integrated circuit (IC) that includes a high-k metal gate (HKMG) non-volatile memory (NVM) device and that provides small scale and high performance, and a method of formation. In some embodiments, the integrated circuit includes a logic region and an embedded memory region disposed adjacent to the logic region. The logic region has a logic device disposed over a substrate and including a first metal gate disposed over a first high-k gate dielectric layer. The memory region has a non-volatile memory (NVM) device including a second metal gate disposed over a second high-k gate dielectric layer. By having HKMG structures in both the logic region and the memory region, IC performance is improved and further scaling becomes possible in emerging technology nodes. | 2017-06-15 |
20170170189 | EMBEDDED HKMG NON-VOLATILE MEMORY - The present disclosure relates to an integrated circuit (IC) that includes a high-k metal gate (HKMG) non-volatile memory (NVM) device and that provides small scale and high performance, and a method of formation. In some embodiments, the integrated circuit includes a logic region having a logic device disposed over a substrate and including a first metal gate disposed over a first high-k gate dielectric layer and an embedded memory region disposed adjacent to the logic region. The embedded memory region has a split gate flash memory cell including a select gate and a control gate. The control gate or the select gate is a metal gate separated from the substrate by a second high-k gate dielectric layer. By having HKMG structures in both the logic region and the memory region, IC performance is improved and further scaling becomes possible in emerging technology nodes. | 2017-06-15 |
20170170190 | MEMORY DEVICES AND SYSTEMS HAVING REDUCED BIT LINE TO DRAIN SELECT GATE SHORTING AND ASSOCIATED METHODS - 3D NAND memory devices and systems having reduced bit line to drain select gate shorting, including associated methods, are provided and described. | 2017-06-15 |
20170170191 | VERTICAL MEMORY DEVICE - A vertical memory device is provided as follows. A substrate has a cell array region and a connection region adjacent to the cell array region. A first gate stack includes gate electrode layers spaced apart from each other in a first direction perpendicular to the substrate. The gate electrode layers extends from the cell array region to the connection region in a second direction perpendicular to the first direction to form a first stepped structure on the connection region. The first stepped structure includes a first gate electrode layer and a second gate electrode layer sequentially stacked. The second gate electrode layer includes a first region having the same length as a length of the first gate electrode layer and a second region having a shorter length than the length of the first gate electrode layer. | 2017-06-15 |
20170170192 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - The present disclosure may provide a semiconductor device with an enhanced integration. The device may include a lower pipe gate; an upper pipe gate including a first horizontal portion and first and second protrusions, the first horizontal portion being parallel to the lower pipe gate, the first and second protrusions extending from the first horizontal portion to the lower pipe gate and crossing each other so as to define a pipe channel region; a partition pipe gate disposed between the lower and upper pipe gates, the partition pipe gate dividing the pipe channel region into first and second pipe channel regions; and first and second pipe channel films disposed respectively in the first and second pipe channel regions. | 2017-06-15 |
20170170193 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a cell structure; n first pad structures formed on one side of the cell structure and each configured to have a step form in which 2n layers form one stage; and n second pad structures formed on the other side of the cell structure each configured to have a step form in which 2n layers form one stage, wherein n is a natural number of 1 or higher, and the first pad structures and the second pad structures have asymmetrical step forms having different heights. | 2017-06-15 |
20170170194 | Semiconductor Chip Including Integrated Circuit Having Cross-Coupled Transistor Configuration and Method for Manufacturing the Same - A first conductive structure forms gate electrodes of a first transistor of a first transistor type and a first transistor of a second transistor type. A second conductive structure forms a gate electrode of a second transistor of the first transistor type. A third conductive structure forms a gate electrode of a second transistor of the second transistor type. A fourth conductive structure forms a gate electrode of a third transistor of the first transistor type. A fifth conductive structure forms a gate electrode of a third transistor of the second transistor type. A sixth conductive structure forms gate electrodes of a fourth transistor of the first transistor type and a fourth transistor of the second transistor type. The second and third transistors of the first transistor type and the second and third transistors of the second transistor type are electrically connected to form a cross-coupled transistor configuration. | 2017-06-15 |
20170170195 | EXTREMELY THIN SILICON-ON-INSULATOR SILICON GERMANIUM DEVICE WITHOUT EDGE STRAIN RELAXATION - A method for forming a semiconductor structure includes forming a strained silicon germanium layer on top of a substrate. At least one patterned hard mask layer is formed on and in contact with at least a first portion of the strained silicon germanium layer. At least a first exposed portion and a second exposed portion of the strained silicon germanium layer are oxidized. The oxidizing process forms a first oxide region and a second oxide region within the first and second exposed portions, respectively, of the strained silicon germanium. | 2017-06-15 |
20170170196 | HYBRID CIRCUIT INCLUDING A TUNNEL FIELD-EFFECT TRANSISTOR - The present invention relates generally to integrated circuits and more particularly, to a structure and method of forming a hybrid circuit including a tunnel field-effect transistor (TFET) and a conventional field effect transistor (FET). Embodiments of the present invention include a hybrid amplifier which features a TFET common-source feeding a common-gate conventional FET (e.g. a MOSFET). A TFET gate may be electrically isolated from an output from a conventional FET. Thus, a high impedance input may be received by a TFET with a high-isolation output (i.e. low capacitance) at a conventional FET. A hybrid circuit amplifier including a TFET and a conventional FET may have a very high input impedance and a low miller capacitance. | 2017-06-15 |
20170170197 | EXTREMELY THIN SILICON-ON-INSULATOR SILICON GERMANIUM DEVICE WITHOUT EDGE STRAIN RELAXATION - A method for forming a semiconductor structure includes forming a strained silicon germanium layer on top of a substrate. At least one patterned hard mask layer is formed on and in contact with at least a first portion of the strained silicon germanium layer. At least a first exposed portion and a second exposed portion of the strained silicon germanium layer are oxidized. The oxidizing process forms a first oxide region and a second oxide region within the first and second exposed portions, respectively, of the strained silicon germanium. | 2017-06-15 |
20170170198 | Array Substrate And Manufacturing Method Thereof - A manufacturing method for an array substrate is provided in the present invention. The method comprises: forming a Poly-Silicon layer on a glass substrate; forming heavily doped regions by performing heavily doping and acticvation process at both sides of the Poly-Silicon layer; forming a souce/a drain of a first metal layer growing on the heavily doped region; forming a gate of both a gate insulator and a second metal layer growing sequentially on the Poly-Silicon layer, wherein, a material of the second metal layer is aluminum. The activation technology process can be improved in the present invention to reduce RC delay in metal wires of product and then further to achieve large sizes for products. | 2017-06-15 |
20170170199 | CONDUCTIVE LAYER IN A SEMICONDUCTOR APPARATUS, DISPLAY SUBSTRATE AND DISPLAY APPARATUS HAVING THE SAME, AND FABRICATING METHOD THEREOF - The present application discloses a conductive layer in a semiconductor apparatus, comprising a metal sub-layer and an anti-reflective coating over the metal sub-layer for reducing light reflection on the metal sub-layer; wherein the anti-reflective coating comprises a light absorption sub-layer on the metal sub-layer for reducing light reflection by absorption and a light destructive interference sub-layer on a side of the light absorption layer distal to the metal sub-layer for reducing light reflection by destructive interference; and the metal sub-layer is made of a material comprising M1, wherein M1 is a single metal or a combination of metals; the light absorption sub-layer is made of a material comprising M2O | 2017-06-15 |
20170170200 | DISPLAY DEVICE - Provided is a display device with extremely high resolution, a display device with higher display quality, a display device with improved viewing angle characteristics, or a flexible display device. Same-color subpixels are arranged in a zigzag pattern in a predetermined direction. In other words, when attention is paid to a subpixel, another two subpixels exhibiting the same color as the subpixel are preferably located upper right and lower right or upper left and lower left. Each pixel includes three subpixels arranged in an L shape. In addition, two pixels are combined so that pixel units including subpixel are arranged in matrix of 3×2. | 2017-06-15 |
20170170201 | DISPLAY PANEL - A display panel is disclosed, which includes: a substrate with a first surface; a first conductive line with a first inclined surface, a second conductive line with a second inclined surface, a third conductive line with a third inclined surface and a fourth conductive line with a fourth inclined surface respectively disposed on the first surface of the substrate, wherein the first conductive line intersects the second conductive line and the fourth conductive line, and the third conductive line intersects the second conductive line and the fourth conductive line, wherein an angle included between the first surface and the first inclined surface or an extension surface thereof of the first conductive line is different from an angle included between the first surface and the third inclined surface or an extension surface thereof of the third conductive line. | 2017-06-15 |
20170170202 | MANUFACTURE METHOD OF TFT SUBSTRATE STRUCTURE AND TFT SUBSTRATE STRUCTURE - The present invention provides a manufacture method of a TFT substrate structure and a TFT substrate structure. In the manufacture method of the TFT substrate structure according to the present invention, by adjusting the parameter of etching as manufacturing the gate, the angular surfaces are formed at the two sides of the gate, and the gate is used to be a mask to implement ion implantation to the polysilicon layer to form the n-type heavy doping area and the n-type light doping area are formed at the polysilicon layer at the same time. In the TFT structure according to the present invention, the polysilicon layer comprises n-type heavy doping areas at two sides and n-type light doping areas between the channel area of the polysilicon layer and the n-type heavy doping areas. | 2017-06-15 |
20170170203 | LTPS ARRAY SUBSTRATE AND MANUFACTORING METHOD THEREOF - The present invention provides a LTPS array substrate and a manufacturing method thereof. The method comprises: forming a source electrode and a drain electrode on a substrate, forming polysilicon layers of a first region and a second region on the substrate including the source electrode and the drain electrode, and the thickness of the polysilicon layer of the first region is greater than the one of the second region, the polysilicon layer of the first region partially covers the source electrode and the drain electrode; passivating the surface of the polysilicon layer in order to turn the part of the adjacent surface of the polysilicon layer of the second region and the first region into an insulating layer; forming a gate electrode on the insulating layer between the source electrode and the drain electrode. The present invention can simplify the LTPS technical process and reduce the producing costs. | 2017-06-15 |
20170170204 | MANUFACTURING METHOD OF SUBSTRATE FOR DISPLAY DEVICE AND MANUFACTURING METHOD OF DISPLAY DEVICE - A substrate for a display device, includes: an insulation substrate; an insulation film, which is formed on the insulation substrate and is primarily made of one of silicon oxide and oxidized metal; an inorganic film, which is formed to be in direct contact with the insulation film and has an insulator part that is formed by changing oxide semiconductor into insulator; and a wiring film, which is formed to be in direct contact with the insulator part. | 2017-06-15 |
20170170205 | SILICON-ON-INSULATOR FIN FIELD-EFFECT TRANSISTOR DEVICE FORMED ON A BULK SUBSTRATE - A method for manufacturing a semiconductor device comprises forming a first diffusion stop layer on a bulk semiconductor substrate, forming a doped semiconductor layer on the first diffusion stop layer, forming a second diffusion stop layer on the doped semiconductor layer, forming a fin layer on the doped semiconductor layer, patterning the first and second diffusion stop layers, the doped semiconductor layer, the fin layer and a portion of the bulk substrate, oxidizing the doped semiconductor layer to form an oxide layer, and forming a dielectric on the bulk substrate adjacent the patterned portion of the bulk substrate, the patterned first diffusion stop layer and the oxide layer. | 2017-06-15 |
20170170206 | Flexible Display Device - A flexible display device of which esthetic appearance is improved by reducing a bezel is disclosed. The flexible display device comprises a substrate including a display area and a non-display area including a bending area; a link line in the non-display area on the substrate; and a bending connection line in the bending area pf the substrate and connected with the link line, and the bending connection line located between a first buffer layer and a second buffer layer of the flexible display device. | 2017-06-15 |
20170170207 | SEMICONDUCTOR DEVICE - A semiconductor device is provided to include a flexible substrate, a barrier layer, a heat insulating layer, a device layer, a dielectric material later and a stress absorbing layer. The barrier layer is disposed on the flexible substrate. The heat insulating layer is disposed on the barrier layer, wherein the heat insulating layer has a thermal conductivity of less than 20 W/mK. The device layer is disposed on the heat insulating layer. The dielectric material layer is disposed on the device layer, and the dielectric material layer and the heat insulating layer include at least one trench. The stress absorbing layer is disposed on the dielectric material layer, and the stress absorbing layer fills into the at least one trench. | 2017-06-15 |
20170170208 | METAL OXIDE SEMICONDUCTOR THIN FILM, THIN FILM TRANSISTOR, AND THEIR FABRICATING METHODS, AND DISPLAY APPARATUS - A metal oxide semiconductor thin film, a thin film transistor (TFT), methods for fabricating the metal oxide semiconductor thin film and the TFT, and a display apparatus are provided. In some embodiments, the metal oxide semiconductor comprises: a first metal element, a second metal element and a third metal element, wherein: the first metal element is at least one of scandium, yttrium, aluminum, indium, and a rare earth element; the second metal element is at least one of calcium, strontium, and barium; and the third metal element is at least one of titanium and tin. | 2017-06-15 |
20170170209 | THIN FILM TRANSISTOR ARRAY PANEL AND METHOD OF MANUFACTURING THE SAME - A thin film transistor array panel according to an exemplary embodiment of the present invention includes: an insulating substrate; a polycrystal semiconductor layer formed on the insulating substrate; a buffer layer formed below the polycrystal semiconductor layer and containing fluorine; a gate electrode overlapping the polycrystal semiconductor layer; a source electrode and a drain electrode overlapping the polycrystal semiconductor layer and separated from each other; and a pixel electrode electrically connected to the drain electrode. | 2017-06-15 |
20170170210 | DISPLAY PANEL - A display panel is disclosed. The display panel includes a first substrate, a display layer, a first conductive layer, a first insulation layer, a first protective layer, and a second insulation layer. The first substrate includes an active area and a peripheral area located adjacent to the active area. The display layer is disposed over the first substrate. The first conductive layer is disposed over the first substrate and located in the peripheral area. The first insulation layer is disposed between the first substrate and the first conductive layer. The first protective layer covers the first conductive layer. The second insulation layer is disposed over the first protective layer. The display panel according to the disclosure has better corrosion resistance to improve its reliability. | 2017-06-15 |
20170170211 | TRANSISTOR, SEMICONDUCTOR DEVICE, AND ELECTRONIC DEVICE - To provide a transistor with favorable electrical characteristics, a transistor with stable electrical characteristics, or a highly integrated semiconductor device. By covering a side surface of an oxide semiconductor layer in which a channel is formed with an oxide semiconductor layer, diffusion of impurities into the inside from the side surface of the oxide semiconductor layer is prevented. By forming a gate electrode in a damascene process, miniaturization and high density of a transistor are achieved. By providing a protective layer covering a gate electrode over the gate electrode, the reliability of the transistor is increased. | 2017-06-15 |
20170170212 | THIN FILM TRANSISTOR ARRAY SUBSTRATE AND METHOD OF FABRICATING THE SAME - A thin film transistor array substrate and a method of fabricating the same are disclosed. The thin film transistor array substrate has a device lamination layer, a passivation layer and a pixel electrode layer; the device lamination layer has a substrate, a first signal line layer, a semiconductor layer and a second signal line layer; the passivation layer is formed with a through hole and grooves; the pixel electrode layer is disposed on the passivation layer and inside the grooves; and the pixel electrode layer is connected with the second signal line layer through the through hole. The fabricating cost can be saved and the fabricating efficiency can be improved. | 2017-06-15 |
20170170213 | ARRAY SUBSTRATE, MANUFACTURING METHOD FOR ARRAY SUBSTRATE AND DISPLAY DEVICE - The present invention provides a manufacturing method for an array substrate including: forming a gate electrode; forming a gate insulation layer on the substrate and the first metal layer, and forming an oxide semiconductor layer on the gate insulation layer which is orthographically projected on the gate electrode; providing a photoresist layer on the oxide semiconductor layer; at two sides of the channel region of the oxide semiconductor layer are respectively a first oxide semiconductor layer and a second oxide semiconductor layer; performing a plasma treatment to the first and the second oxide semiconductor layer disposing with the photoresist layer; removing the photoresist layer; forming an etching stopper layer on the substrate; forming a source electrode and a drain electrode of the array substrate, wherein, the source electrode is contacted with the first oxide conductor layer and the drain electrode is contacted with the second oxide conductor layer. | 2017-06-15 |
20170170214 | Array Substrate, Manufacturing Method Thereof, Display Device, Thin-Film Transistor (TFT) and Manufacturing Method Thereof - An array substrate, a manufacturing method thereof, a display device, a thin-film transistor (TFT) and a manufacturing method thereof are disclosed. The method for manufacturing the TFT comprises: forming a pattern of an active layer and a gate insulating layer provided with a metal film on a base substrate; patterning the metal film by one patterning process, and forming patterns of a gate electrode, a source electrode, a drain electrode, a gate line and a data line; forming a passivation layer on the base substrate; patterning the passivation layer by one patterning process, and forming a source contact hole, a drain contact hole and a bridge structure contact hole; and forming a transparent conductive film on the base substrate, and removing partial transparent conductive film to form a source contact portion, a drain contact portion ( | 2017-06-15 |
20170170215 | SEMICONDUCTOR DEVICE STRUCTURE WITH ANTI-ACID LAYER AND METHOD FOR FORMING THE SAME - A semiconductor device structure and method for forming the same are provided. The semiconductor device structure includes an interconnect structure formed over a substrate and a passivation layer formed over the interconnect structure. The semiconductor device structure also includes an anti-acid layer formed in the passivation layer and a bonding layer formed on the anti-acid layer and the passivation layer. The anti-acid layer has a thickness that is greater than about 140 nm. | 2017-06-15 |
20170170216 | IMAGE SENSOR AND METHOD OF MANUFACTURING THE SAME - An image sensor includes a semiconductor layer including a first surface and a second surface, which are opposite to each other. A plurality of unit pixels is in the semiconductor layer. Each of the unit pixels includes a first photoelectric converter and a second photoelectric converter. A first isolation layer isolates adjacent unit pixels from one another. A second isolation layer is between the first photoelectric converter and the second photoelectric converter. The first isolation layer has a different shape from the second isolation layer. | 2017-06-15 |
20170170217 | SOLID-STATE IMAGING DEVICE, MANUFACTURING METHOD OF SOLID-STATE IMAGING DEVICE, AND ELECTRONIC DEVICE - The present technology relates to a solid-state imaging device, manufacturing method of a solid-state imaging device, and an electronic device, which can provide a solid-state imaging device having further improved features such as reduced optical color mixing and the like. Also, an electronic device using the solid-state imaging device thereof is provided. According to a solid-state imaging device having a substrate and multiple photoelectric converters that are formed on the substrate, an insulating film forms an embedded element separating unit. The element separating unit is configured of an insulating film having a fixed charge that is formed so as to coat the inner wall face of a groove portion, within the groove portion which is formed in the depth direction from the light input side of the substrate. | 2017-06-15 |
20170170218 | TOP GATE METAL OXIDE THIN FILM TRANSISTOR SWITCHING DEVICE FOR IMAGING APPLICATIONS - A method of manufacturing an image sensor device includes providing a substrate; forming a buffer layer on the substrate; forming a metal oxide channel on the buffer layer; forming a gate oxide layer on the buffer layer and the metal oxide channel; forming a gate metal layer on the gate oxide layer; forming a photodiode stack on the gate metal layer; patterning the gate oxide layer and the gate metal layer to form a first portion under the photodiode stack, and a second portion comprising a transistor; forming an interlayer dielectric layer over at least the photodiode stack and the transistor; forming a plurality of vias in the interlayer dielectric layer; and metalizing the vias to form contacts to the image sensor device. | 2017-06-15 |
20170170219 | SOLID-STATE IMAGING APPARATUS - A solid-state imaging apparatus includes: a solid-state imaging device photoelectrically converting light taken by a lens; and a light shielding member shielding part of light incident on the solid-state imaging device from the lens, wherein an angle made between an edge surface of the light shielding member and an optical axis direction of the lens is larger than an incident angle of light to be incident on an edge portion of the light shielding member. | 2017-06-15 |
20170170220 | IMAGE SENSOR HAVING HYBRID COLOR FILTER - An image sensor includes a photoelectric conversion layer, and color filters disposed on the photoelectric conversion layer and respectively in pixel regions, the color filters including a blue filter, a red filter, and a broad green filter. The blue filter includes an organic material, the red filter includes an organic material, and the broad green filter includes sub-micron structures including an inorganic material and disposed on the photoelectric conversion layer, and a dielectric layer covering the sub-microns structures, each of the sub-micron structures having a refractive index greater than a refractive index of the dielectric layer. | 2017-06-15 |
20170170221 | SOLID-STATE IMAGING APPARATUS - A solid-state imaging apparatus includes: a solid-state imaging device photoelectrically converting light taken by a lens; and a light shielding member shielding part of light incident on the solid-state imaging device from the lens, wherein an angle made between an edge surface of the light shielding member and an optical axis direction of the lens is larger than an incident angle of light to be incident on an edge portion of the light shielding member. | 2017-06-15 |
20170170222 | SOLID-STATE IMAGING DEVICE AND ELECTRONIC APPARATUS - The present disclosure relates to a solid-state imaging device that can perform phase difference detection at a high sensitivity even in fine pixels, and an electronic apparatus. | 2017-06-15 |
20170170223 | HYBRID BONDED IMAGE SENSOR AND METHOD OF OPERATING SUCH IMAGE SENSOR - In one form, a hybrid bonded image sensor comprises a photodiode chip, a circuit carrying chip, and an interconnection. The photodiode chip provides charge to a first floating diffusion in response to incident light, wherein the first floating diffusion is coupled to a first terminal on a first surface of the photodiode chip. The circuit carrying chip has a first terminal aligned with the first terminal of the photodiode chip, the circuit carrying chip forming an output voltage based on charge transferred on the first floating diffusion sensed from the first terminal thereof. The interconnection connects the first terminal of the photodiode chip to the first terminal of the circuit carrying chip. | 2017-06-15 |
20170170224 | CMOS IMAGE SENSOR AND FABRICATION METHOD THEREOF - A method to form a stacked CMOS image sensor includes forming a signal processing layer including a plurality of discrete signal processing circuit, an image sensor layer including a plurality of discrete image sensing units, and an intermediate capacitor layer including a dielectric layer and a plurality of capacitors. Each capacitor includes a first electrode, a V-shaped or U-shaped first electrode material layer electrically connecting to the first electrode, a second electrode material layer on the first electrode material layer having the dielectric layer there-between, and a second electrode electrically connecting to the second electrode material layer. The method further includes bonding the signal processing layer to the intermediate capacitor layer with each second electrode electrically connected to a signal processing circuit, and bonding the image sensor layer to the intermediate capacitor layer with each first electrode electrically connected to an image sensing unit. | 2017-06-15 |
20170170225 | PHOTOELECTRIC CONVERSION ELEMENT, IMAGE READING DEVICE, AND IMAGE FORMING APPARATUS - A photoelectric conversion element includes a plurality of light-receiving elements, a plurality of pixel circuits, and a plurality of storage units. The light-receiving elements are aligned in a predetermined alignment direction for each color of light to be received, to receive and convert the light into electric charge. The pixel circuits are disposed respectively adjacent to the plurality of light-receiving elements, to convert the electric charge generated by the corresponding light-receiving element into a voltage signal. The storage units are disposed respectively corresponding to the plurality of the pixel circuits, to store therein the voltage signal generated by the corresponding pixel circuit. The storage units are disposed in an adjacent region that is adjacent to a photoelectric conversion region in which the light-receiving elements and the pixel circuits are disposed. | 2017-06-15 |
20170170226 | SOLID-STATE IMAGING DEVICE - A solid-state imaging device according to the present disclosure includes: a charge storage region that stores a signal charge obtained through photoelectric conversion in a photoelectric conversion film; an amplification transistor that amplifies the signal charge stored in the charge storage region in a corresponding pixel; a contact plug that is electrically connected to the charge storage region and contains a semiconductor material; and a line that is disposed above the contact plug and contains a semiconductor material. The contact plug and the charge storage region are electrically connected, and the contact plug and a gate electrode of the amplification transistor are electrically connected via the line. | 2017-06-15 |
20170170227 | PHOTOELECTRIC CONVERSION APPARATUS AND INFORMATION PROCESSING APPARATUS - A semiconductor apparatus includes a first photodiode arranged in a semiconductor substrate, a second photodiode arranged in the semiconductor substrate, a charge voltage conversion part connected to a cathode of the first photodiode and an anode of the second photodiode and configured to convert a charge amount in accordance with electrons generated in the first photodiode and holes generated in the second photodiode into a voltage, and a signal generation part configured to generate a signal in accordance with the voltage of the charge voltage conversion part. | 2017-06-15 |
20170170228 | IMAGE SENSOR AND METHOD OF MANUFACTURING THE SAME - An image sensor includes a first charge storage region of a first conductive type disposed in a substrate, a second charge storage region of a second conductive type disposed on one side of the first charge storage region, a first floating diffusion region spaced apart from the first charge storage region, a second floating diffusion region spaced apart from the second charge storage region, a first transfer gate disposed on the substrate between the first charge storage region and the first floating diffusion region, and a second transfer gate disposed on the substrate between the second charge storage region and the second floating diffusion region. | 2017-06-15 |
20170170229 | IMAGE SENSOR AND METHOD OF MANUFACTURING THE SAME - An image sensor and a method of manufacturing the image sensor are provided. The image sensor includes: a substrate comprising a pixel area, a first side, and a second side opposite to the first side, wherein the pixel area includes pixels and light is incident to the second side; a photodiode arranged in each of the pixels of the substrate; a pixel separation structure arranged in the substrate to separate the pixels from each other and including a conductive layer therein; and a voltage-applying wire layer spaced apart from the conductive layer and arranged to surround at least a portion of an outer portion of the pixel area. The conductive layer has a mesh structure that is a single unitary structure, and the voltage-applying wire layer is electrically connected to the conductive layer through at least one contact. | 2017-06-15 |
20170170230 | IMAGE CAPTURING APPARATUS, MANUFACTURING METHOD THEREOF, AND CAMERA - A back-side illumination image capturing apparatus includes a semiconductor substrate having a first surface for receiving incident light and a second surface located on the opposite side as the first surface, and including a photoelectric conversion portion, and a gate electrode disposed above the second surface. The apparatus further includes a first insulating layer disposed above the second surface of the semiconductor substrate, an interlayer insulation film disposed on the first insulating layer, a contact plug connected to the gate electrode, and a light-cutting portion for cutting light, of the incident light, that has passed through the photoelectric conversion portion. The light-cutting portion passes through at least part of the interlayer insulation film. The first insulating layer is located between the light-cutting portion and the semiconductor substrate. | 2017-06-15 |
20170170231 | Pixel Isolation Device and Fabrication Method - Backside illuminated (BSI) image sensor devices are described as having pixel isolation structures formed on a sacrificial substrate. A photolayer is epitaxially grown over the pixel isolation structures. Radiation-detecting regions are formed in the photolayer adjacent to the pixel isolation structures. The pixel isolation structures include a dielectric material. The radiation-detecting regions include photodiodes. A backside surface of the BSI image sensor device is produced by planarized removal of the sacrificial substrate to physically expose the pixel isolation structures or at least optically expose the photolayer. | 2017-06-15 |
20170170232 | Wide Band Gap Device Integrated Circuit Architecture on Engineered Substrate - Disclosed herein are wide band gap integrated circuits, such as gallium nitride (GaN) integrated circuits, including a plurality of groups of epitaxial layers formed on an engineered substrate, and methods of making the WBG integrated circuits. The epitaxial layers have a coefficient of thermal expansion (CTE) substantially matching the CTE of the engineered substrate. Mesas, internal interconnects, and electrodes configure each group of epitaxial layers into a WBG device. External interconnects connect different WBG devices into a WBG integrated circuit. The CTE matching allows the formation of epitaxial layers with reduced dislocation density and an overall thickness of greater than 10 microns on a six-inch or larger engineered substrate. The large substrate size and thick WBG epitaxial layers allow a large number of high density WBG integrated circuits to be fabricated on a single substrate. | 2017-06-15 |
20170170233 | Integrated structures of acoustic wave device and varactor, and acoustic wave device, varactor and power amplifier, and fabrication methods thereof - An integrated structure of acoustic wave device and varactor comprises an acoustic wave device and a varactor formed on a first part and a second part of a semiconductor substrate respectively. The acoustic wave device comprises an acoustic wave device upper structure and a first part of a bottom epitaxial structure. The acoustic wave device upper structure is formed on the first part of the bottom epitaxial structure. The varactor comprises a varactor upper structure and a second part of the bottom epitaxial structure. The varactor upper structure is formed on the second part of the bottom epitaxial structure. The integrated structure of the acoustic wave device and the varactor formed on the same semiconductor substrate is capable of reducing the module size, optimizing the impedance matching, and reducing the signal loss between the varactor and the acoustic wave device. | 2017-06-15 |
20170170234 | MAGNETORESISTIVE RANDOM ACCESS MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A magnetoresistive random access memory (MRAM) device including a substrate including a plurality of active patterns arranged along a first direction, each of the active patterns extending in a diagonal direction with respect to the first direction; a plurality of gate structures on the substrate, the gate structures extending in a second direction substantially perpendicular to the first direction; a source line structure electrically connected to source regions of the respective active patterns, the source line structure extending in the first direction; a plurality of magnetic tunnel junction (MTJ) structures electrically connected to drain regions of the respective active patterns, the MTJ structures being spaced apart from each other; and a bit line structure electrically connected to the MTJ structures in respective memory cells, the memory cells sharing with the source line structure. | 2017-06-15 |
20170170235 | SWITCHING DEVICE, AND RESISTIVE RANDOM ACCESS MEMORY INCLUDING THE SAME AS A SELECTION DEVICE - A switching device includes a first electrode, a switching layer and a second electrode that are disposed over a substrate. The switching layer includes an oxide of a first atom or a nitride of the first atom, and a second atom is doped in the oxide or the nitride. A valence of the first atom and a valence of the second atom are different from each other. | 2017-06-15 |
20170170236 | MEMORY CELL STRUCTURE WITH RESISTANCE-CHANGE MATERIAL AND METHOD FOR FORMING THE SAME - Semiconductor structures and methods for forming the same are provided. The semiconductor structure includes a substrate and a memory cell structure formed over the substrate. In addition, the memory cell structure includes a first electrode layer formed over the substrate and a resistance-change material layer formed over the first electrode layer. The memory cell structure further includes a second electrode layer formed over the resistance-change material layer. In addition, the resistance-change material layer includes a semimetal or a semimetal alloy. | 2017-06-15 |
20170170237 | VARIABLE RESISTIVE MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A variable resistive memory device includes a first electrode layer, a variable resistive pattern structure located on the first electrode layer and including a variable resistive layer, a capping layer formed on opposite side walls of the variable resistive pattern structure and including regions having different impurity concentrations, and a second electrode layer formed on the capping layer. | 2017-06-15 |
20170170238 | IMAGE SENSORS AND METHODS OF FORMING IMAGE SENSORS - Image sensors are provided. An image sensor includes a color filter layer. The image sensor includes a metal structure adjacent a sidewall of the color filter layer. The image sensor includes an insulating layer on the color filter layer. Moreover, the image sensor includes an electrode layer on the insulating layer. Methods of forming image sensors are also provided. | 2017-06-15 |
20170170239 | IMAGE SENSOR - An image sensor includes a substrate comprising a first face and a second surface which faces the first surface and on which light is incident, a semiconductor photoelectric conversion device on the substrate, a gate electrode located between the first surface of the substrate and the semiconductor photoelectric conversion device and extending in a first direction perpendicular to the first surface, and an organic photoelectric conversion device stacked on the second surface of the substrate. | 2017-06-15 |
20170170240 | SOLID-STATE IMAGE PICKUP DEVICE AND ELECTRONIC APPARATUS - A solid-state image pickup device includes at least two stacked first and second photoelectric conversion sections in each of a plurality of pixels. Sensitivity of the first photoelectric conversion section to a light incident angle is equivalent to sensitivity of the second photoelectric conversion section to a light incident angle, for each of the pixels. | 2017-06-15 |
20170170241 | DISPLAY PANEL - A display panel includes a first substrate, a lighting device emitting a monochrome light, and a quantum dots layer. The display panel defines a plurality of pixel areas, each pixel area includes a plurality of sub-pixels for correspondingly emitting light of different colors. The quantum dots layer receives the monochrome light and converts the monochrome light to the light of different colors. The light passing through the quantum dots layer is directly emitted into the first sub-pixel, the second sub-pixel, and the third sub-pixel respectively. | 2017-06-15 |
20170170242 | DISPLAY DEVICE AND MANUFACTURING METHOD OF THE SAME - A display device includes a first substrate including a first area and a second area, light emitting elements arranged in the first area, connecting pads arranged in the second area, a thin film encapsulation layer arranged on the light emitting elements, a second substrate including a third area and a fourth area, sensing pads arranged in the fourth area, a touch sensor layer including sensing electrodes arranged in the third area and sensing lines connected between the sensing electrodes and the sensing pads, an interlayer arranged between the thin film encapsulation layer and the touch sensor layer, and a conductive member connected between the connecting pads and the sensing pads. | 2017-06-15 |
20170170243 | REFLECTIVE DISPLAY DEVICE - A reflective display device is disclosed, which includes first and second substrates facing each other, each of which includes a display area and a reflective area; a display element provided in the display area; and a reflective control element provided in the reflective area, controlling reflectance of externally incident light. The reflective display device may improve a contrast ratio by controlling reflectance of a reflective area when an image is displayed. | 2017-06-15 |
20170170244 | BANK REPAIR METHOD, ORGANIC EL DISPLAY DEVICE AND MANUFACTURING METHOD THEREOF - An examination is performed of whether or not a bank having a defect portion is present. When a bank having a defect portion is present, the bank having the defect portion is repaired by forming a dam in each of adjacent concave spaces between which the bank having the defect portion is located. A dam formed in a concave space partitions the concave space into a first space in a vicinity of the defect portion and a second space outside the vicinity of the defect portion. The dam, at a portion thereof with lowest height, satisfies (h/H)+0.1W≧1.5, 0.5≦(h/H)≦2.0, and 5≦W≦50, where a ratio of the height h of the dam to a height H of the banks is denoted as h/H, and a width of the dam is denoted as W μm. | 2017-06-15 |
20170170245 | ORGANIC LIGHT EMITTING DIODE DISPLAY AND METHOD FOR MANUFACTURING THE SAME - The present disclosure relates to an organic light emitting diode display. The display includes: a substrate; a thin film transistor array disposed on the substrate; a light emitting module including: a pixel-defining layer disposed on the thin film transistor array and provided with a plurality of openings for defining positions of pixels; and a plurality of light emitting units disposed on the thin film transistor array and in the openings of the pixel-defining layer; color filter units on the light emitting module which are disposed in the openings of the pixel-defining layer so that the color filter units corresponds to the light emitting units in the openings of the pixel-defining layer; and a package layer disposed on and covering the color filter units. The organic light emitting diode display in the present disclosure may be applied into large-sized displays and meet lighting and thinning requirements. | 2017-06-15 |
20170170246 | ORGANIC LIGHT EMITTING DISPLAY DEVICE - An organic light emitting display device can include a substrate; an anode electrode on the substrate; an organic emitting layer on the anode electrode; a cathode electrode on the organic emitting layer; an auxiliary electrode connected to the cathode electrode; a bank provided on either side of the auxiliary electrode; and a partition spaced apart from the bank and provided on the auxiliary electrode, in which the partition includes a plurality of first partitions provided on the auxiliary electrode and spaced apart from each other, and the partition further includes a second partition provided on the plurality of first partitions, and a width of an upper surface of the second partition is larger than a width of a lower surface of the second partition. | 2017-06-15 |
20170170247 | ORGANIC LIGHT-EMITTING DISPLAY DEVICE - Described herein is an organic light-emitting display (OLED) device, comprising: a first substrate comprising an array of pixels; a second substrate facing the first substrate and comprising a color layer corresponding to each pixel in the array of pixels, and comprising a black matrix separating each pixel in the array of pixels from one another; a filler layer between the first substrate and the second substrate; a side encapsulation structure between the first substrate and the second substrate along side edges thereof, wherein the side encapsulation layer is around the filler layer; and a first support on an outer portion of the side encapsulation structure on the first substrate. | 2017-06-15 |
20170170248 | DISPLAY DEVICE - The display device includes a first substrate having flexibility and including pixels arranged in matrix form in a first direction and a second direction, the first direction and second direction mutually intersecting each other, a transistor layer arranged above the first substrate and including at least one transistor arranged in each of the pixels, an inorganic insulation film formed continuously across the pixels in the second direction, and a plurality of aperture parts extending in the second direction and arranged between two transistors arranged in two of the plurality of pixels adjacent in the first direction, a plurality of first groups of wiring extending in the first direction and connected to each of the pixels arranged in the first direction, and a plurality of second groups of wiring extending in the second direction and connected to each of the pixels arranged in the second direction. | 2017-06-15 |
20170170249 | ORGANIC LIGHT EMITTING DISPLAY DEVICE AND METHOD OF MANUFACTURING THE SAME - An organic light emitting display device includes a substrate including a plurality of pixel regions each including a light emitting region and a transparent region, a gate electrode in the light emitting region, a first insulating interlayer covering the gate electrode and extending from the light emitting region to the transparent region, a drain electrode on the first insulating interlayer and constituting a transistor in conjunction with the gate electrode, a planarization layer covering the transistor and exposing a top surface of the first insulating interlayer in the transparent region, and a first electrode on the planarization layer. | 2017-06-15 |
20170170250 | ORGANIC EL DISPLAY DEVICE - An organic EL display device includes a substrate, a fin structure on the substrate, the fin structure standing upright in a thickness direction of the substrate, a first electrode formed on at least a part of a side surface of the fin structure, an organic film which is laminated so as to cover a surface of the first electrode on the side surface of the fin structure, a second electrode that is transparent and laminated so as to cover a surface of the organic film on the side surface and a top portion of the fin structure, a color filter layer that is formed on a path that light travels after being emitted from the light emitting layer and passing through the second electrode and formed at least above the organic film laminated on the side surface, and a light blocking layer configured to block light formed above the top portion of the fin structure. | 2017-06-15 |
20170170251 | ORGANIC LIGHT-EMITTING DEVICE - An organic light-emitting device includes an oxide semiconductor layer disposed in a pixel area. The oxide semiconductor layer includes a channel region, a source region and a drain region. A gate insulating layer is disposed on the oxide semiconductor layer. A gate electrode is disposed on the gate insulating layer. A conductive layer is disposed between the substrate and the oxide semiconductor layer. A bridge electrode is in contact with the conductive layer and one of the source region and the drain region. A first insulation film covers the gate electrode and the bridge electrode. An organic light-emitting diode includes a pixel electrode. An emissive layer is disposed on the pixel electrode, and an opposite electrode is disposed on the emissive layer. At least a portion of the oxide semiconductor layer overlaps the organic light-emitting diode. The conductive layer includes a light transmittance material. | 2017-06-15 |
20170170252 | ORGANIC LIGHT EMITTING DIODE DISPLAY AND MANUFACTURING METHOD THEREOF - An organic light emitting diode display, includes a substrate; a thin film transistor and a storage capacitor that are disposed and spaced apart from each other on the substrate; and an organic light emitting diode that is connected to the thin film transistor. The storage capacitor includes a capacitor lower electrode, a capacitor insulating layer disposed on the capacitor lower electrode, and a capacitor upper electrode disposed on the capacitor insulating layer. The capacitor lower electrode is a conducting oxide semiconductor into which hydrogen has diffused. | 2017-06-15 |
20170170253 | DISPLAY DEVICE - A display device is disclosed. In one aspect, the display device includes a flexible substrate including a first region, a second region separated from the first region, and a bending region positioned between the first and second regions. The bending region is configured to be bent so as to have a plurality of different curvatures depending on degrees of bending of the flexible substrate. The display device also includes a first display unit positioned in the first region, a second display unit separated from the first display unit and positioned in the second region and an encapsulation layer positioned over the flexible substrate with the first and second display units interposed therebetween. The encapsulation layer directly contacts the bending region of the flexible substrate. | 2017-06-15 |
20170170254 | DISPLAY DEVICE - A filling material is provided in an interval part between a first substrate provided with a light emitting device in a pixel and a second substrate provided with a color filter layer corresponding to each pixel which is provided to face each other and a protruding part is provided in the interval part. The protruding part is provided separated along one edge of each pixel. An end part in a length direction of the protruding part is formed in a cone or streamlined shape. In addition, the protruding part is formed from a material having light absorbing properties such as carbon black so as to provide light shielding properties. By adopting this structure, it is possible to solve a problem of mixing colors produced between pixels. It is possible to ensure that the flow of the filling material provided between the first substrate and the second substrate is not obstructed. | 2017-06-15 |
20170170255 | FLEXIBLE DISPLAY APPARATUS - A flexible display apparatus includes a display substrate including a light-emitting area, and a non-emitting area including a bending area foldable in a folding direction outside of the light-emitting area, and a pad area outside of the bending area, a thin film encapsulation layer over the light-emitting area, and a driver inside a curvature portion of the display substrate at the bending area, and including a plurality of driving terminals electrically connected to a plurality of pad terminals in the pad area through penetration wirings in via holes defined by the display substrate. | 2017-06-15 |
20170170256 | CAPACITOR AND FABRICATION METHOD THEREOF - A method for fabricating capacitor is disclosed. The method includes the steps of: providing a material layer; forming a first conductive layer, a first dielectric layer, and a second conductive layer on the material layer; patterning the first dielectric layer and the second conductive layer to form a patterned first dielectric layer and a middle electrode; forming a second dielectric layer on the first conductive layer and the middle electrode; removing part of the second dielectric layer to form a patterned second dielectric layer; forming a third conductive layer on the first conductive layer and the patterned second dielectric layer, wherein the third conductive layer contacts the first conductive layer directly; and removing part of the third conductive layer to expose part of the patterned second dielectric layer. | 2017-06-15 |
20170170257 | CAPACITOR AND METHOD FOR FABRICATING THE SAME - A capacitor includes: a bottom electrode; a middle electrode on the bottom electrode; a top electrode on the middle electrode; a first dielectric layer between the bottom electrode and the middle electrode; and a second dielectric layer between the middle electrode and the top electrode. Preferably, the second dielectric layer is disposed on at least a sidewall of the middle electrode to physically contact the first dielectrically, and the middle electrode includes a H-shape. | 2017-06-15 |
20170170258 | VERTICAL MOSFET - In order to improve the dynamic characteristics of a vertical MOSFET using GaN, it is an objective of the present invention to reduce the resistance of a current path with a long hole movement distance in a p-type well. Provided is a vertical MOSFET including a gallium nitride layer having a main surface that is a non-polar surface; a p-type well region that is provided with a stripe shape in the main surface of the gallium nitride layer; and a stripe-shaped electrode provided above the p-type well region. Hole mobility is higher in a direction orthogonal to an extension direction of the stripe-shaped electrode than in the extension direction, among directions in a plane parallel to the main surface. | 2017-06-15 |
20170170259 | SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor layer made of a wide bandgap semiconductor and including a gate trench; a gate insulating film formed on the gate trench; and a gate electrode embedded in the gate trench to be opposed to the semiconductor layer through the gate insulating film. The semiconductor layer includes a first conductivity type source region; a second conductivity type body region; a first conductivity type drift region; a second conductivity type first breakdown voltage holding region; a source trench passing through the first conductivity type source region and the second conductivity type body region from the front surface and reaching a drain region; and a second conductivity type second breakdown voltage region selectively formed on an edge portion of the source trench where the sidewall and the bottom wall thereof intersect with each other in a parallel region of the source trench. | 2017-06-15 |
20170170260 | Universal Methodology to Synthesize Diverse Two-Dimensional Heterostructures - A two-dimensional heterostructure is synthesized by producing a patterned first two-dimensional material on a growth substrate. The first two-dimensional material is patterned to define at least one void through which an exposed region of the growth substrate is exposed. Seed molecules are selectively deposited either on the exposed region of the growth substrate or on the patterned first two-dimensional material. A second two-dimensional material that is distinct from the first two-dimensional material is then grown from the deposited seed molecules. | 2017-06-15 |
20170170261 | COALESCED NANOWIRE STRUCTURES WITH INTERSTITIAL VOIDS AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device, such as an LED, includes a plurality of first conductivity type semiconductor nanowire cores located over a support, a continuous second conductivity type semiconductor layer extending over and around the cores, a plurality of interstitial voids located in the second conductivity type semiconductor layer and extending between the cores, and first electrode layer that contacts the second conductivity type semiconductor layer. | 2017-06-15 |
20170170262 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes a first conductivity type semiconductor substrate, a second conductivity type first and second buried diffusion layers that are arranged in the semiconductor substrate, a semiconductor layer arranged on the semiconductor substrate, a second conductivity type first impurity diffusion region that is arranged in the semiconductor layer, a second conductivity type second impurity diffusion region that is arranged, in the semiconductor layer, on the second buried diffusion layer, a second conductivity type first well that is arranged in a first region of the semiconductor layer, a first conductivity type second well that is arranged, in the semiconductor layer, in a second region, a first conductivity type third and fourth impurity diffusion regions that are arranged in the first well, and a first conductivity type fifth impurity diffusion region that is arranged in the second well. | 2017-06-15 |
20170170263 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF - A semiconductor device and a fabrication method are provided. The semiconductor device is fabricated by providing a substrate with a device area surrounded by a seal ring area, forming a buried deep-well layer in the substrate of the seal ring area, forming a first well region and a second well region in the substrate above the buried deep-well layer with the first well region surrounding the device area and the second well region surrounding the first well region, forming a heavily doped region in the substrate above the buried deep-well layer and between the first well region and the second well region, and forming a seal ring structure connecting to the heavily doped region. The buried deep-well layer, the first well region, and the second well region all have a first doping type while the heavily doped region and the substrate have a second doping type. | 2017-06-15 |
20170170264 | Semiconductor Devices and a Circuit for Controlling a Field Effect Transistor of a Semiconductor Device - A semiconductor device includes a plurality of drift regions of a plurality of field effect transistor structures arranged in a semiconductor substrate. The plurality of drift regions has a first conductivity type. The semiconductor device further includes a plurality of compensation regions arranged in the semiconductor substrate. The plurality of compensation regions has a second conductivity type. Each drift region of the plurality of drift regions is arranged adjacent to at least one compensation region of the plurality of compensation regions. The semiconductor device further includes a Schottky diode structure or metal-insulation-semiconductor gated diode structure arranged at the semiconductor substrate. | 2017-06-15 |
20170170265 | THICK GATE OXIDE FET INTEGRATED WITH FDSOI WITHOUT ADDITIONAL THICK OXIDE FORMATION - A semiconductor structure formed based on a buried oxide (BOX) layer configured as a gate dielectric; a substrate adjacent to the BOX layer configured as a first gate electrode; a first source structure and a first drain structure, each residing above the BOX layer; a first channel structure residing between the first drain and first source structures; a second gate electrode residing above the first channel structure; a first shallow trench isolation (STI) structure and a second STI structure, each residing coplanar with and at opposite ends of the first source and first drain structures; and a second gate dielectric residing between the first channel structure and the second gate electrode, wherein a thickness of the second gate dielectric is less than a thickness of the BOX layer. | 2017-06-15 |
20170170266 | GATE CONTACT WITH VERTICAL ISOLATION FROM SOURCE-DRAIN - A method of forming a semiconductor structure includes forming a gate structure having a first conductive material above a semiconductor substrate, gate spacers on opposing sides of the first conductive material, and a first interlevel dielectric (ILD) layer surrounding the gate spacers and the first conductive material. An upper portion of the first conductive material is recessed. The gate spacers are recessed until a height of the gate spacers is less than a height of the gate structure. An isolation liner is deposited above the gate spacers and the first conductive material. A portion of the isolation liner is removed so that a top surface of the first conductive material is exposed. A second conductive material is deposited in a contact hole created above the first conductive material and the gate spacers to form a gate contact. | 2017-06-15 |
20170170267 | STACKED CARBON NANOTUBE MULTIPLE THRESHOLD DEVICE - A device structure including a gate structure containing a first layer of carbon nanotubes and a second layer of carbon nanotubes. The first and the second layers are stacked vertically. The first and the second layers have carbon nanotubes which have substantially homogeneous electric characteristics within each layer. The carbon nanotubes in the first layer have different electric characteristics than the carbon nanotubes in the second layer, so that the device structure exhibits a multiple threshold behavior when coupled to a voltage source. The disclosure also includes a method for fabricating a multithreshold device structure. | 2017-06-15 |
20170170268 | NANOWIRE METAL-OXIDE SEMICONDUCTOR (MOS) FIELD-EFFECT TRANSISTORS (FETs) (MOSFETs) EMPLOYING A NANOWIRE CHANNEL STRUCTURE HAVING ROUNDED NANOWIRE STRUCTURES - Nanowire metal-oxide semiconductor (MOS) Field-Effect Transistors (FETs) (MOSFETs) employing a nanowire channel structure having rounded nanowire structures is disclosed. To reduce the distance between adjacent nanowire structures to reduce parasitic capacitance while providing sufficient gate control of the channel, the nanowire channel structure employs rounded nanowire structures. For example, the rounded nanowire structures provide for a decreased height from a center area of the rounded nanowire structures to end areas of the rounded nanowire structures. Gate material is disposed around rounded ends of the rounded nanowire structures to extend into a portion of separation areas between adjacent nanowire structures. The gate material extends in the separation areas between adjacent nanowire structures sufficient to create a fringing field to the channel where gate material is not adjacently disposed, to provide strong gate control of the channel even though gate material does not completely surround the rounded nanowire structures. | 2017-06-15 |
20170170269 | STACKED NANOSHEETS BY ASPECT RATIO TRAPPING - A semiconductor structure is provided that includes a plurality of suspended and stacked nanosheets of semiconductor channel material located above a pillar of a sacrificial III-V compound semiconductor material. Each semiconductor channel material comprises a semiconductor material that is substantially lattice matched to, but different from, the sacrificial III-V compound semiconductor material, and each suspended and stacked nanosheets of semiconductor channel material has a chevron shape. A functional gate structure can be formed around each suspended and stacked nanosheet of semiconductor channel material. | 2017-06-15 |
20170170270 | NANOWIRE FIELD EFFECT TRANSISTOR (FET) AND METHOD FOR FABRICATING THE SAME - A semiconductor structure includes a plurality of semiconductor fins located on a semiconductor substrate, in which each of the semiconductor fins comprises a sequential stack of a buffered layer including a III-V semiconductor material and a channel layer including a III-V semiconductor material. The semiconductor structure further includes a gap filler material surrounding the semiconductor fins and including a plurality of trenches therein. The released portions of the channel layers of the semiconductor fins located in the trenches constitute nanowire channels of the semiconductor structure, and opposing end portions of the channel layers of the semiconductor fins located outside of the trenches constitute a source region and a drain region of the semiconductor structure, respectively. In addition, the semiconductor structure further includes a plurality of gates structures located within the trenches that surround the nanowire channels in a gate all around configuration. | 2017-06-15 |
20170170271 | FABRICATION OF SEMICONDUCTOR JUNCTIONS - A method comprises providing a cavity structure on the substrate comprising a first growth channel extending in a first direction, a second growth channel extending in a second direction, wherein the second direction is different from the first direction and the second channel is connected to the first channel at a channel junction, a first seed surface in the first channel, at least one opening for supplying precursor materials to the cavity structure, selectively growing from the first seed surface a first semiconductor structure substantially only in the first direction and in the first channel, thereby forming a second seed surface for a second semiconductor structure at the channel junction, growing in the second channel the second semiconductor structure in the second direction from the second seed surface, thereby forming the semiconductor junction comprising the first and the second semiconductor structure. | 2017-06-15 |
20170170272 | COINTEGRATION OF DIRECTED SELF ASSEMBLY AND SIDEWALL IMAGE TRANSFER PATTERNING FOR SUBLITHOGRAPHIC PATTERNING WITH IMPROVED DESIGN FLEXIBILITY - After forming transfer layer portions over a portion of a dielectric cap layer overlying a first portion of a substrate by a directed self-assembly process, a hard mask layer is formed over the dielectric cap layer to fill spaces between the transfer layer portions. Spacers are then formed over a portion of the hard mask layer overlying a second portion of the substrate by a sidewall image transfer process. A top semiconductor layer of the substrate is subsequently patterned using the transfer layer portions and the spacers as an etch mask to provide densely packed semiconductor fins in the first region and semi-isolated semiconductor fins in the second region of the substrate. | 2017-06-15 |
20170170273 | SEMICONDUCTOR DEVICE - Provided is a semiconductor device including a plurality of dummy trench portions that are provided in a front surface side of a semiconductor substrate and each have provided therein an electrode to which an emitter potential is supplied, and a gate trench portion that is provided in a manner to surround two or more dummy trench portions from among the plurality of dummy trench portions in the front surface side of the semiconductor substrate and has provided therein an electrode to which a gate potential is supplied. | 2017-06-15 |
20170170274 | Semiconductor Device Comprising a First Gate Trench and a Second Gate Trench - A semiconductor device includes a first gate trench and a second gate trench in a first main surface of a semiconductor substrate. A mesa is arranged between the first gate trench and the second gate trench. The mesa separates the first gate trench from the second gate trench. Each of the first and second gate trenches includes first sections extending in a first direction and second sections connecting adjacent ones of the first sections. The second sections of the first gate trench are disposed opposite to the second sections of the second gate trench with respect to a plane perpendicular to the first direction. | 2017-06-15 |