24th week of 2011 patent applcation highlights part 18 |
Patent application number | Title | Published |
20110140214 | PATTERN ARRANGEMENT METHOD, SILICON WAFER AND SEMICONDUCTOR DEVICE - A pattern arrangement method including using a stepper to arrange a plurality of chip patterns arranged parallel to a first direction and a second direction on a silicon wafer using a reticule which includes a plurality of patterns expanded in the first direction and the second direction which intersects the first direction and arranged linearly and intermittently, wherein the stepper adjusts the position of the reticule and the silicon wafer which faces the reticule so that an axis in which a cleavage plane of the silicon wafer and a surface arranged with the pattern on the silicon wafer intersect, and the first direction are different. | 2011-06-16 |
20110140215 | SEMICONDUCTOR PRESSURE SENSOR AND METHOD FOR MANUFACTURING THE SAME - A semiconductor pressure sensor comprises: a substrate having a through-hole; a polysilicon film provided on the substrate and having a diaphragm above the through-hole; an insulating film provided on the polysilicon film; first, second, third, and forth polysilicon gauge resistances provided on the insulating film and having a piezoresistor effect; and polysilicon wirings connecting the first, second, third, and forth polysilicon gauge resistances in a bridge shape, wherein each of the first and second polysilicon gauge resistances is disposed on a central portion of the diaphragm and has a plurality of resistors connected in parallel, a structure of the first polysilicon gauge resistance is same as a structure of the second polysilicon gauge resistance, and a direction of the first polysilicon gauge resistance is same as a direction of the second polysilicon gauge resistance. | 2011-06-16 |
20110140216 | Method of wafer-level fabrication of MEMS devices - The present disclosure relates to a method of fabricating a micromachined CMOS-MEMS integrated device as well as the devices/apparatus resulting from the method. In the disclosed method, the anisotropic etching (e.g., DRIE) for isolation trench formation on a MEMS element is performed on the back side of a silicon wafer, thereby avoiding the trench sidewall contamination and the screen effect of the isolation beams in a plasma etching process. In an embodiment, a layered wafer including a substrate and a composite thin film thereon is subjected to at least one (optionally at least two) back side anisotropic etching step to form an isolation trench (and optionally a substrate membrane). The method overcomes drawbacks of other microfabrication processes, including isolation trench sidewall contamination. | 2011-06-16 |
20110140217 | SPIN TRANSFER MAGNETIC ELEMENT WITH FREE LAYERS HAVING HIGH PERPENDICULAR ANISOTROPY AND IN-PLANE EQUILIBRIUM MAGNETIZATION - A method and system for providing a magnetic element that can be used in a magnetic memory is disclosed. The magnetic element includes pinned, nonmagnetic spacer, and free layers. The spacer layer resides between the pinned and free layers. The free layer can be switched using spin transfer when a write current is passed through the magnetic element. The free layer includes a first ferromagnetic layer and a second ferromagnetic layer. The second ferromagnetic layer has a very high perpendicular anisotropy and an out-of-plane demagnetization energy. The very high perpendicular anisotropy energy is greater than the out-of-plane demagnetization energy of the second layer. | 2011-06-16 |
20110140218 | Memory Constructions Comprising Magnetic Materials - The invention includes a method of forming a semiconductor construction, such as an MRAM construction. A block is formed over a semiconductor substrate. First and second layers are formed over the block, and over a region of the substrate proximate the block. The first and second layers are removed from over the block while leaving portions of the first and second layers over the region proximate the block. At least some of the first layer is removed from under the second layer to form a channel over the region proximate the block. A material, such as a soft magnetic material, is provided within the channel. The invention also includes semiconductor constructions. | 2011-06-16 |
20110140219 | PHOTOELECTRIC CONVERSION DEVICE - A device includes a plurality of photoelectric conversion regions, an interlayer insulating film arranged on the plurality of photoelectric conversion regions, a protective insulating film that is arranged in contact with the interlayer insulating film and has a refractive index different from that of the interlayer insulating film, recesses arranged in a light-receiving surface of each of the plurality of photoelectric conversion regions, and embedded regions embedded in the recesses. When a wavelength of incident light to each of the plurality of photoelectric conversion regions is denoted by λ and a refractive index of the embedded regions is denoted by n, a depth d of the recesses is represented by an expression d≧λ/4n. | 2011-06-16 |
20110140220 | MICROELECTRONIC DEVICE, IN PARTICULAR BACK SIDE ILLUMINATED IMAGE SENSOR, AND PRODUCTION PROCESS - A process for producing a microelectronic device includes producing a first semiconductor substrate which includes a first layer and a second layer present between a first side and a second side of the substrate. First electronic components and an interconnecting part are produced on and above the second side. The substrate is then thinned by a first selective etch applied from the first side and stopping on the first layer followed by a second selective etch stopping on the second layer. A second substrate is attached over the interconnecting part. The electronic components may comprise optoelectronic devices which are illuminated through the second layer. | 2011-06-16 |
20110140221 | IMAGE SENSOR HAVING CURVED MICRO-MIRRORS OVER THE SENSING PHOTODIODE AND METHOD FOR FABRICATING - The invention involves the integration of curved micro-mirrors over a photodiode active area (collection area) in a CMOS image sensor (CIS) process. The curved micro-mirrors reflect light that has passed through the collection area back into the photo diode. The curved micro-mirrors are best implemented in a backside illuminated device (BSI). | 2011-06-16 |
20110140222 | PASSIVATION PLANARIZATION - A pixel cell is formed by locating a first passivation layer over the final layer of metal lines. Subsequently, the uneven, non-uniform passivation layer is subjected to a planarization process such as chemical mechanical polishing, mechanical abrasion, or etching. A spin-on glass layer may be deposited over the non-uniform passivation layer prior to planarization. Once a uniform, flat first passivation layer is achieved over the final metal, a second passivation layer, a color filter array, or a lens forming layer with uniform thickness is formed over the first passivation layer. The passivation layers can be oxide, nitride, a combination of oxide and nitride, or other suitable materials. The color filter array layer may also undergo a planarization process prior to formation of the lens forming layer. The present invention is also applicable to other devices. | 2011-06-16 |
20110140223 | LIGHT DETECTING APPARATUS AND METHOD OF MANUFACTURING SAME - A light detecting apparatus includes an SOI substrate. In the SOI substrate, a semiconductor layer and a silicon substrate are laminated via an insulating layer. The semiconductor layer has a light receiving unit and a circuit unit formed therein. The light detecting apparatus also includes an interlayer insulating film formed on a first main surface of the SOI substrate. The light detecting apparatus also includes a front surface circuit wiring embedded in the interlayer insulating film. The light detecting apparatus also includes a front surface pseudo-wiring having a grid unit. The grid unit has at least one opening allowing passage of a light of a predetermined wavelength range to the light receiving unit. The light detecting apparatus also includes a rear surface circuit wiring and a rear surface pseudo-wiring formed on a second main surface of the SOI substrate. The light detecting apparatus also includes a penetration circuit wiring that connects the front surface circuit wiring to the rear surface circuit wiring. The light detecting apparatus also includes a penetration pseudo-wiring that electrically connects the front surface pseudo-wiring to the rear surface pseudo-wiring. The light receiving unit is surrounded by the front surface pseudo-wiring, the rear surface pseudo-wiring, and the penetration pseudo-wiring. | 2011-06-16 |
20110140224 | DIODE BOLOMETER AND METHOD FOR PRODUCING A DIODE BOLOMETER - A bolometer has a semiconductor membrane having a single-crystalline portion, and spacers so as to keep the semiconductor membrane at a predetermined distance from an underlying substrate. The complementarily doped regions of the single-crystalline portion form a diode and the predetermined distance corresponds to a fourth of an infrared wavelength. | 2011-06-16 |
20110140225 | SEMICONDUCTOR DEVICE - In a first interlevel insulating film, a first region which is made of the first interlevel insulating film and in which first wiring films are not provided is formed to be located above a first light receiving part of the plurality of light receiving parts, and a second region which is made of the first interlevel insulating film and in which the first wiring films are not provided is formed to be located above a second light receiving part of the plurality of light receiving parts which is adjacent to the first light receiving part. A space between ones of the first wiring films with the first region interposed therebetween is larger than a space between ones of the first wiring films with the second region interposed therebetween. | 2011-06-16 |
20110140226 | SEMICONDUCTOR DEVICES AND METHODS FOR MANUFACTURING THE SAME - A semiconductor device includes a substrate and a first insulating layer. The first insulating layer includes a first lower layer and a first upper layer on the first lower layer. The first insulating layer has a first opening through the first lower layer and the first upper layer. A maximum width of the first opening at the first lower layer is different from a maximum width of the first opening at the first upper layer. | 2011-06-16 |
20110140227 | Depletion mode circuit protection device - A non-volatile microelectronic memory device that includes a depletion mode circuit protection device that prevents high voltages, which are applied to bitlines during an erase operation, from being applied to and damaging low voltage circuits which are electrically coupled to the bitlines. | 2011-06-16 |
20110140228 | Method of Filling Large Deep Trench with High Quality Oxide for Semiconductor Devices - A method is disclosed for creating a semiconductor device structure with an oxide-filled large deep trench (OFLDT) portion having trench size TCS and trench depth TCD. A bulk semiconductor layer (BSL) is provided with a thickness BSLT>TCD. A large trench top area (LTTA) is mapped out atop BSL with its geometry equal to OFLDT. The LTTA is partitioned into interspersed, complementary interim areas ITA-A and ITA-B. Numerous interim vertical trenches of depth TCD are created into the top BSL surface by removing bulk semiconductor materials corresponding to ITA-B. The remaining bulk semiconductor materials corresponding to ITA-A are converted into oxide. If any residual space is still left between the so-converted ITA-A, the residual space is filled up with oxide deposition. Importantly, the geometry of all ITA-A and ITA-B should be configured simple and small enough to facilitate fast and efficient processes of oxide conversion and oxide filling. | 2011-06-16 |
20110140229 | TECHNIQUES FOR FORMING SHALLOW TRENCH ISOLATION - Techniques are disclosed for shallow trench isolation (STI). The techniques can be used to form STI structures on any number of semiconductor materials, including germanium (Ge), silicon germanium (SiGe), and III-V material systems. In general, an interfacial passivation layer is used as a liner between the semiconductor surface (such as diffusion) and isolation materials within the STI. The interfacial layer provides a passivation layer on trench surfaces to restrict free bonding electrons of the substrate material. In addition, this passivation layer is oxidized, thereby effectively forming a bi-layer (passivation and oxidation sub-layers) to form an electrically defect free interface. The interfacial bi-layer structure can be implemented, for example, with materials that will covalently bond with free bonding electrons of the substrate materials, and that will oxidize to provide transition to oxide material. | 2011-06-16 |
20110140230 | MANUFACTURE OF THIN SILICON-ON-INSULATOR (SOI) STRUCTURES - The present invention relates to a method of forming a SOI structure having a thin silicon layer by forming a first etch stop layer on a donor substrate, forming a second etch stop layer on the first etch stop layer, wherein the material of the second etch stop layer differs from the material of the first etch stop layer, forming a thin silicon layer on the second etch stop layer, preferably by epitaxy, and bonding the intermediate structure to a target substrate, followed by detaching the donor substrate by splitting initiated in the first etch stop layer at a weakened region and removing the remaining material of the etch stop layers to produce a final ETSOI structure. The invention also relates to the ETSOI structure produces by the described method. | 2011-06-16 |
20110140231 | INTEGRATED MICROELECTRONIC DEVICE WITH THROUGH-VIAS - An integrated microelectronic device is formed from a substrate having a first side and a second side and including a doped active zone ( | 2011-06-16 |
20110140232 | METHODS OF FORMING A THERMAL CONDUCTION REGION IN A SEMICONDUCTOR STRUCTURE AND STRUCTURES RESULTING THEREFROM - An electronic system, method of manufacture of a semiconductor structure, and one or more semiconductor structures are disclosed. For example, a method of manufacture of a semiconductor structure is disclosed, which includes forming a semiconductor layer over a thermal conduction layer, forming an isolation region over the thermal conduction layer, and forming a thermal conduction region in the isolation region. | 2011-06-16 |
20110140233 | Parasitic vertical PNP bipolar transistor and its fabrication method in BiCMOS process - A parasitic vertical PNP bipolar transistor in BiCMOS process comprises a collector, a base and an emitter. The collector is formed by active region with p-type ion implanting layer (P type well in NMOS). It connects a P-type conductive region, which formed in the bottom region of shallow trench isolation (STI). The collector terminal connection is through the P-type buried layer and the adjacent active region. The base is formed by N type ion implanting layer above the collector which shares a N-type lightly doped drain (NLDD) implanting of NMOS. Its connection is through the N-type poly on the base region. The emitter is formed by the P-type epitaxy layer on the base region with heavy p-type doped, and connected by the extrinsic base region of NPN bipolar transistor device. This invention also includes the fabrication method of this parasitic vertical PNP bipolar transistor in BiCMOS process. And this PNP bipolar transistor can be used as the I/O (input/output) device in high speed, high current and power gain BiCMOS circuits. It also provides a device option with low cost. | 2011-06-16 |
20110140234 | FUSE OF SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME - A fuse of a semiconductor device comprises: a first insulating film formed over a semiconductor substrate; a conductive pattern formed over the first insulating film; a fuse metal formed over the conductive pattern; a contact plug electrically coupling the conductive pattern and the fuse metal; and an energy absorbent pattern formed in the first insulating film and located below an area where the contact plug and the conductive pattern are interconnected. The fuse of the semiconductor device includes a void and a step difference in the lower portion of the contact connected to the fuse pattern. As a result, an energy of a laser applied in the blowing process is absorbed in the void or the step difference, which does not affect peripheral patterns, thereby preventing defects. | 2011-06-16 |
20110140235 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device include an insulating interlayer formed over a substrate; an electrical fuse which is composed of a first wiring formed in the insulating interlayer, and has a cutting portion; and a second wiring and a third wiring, formed respectively on both sides of the cutting portion to extend along the cutting portion in the same layer as the first wiring. Air gaps formed to extend along the cutting portion are respectively provided between the cutting portion and the second wiring and between the cutting portion and the third wiring. | 2011-06-16 |
20110140236 | Integrated Circuit with Pads Connected by an Under-Bump Metallization and Method for Production Thereof - A semiconductor device includes a semiconductor chip. External connection pads and further pads are disposed over a surface of the semiconductor chip. Selected ones of the further pads are electrically connected to one another so as to activate selected functions within the semiconductor chip. | 2011-06-16 |
20110140237 | SEMICONDUCTOR PACKAGE - A semiconductor package includes a semiconductor chip and a passive element. The semiconductor chip has a semiconductor chip s body which possesses a first surface and a second surface facing away from the first surface, and a circuit section is formed in the semiconductor chip body. The passive element includes passive element bodies which are disposed in through-electrodes passing through the semiconductor chip body and connection members to which are disposed on at least one of the first surface and the second surface of the semiconductor chip body and which electrically connect to at least one of the passive element bodies. | 2011-06-16 |
20110140238 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - According to an embodiment, there is provided a method for manufacturing a semiconductor device having a ferroelectric capacitor including a lower electrode, an upper electrode, and a dielectric film provided between the lower electrode and the upper electrode. The method includes firstly forming a conductive film on the lower electrode. Next, it includes forming an SRO film on the conductive film. Then, it includes performing a first thermal treatment crystallizing the SRO film. Then, it includes forming a first PZT film on the SRO film by the sputtering method and performing a second thermal treatment crystallizing the first PZT film. Then, it includes forming the second PZT film on the first PZT film by the CVD method. | 2011-06-16 |
20110140239 | High Voltage Bipolar Transistor with Pseudo Buried Layers - A high voltage bipolar transistor with shallow trench isolation (STI) comprises the areas of a collector formed by implanting first electric type impurities into active area and connected with pseudo buried layers at two sides; Pseudo buried layers which are formed by implanting high dose first type impurity through the bottoms of STI at two sides if active area, and do not touch directly; deep contact through field oxide to contact pseudo buried layers and pick up the collectors; a base deposited on the collector by epitaxial growth and in-situ doped by second electric type impurity, in which the intrinsic base touches local collector and extrinsic base is used for base pick-up; a emitter which is a polysilicon layer deposited on the intrinsic base and doped with first electric type impurities. This invention makes the depletion region of collector/base junction from 1D (vertical) distribution to 2D (vertical and lateral) distribution. The bipolar transistor's breakdown voltages are increased by only enlarge active critical dimension (CD). This is low-cost process. | 2011-06-16 |
20110140240 | VARACTOR DIODES - An improved varactor diode is obtained by providing a substrate having a first surface and in which are formed a first N region having a first peak dopant concentration located at a first depth beneath the surface, and a first P region having a second peak dopant concentration greater than the first peak dopant concentration located at a second depth beneath the surface less than the first depth, and a second P region having a third peak dopant concentration greater than the second peak dopant concentration and located at a third depth at or beneath the surface less than the second depth, so that the first P region provides a retrograde doping profile whose impurity concentration increases with distance from the inward edge of the second P region up to the second peak dopant concentration. | 2011-06-16 |
20110140241 | PROCESSES FOR PRODUCTION OF SILICON INGOT, SILICON WAFER AND EPITAXIAL WAFER , AND SILICON INGOT - A process for production of a silicon ingot, by which a silicon ingot exhibiting a low resistivity even in the top portion can be produced. The process for the production of a silicon ingot comprises includes withdrawing a silicon seed crystal ( | 2011-06-16 |
20110140242 | Stress compensation for large area gallium nitride or other nitride-based structures on semiconductor substrates - A method includes forming a stress compensating stack over a substrate, where the stress compensating stack has compressive stress on the substrate. The method also includes forming one or more Group III-nitride islands over the substrate, where the one or more Group III-nitride islands have tensile stress on the substrate. The method further includes at least partially counteracting the tensile stress from the one or more Group III-nitride islands using the compressive stress from the stress compensating stack. Forming the stress compensating stack could include forming one or more oxide layers and one or more nitride layers over the substrate. The one or more oxide layers can have compressive stress, the one or more nitride layers can have tensile stress, and the oxide and nitride layers could collectively have compressive stress. Thicknesses of the oxide and nitride layers can be selected to provide the desired amount of stress compensation. | 2011-06-16 |
20110140243 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device comprises a semiconductor substrate, a first electrode formed on a first main surface of the semiconductor substrate, and a second electrode formed on a second main surface of the semiconductor substrate. The semiconductor substrate includes a first region in which a density of oxygen-vacancy defects is greater than a density of vacancy cluster defects, and a second region in which the density of vacancy cluster defects is greater than the density of oxygen-vacancy defects. | 2011-06-16 |
20110140244 | METHOD FOR ROUTING A CHAMFERED SUBSTRATE - The invention relates to a method for routing a chamfered substrate, having applications in the field of electronics, optics, or optoelectronics, which involves depositing a layer of a protective material on a peripheral annular zone of the substrate preferably with the aid of a plasma, partially etching the protective material with the aid of a plasma, so as to preserve a protective ring of the deposited material on the front face of the substrate, this ring located at a distance from the edge of the substrate, so as to delimit an accessible peripheral annular zone, etching a thickness of the material constituting the substrate to be routed, preferably with the aid of a plasma that is level with the accessible peripheral annular zone of the substrate, and removing the ring of protective material preferably with the aid of a plasma. | 2011-06-16 |
20110140245 | STRUCTURE FOR INHIBITING BACK END OF LINE DAMAGE FROM DICING AND CHIP PACKAGING INTERACTION FAILURES - A semiconductor product comprises a semiconductor substrate having a top surface and a bottom surface including a semiconductor chip. The semiconductor substrate has a top surface and a perimeter. A barrier is formed in the chip within the perimeter. An Ultra Deep Isolation Trench (UDIT) is cut in the top surface of the chip extending down therein between the perimeter and the barrier. A ILD structure with low-k pSICOH dielectric and hard mask layers is formed over the substrate prior to forming the barrier and the UDIT. The ILD structure interconnection structures can be recessed down to the substrate aside from the UDIT. | 2011-06-16 |
20110140246 | DELTA-DOPING AT WAFER LEVEL FOR HIGH THROUGHPUT, HIGH YIELD FABRICATION OF SILICON IMAGING ARRAYS - Systems and methods for producing high quantum efficiency silicon devices. A silicon MBE has a preparation chamber that provides for cleaning silicon surfaces using an oxygen plasma to remove impurities and a gaseous (dry) NH | 2011-06-16 |
20110140247 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH SHIELDED PACKAGE AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a substrate assembly having a connection path; mounting a base device over the substrate assembly with a mount layer; mounting a stack device over the base device and having a stack die and a stack-organic-material; forming a stack-through-via in the stack-organic-material of the stack device and connected to the stack die and the substrate assembly; and applying a shield layer directly on a planarized surface of the stack-through-via partially exposed from the stack-organic-material. | 2011-06-16 |
20110140248 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device and manufacturing method thereof are disclosed. The device comprises a semiconductor die, a passivation layer, a wiring redistribution layer (RDL), an Ni/Au layer, and a solder mask. The semiconductor die comprises a top metal exposed in an active surface thereof. The passivation layer overlies the active surface of the semiconductor die, and comprises a through passivation opening overlying the top metal. The wiring RDL, comprising an Al layer, overlies the passivation layer, and electrically connects to the top metal via the passivation opening. The solder mask overlies the passivation layer and the wiring RDL, exposing a terminal of the wiring RDL. | 2011-06-16 |
20110140249 | TIE BAR AND MOLD CAVITY BAR ARRANGEMENTS FOR MULTIPLE LEADFRAME STACK PACKAGE - A semiconductor chip package having multiple leadframes is disclosed. Packages can include a first leadframe having a first plurality of electrical leads and a die attach pad having a plurality of tie bars, a second leadframe generally parallel to the first leadframe and having a second plurality of electrical leads, and a mold or encapsulant. Tie bars can be located on three main sides of the die attach pad, but not the fourth main side. Gaps in the first and second plurality of electrical leads can be enlarged or aligned with each other to enable the elimination of mold flash outside the encapsulated region, which can be accomplished with mold cavity bar protrusions. Additional components can include a primary die, a secondary die, an inductor and/or a capacitor. The first and second leadframes can be substantially stacked atop one another, and one or both leadframes can be leadless leadframes. | 2011-06-16 |
20110140250 | LEADFRAME FOR SEMICONDUCTOR PACKAGE - A semiconductor package including a lead frame comprising a frame including both a ground ring and a chip mounting board located therein. Extending between the ground ring and the chip mounting board are a plurality of elongate slots or apertures. The ground ring is formed to include recesses within the bottom surface thereof which create regions of reduced thickness. A semiconductor chip bonded to the chip mounting board may be electrically connected to leads of the lead frame and to the ground ring via conductive wires. Those conductive wires extending to the ground ring are bonded to the top surface thereof at locations which are not aligned with the recesses within the bottom surface, i.e., those regions of the ground ring of maximum thickness. | 2011-06-16 |
20110140251 | INTEGRATED CIRCUIT PACKAGE SYSTEM WITH REMOVABLE BACKING ELEMENT HAVING PLATED TERMINAL LEADS AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit package system includes providing a first frame having a first removable backing element connecting a first die attach pad and a first plurality of terminal leads. A first die is attached to the first die attach pad. A substrate is provided. A second die is attached to the substrate. The first die is attached to the second die with a plurality of die interconnects. The first removable backing element is removed after connecting the first die to the second die. | 2011-06-16 |
20110140252 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH DUAL ROW LEAD-FRAME HAVING TOP AND BOTTOM TERMINALS AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: forming outer leads having outer terminal sections, the outer terminal sections having an upper terminal and a bottom terminal; forming inner leads having inner terminal sections wider than a distance between the outer terminal sections of the outer leads, and the inner terminal sections have an upper terminal and a bottom terminal; connecting an integrated circuit to the inner leads and the outer leads; and encapsulating the integrated circuit, the inner leads, and the outer leads with an encapsulation while leaving the upper terminals and the bottom terminals of the outer terminal sections and the upper terminals and bottom terminals of the inner terminal sections exposed from the encapsulation. | 2011-06-16 |
20110140253 | DAP GROUND BOND ENHANCEMENT - A variety of semiconductor package arrangements and packaging methods are described that improve the reliability of bonding wires that down bond a die to a die attach pad. In one aspect, selected portions of the top surface of a lead frame (which may be in panel form) are plated (e.g., silver plated) to facilitate wire bonding. The plating covers some, but not all of a die attach surface of the die attach pad. In some preferred embodiments, the plating on the die attach pad is arranged as a peripheral ring that surrounds an unplated central region of the die support surface. In other embodiments, the plating on the die attach pad takes the form of bars or other geometric patterns that do not fully cover the die support surface. Unplated portions of the die support surface are roughened to improve the adherence of the die to the die attach pad, thereby reducing the probability of die attach pad delamination and the associated risks to down bonded bonding wires. The described lead frames may be used in a variety of packages. Most commonly, a die is attached to the die support surface of the die attach pad and electrically connected to the lead frame leads by wire bonding as appropriate. At least one of the die's bond pads (typically the ground bond pad(s)) is down bonded to the die attach pad. The die, the bonding wires and at least portions of the lead frame are then typically encapsulated with a plastic encapsulant material while leaving a contact surface of the die attach pad exposed to facilitate electrically coupling the die attach pad to an external device. | 2011-06-16 |
20110140254 | Panel Based Lead Frame Packaging Method And Device - A packaged semiconductor die has a preformed lead frame with a central recessed portion, and a plurality of conductive leads. An integrated circuit die has a top surface and a bottom surface opposite thereto, with the top surface having a plurality of bonding pads for electrical connection to the die. The die is positioned in the central recessed portion with the top surface having the bonding pads facing upward, and the bottom surface in contact with the recessed portion. Each of the leads has a top portion and a bottom portion. The leads are spaced apart and insulated from the central recessed portion. A conductive layer is deposited on the top surface of the die and the top portion of the leads and is patterned to electrically connect certain of the bonding pads of the die to certain of the conductive leads. An insulator covers the conductive layer. The present invention also relates to a method of packaging such an integrated circuit die. | 2011-06-16 |
20110140255 | SEMICONDUCTOR DIE PACKAGE INCLUDING IC DRIVER AND BRIDGE - A semiconductor die package. Embodiments of the semiconductor die package are usable in backlight circuitry. Systems in packages may include a bridge circuit or a part thereof, and a integrated circuit die, such as a driver die, encapsulated by a molding material or other package. The bridge circuit may be stacked on opposing surfaces of a leadframe. | 2011-06-16 |
20110140256 | SEMICONDUCTOR DEVICE, SUBSTRATE AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD - The semiconductor device can prevent damages on a semiconductor chip even when a soldering material is used for bonding the back surface of the semiconductor chip to the junction plane of a chip junction portion such as an island or a die pad. This semiconductor device includes a semiconductor chip and a chip junction portion having a junction plane that is bonded to the back surface of the semiconductor chip with a soldering material. The junction plane is smaller in size than the back surface of the semiconductor chip. This semiconductor device may further include a plurality of extending portions which extend respectively from the periphery of the junction plane to directions parallel with the junction plane. | 2011-06-16 |
20110140257 | Printed Circuit Board having Embedded Dies and Method of Forming Same - A package includes a printed circuit board (PCB) having a first side and a second side and a thickness between the first side and the second side and a stacked die including a top die mounted on a bottom die, the bottom die being at least partially embedded in the PCB. Also a method of forming a package that includes forming an opening in a top surface of the PCB layer, placing a stacked die including a top die stacked on a bottom die into the opening, laminating the PCB layer to form a laminate layer, and forming an electrical connection with the stacked die. | 2011-06-16 |
20110140258 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH PACKAGE STACKING AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system including: fabricating a base package substrate having component pads and stacking pads; coupling a base integrated circuit die to the component pads; forming a penetrable encapsulation material for enclosing the base integrated circuit die and the component pads on the base package substrate; and coupling stacked interconnects on the stacking pads adjacent to and not contacting the penetrable encapsulation material. | 2011-06-16 |
20110140259 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH STACKING INTERCONNECT AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: fabricating a base package substrate; coupling a conductive column lead frame to the base package substrate by: providing a lead frame support, patterning a conductive material on the lead frame support including forming an interconnect securing structure, and coupling the conductive material to the base package substrate; forming a base package body between the base package substrate and the conductive column lead frame; and removing the lead frame support from the conductive column lead frame for exposing the interconnect securing structure from the base package body. | 2011-06-16 |
20110140260 | CHIP ASSEMBLY WITH CHIP-SCALE PACKAGING - A chip assembly may comprise a substrate having a top surface and a bottom surface. The chip assembly may comprise a first die having a circuit surface and a connecting surface, the circuit surface comprising one or more integrated circuits. The chip assembly may comprise a chip-scale frame having an inside surface, an outside surface, and a well region, the well region having an opening within the inside surface, the well region having a wall, the well region housing the first die, the first die attached to the wall by a first coupling mechanism, the inside surface coupled to the top surface of the substrate by a second coupling mechanism. The chip assembly may comprise a heat sink coupled to the outside surface of the chip-scale frame using a third coupling mechanism. | 2011-06-16 |
20110140261 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH INTERCONNECT AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a substrate external layer having an opening; forming a convex interconnect within the opening with the convex interconnect having a protrusion and a horizontal flange substantially horizontally coplanar with the substrate external layer; forming an insulation layer over the substrate external layer and the convex interconnect; forming a horizontal conductive pathway on the insulation layer; forming a single interlayer conductive connector from the horizontal conductive pathway to the convex interconnect; and connecting an integrated circuit and the horizontal conductive pathway. | 2011-06-16 |
20110140262 | MODULE PACKAGE WITH EMBEDDED SUBSTRATE AND LEADFRAME - An integrated circuit package is described that includes a substrate, a leadframe and one or more integrated circuits that are positioned between the substrate and the leadframe. Multiple electrical components may be attached to one or both sides of the substrate. The active face of the integrated circuit is electrically and physically connected to the substrate. The back side of the integrated circuit is mounted on a die attach pad of the leadframe. The leadframe includes multiple leads that are physically attached to and electrically coupled with the substrate. A molding material encapsulates portions of the substrate, the leadframe and the integrated circuit. Methods for forming such packages are also described. | 2011-06-16 |
20110140263 | Semiconductor Device and Method of Forming PIP with Inner Known Good Die Interconnected with Conductive Bumps - A PiP semiconductor device has an inner known good semiconductor package. In the semiconductor package, a first via is formed in a temporary carrier. A first conductive layer is formed over the carrier and into the first via. The first conductive layer in the first via forms a conductive bump. A first semiconductor die is mounted to the first conductive layer. A first encapsulant is deposited over the first die and carrier. The semiconductor package is mounted to a substrate. A second semiconductor die is mounted to the first conductive layer opposite the first die. A second encapsulant is deposited over the second die and semiconductor package. A second via is formed in the second encapsulant to expose the conductive bump. A second conductive layer is formed over the second encapsulant and into the second via. The second conductive layer is electrically connected to the second die. | 2011-06-16 |
20110140264 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - There is provided a low-cost semiconductor device that commercial and quality-assured (inspected) chip size packages can be stacked and has a small co-planarity value and a high mounting reliability. A semiconductor device in which a flexible circuit substrate is adhered to at least a part of a lateral side of a semiconductor package, and the flexible circuit substrate, which is on a side facing solder balls of the semiconductor package, is folded at a region inside of an edge of the semiconductor package (FIG. | 2011-06-16 |
20110140265 | Packaging of Silicon Wafers and Mating Pieces - By creating a package (MVLC) that has a redundant set of pins, twice as many points of contact are generated. More contacts create more routing and component placement options. | 2011-06-16 |
20110140266 | ELECTROSTATIC CAPACITANCE-TYPE INPUT DEVICE AND METHOD OF MANUFACTURING THEREOF - An electrostatic capacitance-type input device includes: a first translucent conductive film that configures a first electrode that extends in a first direction in an input area on a substrate and second electrodes that extend in a second direction intersecting the first direction in the input area and are disconnected in intersection portions with the first electrode; an interlayer insulating film that is formed at least in areas overlapping the intersection portions; and a second translucent conductive film that configures relay electrodes formed on the interlayer insulating film to have sheet resistance lower than that of the first translucent conductive film and electrically connecting the second electrodes disconnected in the intersection portion by being electrically connected to the second electrodes in an area in which the interlayer insulating film is not formed and a peripheral wiring extending in a peripheral area of the substrate located to the outer side of the input area. | 2011-06-16 |
20110140267 | ELECTRONIC DEVICE PACKAGE AND METHOD FOR FABRICATING THE SAME - The invention provides an electronic device package and a method for fabricating the same. The electronic device package includes a carrier wafer. An electronic device chip with a plurality of conductive pads thereon is disposed over the carrier wafer. An isolation laminating layer includes a lower first isolation layer, which covers the carrier wafer and the electronic device chip, and an upper second isolation layer. The isolation laminating layer has a plurality of openings to expose the conductive pads. A plurality of redistribution patterns is conformably formed on the isolation laminating layer and in the openings. The redistribution patterns are electrically connected to the conductive pads, respectively. A plurality of conductive bumps is respectively formed on the redistribution patterns, electrically connected to the conductive pads. | 2011-06-16 |
20110140268 | HIGH-DENSITY INTER-PACKAGE CONNECTIONS FOR ULTRA-THIN PACKAGE-ON-PACKAGE STRUCTURES, AND PROCESSES OF FORMING SAME - An apparatus includes a coreless mounting substrate and an interposer disposed on the coreless mounting substrate with a chip disposed in a recess in the interposer and upon the coreless substrate. The apparatus may include an inter-package solder bump in contact with an interconnect channel in the interposer, and a top chip package including a top package substrate and a top die disposed on the top package substrate. The top package substrate is in contact with the inter-package solder bump. | 2011-06-16 |
20110140269 | Semiconductor device and method for manufacturing the same - A semiconductor device includes an electrode pad and a protective insulating film having an opening to expose the electrode pad. The semiconductor device further includes a bump (resin core bump) that includes a bump core (resin core) formed on the protective insulating film and a conductive layer formed on the bump core. The semiconductor device further includes an interconnect that connects the conductive layer and the electrode pad. The bump core is in the form of a laminate of plural resin layers (for example, first and second resin layers) that have different elastic modulus. | 2011-06-16 |
20110140270 | SEMICONDUCTOR MOUNTING SUBSTRATE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor mounting substrate according to the present invention comprises: a substrate; a semiconductor device, mounted on this substrate; solder bumps, which connect the semiconductor device and the substrate; a first resin, filled in a space between the semiconductor device and the substrate; and electronic components, mounted on a face side of the semiconductor device where the semiconductor device is mounted, wherein bond strength reinforcing resin section is provided at least between a side face in the vicinity of a corner part of the semiconductor device and a substrate surface of the substrate in a position corresponding to the corner part. | 2011-06-16 |
20110140271 | INTEGRATED CIRCUIT CHIP WITH PYRAMID OR CONE-SHAPED CONDUCTIVE PADS FOR FLEXIBLE C4 CONNECTIONS AND A METHOD OF FORMING THE INTEGRATED CIRCUIT CHIP - Disclosed is a chip and method of forming the chip with improved conductive pads that allow for flexible C4 connections with a chip carrier or with another integrated circuit chip. The pads have a three-dimensional geometric shape (e.g., a pyramid or cone shape) with a base adjacent to the surface of the chip, a vertex opposite the base and, optionally, mushroom-shaped cap atop the vertex. Each pad can include a single layer of conductive material or multiple layers of conductive material (e.g., a wetting layer stacked above a non-wetting layer). The pads can be left exposed to allow for subsequent connection to corresponding solder bumps on a chip carrier or a second chip. Alternatively, solder balls can be positioned on the conductive pads to allow for subsequent connection to corresponding solder-paste filled openings on a chip carrier or a second chip. | 2011-06-16 |
20110140272 | Ball Grid Array Package Enhanced With a Thermal and Electrical Connector - A package is provided. The package includes a substrate having first and second surfaces, a stiffener coupled to the first surface of the substrate, and a thermal connector coupled to the second surface of the substrate that is configured to be coupled to a printed circuit board. | 2011-06-16 |
20110140273 | Semiconductor Devices Including Voltage Switchable Materials for Over-Voltage Protection - Semiconductor devices are provided that employ voltage switchable materials for over-voltage protection. In various implementations, the voltage switchable materials are substituted for conventional die attach adhesives, underfill layers, and encapsulants. While the voltage switchable material normally functions as a dielectric material, during an over-voltage event the voltage switchable material becomes electrically conductive and can conduct electricity to ground. Accordingly, the voltage switchable material is in contact with a path to ground such as a grounded trace on a substrate, or a grounded solder ball in a flip-chip package. | 2011-06-16 |
20110140274 | FORMING THICK METAL INTERCONNECT STRUCTURES FOR INTEGRATED CIRCUITS - Embodiments of an apparatus and methods for forming thick metal interconnect structures for integrated structures are generally described herein. Other embodiments may be described and claimed. | 2011-06-16 |
20110140275 | Semiconductor device and manufacturing method of the same - In a semiconductor device, capacitance between copper interconnections is decreased and the insulation breakdown is improved simultaneously, and a countermeasure is taken for misalignment via by a manufacturing method including the steps of forming an interconnection containing copper as a main ingredient in an insulative film above a substrate, forming insulative films and a barrier insulative film for a reservoir pattern, forming an insulative film capable of suppressing or preventing copper from diffusing on the upper surface and on the lateral surface of the interconnection and above the insulative film and the insulative film, forming insulative films of low dielectric constant, in which the insulative film is formed such that the deposition rate above the opposing lateral surfaces of the interconnections is larger than the deposition rate therebelow to form an air gap between the adjacent interconnections and, finally, planarizing the insulative film by interlayer CMP. | 2011-06-16 |
20110140276 | INTERLAYER INSULATING FILM, INTERCONNECTION STRUCTURE, AND METHODS OF MANUFACTURING THE SAME - This invention provides an interlayer insulating film for a semiconductor device, which has low permittivity, is free from the evolution of gas such as CFx and SiF | 2011-06-16 |
20110140277 | SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor substrate including a main surface; a plurality of first interconnections formed in a capacitance forming region defined on the main surface and extending in a predetermined direction; a plurality of second interconnections each adjacent to the first interconnection located at an edge of the capacitance forming region, extending in the predetermined direction, and having a fixed potential; and an insulating layer formed on the main surface and filling in between each of the first interconnections and between the first interconnection and the second interconnection adjacent to each other. The first interconnections and the second interconnections are located at substantially equal intervals in a plane parallel to the main surface, and located to align in a direction substantially perpendicular to the predetermined direction. | 2011-06-16 |
20110140278 | OPTICAL PROXIMITY CORRECTION AWARE INTEGRATED CIRCUIT DESIGN OPTIMIZATION - An EDA method is implemented for modifying a layout file after place and route. The method includes storing a library of shape modifications for cells in the design library used for implementation of the circuit. The library of shape modifications includes the results of process-specific calibration of the shape modifications which indicate adjustment of a circuit parameter caused by applying the shape modifications to the cells. The layout file is analyzed to identify a cell for adjustment of the circuit parameter. A shape modification calibrated to achieve the desired adjustment is selected from the library. The shape modification is applied to the identified cell in the layout file to produce a modified layout file. The modified layout file can be used for tape out, and subsequently for manufacturing of an improved integrated circuit. | 2011-06-16 |
20110140279 | SEMICONDUCTOR STRUCTURE INCORPORATING MULTIPLE NITRIDE LAYERS TO IMPROVE THERMAL DISSIPATION AWAY FROM A DEVICE AND A METHOD OF FORMING THE STRUCTURE - Disclosed are embodiments of a semiconductor structure that incorporates multiple nitride layers stacked between the center region of a device and a blanket oxide layer. These nitride layers are more thermally conductive than the blanket oxide layer and, thus provide improved heat dissipation away from the device. Also disclosed are embodiments of a method of forming such a semiconductor structure in conjunction with the formation of any of the following nitride layers during standard processing of other devices: a nitride hardmask layer (OP layer), a “sacrificial” nitride layer (SMT layer), a tensile nitride layer (WN layer) and/or a compressive nitride layer (WP layer). Optionally, the embodiments also incorporate incomplete contacts that extend through the blanket oxide layer into one or more of the nitride layers without contacting the device in order to further improve heat dissipation | 2011-06-16 |
20110140280 | Semiconductor apparatus capable of error revision using pin extension technique and design method therefor - A semiconductor apparatus and a design method for the semiconductor apparatus allow debugging or repairs by using a spare cell. The semiconductor apparatus includes a plurality of metal layers. At least one repair block performs a predetermined function. A spare block is capable of substituting for a function of the repair block. And at least one of the plurality of metal layers is predetermined to be a repair layer for error revision. At least one pin of the repair block is connected to the repair layer through a first pin extension, and at least one pin of the spare block is capable of extending to the repair layer. When the repair block is to be repaired, the pin extension of the repair layer and the repair block is disconnected, and at least one pin of the spare block is connected to the repair layer through a second pin extension. | 2011-06-16 |
20110140281 | SUBSTRATE FOR ELECTRONIC DEVICE, STACK FOR ELECTRONIC DEVICE, ELECTRONIC DEVICE, AND METHOD FOR MANUFACTURING THE SAME - A method for manufacturing an electronic device, including a step of aligning and stacking a plurality of substrates, each of the plurality of substrates having a plurality of vertical conductors and magnetic films, the vertical conductors being directed along a thickness direction of the substrate and distributed in a row with respect to a substrate surface, the magnetic films being disposed in place on the substrate surface in a predetermined positional relationship with the vertical conductors, upon aligning the plurality of substrates, the electronic device manufacturing method including a step of applying an external magnetic field to produce a magnetic attractive force between the magnetic films of adjacent stacked substrates and align the vertical conductors by the magnetic attractive force. | 2011-06-16 |
20110140282 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD - A semiconductor device includes: a semiconductor substrate, first and second internal electrodes provided on a surface of the semiconductor substrate; a first through electrode which penetrates through the semiconductor substrate in a thickness direction and is electrically connected to the first internal electrode; and a second through electrode connected to the second internal electrode, and the second internal electrode is thinner than the first internal electrode. The second through electrode may penetrate through the second internal electrode. | 2011-06-16 |
20110140283 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH A STACKABLE PACKAGE AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: forming a base assembly having a cavity and a through conductor adjacent to the cavity; connecting a first device to the base assembly with the first device within the cavity; connecting a second device to the base assembly with the second device within the cavity; and connecting an interposer substrate having an exposed external side over the through conductor with the exposed external side facing away from the through conductor and exposed to ambient. | 2011-06-16 |
20110140284 | OPTOELECTRONIC COMPONENT - An optoelectronic component includes a carrier with a mounting side and having at least one functional element, at least one substrateless optoelectronic semiconductor chip with a top and an opposed bottom and is electrically conductive by way of the top and the bottom, wherein the bottom faces the mounting side and the semiconductor chip is mounted on the mounting side, and at least one structured electrical contact film located on the top. | 2011-06-16 |
20110140285 | Semiconductor Device - A semiconductor device with semiconductor chips stacked thereon is provided. The semiconductor device is reduced in size and thickness. In a first memory chip and a second memory chip, first pads of the first memory chip located at a lower stage and hidden by the second memory chip located at an upper stage are drawn out by re-wiring lines, whereby the first pads projected and exposed from the overlying second memory chip and second pads of the second memory chip can be coupled together through wires. Further, a microcomputer chip and third pads formed on re-wiring lines are coupled together through wires over the second memory chip, whereby wire coupling of the stacked memory chips can be done without intervention of a spacer. | 2011-06-16 |
20110140286 | MULTILAYER WIRING SUBSTRATE MOUNTED WITH ELECTRONIC COMPONENT AND METHOD FOR MANUFACTURING THE SAME - A multilayer wiring substrate mounted with an electronic component includes an electronic component, a core material layer having a first opening for accommodating the electronic component, a resin layer which is formed on one surface of the core material layer and which has a second opening greater than the first opening, a supporting layer which is formed on the other surface of the core material layer and which supports the electronic component, a plurality of connection conductor sections which are provided around the first opening and within the second opening on the one surface of the core material layer, bonding wires for electrically connecting the electronic component to the connection conductor sections, and a sealing resin filled into the first and second openings in order to seal the electronic component and the bonding wires. | 2011-06-16 |
20110140287 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH BOND WIRE PADS AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: forming a device over a substrate including a bond wire pad row located between a perimeter of the substrate and the device; configuring the bond wire pad row to include three sided bond wire pads that horizontally overlap; and forming an interconnection between the device and the bond wire pad row. | 2011-06-16 |
20110140288 | Systems and Methods Employing a Physically Asymmetric Semiconductor Device Having Symmetrical Electrical Behavior - An integrated circuit device comprising a first elongate structure and a second elongate structure arranged parallel to each other and defining a space therebetween. The integrated circuit device also includes conductive structures distributed in the space between the first and second elongate structures. At least a first one of the conductive structures is placed closer to the first elongate structure than to the second elongate structure. At least a second one of the conductive structures is placed closer to the second elongate structure than to the first elongate structure. | 2011-06-16 |
20110140289 | RESIN COMPOSITION FOR ENCAPSULATING OPTICAL SEMICONDUCTOR ELEMENT AND OPTICAL SEMICONDUCTOR DEVICE - A resin composition containing a silica-based filler which differs in refractive index by ±0.03 from the curable base resin and has a thermal conductivity no lower than 0.5 W/m·K, and a light-emitting diode encapsulated with said resin composition. The resin composition is preferably prepared from a curable silicone resin which imparts a cured product having a refractive index of 1.45 to 1.55 and cristobalite powder dispersed therein. | 2011-06-16 |
20110140290 | CHARGE FORMING DEVICE AND VALVE FOR THE SAME - One implementation of a carburetor may have a fuel bowl in which a supply of fuel is received for delivery from the carburetor to an engine, and may include a valve rotatably supported by a body, an operating lever coupled to the valve, and a stopper. The operating lever may move the valve between a running position in which fuel flows through the valve in a first direction and into the fuel bowl, a stop position in which fuel does not flow either into or out of the fuel bowl through the valve, and a drainage position in which fuel flows in a second direction out of the fuel bowl through the valve. The stopper may be moveable between a non-permissive state in which the operating lever is not permitted to move in a first direction from one of the running position and the stop position to the other position, and a permissive state in which the operating lever is allowed to move in the first direction. | 2011-06-16 |
20110140291 | STEAM HUMIDIFIER WITH AUTO-CLEANING FEATURE - The disclosure relates generally to steam humidifiers with an auto-cleaning feature, and more particularly, to steam humidifiers that include an auto-cleaning feature for automatically cleaning impurities and/or other byproducts from the steam humidifier while still operating the humidifier in a relatively efficient manner. In some illustrative embodiment, this may be accomplished by providing some level of flexibility of when an auto-cleaning routine is initiated and performed. For example, tank flushing may be initiated and performed preferentially during non-heating states of the steam humidifier, which may potentially decrease down time and increase attainable output capacity and efficiency of the steam humidifier. | 2011-06-16 |
20110140292 | METHODS FOR MAKING SILICONE HYDROGEL LENSES FROM WATER-BASED LENS FORMULATIONS - Described herein are methods for producing silicone hydrogel lenses. The methods involve introducing into a mold a water-based lens-forming composition, curing the lens-forming composition in a mold to form the lens, and removing the lens from the mold. The lens-forming composition comprises (i) a polysiloxane-containing vinylic monomer or macromer, (ii) at least one hydrophilic vinylic monomer, (iii) a surfactant, and, and (iv) water. The surfactant is polysiloxane-containing surfactant that is free of actinically-polymerizable groups and is a copolymer having from about 10% to about 40% by weight of one or more polysiloxane segments and from about 90% to about 60% by weight hydrophilic units and/or segments. The methods permit the use of water as a solvent and reduce the need for organic solvents. Additionally, the lenses produced by the methods can have improved properties such oxygen permeability. | 2011-06-16 |
20110140293 | Method of manufacturing explosives - A method of manufacturing explosives from a raw explosive material by gelatinizing the raw explosive, characterized in that the raw explosive is subjected to isostatic pressing prior to the gelatinization step. | 2011-06-16 |
20110140294 | Sulphur Granulation Apparatus and Process - A portable apparatus for producing sulphur granules includes a granulator with a rotatable drum having distinct zones for seed generation and product growth. The seed generation zone has an intense water spray pattern for each sulphur spray nozzle with intersecting water sprays to solidify molten sulphur and create seeds. The growth zone has a moderate, non-intersecting water spray pattern to allow sulphur nozzles to coat and grow a curtain of seeds into granules. The granulator's exhaust air is filtered either by a heated cyclone separator to recapture residual sulphur particles and moisture before venting, and/or by a granular air filter which uses the produced granules to filter the granulator's exhaust air. A two piece collar enhances maintenance of the granulator's drive system. | 2011-06-16 |
20110140295 | Electrospun Apatite/Polymer Nano-Composite Scaffolds - An artificial bone composite structure is provided. This structure includes a fibrous matrix that itself includes a plurality of fibers. Also, the structure includes a plurality of hydroxyapatite (HA) particles. These particles are dispersed within the fibrous matrix. Also, the HA particles have controlled size and aspect ratios and are aligned along long axes of the fibers. In some instances, the fibers include poly-(L-lactic acid) (PLLA). | 2011-06-16 |
20110140296 | ROBUST CARBON MONOLITH HAVING HIERARCHICAL POROSITY - A carbon monolith includes a robust carbon monolith characterized by a skeleton size of at least 100 nm, and a hierarchical pore structure having macropores and mesopores | 2011-06-16 |
20110140297 | WATER-DISPERSIBLE AND MULTICOMPONENT FIBERS FROM SULFOPOLYESTERS - Disclosed are water-dispersible fibers derived from sulfopolyesters having a Tg of at least 25° C. The fibers may contain a single sulfopolyester or a blend of a sulfopolyester with a water-dispersible or water-nondispersible polymer. Also disclosed are multicomponent fibers comprising a water dispersible sulfopolyester having a Tg of at least 57° C. and a water non-dispersible polymer. The multicomponent fibers may be used to produce microdenier fibers. Fibrous articles may be produced from the water-dispersible fibers, multicomponent fibers, and microdenier fibers. The fibrous articles include water-dispersible and microdenier nonwoven webs, fabrics, and multilayered articles such as wipes, gauze, tissue, diapers, panty liners, sanitary napkins, bandages, and surgical dressings. Also disclosed is a process for water-dispersible fibers, nonwoven fabrics, and microdenier webs. The fibers and fibrous articles have further applications in flushable personal care and cleaning products, disposable protective outerwear, and laminating binders. | 2011-06-16 |
20110140298 | METHOD AND APPARATUS OR DRY GRANULATION - The invention provides, inter alia, a method for producing granules from a powder, characterized in that compaction force is applied to the powder to produce a compacted mass comprising a mixture of fine particles and granules and separating and removing fine particles and/or small granules from the other granules by entraining the fine particles and/or small granules in a gas stream. Also provided are apparatus for use in the process and tablets formed by compression of the resultant granules. | 2011-06-16 |
20110140299 | SEMI-CONTINUITY FIBER PREPREG MATERIAL, MANUFACTURING METHOD THEREOF, AND COMPOSITE MATERIAL MADE OF SEMI-CONTINUITY FIBER PREPREG MATERIAL - The invention provides a semi-continuity fiber prepreg material, a manufacturing method thereof, and a composite material made of the semi-continuity fiber prepreg material. The semi-continuity fiber prepreg material includes a plurality of intermittency notches and/or continuity notches formed on a fiber prepreg material along at least one direction to make the fiber prepreg material soft and suitable for molding. | 2011-06-16 |
20110140300 | Microfluid-System-Supporting Unit And Production Method Thereof - The present invention relates to a microfluid-system-supporting unit, comprising a fixing layer formed on a substrate, a protective layer or a fixing layer, wherein part of at least one hollow filament in any shape is placed and fixed in the fixing layer. Thus, it provides a microfluid-system-supporting unit lower in surface irregularity even when there are multiple hollow filaments different in external diameter or the hollow filaments crosses each other and resistant to positional deviation of the hollow filament in the crossing regions, and a production method thereof. | 2011-06-16 |
20110140301 | PROCESS FOR PRODUCING A PLURALITY OF HIGH-STRENGTH, HIGH MODULUS AROMATIC POLYAMIDE FILAMENTS - A process for producing a plurality of high strength, high modulus aromatic polyamide filaments that includes extruding an acid solution containing at least 15% by weight of an aromatic polyamide through linearly arranged orifices in a spinneret to provide a warp of filaments, passing the warp of filaments through a layer of non-coagulating fluid into a coagulation bath and subsequently passing the warp through a spin tube, the spin tube having an elongated cross section with at least two opposite sides being parallel to the filament warp with the length of these sides being at least as long as the width of the filament warp, jetting additional coagulating liquid at a constant flow rate about the filaments in a downward direction at an angle between 15° and 75° with respect to the filaments, the jetted coagulating liquid moving downward with the warp of filaments through the spin tube at a velocity of about 50% to 100% of the velocity of the filaments, the coagulating liquid being jetted through a jet channel from either one side of the spin tube which is parallel to the filament warp, and the jet channel having at least the same width as the filament warp. | 2011-06-16 |
20110140302 | Capillary Imprinting Technique - The present invention provides a method for patterning a substrate with a template having a mold that features positioning conformable material between the substrate and the mold and filling a volume defined between the mold and the substrate with the conformable material through capillary action between the conformable material and one of the mold and the substrate. Thereafter, the conformable material is solidified. Specifically, the distance between the mold and the substrate is controlled to a sufficient degree to attenuate, if not avoid, compressive forces between the mold and the substrate. As a result, upon initial contact of the mold with the conformable material, capillary filling of the volume between the mold and the substrate occurs. | 2011-06-16 |
20110140303 | METHODS OF FABRICATING IMPRINT MOLD AND OF FORMING PATTERN USING THE IMPRINT MOLD - A method of fabricating an imprint mold is disclosed. The method includes: forming a first photo resist pattern on a substrate; etching the substrate using the first photo resist pattern as an etch mask to form a first pattern in the substrate; ashing the first photo resist pattern to form a second photo resist pattern; and etching the substrate using the second photo resist pattern to form a second pattern derived from the substrate and a third pattern derived from the first pattern. | 2011-06-16 |
20110140304 | IMPRINT LITHOGRAPHY TEMPLATE - Nano imprint lithography templates for purging of fluid during nano imprint lithography processes are described. The templates may include an inner channel and an outer channel. The inner channel constructed to provide fluid communication with a process gas supply to a region between the template and a substrate during the nano imprint lithography process. The outer channel constructed to evacuate fluid and/or confine fluid between the active area of template and the substrate. | 2011-06-16 |
20110140305 | METHOD OF LOW TEMPERATURE IMPRINTING PROCESS WITH HIGH PATTERN TRANSFER YIELD - The present invention is directed to novel methods of imprinting substrate-supported or freestanding structures at low cost, with high pattern transfer yield, and using low processing temperature. Such methods overcome many of the above-described limitations of the prior art. Generally, such methods of the present invention employ a sacrificial layer of film. | 2011-06-16 |
20110140306 | Composition for an Etching Mask Comprising a Silicon-Containing Material - The present invention includes a composition for a silicon-containing material used as an etch mask for underlying layers. More specifically, the silicon-containing material may be used as an etch mask for a patterned imprinted layer comprising protrusions and recessions. To that end, in one embodiment of the present invention, the composition includes a hydroxyl-functional silicone component, a cross-linking component, a catalyst component, and a solvent. This composition allows the silicon-containing material to selectively etch the protrusions and the segments of the patterned imprinting layer in superimposition therewith, while minimizing the etching of the segments in superposition with the recessions, and therefore allowing an in-situ hardened mask to be created by the silicon-containing material, with the hardened mask and the patterned imprinting layer forming a substantially planarized profile. | 2011-06-16 |
20110140307 | METHOD OF MAKING POLYLACTIC ACID AND ITS PRODUCTS - The present disclosure provides a method for preparing polylactic acid and its products using a twin-screw extruder, comprising the step of mixing carbon dioxide adducts of carbene and lactide, and obtaining polylactic acid and its products via reactive extrusion using a twin-screw extruder. Some of the carbon dioxide adducts or carbene have the following general formula: | 2011-06-16 |
20110140308 | TAMPON APPLICATOR BARRELS HAVING GRIPPING STRUCTURES AND METHODS OF FORMING - A tampon applicator barrel including a cardboard tube having a first end and a second end and at least one gripping structure defined from the cardboard tube proximate the second end is provided. The cardboard tube has a wall thickness of between about 0.015 and about 0.020 inches, while the gripping structure has a height of up to about 0.035 inches. | 2011-06-16 |
20110140309 | METHOD FOR MAKING CARBON NANOTUBE STRUCTURE - The present disclosure relates to a method for making a carbon nanotube structure. The method includes steps of providing a tubular carbon nanotube array; selecting a carbon nanotube segment having a predetermined width from the tubular carbon nanotube array using a drawing tool; and drawing the carbon nanotube segment along a radial direction of the tubular carbon nanotube array to achieve the carbon nanotube structure. | 2011-06-16 |
20110140310 | Injection mold having pre-heating device, the pre-heating device, and method for pre-heating injection mold - An injection mold having pre-heating device, the pre-heating device, and method for pre-heating injection mold are provided. The pre-heating device includes a high frequency coil member and a transportation device having a Z axle servo motor, a Z axle linear sliding rail, an annular transportation belt and a lifting rack. The annular transportation belt is driven by the Z axle servo motor. The high frequency coil member is hung on the lifting rack. The lifting rack is moveably connected to the Z axle linear sliding rail, coupled to the annular transportation belt and is driven by the annular transportation belt to perform an ascent or descent movement along the Z axle linear sliding rail. | 2011-06-16 |
20110140311 | Injection Molding Method and Apparatus - A thermoplastic injection molding system and method of use is described for molding parts from heated plastics and other organic resins. The machine uses heat sources located along the barrel to heat the source material while an auger screw transports the source material in the barrel. This transport step does not shear the source material, nor does it use friction to produce the heat necessary to melt the source material. The material becomes substantially liquid or melted during the heating process, and the melted material is forced, by the auger screw, into a chamber whereupon a plunger, situated concentrically with the auger screw, injects the material from the chamber into a mold. Sensors located along the barrel and in the chamber ensure consistency between mold cycles. The controller dynamically adjusts the injection molding process to achieve more consistent and reliable molded parts. | 2011-06-16 |
20110140312 | COMPOSITE OF SUPPORT MATRIX AND COLLAGEN, AND METHOD FOR PRODUCTION OF SUPPORT MATRIX AND COMPOSITE - A cylindrical body is produced which is composed of a fiber structure with a basis weight of 1-50 g/m | 2011-06-16 |
20110140313 | Insertion Plunger and Method for Inserting Wrap-Around Labels and Container Bottom Labels into an Injection Mold - An insertion plunger for inserting at least one wrap-around label and at least one bottom label into an injection mold for producing a plastic container has an outer plunger and an inner plunger that is movable relative to the outer plunger. In a method for insertion of a wrap-around label and a bottom label into an injection mold, the labels are inserted by an insertion plunger in that the wrap-around label and the bottom label are inserted in a single stroke performed by the insertion plunger into the injection mold. | 2011-06-16 |