24th week of 2016 patent applcation highlights part 65 |
Patent application number | Title | Published |
20160172204 | DEVICE OF CHANGING GAS FLOW PATTERN AND A WAFER PROCESSING METHOD AND APPARATUS | 2016-06-16 |
20160172205 | PLASMA ETCHING METHOD | 2016-06-16 |
20160172206 | FAST-GAS SWITCHING FOR ETCHING | 2016-06-16 |
20160172207 | PELLICLE MEMBRANE AND METHOD OF MANUFACTURING THE SAME | 2016-06-16 |
20160172208 | CHEMICAL MECHANICAL PLANARIZATION TOPOGRAPHY CONTROL VIA IMPLANT | 2016-06-16 |
20160172209 | CMP-FRIENDLY COATINGS FOR PLANAR RECESSING OR REMOVING OF VARIABLE-HEIGHT LAYERS | 2016-06-16 |
20160172210 | SEMICONDUCTOR MANUFACTURING APPARATUS AND SEMICONDUCTOR MANUFACTURING METHOD | 2016-06-16 |
20160172211 | UV ASSISTED CVD ALN FILM FOR BEOL ETCH STOP APPLICATION | 2016-06-16 |
20160172212 | PLASMA PROCESSING METHOD | 2016-06-16 |
20160172213 | THERMAL PROCESSING IN SILICON | 2016-06-16 |
20160172214 | Molded Electronic Package Geometry To Control Warpage And Die Stress | 2016-06-16 |
20160172215 | METHOD FOR REPAIRING SEMICONDUCTOR PROCESSING COMPONENTS | 2016-06-16 |
20160172216 | Ion Energy Control By RF Pulse Shape | 2016-06-16 |
20160172217 | PLASMA PROCESSING APPARATUS | 2016-06-16 |
20160172218 | HEAT TREATMENT APPARATUS, HEAT TREATMENT METHOD, AND STORAGE MEDIUM | 2016-06-16 |
20160172219 | TEMPERATURE CONTROL SYSTEM FOR SEMICONDUCTOR MANUFACTURING SYSTEM | 2016-06-16 |
20160172220 | SELENIZATION PROCESS APPARATUS FOR GLASS SUBSTRATE | 2016-06-16 |
20160172221 | SUBSTRATE PROCESSING APPARATUS | 2016-06-16 |
20160172222 | METHODS AND DEVICES FOR SECURING AND TRANSPORTING SINGULATED DIE IN HIGH VOLUME MANUFACTURING | 2016-06-16 |
20160172223 | GAS PURGE DEVICE AND GAS PURGE METHOD | 2016-06-16 |
20160172224 | SUBSTRATE TRANSFER UNIT, SUBSTRATE TREATING APPARATUS INCLUDING THE SAME, AND SUBSTRATE TREATING METHOD | 2016-06-16 |
20160172225 | SUBSTRATE PROCESSING APPARATUS, SUBSTRATE PROCESSING SYSTEM, AND METHOD OF DETECTING ABNORMALITY IN TRANSPORT CONTAINER | 2016-06-16 |
20160172226 | GAS COOLED MINIMAL CONTACT AREA(MCA) ELECTROSTATIC CHUCK(ESC) FOR ALUMINUM NITRIDE(ALN) PVD PROCESS | 2016-06-16 |
20160172227 | ELECTROSTATIC CHUCK DESIGN FOR HIGH TEMPERATURE RF APPLICATIONS | 2016-06-16 |
20160172228 | Method of laser separation of the epitaxial film or the epitaxial film layer from the growth substrate of the epitaxial semiconductor structure (variations) | 2016-06-16 |
20160172229 | STIFFENER TAPE FOR ELECTRONIC ASSEMBLY | 2016-06-16 |
20160172230 | DICING TAPE-INTEGRATED FILM FOR SEMICONDUCTOR BACK SURFACE AND METHOD FOR PRODUCING THE FILM, AND METHOD FOR PRODUCING SEMICONDUCTOR DEVICE | 2016-06-16 |
20160172231 | METHOD FOR RESIDUE-FREE BLOCK PATTERN TRANSFER ONTO METAL INTERCONNECTS FOR AIR GAP FORMATION | 2016-06-16 |
20160172232 | Interconnect Having Air Gaps and Polymer Wrapped Conductive Lines | 2016-06-16 |
20160172233 | METHOD OF FABRICATING SEMICONDUCTOR DEVICE | 2016-06-16 |
20160172234 | METHOD OF FORMING A SEMICONDUCTOR DEVICE INCLUDING TRENCH TERMINATION AND TRENCH STRUCTURE THEREFOR | 2016-06-16 |
20160172235 | IN-SITU DOPED POLYSILICON FILLER FOR TRENCHES | 2016-06-16 |
20160172236 | DEVICE SUBSTRATES, INTEGRATED CIRCUITS AND METHODS FOR FABRICATING DEVICE SUBSTRATES AND INTEGRATED CIRCUITS | 2016-06-16 |
20160172237 | NON-LITHOGRAPHICALLY PATTERNED DIRECTED SELF ASSEMBLY ALIGNMENT PROMOTION LAYERS | 2016-06-16 |
20160172238 | SELECTIVE SEALANT REMOVAL | 2016-06-16 |
20160172239 | ULTRA-THIN DIELECTRIC DIFFUSION BARRIER AND ETCH STOP LAYER FOR ADVANCED INTERCONNECT APPLICATIONS | 2016-06-16 |
20160172240 | METHOD FOR FORMING A COUPLING LAYER | 2016-06-16 |
20160172241 | ELECTROLESS METAL THROUGH SILICON VIA | 2016-06-16 |
20160172242 | SEMICONDUCTOR DEVICES AND METHODS FOR BACKSIDE PHOTO ALIGNMENT | 2016-06-16 |
20160172243 | WAFER MATERIAL REMOVAL | 2016-06-16 |
20160172244 | METHOD FOR MANUFACTURING ELECTRONIC DEVICE COMPRISING A RESIN SUBSTRATE AND AN ELECTRONIC COMPONENT | 2016-06-16 |
20160172245 | Method of forming a Gate Shield in an ED-CMOS Transistor and a base of a bipolar transistor using BICMOS Technologies | 2016-06-16 |
20160172246 | NANOWIRE CMOS STRUCTURE AND FORMATION METHODS | 2016-06-16 |
20160172247 | METHOD OF FORMING SEMICONDUCTOR DEVICE WITH DIFFERENT THRESHOLD VOLTAGES | 2016-06-16 |
20160172248 | Method of Forming Semiconductor Device with Different Threshold Voltages | 2016-06-16 |
20160172249 | DESIGN STRUCTURE FOR METAL OXIDE SEMICONDUCTOR CAPACITOR | 2016-06-16 |
20160172250 | Semiconductor Isolation Structure with Air Gaps in Deep Trenches | 2016-06-16 |
20160172251 | INTEGRATED CIRCUITS AND METHODS OF FORMING THE SAME WITH EFFECTIVE DUMMY GATE CAP REMOVAL | 2016-06-16 |
20160172252 | ALIGNMENT OF THREE DIMENSIONAL INTEGRATED CIRCUIT COMPONENTS | 2016-06-16 |
20160172253 | ELECTRIC-PROGRAMMABLE MAGNETIC MODULE AND PICKING-UP AND PLACEMENT PROCESS FOR ELECTRONIC DEVICES | 2016-06-16 |
20160172254 | MEASURING DEVICE AND METHOD FOR MEASURING LAYER THICKNESSES AND DEFECTS IN A WAFER STACK | 2016-06-16 |
20160172255 | WAFER PROCESSING APPARATUSES AND METHODS OF OPERATING THE SAME | 2016-06-16 |
20160172256 | Detection of Lost Wafer from Spinning Chuck | 2016-06-16 |
20160172257 | ETCHING PROCESSING METHOD AND BEVEL ETCHING APPARATUS | 2016-06-16 |
20160172258 | METHOD OF ENDPOINT DETECTION OF PLASMA ETCHING PROCESS USING MULTIVARIATE ANALYSIS | 2016-06-16 |
20160172259 | CUSTOMIZED MODULE LID | 2016-06-16 |
20160172260 | ELECTRONIC COMPONENT HOUSING PACKAGE AND ELECTRONIC APPARATUS | 2016-06-16 |
20160172261 | ULTRA FINE PITCH PoP CORELESS PACKAGE | 2016-06-16 |
20160172262 | INTEGRATED CIRCUIT DEVICE WITH SHAPED LEADS AND METHOD OF FORMING THE DEVICE | 2016-06-16 |
20160172263 | METHOD AND STRUCTURE FOR WAFER-LEVEL PACKAGING | 2016-06-16 |
20160172264 | PACKAGE STRUCTURE AND FABRICATION METHOD THEREOF | 2016-06-16 |
20160172265 | SEMICONDUCTOR PACKAGE | 2016-06-16 |
20160172266 | SEMICONDUCTOR DEVICE | 2016-06-16 |
20160172267 | CIRCUIT DEVICE AND METHOD OF MANUFACTURING A CIRCUIT DEVICE FOR CONTROLLING A TRANSMISSION OF A VEHICLE | 2016-06-16 |
20160172268 | Bond Via Array for Thermal Conductivity | 2016-06-16 |
20160172269 | SEMICONDUCTOR PACKAGE | 2016-06-16 |
20160172270 | INSULATING SHEET AND MANUFACTURING METHOD FOR SAME | 2016-06-16 |
20160172271 | Techniques for Interconnecting Stacked Dies Using Connection Sites | 2016-06-16 |
20160172272 | INTEGRATED CIRCUIT (IC) PACKAGE WITH A SOLDER RECEIVING AREA AND ASSOCIATED METHODS | 2016-06-16 |
20160172273 | INTEGRATED CIRCUIT DEVICE WITH PLATING ON LEAD INTERCONNECTION POINT AND METHOD OF FORMING THE DEVICE | 2016-06-16 |
20160172274 | SYSTEM, APPARATUS, AND METHOD FOR SEMICONDUCTOR PACKAGE GROUNDS | 2016-06-16 |
20160172275 | PACKAGE FOR A SURFACE-MOUNT SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF | 2016-06-16 |
20160172276 | Bonding clip, carrier and method of manufacturing a bonding clip | 2016-06-16 |
20160172277 | LAND STRUCTURE FOR SEMICONDUCTOR PACKAGE AND METHOD THEREFOR | 2016-06-16 |
20160172278 | ASSEMBLY OF AN INTEGRATED CIRCUIT CHIP AND OF A PLATE | 2016-06-16 |
20160172279 | Integrated Power Assembly with Reduced Form Factor and Enhanced Thermal Dissipation | 2016-06-16 |
20160172280 | POWER FIELD-EFFECT TRANSISTOR (FET), PRE-DRIVER, CONTROLLER, AND SENSE RESISTOR INTEGRATION FOR MULTI-PHASE POWER APPLICATIONS | 2016-06-16 |
20160172281 | PACKAGING STRUCTURE | 2016-06-16 |
20160172282 | POST-MOLD FOR SEMICONDUCTOR PACKAGE HAVING EXPOSED TRACES | 2016-06-16 |
20160172283 | Power Semiconductor Package Having Reduced Form Factor and Increased Current Carrying Capability | 2016-06-16 |
20160172284 | Integrated Power Assembly with Stacked Individually Packaged Power Devices | 2016-06-16 |
20160172285 | POWER MODULE | 2016-06-16 |
20160172286 | SEMICONDUCTOR PACKAGE, MODULE SUBSTRATE AND SEMICONDUCTOR PACKAGE MODULE HAVING THE SAME | 2016-06-16 |
20160172287 | WIRING BOARD AND SEMICONDUCTOR DEVICE | 2016-06-16 |
20160172288 | INTERPOSER WITH LATTICE CONSTRUCTION AND EMBEDDED CONDUCTIVE METAL STRUCTURES | 2016-06-16 |
20160172289 | CIRCUIT SUBSTRATE AND PACKAGE STRUCTURE | 2016-06-16 |
20160172290 | INTERPOSER WITH LATTICE CONSTRUCTION AND EMBEDDED CONDUCTIVE METAL STRUCTURES | 2016-06-16 |
20160172291 | SEMICONDUCTOR PACKAGE | 2016-06-16 |
20160172292 | SEMICONDUCTOR PACKAGE ASSEMBLY | 2016-06-16 |
20160172293 | INTERPOSER WITH SIGNAL-CONDITIONED EDGE PROBE POINTS | 2016-06-16 |
20160172294 | HIGH ASPECT RATIO STRUCTURE | 2016-06-16 |
20160172295 | Power FET Having Reduced Gate Resistance | 2016-06-16 |
20160172296 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME | 2016-06-16 |
20160172297 | DESIGNED-BASED INTERCONNECT STRUCTURE IN SEMICONDUCTOR STRUCTURE | 2016-06-16 |
20160172298 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME | 2016-06-16 |
20160172299 | INTEGRATED DEVICE PACKAGE COMPRISING PHOTO SENSITIVE FILL BETWEEN A SUBSTRATE AND A DIE | 2016-06-16 |
20160172300 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME | 2016-06-16 |
20160172301 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR | 2016-06-16 |
20160172302 | PACKAGE ON PACKAGE (POP) DEVICE COMPRISING A HIGH PERFORMANCE INTER PACKAGE CONNECTION | 2016-06-16 |
20160172303 | Contact Critical Dimension Control | 2016-06-16 |