24th week of 2022 patent applcation highlights part 64 |
Patent application number | Title | Published |
20220189509 | METHODS AND APPARATUS TO PERFORM SPEED-ENHANCED PLAYBACK OF RECORDED MEDIA - Methods, apparatus, systems, and articles of manufacture to perform speed-enhanced playback of recorded media are disclosed. Example apparatus to playback media disclosed herein comprise at least one memory, machine-readable instructions, and processor circuitry to execute the machine-readable instructions to parse an audio frame included in the media to determine a number of skip bytes included in the audio frame, compare the number of skip bytes to a threshold, associate the audio frame with a plurality of candidate frames identified in the media when the number of skip bytes satisfies the threshold, and calculate a speed-enhanced playback rate for the media based on the plurality of candidate frames identified in the media. | 2022-06-16 |
20220189510 | MUSIC DATA EDITING DEVICE AND MUSIC DATA EDITING PROGRAM - A music data editing device includes: a music data player configured to play music data to which a unit section for playing a music piece is assigned; a unit section recorder configured to record the music data of every unit section in time series, the music data being currently played; and a unit section reader configured to read the unit section recorded by the unit section recorder. | 2022-06-16 |
20220189511 | USER INTERFACE FOR VIDEO EDITING SYSTEM - Methods, systems and software products for video editing systems are disclosed herein. The software product includes a computer readable medium storing instructions which, when executed by a processors, cause the processor to display a graphical user interface for a video editing system, the graphical user interface including first and second spaced apart timelines, and responsive to detecting a user interaction with one of the timelines, apply a corresponding interaction to the other timeline. | 2022-06-16 |
20220189512 | MEMORY DEVICES INCLUDING HEATERS - Memory devices might include an array of memory cells, a plurality of access lines, and a heater. The array of memory cells might include a plurality of strings of series-connected memory cells. Each access line of the plurality of access lines might be connected to a control gate of a respective memory cell of each string of series-connected memory cells of the plurality of strings of series-connected memory cells. The heater might be adjacent to an end of each access line of the plurality of access lines. | 2022-06-16 |
20220189513 | RECOVERY OF MEMORY FROM ASYNCHRONOUS POWER LOSS - Systems and methods are disclosed, including determining whether to write dummy data to a first physical page of memory cells of a storage system, such as in response to a detected asynchronous power loss (APL) at the storage system, using a determined number of ones stored in the first physical page. | 2022-06-16 |
20220189514 | DIFFERENTIAL AMPLIFIER SCHEMES FOR SENSING MEMORY CELLS - Methods, systems, and devices for differential amplifier schemes for sensing memory cells are described. In one example, an apparatus may include a memory cell, a differential amplifier having a first input node, a second input node, and an output node that is coupled with the first input node via a first capacitor, and a second capacitor coupled with the first input node. The apparatus may include a controller configured to cause the apparatus to bias the first capacitor, couple the memory cell with the first input node, and generate, at the output node, a sense signal based at least in part on biasing the first capacitor and coupling the memory cell with the first input node. The apparatus may also include a sense component configured to determine a logic state stored by the memory tell based at least in part on the sense signal. | 2022-06-16 |
20220189515 | 3D Memory with 3D Sense Amplifier - Structures for 3D sense amplifiers for 3D memories are disclosed. A first embodiment uses one type of vertical transistors in constructing 3D sense amplifiers. A second embodiment uses both n- and p-type transistors for 3D sense amplifiers. Either or both of n- and p-type transistors are vertical transistors. The n- and p-type transistors may reside on different levels, or on the same level above a substrate if both are vertical transistors. In any embodiment, different options are available for gate contact formation. In any embodiments and options or alternatives thereof, one or more sense-enable circuits may be used. Sense amplifiers for several bit lines may be staggered on one or both sides of a memory array. Column multiplexers may be used to couple particular bit lines to data outputs. Bit-line multiplexers may be used to couple certain bit lines to shared 3D sense amplifiers. | 2022-06-16 |
20220189516 | PIPE LATCH CIRCUIT, OPERATING METHOD THEREOF, AND SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME - A pipe latch circuit may include first and second latching circuit groups. The first latching circuit group may control a latching operation and an output operation based on a plurality of pipe input control signals. The second latching circuit group may control a latching operation and an output operation based on the plurality of pipe input control signals and a plurality of pipe output control signals. | 2022-06-16 |
20220189517 | MEMORY DEVICES FOR MULTILPLE READ OPERATIONS - Memory devices might include an array of memory cells, a plurality of access lines, and control logic. The array of memory cells includes a plurality of strings of series-connected memory cells. Each access line of the plurality of access lines is connected to a control gate of a respective memory cell of each string of series-connected memory cells of the plurality of strings of series-connected memory cells. The control logic is configured to: open the array of memory cells for multiple read operations; read first page data from respective memory cells coupled to a selected access line of the plurality of access lines; read second page data from the respective memory cells coupled to the selected access line; and close the array of memory cells subsequent to reading the first page data and the second page data. | 2022-06-16 |
20220189518 | METHOD AND APPARATUS AND COMPUTER PROGRAM PRODUCT FOR READING DATA FROM MULTIPLE FLASH DIES - The invention relates to a method, an apparatus and a computer program product for reading data from multiple flash dies. The method is performed by a processing unit when loading and executing program code to include: issuing a read instruction to a flash interface to drive the flash interface to activate a data read operation for reading data from a location in a die; calculating an output time point corresponding to the read instruction; and issuing a random out instruction corresponding to the read instruction to the flash interface to drive the flash interface to store the data in a random access memory (RAM) when a current time reaches to, or is later than the output time point. | 2022-06-16 |
20220189519 | Memory Subsystem Calibration Using Substitute Results - A memory subsystem and method for performing calibrations therein is disclosed. A memory subsystem includes a memory controller coupled to a memory by a plurality of signal paths. The memory controller is configured to perform an initial calibration to determine respective eye patterns corresponding to the ones of the plurality of signal paths. For a subsequent calibrations, updated eye patterns are determined for a subset of the plurality of signal paths. Remaining ones of the plurality of signal paths (not included in the subset), are not active during the subsequent calibrations. Updated eye patterns for the remaining ones of the plurality of signal paths are determined based on information obtained during the initial calibration and information from signal paths in the subset designated proxies for the remaining ones of the plurality of signal paths. | 2022-06-16 |
20220189520 | MEMORY SYSTEM AND METHOD OF CONTROLLING A MEMORY CHIP - A memory system includes a memory chip and a memory controller that controls the memory chip. In a write operation, the memory controller transfers a first timing signal synchronized with a first clock and first data synchronized with the first timing signal to the memory chip. In a read operation, the memory controller transfers a second timing signal synchronized with at least a second clock to the memory chip. The second clock has a frequency different from a frequency of the first clock. In the read operation, the memory chip generates a third timing signal synchronized with the second clock based on the second timing signal, and transfers the third timing signal and second data synchronized with the third timing signal to the memory controller. | 2022-06-16 |
20220189521 | STORAGE CONTROLLER, STORAGE DEVICE, AND OPERATION METHOD OF STORAGE DEVICE - An operation method of a storage device, which includes a storage controller and a nonvolatile memory device, includes performing first boot-up operation, performing first training on a plurality of data signals such that a detection operation of the first training is repeatedly performed on windows of the data signals, storing offset information generated based on a result of the first training, performing a normal operation based on the result of the first training, performing a second boot-up operation, performing second training on the plurality of data signals based on the offset information generated in the first training such that a detection operation of the second training is repeatedly performed on a left edge section and a right edge section of windows of the data signals, and performing the normal operation based on a result of the second training. | 2022-06-16 |
20220189522 | MULTI-ACCESS MEMORY CELL - An example device includes a memory element configured to store a state for a bit in response to a write operation and to output an indication of the state for the bit in response to a read operation. The device includes first access circuitry coupled to the memory element. The first access circuitry is configured to allow a first current to flow through the first access circuitry in response to being driven in the read operation or the write operation. The device includes second access circuitry coupled to the memory element. The second access circuitry is configured to allow a second current to flow through the second access circuitry in response to being driven in the write operation. A transconductance of the first access device is different than a transconductance of the second access device. | 2022-06-16 |
20220189523 | MEMORY CELL, DEVICE AND METHOD FOR WRITING TO A MEMORY CELL - According to an aspect there is provided a memory cell. The memory cell comprises: a first and a second electrode; a spin-orbit-torque, SOT, layer comprising a first and a second electrode contact portion arranged in contact with the first and the second electrode, respectively, and an intermediate portion between the first and second electrode contact portions; a first magnetic tunnel junction, MTJ, layer stack arranged in contact with the intermediate portion; and a second MTJ layer stack arranged in contact with the second electrode contact portion and directly above the second electrode. | 2022-06-16 |
20220189524 | MEMORY CELL, MEMORY CELL ARRANGEMENT, AND METHODS THEREOF - According to various aspects, a memory cell is provided, the memory cell may include a field-effect transistor; a first control node and a second control node, a first capacitor structure including a first electrode connected to the first control node, a second electrode connected to a gate region of the field-effect transistor, and a remanent-polarizable region disposed between the first electrode and the second electrode of the first capacitor structure; and a second capacitor structure including a first electrode connected to the second control node, a second electrode connected to the gate region of the field-effect transistor. In some aspects, the first capacitor structure may have a first capacitance and the second capacitor structure may have a second capacitance different from the first capacitance. | 2022-06-16 |
20220189525 | FERROELECTRIC MEMORY AND MEMORY ELEMENT THEREOF - A ferroelectric memory is intended to reduce an applied voltage required at the times of writing and reading. A ferroelectric capacitor includes a ferroelectric film and a top electrode and a bottom electrode including materials with different work functions formed above and below the ferroelectric film. The transistor is connected to either the top electrode or the bottom electrode to select the ferroelectric capacitor. A drive control unit applies, at the times of writing and reading, a voltage lower than that at the time of erasing by a predetermined potential difference to the ferroelectric film. | 2022-06-16 |
20220189526 | NON-VOLATILE ANALOG RESISTIVE MEMORY CELLS IMPLEMENTING FERROELECTRIC SELECT TRANSISTORS - A device includes a non-volatile analog resistive memory cell. The non-volatile analog resistive memory device includes a resistive memory device and a select transistor. The resistive memory device includes a first terminal and a second terminal. The resistive memory device has a tunable conductance. The select transistor is a ferroelectric field-effect transistor (FeFET) device which includes a gate terminal, a source terminal, and a drain terminal. The gate terminal of the FeFET device is connected to a word line. The source terminal of the FeFET device is connected to a source line. The drain terminal of the FeFET device is connected to the first terminal of the resistive memory device. The second terminal of the resistive memory device is connected to a bit line. | 2022-06-16 |
20220189527 | MEMORY SYSTEM AND MEMORY MODULE INCLUDING MEMORY CHIPS SHARING CHANNEL - A memory system includes: a plurality of memory chips each including a plurality of banks and each suitable for generating a tracking address by tracking a row-hammer risk of selected banks among the banks, encrypting the tracking address using an encryption key to output tracking information to a corresponding data bus of a plurality of data buses and performing a target refresh operation according to a row-hammer address transferred through a command/address bus; and a memory controller suitable for collecting the tracking information for the banks transferred through the plurality of data buses to generate and output the row-hammer address to the command/address bus. | 2022-06-16 |
20220189528 | WORDLINE BOOST DRIVER - An example apparatus for writing a bit to a memory cell includes wordline driver circuitry configured to generate a first voltage in response to a row access enable signal. The apparatus also includes boost driver circuitry coupled to the wordline driver circuitry. The boost driver circuitry is configured to charge a capacitor using the first voltage and to generate a second voltage using the first voltage and a voltage at the capacitor in response to a boost enable signal. The apparatus also includes a wordline coupled to the memory cell and the wordline driver circuitry. The wordline is configured to output the first voltage or the second voltage to the memory cell. | 2022-06-16 |
20220189529 | ULTRA-COMPACT PAGE BUFFER - A device includes a memory array and a sense amplifier (SA) coupled with the memory array and with an input/output (I/O) data line. The SA is to receive bits of data over the I/O data line in association with a program operation. A digital-to-analog converter (DAC) is coupled with the SA, the DAC to convert the bits of data to an analog voltage value. An analog memory element is coupled with the DAC, the analog memory element to store the analog voltage value for a period of time until the bits of data are programmed to the memory array. | 2022-06-16 |
20220189530 | TERMINALS AND DATA INPUT/OUTPUT CIRCUITS LAYOUT - Apparatuses for providing pads included in external terminals of a semiconductor device are described. An example apparatus includes a memory cell array, a data queue (DQ) circuit, a data pad and a power pad. The memory cell array may include one or more memory cells. In a write operation, the data pad receives write data and provides the write data to the DQ circuit. The DQ circuit receives the write data and provides the write data to the memory cell array. In a read operation, the DQ circuit receives read data from the memory cell array and provides the read data. The data pad receives the read data from the DQ circuit and provides the read data. The power pad provides a power supply voltage. The data pad and the power pad are disposed across from each other with respect to the DQ circuit. | 2022-06-16 |
20220189531 | RECONFIGURABLE PROCESSING-IN-MEMORY LOGIC - An example system implementing a processing-in-memory pipeline includes: a memory array to store data in a plurality of memory cells electrically coupled to a plurality of wordlines and a plurality of bitlines; a logic array coupled to the memory array, the logic array to implement configurable logic controlling the plurality of memory cells; and a control block coupled to the memory array and the logic array, the control block to control a computational pipeline to perform computations on the data by activating at least one of: one or more bitlines of the plurality of bitlines or one or more wordlines of the plurality of wordlines. | 2022-06-16 |
20220189532 | REFRESH COMMAND CONTROL FOR HOST ASSIST OF ROW HAMMER MITIGATION - A memory device with internal row hammer mitigation couples to a memory controller. The memory controller or host can assist with row hammer mitigation by sending additional refresh cycles or refresh commands. In response to an extra refresh command the memory device can perform refresh for row hammer mitigation instead of refresh for standard data integrity. The memory controller can keep track of the number of activate commands sent to the memory device, and in response to a threshold number of activate commands, the memory controller sends the additional refresh command. With the extra refresh command the memory device can refresh the potential victim rows of a potential aggressor row, instead of simply refreshing a row that has not been accessed for a period of time. | 2022-06-16 |
20220189533 | SEMICONDUCTOR MEMORY DEVICE AND MEMORY SYSTEM INCLUDING THE SAME - A memory system includes: a memory controller suitable for: generating a first target address by sampling an active address according to an active command, providing the active address together with the active command, and providing a first target refresh command together with the first target address; and a memory device suitable for: generating a second target address by sampling the active address according to the active command, performing a target refresh operation on at least one word line corresponding to the first target address according to the first target refresh command, and performing the target refresh operation on at least one word line corresponding to the second target address according to a second target refresh command. | 2022-06-16 |
20220189534 | ELECTRONIC DEVICE FOR PERFORMING SMART REFRESH OPERATION - An electronic device includes a target address generation circuit configured to generate a counting signal by counting the number of times each logic level combination of an address is input by performing an internal read operation and an internal write operation during an active operation, configured to store the counting signal as the storage counting signal when the counting signal is counted more than a storage counting signal that is stored therein, and configured to store the address, corresponding to the counting signal, as a target address; and a refresh control circuit configured to control a smart refresh operation on the target address. | 2022-06-16 |
20220189535 | MEMORY CONTROLLER AND MEMORY SYSTEM - A memory controller includes: a security level setting circuit suitable for setting a security level by monitoring a risk of a row hammer attack; and a refresh management command control circuit suitable for controlling the number of times that a refresh management command is to be applied to a memory per unit time according to the security level. | 2022-06-16 |
20220189536 | APPARATUS AND METHOD FOR PERFORMING TARGET REFRESH OPERATION - A memory apparatus comprises: a sampling circuit for sampling an input address through a sampling method corresponding to a first selection signal among at least two sampling methods, a storage circuit for storing up to N number of addresses having different values among sampled addresses received from the sampling circuit, an arranging circuit for determining an output sequence of addresses stored in the storage circuit through an arranging method corresponding to a second selection signal among the two arranging methods, and setting, as a target address, an address outputted according to the output sequence, a selection control circuit for setting each of the first selection signal and the second selection signal based on a state of the storage circuit, and a refresh operation circuit for controlling a target refresh operation on a row of memory cells corresponding to the target address. | 2022-06-16 |
20220189537 | SEMICONDUCTOR MEMORY DEVICE AND MEMORY SYSTEM INCLUDING THE SAME - A memory system includes: a memory device including at least one bank; and a memory controller suitable for: dividing the bank into a plurality of sub-regions according to an active address, generating an aging signal for the bank based on a plurality of counting values generated by counting a number of inputs of an active command for each of the sub-regions, and providing the active command, the active address, the aging signal, and a target refresh command, wherein the memory device is suitable for: generating a sampling address by sampling the active address according to the active command, and performing a target refresh operation on a word line corresponding to the sampling address according to the target refresh command while adjusting a refresh period of the bank according to the aging signal. | 2022-06-16 |
20220189538 | MEMORY SYSTEM - A memory system includes: a normal memory area suitable for storing normal data; a security memory area suitable for storing security data; a first row hammer detection circuit suitable for sampling and counting a portion of rows that are activated in the normal memory area to select first rows that need to be refreshed; and a second row hammer detection circuit suitable for counting all rows that are activated in the security memory area to select second rows that need to be refreshed. | 2022-06-16 |
20220189539 | APPARATUSES AND METHODS FOR DYNAMIC TARGETED REFRESH STEALS - Embodiments of the disclosure are drawn to apparatuses, systems, and methods for dynamic targeted refresh steals. A memory bank ma receive access commands and then periodically enter a refresh mode, where auto refresh operations and targeted refresh operations are performed. The memory bank may receive a refresh management command based on a count of access commands directed to the memory bank. Responsive to the refresh management signal, a panic targeted refresh operation may be performed on the memory bank. A number of times the refresh management signal was issued may be counted, and based on that count a next periodic targeted refresh operation may be skipped. | 2022-06-16 |
20220189540 | MEMORY WITH PARTIAL ARRAY REFRESH - Memory devices and systems with partial array refresh control over memory regions in a memory array, and associated methods, are disclosed herein. In one embodiment, a memory device includes a memory array having a first memory region and a second memory region. The memory device is configured to write data to the memory array in accordance with a programming sequence by initially writing data to unutilized memory cells of the first memory region before initially writing data to unutilized memory cells of the second memory region. The memory device is further configured to determine that the data stored on the first and/or second memory regions is not consolidated, and to consolidate at least a portion of the data by rewriting the portion of the data to physically or logically contiguous memory cells of the first memory region and/or the second memory region. | 2022-06-16 |
20220189541 | CONTROL CIRCUIT OF MEMORY DEVICE - A circuit includes a tracking word line, a power switch, a tracking bit line, a sense circuit. The power switch is coupled between the tracking word line and a first node. The power switch is configured to discharge a voltage level on the first node in response to a clock pulse signal transmitted through the tracking word line to the power switch. The tracking bit line is coupled between the first node and a plurality of tracking cells in a memory array. The sense circuit is coupled between the first node and a second node. The sense circuit is configured to generate a negative bit line enable signal in response to that the voltage level on the first node is below a threshold voltage value of the sense circuit. | 2022-06-16 |
20220189542 | CIRCUIT AND METHOD OF WRITING TO A BIT CELL - A circuit includes first and second bit lines, a second power node having a voltage level below that of a first power node, a reference node having a reference voltage level, first and second pass gates and drivers, first and second logic gates coupled to the second power node, first and second conversion circuits coupled between the first power node and respective first and second logic and pass gates, and first and second NOR gates coupled between the second power node and respective first and second logic gates and drivers. The first and second pass gates selectively couple the first and second bit lines to the first power node responsive to the respective second and first logic gates and conversion circuits, and the first and second drivers selectively couple the first and second bit lines to the reference node responsive to the respective first and second logic and NOR gates. | 2022-06-16 |
20220189543 | ENHANCED STATE DUAL MEMORY CELL - A circuit may include a memory cell. The memory cell may include a first memory element, a second memory element, a first transistor, and a second transistor. The first memory element may be connected to a bit line. The second memory element may be connected to a select line. The first transistor may be connected to a first word line. The second transistor may be connected to a second word line. The first memory element may be programmed by applying a first write voltage to the bit line, applying a second write voltage to the second word line, applying a first intermediate voltage to the select line, and applying a second intermediate voltage to the first word line. The select line may be connected to a high impedance. The first write voltage may be a positive supply voltage, the second write voltage may be a negative supply voltage. | 2022-06-16 |
20220189544 | Data Programming Techniques to Store Multiple Bits of Data Per Memory Cell with High Reliability - A memory system to generate data with a relation among data groups for reliably storing a predetermined number of bits per memory cell in memory cells. For example, from first groups of date bits, a second group of data bits is generated. Data groups of the predetermined number is formed to have the first groups and the second group and a predetermined relation (e.g., XOR or XNOR) among the data groups. Threshold levels of memory cells in a memory cell group are determined based on a predetermined mapping, where a threshold level of each memory cell is determined to represent one bit from each of the data groups. In the predetermined mapping, bit values represented by any two successive threshold levels differ by one bit. Threshold voltages in the memory cell group are programmed according to the threshold levels to store the data groups with improved reliability. | 2022-06-16 |
20220189545 | MANAGING READ LEVEL VOLTAGE OFFSETS FOR LOW THRESHOLD VOLTAGE OFFSET BIN PLACEMENTS - A block family associated with a memory device is created. The block family is associated with a threshold voltage offset bin. A set of read level voltage offsets is determined such that, applying the set of read level voltage offsets to a base read level threshold voltage associated with the block family, result in a suboptimal error rate not exceeding a maximum allowable error rate. The determined set of read level offsets is associated with the threshold voltage offset bin by updating a block family metadata. | 2022-06-16 |
20220189546 | MULTI-LEVEL FERROELECTRIC FIELD-EFFECT TRANSISTOR DEVICES - A device comprises a non-volatile memory and a control system. The non-volatile memory includes an array of non-volatile memory cells, wherein at least one non-volatile memory cell includes a ferroelectric field-effect transistor (FeFET) device. The FeFET device includes first and second source/drain regions, and a gate structure which comprises a ferroelectric layer, and a gate electrode disposed over the ferroelectric layer. The ferroelectric layer comprises a first region adjacent to the first source/drain region and a second region adjacent to the second source/drain region. The control system is operatively coupled to the non-volatile memory to program the FeFET device to have a logic state among a plurality of different logic states. At least one logic state among the plurality of different logic states corresponds to a polarization state of the FeFET device in which the first and second regions of the ferroelectric layer have respective remnant polarizations with opposite polarities. | 2022-06-16 |
20220189547 | Sensing Techniques for Resistive Memory - Various implementations described herein are related to a device having a sense amplifier that provides output data based on sensing a difference between input signals. The device may have a tracking circuit that tracks a resistive state of a bitcell and provides an input signal to the sense amplifier based on the tracked resistive state of the bitcell. The device may have a bitcell circuit that senses a data value associated with the resistive state of the bitcell and provides another input signal to the sense amplifier based on the sensed data value of the bitcell. | 2022-06-16 |
20220189548 | DECODING FOR A MEMORY DEVICE - Methods, systems, and devices for decoding for a memory device are described. A decoder may include a first vertical n-type transistor and a second vertical n-type transistor that extends in a third direction relative to a die of a memory array. The first vertical n-type transistor may be configured to selectively couple an access line with a source node and the second n-type transistor may be configured to selectively couple the access line with a ground node. To activate the access line coupled with the first and second vertical n-type transistors, the first vertical n-type transistor may be activated, the second vertical n-type transistor may be deactivated, and the source node coupled with the first vertical n-type transistor may have a voltage applied that differs from a ground voltage. | 2022-06-16 |
20220189549 | DECODING FOR A MEMORY DEVICE - Methods, systems, and devices for decoding for a memory device are described. A decoder of a memory device may include transistors in a first layer between a memory array and a second layer that includes one or more components associated with the memory array. The second layer may include CMOS pre-decoding circuitry, among other components. The decoder may include CMOS transistors in the first layer. The CMOS transistors may control which voltage source is coupled with an access line based on a gate voltage applied to a p-type transistor and a n-type transistor. For example, a first gate voltage applied to a p-type transistor may couple a source node with the access line and bias the access line to a source voltage. A second gate voltage applied to the n-type transistor may couple a ground node with the access line and bias the access line to a ground voltage. | 2022-06-16 |
20220189550 | MIXED CONDUCTING VOLATILE MEMORY ELEMENT FOR ACCELERATED WRITING OF NONVOLATILE MEMRISTIVE DEVICE - An embodiment in the application may include an analog memory structure, and methods of writing to such a structure, including a volatile memory element in series with a non-volatile memory element. The analog memory structure may change resistance upon application of a voltage. This may enable accelerated writing of the analog memory structure. | 2022-06-16 |
20220189551 | TECHNIQUES FOR PROGRAMMING A MEMORY CELL - Techniques are provided for programming a self-selecting memory cell that stores a first logic state. To program the memory cell, a pulse having a first polarity may be applied to the cell, which may result in the memory cell having a reduced threshold voltage. During a duration in which the threshold voltage of the memory cell may be reduced (e.g., during a selection time), a second pulse having a second polarity (e.g., a different polarity) may be applied to the memory cell. Applying the second pulse to the memory cell may result in the memory cell storing a second logic state different than the first logic state. | 2022-06-16 |
20220189552 | APPARATUS AND METHODS INCLUDING SOURCE GATES - Apparatus and methods are disclosed, such as an apparatus that includes a string of charge storage devices associated with a pillar (e.g., of semiconductor material), a source gate device, and a source select device coupled between the source gate device and the string. Additional apparatus and methods are described. | 2022-06-16 |
20220189553 | METHODS OF FORMING TRANSISTORS HAVING RAISED EXTENSION REGIONS - Methods of forming a transistor might include forming a dielectric overlying a semiconductor having a first conductivity type, forming a conductor overlying the dielectric, patterning the conductor and dielectric to define a gate stack of the transistor, forming a first extension region base and a second extension region base in the semiconductor, forming a first extension region riser overlying the first extension region base and forming a second extension region riser overlying the second extension region base, and forming a first source/drain region in the first extension region riser and forming a second source/drain region in the second extension region riser, wherein the first extension region base, the second extension region base, the first source/drain region, and the second source/drain region each have a second conductivity type different than the first conductivity type. | 2022-06-16 |
20220189554 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SAME - The disclosure relates to a semiconductor memory device and a method of operating the same. The semiconductor memory device includes a memory block including a plurality of memory strings, a pass circuit connected between local word lines of the memory block and global word lines and configured to connect the local word lines to the global word lines in response to a block selection signal, and a voltage providing circuit configured to generate an operation voltage during a program or read operation, apply the operation voltage to the global word lines, and discharge the global word lines when the program operation or the read operation is completed, and the pass circuit is configured to control the local word lines to be in a floating state after the program operation or the read operation is completed and before discharging the global word lines. | 2022-06-16 |
20220189555 | ENHANCED GRADIENT SEEDING SCHEME DURING A PROGRAM OPERATION IN A MEMORY SUB-SYSTEM - Control logic in a memory device initiates a program operation on a memory array, the program operation comprising a seeding phase. During the seeding phase, the control logic causes a seeding voltage to be applied to a string of memory cells in a data block of the memory array during the seeding phase of the program operation and causes a first positive voltage to be applied to a first plurality of word lines of the data block during the seeding phase, wherein each of the first plurality of word lines is coupled to a corresponding memory cell of a first plurality of memory cells in the string of memory cells, the first plurality of word lines comprising a selected word line associated with the program operation. The control logic further causes a second positive voltage to be applied to one or more second word lines coupled to one or more second memory cells on a source-side of the first plurality of memory cells in the string of memory cells during the seeding phase, wherein the second positive voltage is less than the first positive voltage. | 2022-06-16 |
20220189556 | SEMICONDUCTOR STORAGE DEVICE - A semiconductor storage device includes a first word line, a second word line provided in the same layer with the first word line and configured to be controlled independently from the first word line, a plurality of memory pillars between the first word line and the second word line, each of the plurality of memory pillars including a first memory cell facing to the first word line and a second memory cell facing to the second word line, the plurality of memory pillars being arranged in a first direction and a second direction intersecting to the first direction and a control circuit. The control circuit is configured to perform a write operation to the second memory cell included in the plurality of memory pillars after performing a write operation to the first memory cell included in each of the plurality of memory pillars. | 2022-06-16 |
20220189557 | MEMORY DEVICE AND METHOD OF OPERATING THE SAME - A memory device comprises a plurality of memory cells each having a threshold voltage corresponding to any one of a plurality of program states according to target data to be stored by performing a program operation, page buffers configured to store data provided from a memory controller, a data conversion controller configured to control the page buffers to convert the data into the target data including a plurality of logical page bits and a program operation controller configured to perform the program operation to store the target data in the plurality of memory cells, wherein the plurality of logical page bits include at least one logical page bit distinguishing even program states from odd program states among the plurality of program states and remaining logical page bits other than the at least one logical page bit having a same value as at least one program state among adjacent program states. | 2022-06-16 |
20220189558 | TEMPERATURE-BASED MEMORY MANAGEMENT - A memory device and method of operation are described. The memory device may include memory cells of a first type that each store a single bit of information and memory cells of a second type that each store multiple bits of information. The memory cells of the first type may be more robust to extreme operating conditions than the second type but may have one or more drawbacks (e.g., lower density). The memory device may identify data to be written, and in response, may identify a temperature of the memory device. If the temperature is within a nominal operating range associated with a low risk of memory errors, the memory device may write the data to the memory cells of the second type. If the temperature is outside the nominal operating range, the memory device may write the data to the memory cells of the first type. | 2022-06-16 |
20220189559 | PAGE BUFFER CIRCUIT WITH BIT LINE SELECT TRANSISTOR - Aspects of the disclosure provide a memory device. For example, the memory device can include a memory array, a bitline and a buffer. The memory array can include a plurality of memory strings. The memory strings can be divided into a first memory string group and a second memory string group. The bitline can include a first bitline segment coupled to the first memory string group and a second bitline segment coupled to the second memory string group. The first bitline segment can be disposed between the first memory string group and the buffer and be connected to the buffer through a first conduction path. The second bitline segment can be disposed between the second memory string group and the buffer and be connected to the buffer through a second conduction path. | 2022-06-16 |
20220189560 | OPTIMAL DETECTION VOLTAGE OBTAINING METHOD, READING CONTROL METHOD AND APPARATUS OF MEMORY - An optimal detection voltage obtaining method, a reading control method and an apparatus are provided. The method includes: obtain a plurality of first difference values and a plurality of second difference values, the second difference value characterizes a difference value of two detection voltages which are adjacent in numerical value, the first difference value characterizes a difference between numbers of memory cells whose threshold voltages respectively equal to the two detection voltages used by the second difference value; dividing the first difference by the second difference to obtain a plurality of tangent approximations; selecting a first tangent approximation and a second tangent approximation from the plurality of tangent approximations, the first tangent approximation is a positive number and the second tangent approximation is a negative number; calculating an optimal detection voltage according to the first tangent approximation, the second tangent approximation, a first detection voltage and a second detection voltage. | 2022-06-16 |
20220189561 | MEMORY SYSTEM - According to one embodiment, a memory system includes a nonvolatile memory and a memory controller configured to cause the nonvolatile memory to execute a first process of reading data based on a first request from a host device. The memory controller is configured to, when the first request is received from the host device while causing the nonvolatile memory to execute a second process, hold interruption of the second process until a first number becomes a first threshold value or more. The first number is a number of the first requests to be performed in the memory controller. The first threshold value is an integer of 2 or more. | 2022-06-16 |
20220189562 | SEMICONDUCTOR INTEGRATED CIRCUIT, MEMORY CONTROLLER, AND MEMORY SYSTEM - A semiconductor integrated circuit includes: a first circuit, a second circuit, a third circuit, and a first switch circuit. The first circuit is configured to output a first signal. The second circuit is configured to output a second signal different from the first signal. The third circuit is configured to output a third signal corresponding to either the first signal or the second signal. The first switch circuit is configured to output the third signal to the first circuit in a case that the first circuit outputs the first signal. The first switch circuit is configured to output the third signal to the second circuit in a case that the second circuit outputs the second signal. | 2022-06-16 |
20220189563 | SEMICONDUCTOR DEVICE - A semiconductor device includes a memory circuit, a first FIFO, a second FIFO and an input/output circuit. The memory circuit outputs data. The first FIFO receives data from the memory circuit and outputs data synchronously with a first clock signal. The second FIFO receives data output from the first FIFO and outputs data synchronously with the first clock signal. The input/output circuit outputs data output from the second FIFO. The second FIFO is disposed in the vicinity of the input/output circuit than the first FIFO. | 2022-06-16 |
20220189564 | DETERMINING THRESHOLD VALUES FOR VOLTAGE DISTRIBUTION METRICS IN MEMORY SYSTEM - Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations including determining a voltage distribution metric associated with a at least part of a block of the memory device; determining a threshold value for the voltage distribution metric associated with the block; and responsive to determining that the voltage distribution metric exceeds the threshold value, performing a media management operation with respect to the block. | 2022-06-16 |
20220189565 | SHORT PROGRAM VERIFY RECOVERY WITH REDUCED PROGRAMMING DISTURBANCE IN A MEMORY SUB-SYSTEM - Control logic in a memory device initiates a program operation on the memory device, the program operation comprising a program phase, a program recovery phase, a program verify phase, and a program verify recovery phase. The control logic further causes a negative voltage signal to be applied to a first plurality of word lines of a data bock of the memory device during the program verify recovery phase of the program operation, wherein each of the first plurality of word lines is coupled to a corresponding memory cell of a first plurality of memory cells in a string of memory cells in the data block, the first plurality of word lines comprising a selected word line associated with the program operation and one or more data word lines adjacent to the selected word line. | 2022-06-16 |
20220189566 | ARCHITECTURE AND METHOD FOR NAND MEMORY OPERATION - In a method for reading a memory device including a first memory cell string, in a pre-verify stage, a first verify voltage is applied on a gate terminal of a selected memory cell of the first memory cell string, where the selected memory cell is programmed and arranged between a first adjacent memory cell and a second adjacent memory cell. A first bias voltage is applied on a gate terminal of at least one memory cell of the first memory cell string that is not programmed. In a verify stage, a second verify voltage is applied on the gate terminal of the selected memory cell of the first memory cell string. A second bias voltage is applied on the gate terminal of the at least one memory cell of the first memory cell string that is not programmed, where the second bias voltage is smaller than the first bias voltage. | 2022-06-16 |
20220189567 | MEMORY DEVICE AND METHOD OF OPERATING THE SAME - The memory device may include a plurality of memory cells, a peripheral circuit, and a control logic. The peripheral circuit may perform a program operation on the plurality of memory cells and may perform program verify operations each including at least one verify loop corresponding to a plurality of program states programmed in the program operation. The control logic may control the peripheral circuit to perform a verify pulse apply operation and an additional verify pulse apply operation when a target verify loop count exceeds a reference count corresponding to the target program state, and may determine a failure of the program verify operation corresponding to the target program state based on results of the verify pulse apply operation and the additional verify pulse apply operation. A verify voltage of the additional verify pulse apply operation is higher than a verify voltage of the verify pulse apply operation. | 2022-06-16 |
20220189568 | MEMORY DEVICE AND METHOD OF OPERATING THE MEMORY DEVICE - The present technology relates to an electronic device. A memory device that controls a voltage applied to each line to prevent or mitigate a channel negative boosting phenomenon during a sensing operation includes a memory block connected to a plurality of lines, a peripheral circuit configured to perform a sensing operation on selected memory cells connected to a selected word line among the plurality of lines, and control logic configured to control voltages applied to drain select lines, source select lines, and word lines between the drain select lines and the source select lines among the plurality of lines, during the sensing operation and an equalizing operation performed after the sensing operation. The control logic controls a voltage applied to an unselected drain select line according to whether a cell string is shared with a selected drain select line among the drain select lines, during the sensing operation. | 2022-06-16 |
20220189569 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device according to an embodiment includes memory cell transistors, a word line, and a controller. A memory cell transistor whose threshold voltage is included in first and second states store first and second data, respectively. In a verify operation of the first data, during application of a verify high voltage of the first data to the word line, the controller is configured to determine whether or not a threshold voltage of a memory cell transistor to which the first data is to be written exceeds the verify high voltage of the first data, and also determine whether or not a threshold voltage of a memory cell transistor to which the second data is to be written exceeds a verify low voltage of the second data. | 2022-06-16 |
20220189570 | DISTRIBUTED COMPACTION OF LOGICAL STATES TO REDUCE PROGRAM TIME - A memory device includes a memory array of memory cells and control logic, operatively coupled with the memory array. The control logic is to perform operations, which include causing the memory cells to be programmed with an initial voltage distribution representing multiple logical states; causing the memory cells to be programmed with a subsequent voltage distribution representing a subset of the multiple logical states at a higher voltage than that of the initial voltage distribution, wherein the subset of the multiple logical states is compacted above a program verify voltage level for the subsequent voltage distribution; and causing a first program verify operation of the subsequent voltage distribution to be performed on the memory cells to verify one or more voltage levels of the subsequent voltage distribution. | 2022-06-16 |
20220189571 | TRIMS CORRESPONDING TO PROGRAM/ERASE CYCLES - Instructions can be executed to adjust a trim at first intervals until a quantity of program/erase cycles (PEC) have occurred. The trim defines a valley width between data states. Instructions can be executed to adjust the trim at second intervals, greater than the first intervals, after the quantity of PEC have occurred. | 2022-06-16 |
20220189572 | DATA INTEGRITY CHECKS BASED ON VOLTAGE DISTRIBUTION METRICS - Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations including determining a value of a data state metric of a memory page; responsive to the data state metric satisfying a first threshold criterion, determining a value of a voltage distribution metric associated with the page; and responsive to the voltage distribution metric value satisfying a second threshold criterion, performing a media management operation with respect to a block associated with the page. | 2022-06-16 |
20220189573 | MEMORY SYSTEM INCLUDING MEMORY DEVICE PERFORMING TARGET REFRESH - A memory controller includes: a test module for generating a test command, a test address, and test data during a test operation; a refresh control module for receiving the test command and the test address as an active command and an active address, and generating a first target address by sampling the active address according to the active command, during the test operation; a command/address generation module for providing the active address together with the active command, and providing the first target refresh command together with the first target address to a memory device, while determining whether to repair the active address according to a repair control signal; and a repair analysis module for generating the repair control signal based on a comparison result of the test data and read data from the memory device, during the test operation. | 2022-06-16 |
20220189574 | MEMORY DEVICE PROTECTION USING INTERLEAVED MULTIBIT SYMBOLS - Symbols interleaved among a set of codewords can provide an error correction/detection capability to a dual in-line memory module (DIMM) with memory chips having a comparatively larger bus width. Data corresponding to a set of multibit symbols and received from one or more memory devices can be interleaved/distributed with other bits of at least one codeword. | 2022-06-16 |
20220189575 | MEMORY CONTROLLER, MEMORY DEVICE, AND STORAGE DEVICE - A memory device may determine cell count information from a threshold voltage distribution of memory cells and may determine a detection case based on cell count information when correction of an error in read data, received from the memory device performing a read operation, fails. The memory controller may control the memory device to perform a read operation using a development time determined in consideration of an offset voltage of a read voltage corresponding to the detection case. When correction of the error in the read data fails again, the memory controller may control the memory device to perform a read operation using a corrected read voltage generated using a dynamic offset voltage obtained by inputting the cell count information to a machine learning model. | 2022-06-16 |
20220189576 | MISSION MODE VMIN PREDICTION AND CALIBRATION - The low end operating voltage of an integrated circuit is adjusted. Oscillations are counted at a ring oscillator on the integrated circuit over a designated period of clock cycles. Based on the number of oscillations, a prediction model associated with a first set of device degradation data and a second set of static random-access memory (SRAM) low end operating voltage data is used to select a low end operating voltage limit for a processor on the integrated circuit. The low end operating voltage of the processor is set based on the selected low end operating voltage limit. These steps are repeated multiple times during operation of the processor. A method of testing integrated circuits to provide the data employed to produce the prediction model is also provided. | 2022-06-16 |
20220189577 | GENOTYPE ANALYSIS DEVICE AND METHOD - A genotype analysis device includes an electrophoresis device and a data analysis device. A mobility model management unit including an environment information receiving unit, a prediction model storage unit, and a mobility prediction unit is provided in an STR analysis unit of the data analysis device. The mobility prediction unit generates a prediction model for predicting a correction amount of a standard base length of an allele, based upon an environmental condition at the time of electrophoresis received by the environmental information receiving unit and an electrophoresis result of an allelic ladder. A base length of the allele is corrected from the environmental condition without using the allelic ladder by using the prediction model. | 2022-06-16 |
20220189578 | INTERPRETABLE MOLECULAR GENERATIVE MODELS - An approach to training a molecule generative model with interpretable a latent space to identify substructures for a generated molecule generative from the latent space generated from an input molecule with a target property may be provided. A molecule generative model may be trained with a dataset of molecular structures with associated properties and known substructures. The model may generate a latent space in which a substructure predictor model may further be trained to predict the number of substructures of a molecule with target properties from an input molecule with the target properties and identified substructures. | 2022-06-16 |
20220189579 | PROTEIN COMPLEX STRUCTURE PREDICTION FROM CRYO-ELECTRON MICROSCOPY (CRYO-EM) DENSITY MAPS - In some embodiments, a method of determining a molecular structure of a protein is provided. A computing system receives voxel data representing electron density obtained via cryo-electron microscopy. The computing system uses one or more neural networks to predict one or more likelihoods for each voxel. The computing system determines a backbone structure based on the predicted likelihoods. The computing system maps amino acid sequences to the backbone structure based on the predicted likelihoods. Mapping the amino acid sequences to the backbone structure based on the predicted likelihoods includes conducting an alignment technique that uses a reward function and a gap penalty. The computing system determines locations of carbon, nitrogen, and oxygen atoms within the backbone structure based on the predicted likelihoods. The computing system determines side-chain atoms based on the predicted backbone structure and the amino acid sequences to complete the molecular structure. | 2022-06-16 |
20220189580 | TRAIT PREDICTION MODEL GENERATION APPARATUS, TRAIT PREDICTION APPARATUS, AND METHOD FOR GENERATING A TRAIT PREDICTION MODEL - According to one embodiment, a trait prediction model generation apparatus generates a plurality of first trait prediction models for each of a plurality of populations, based on summary statistics and inter-polymorphism correlated information. The apparatus generates a second trait prediction model for a specific one of the populations based on regularized regression of the first trait prediction models of each of the populations using a plurality of data sets including single-nucleotide polymorphism data and a trait value. | 2022-06-16 |
20220189581 | METHOD AND APPARATUS FOR CLASSIFICATION AND/OR PRIORITIZATION OF GENETIC VARIANTS - A method of classifying a genetic variant comprising receiving, at a first plurality of trained nodes of a hierarchical Bayesian Network, input data comprising data of a genetic variant of a patient, receiving, at a second plurality of trained nodes of the hierarchical Bayesian Network, input data comprising said data, receiving, at one or more trained nodes of the hierarchical Bayesian Network input from the first plurality of trained nodes and from the second plurality of trained nodes, providing by the one or more nodes a posterior probability of a functional disruption the genetic variant causes and classifying the genetic variant using said posterior probability of the functional disruption caused by the genetic variant. The first plurality of nodes within the plurality of trained nodes are configured to represent a constraint of a genetic region to variation and the second plurality of nodes within the plurality trained nodes are configured to represent molecular consequences of a genetic variant. | 2022-06-16 |
20220189582 | ANTIBODY LIBRARY CONSTRUCTION METHOD AND DEVICE BASED ON DEEP LEARNING - An antibody library construction method based on deep learning, comprising the steps of: obtaining a corresponding relation among antigen epitopes, antigen recognition regions and coding genes, and constructing a first database matching with the antigen epitopes, the antigen recognition regions and the coding genes; processing the antigen epitopes; carrying out clustering and characteristic extraction on the first database; and taking the multi-dimensional vector as the input of a temporal convolutional neural network, and stopping training until the error is lower than the threshold and tends to be stable to obtain the trained neural network model; and screening out antibody sequences having different activities, stability and specificity to the antigens in the coding gene sequence set X according to molecular docking, molecular dynamics and an existing gene sequence database Y so as to establish a secondary antibody library. | 2022-06-16 |
20220189583 | METHODS AND SYSTEMS FOR MICROSATELLITE ANALYSIS - The present disclosure provides methods and systems for classifying microsatellite and minor alleles in a sample. Also, the present disclosure provides methods and systems for generating classifiers for conditions based on microsatellite loci and for performing pan-cancer assays. The methods and systems can involve next-generation sequencing of nucleic acid samples from subjects and genotyping microsatellite loci in the samples. | 2022-06-16 |
20220189584 | Microbiome Byproducts and Uses Thereof - A method for treating a microorganism-related condition in a patient may include detecting microorganisms in a set of samples collected from a population and comparing a relative abundance of and co-occurrence between different microbial taxa in the set of samples. The method further includes associating a change in the relative abundance of or the co-occurrence between the microbial taxa with samples from people, among the population, with the microorganism-related condition and samples from people, among the population, without the microorganism-related condition to determine a target taxa. A blend of bacteriophages is then identified, the blend being configured to remove the target taxa from a community of microorganisms A therapeutic composition comprising the blend is then administered to the patient with the microorganism-related condition. | 2022-06-16 |
20220189585 | MASSIVELY PARALLEL PROCESSING DATABASE FOR SEQUENCE AND GRAPH DATA STRUCTURES APPLIED TO RAPID-RESPONSE DRUG REPURPOSING - Systems and methods disclosed herein may include a parallel-processing graph-database solution for protein-sequence analytics to determine a viable therapeutic for a given condition, and may include: determining a protein sequence for the given condition; using sequence database to compare a query sequence of the sequence of the given condition with sequences of other known proteins in the sequence database using the sequence database to determine a similarity of the query sequence with sequences of the other known proteins in the sequence database based on the comparison; and querying a graph database based on the similarity of sequences to identify potential therapeutics that could be have an inhibitory effect on the given condition. | 2022-06-16 |
20220189586 | MOLECULAR FORCE FIELD MULTI-OBJECTIVE FITTING ALGORITHM LIBRARY AND WORKFLOW - The present invention provides a molecular force field multi-objective fitting algorithm library and the workflow, including: FFOptlterator as the main module for input and output and force field parameter training iteration; EnergyCalculator module used for MM energy and energy derivatives calculation for the required value of each iteration in the optimization algorithm; the PropertyEstimator module used for the thermodynamic property calculation based on the MD simulation. Wherein, when initializing the FFOptlterator and EnergyCalculator objects, the user specifies the training force field parameters, adjustable parameter ranges, system setting arguments, and MD simulation parameters. The invention is suitable for the related applications of molecular force field training and verification, and implement the framework for different training targets, the prediction of different molecular physical properties, the compatibility and conversion of force field parameters in different formats, integration of multi-objective optimization, result analysis and graphing, etc. | 2022-06-16 |
20220189587 | GENERATION OF CODES FOR CHEMICAL STRUCTURES FROM NMR SPECTROSCOPY DATA - A method of generating codes for chemical structures from NMR spectroscopy data comprises receiving spectroscopic data of a chemical compound, inputting the spectroscopic data into a first artificial neural network to generate molecular descriptors, receiving a molecular descriptor from the first artificial neural network, inputting the molecular descriptor a second artificial neural network to convert structure data of the chemical reference compounds to molecular descriptors and to convert the molecular descriptors back to the structure data, and receiving structure data of the chemical compound from the second artificial neural network. | 2022-06-16 |
20220189588 | PTF-BASED METHOD FOR PREDICTING TARGET SOIL PROPERTY AND CONTENT - Provided is a pedo-transfer function (PTF)-based method for predicting a target soil property. Based on the collection of a multi-source soil dataset and environmental variables, a dataset containing all measured information is divided. Second-level regions are obtained by zoning according to the spatial variation in soil properties. An optimal independent variable set of PTFs in different regions is obtained by screening. Then, linear fitting and nonlinear fitting of the PTFs are performed for different zones separately. By comparing the accuracy of different functions between different zones, optimal PTFs oriented toward sampling sites are selected, so as to build a database including soil sampling sites. Further, regional independent variable layers are constructed by means of machine learning, to establish region-oriented PTFs; and a spatial distribution map of the target soil property and content for a target region is produced. | 2022-06-16 |
20220189589 | HIGHLY RELIABLE DATA TRANSACTION SYSTEM, AND HIGHLY RELIABLE DATA TRANSACTION METHOD - PROBLEM TO BE SOLVED: To provide a highly reliable data transaction systems with a distributed network, and a highly reliable data transaction method. | 2022-06-16 |
20220189590 | SYSTEM AND METHOD FOR DETERMINING TESTING AND TREATMENT - A system and method for determining a testing and treatment protocol for a predetermined medical condition are provided. The system comprises having a processor and a non-transitory computer readable medium, a medical evidence database written on and stored to the non-transitory computer readable medium, and a processor configured to execute the computer executable instructions embodied on the non-transitory computer readable medium, and thereby execute the present method of determining a testing and treatment protocol for a predetermined medical condition including: comparing a patient profile to a predetermined set of patient characteristics defined by a plurality of patient cohorts; matching the patient profile to a patient cohort; identifying markers for evaluation and testing based on the matched patient cohort; matching the identified markers to a plurality of test order sets; matching a treatment protocol to the patient profile based on a result returned by the test order set. | 2022-06-16 |
20220189591 | SYSTEMS AND METHODS FOR DETERMINING WHETHER AN INDIVIDUAL IS SICK BASED ON MACHINE LEARNING ALGORITHMS AND INDIVIDUALIZED DATA - In some instances, a user device for determining whether an individual is sick is provided. The user device is configured to obtain a facial image of an individual; obtain an audio file comprising a voice recording of the individual; determine a facial recognition confidence value associated with whether the individual is sick based on inputting the facial image into a facial recognition machine learning dataset that is individualized for the individual; determine a voice recognition confidence value associated with whether the individual is sick based on inputting the audio file into a voice recognition machine learning dataset that is individualized for the individual; determine whether the individual is sick based on the facial recognition confidence value and the voice recognition confidence value; and causing display of a prompt indicating whether the individual is sick. | 2022-06-16 |
20220189592 | AUTOMATED TRANSFORMATION DOCUMENTATION OF MEDICAL DATA - Systems, methods, and storage media useful in a healthcare cloud computing platform to transform, deduplicate and store medical data from third-party databases to a patient's primary medical record in the healthcare cloud computing platform. Exemplary implementations may: load and read data from third-party databases, and determine if it is duplicative of what is in the patient's primary record. Other embodiments, provide a method for ranking medical data from two different third-party databases to determine which medical data should be written to the patient's primary medical record in the healthcare computing platform. | 2022-06-16 |
20220189593 | SYSTEMS AND METHODS FOR ESTIMATING A NET HEALTH CARE DEMAND OF POTENTIAL PATIENTS IN ONE OR MORE GEOGRAPHIC AREAS - Systems and methods for estimating a net health visit demand of potential patients located in one or more geographic areas include one or more electronic databases that store electronic information associated with the potential patients, health care service providers, and general health visit recommendations for the potential patients. A computing device in communication with the database includes a control circuit configured to calculate an estimated total number of health care visits recommended for the potential patients located in a geographic area within a window of time, and to calculate an estimated total number of health care visits that the health care service providers located in the geographic area can accommodate within the window of time. Based on correlating these numbers, the control circuit generates an output indicating whether the health care visit capacity of health care service providers in the selected geographic area is suggested to be increased or reduced. | 2022-06-16 |
20220189594 | HEALTHCARE INFORMATION ANALYSIS AND GRAPHICAL DISPLAY PRESENTATION SYSTEM - Systems, methods, and computer-readable media for analyzing and presenting healthcare information are described. Some embodiments may include a system configured to receive healthcare information relating to a patient and to generate a patient profile. The patient profile may include a physiological status as well as a physiological assessment and a treatment assessment based on the automatic and dynamic analysis of the healthcare information. The healthcare information and the patient profile may be updated and/or accessed in real-time or substantially real-time through client logic devices in communication with the system. In this manner, a healthcare professional may enter healthcare information for a patient that is readily accessible by other healthcare professionals through the system. The system may present navigation objects that include a plurality of navigation layers selectively displayed based on user input. In addition, information objects may be displayed to users based on user navigation selections. | 2022-06-16 |
20220189595 | MEDICAL DATA AGGREGATION, TRANSFORMATION, AND PRESENTATION SYSTEM - Systems and methods for medical data aggregation, transformation, and presentation are provided. In one example, a method comprises sets of attributes and supplementary attributes are selectively presented as directly editable medical notes in an interface with enhanced functionality. | 2022-06-16 |
20220189596 | AUTOMATED TRANSFORMATION DOCUMENTATION OF MEDICAL DATA - Systems, methods, and storage media useful in a healthcare cloud computing platform to transform, deduplicate and store medical data from third-party databases to a patient's primary medical record in the healthcare cloud computing platform. Exemplary implementations may: load and read data from third-party databases, and determine if it is duplicative of what is in the patient's primary record. Other embodiments, provide a method for ranking medical data from two different third-party databases to determine which medical data should be written to the patient's primary medical record in the healthcare computing platform. | 2022-06-16 |
20220189597 | PERSONALIZED DIETARY SUPPLEMENT PROTOCOL AND DOSAGE FORMULATIONS - A personalized dynamic dietary supplement protocol can include: analyzing health information of a subject by processing user information through a nutritional model; identifying a health condition (improvement or homeostasis) based on the nutritional condition of the subject; generating a dietary supplement protocol for the subject; determining a dosing regimen; and providing dosage formulations to the subject in data form or as physical formulations for administration of the dosage formulations to the subject in accordance with the dosing regimen to perform the dietary supplement protocol. The dosage formulations each include a temporally-personalized dosage that is formulated with a combination of the plurality of dietary supplements to provide the subject with a personalized dietary supplement regimen that dynamically personalizes delivery of each dietary supplement in each temporally-personalized dosage in accordance with the dietary supplement protocol. | 2022-06-16 |
20220189598 | SYSTEM AND METHOD OF TUBERCULOSIS THERAPY - The present disclosure relates to methods, devices, and systems for treating a patient with tuberculosis. In an aspect of the present disclosure, a method includes receiving patient data corresponding to a TB patient. The patient data is associated with sputum time-to-positivity (TTP) data associated with a time period. The method further includes identifying, based on the patient data, a kill rate of semidormant/persistent (Y | 2022-06-16 |
20220189599 | SYSTEM AND METHOD FOR NATURAL LANGUAGE PROCESSING - A method includes receiving at least one data object and identifying, for a first aspect of the at least one data object, text strings of free form textual information having a first text string type. The method also includes generating updated free form textual information by removing the at least one text string having the first text string type. The method also includes generating one or more feature vectors based on the updated free form textual information using at least one of a unigram, a bigram, and a trigram. The method also includes using an artificial intelligence engine that uses at least one machine learning model configured to provide, using the one or more feature vectors, an output that includes at least one prediction indicating at least one resource domain and a weight value indicating a probability that the at least one resource domain corresponds to the free form textual information. | 2022-06-16 |
20220189600 | Unsupervised Learning And Prediction Of Lines Of Therapy From High-Dimensional Longitudinal Medications Data - In one aspect, the present disclosure provides a method for labeling one or more medications concurrently administered to a patient as a line of therapy. The method includes identifying medical records of the patient from a plurality of digital records, creating, from the subset of medical records, a plurality of treatment intervals including at least one medication administered to the patient and a time interval, associating medications of the one or more treatments with a respective treatment interval when the administration of the medication falls within the time interval, refining the time interval of a respective treatment interval when a treatment of the one or more treatments falls outside the time interval but within an extension period, identifying one or more potential lines of therapy from the plurality of treatment intervals, and labeling the potential line of therapy having the highest maximum likelihood estimation as the line of therapy. | 2022-06-16 |
20220189601 | MODULAR BLOOD GLUCOSE CONTROL SYSTEMS - Blood glucose control systems are disclosed. A blood glucose control system can receive a glucose level signal from a glucose sensor operatively coupled to a subject. The system can decode encoded data of the glucose level signal to obtain the glucose level of the subject and the indication of the glucose trend. The system can automatically calculate the dose control signal using a control algorithm configured to calculate regular correction boluses of glucose control agent in response to at least the glucose level of the subject. The system can select a dose control signal encoding profile from a plurality of dose control signal encoding profiles and, based on the dose control signal encoding profile, encode the dose control signal such that the pump controller can read the dose control signal. The system can transmit an encoded dose control signal to the pump controller. | 2022-06-16 |
20220189602 | AMBULATORY MEDICAMENT PUMP WITH SAFE ACCESS CONTROL - Systems and methods are disclosed herein for managing access to therapy controls of an ambulatory medicament pump that provides therapy to a subject using safe access levels associated with the therapy controls. The therapy change controls may enable modification of the corresponding therapy control parameters. The disclosed systems and methods can determine the eligibility of a subject receiving therapy from the ambulatory medicament pump or a user of the ambulatory medicament pump, for a safe access level and provide access to the corresponding therapy change controls. The ambulatory medicament pump may provide access to the therapy change controls upon receiving an access signal. In some cases, the ambulatory medicament pump may receive a time-based passcode and provide access to the therapy change controls upon receiving a matching passcode from the user. | 2022-06-16 |
20220189603 | MEDICAMENT PUMPS AND CONTROL SYSTEMS FOR MANAGING GLUCOSE CONTROL THERAPY DATA OF A SUBJECT - Glucose control systems are disclosed. An ambulatory medicament pump that is configured to wirelessly transmit one or more of a plurality of glucose control parameters and glucose control therapy data to a second ambulatory medicament pump is disclosed. A control system for transferring historical pump data from a first ambulatory medicament pump to a second ambulatory medicament pump is also disclosed. The control system can receive the historical pump data from a first ambulatory medicament pump, determine that at least one of a plurality of pairing conditions is satisfied to connect the data interface to the second ambulatory medicament pump, transmit, via the data interface, a pairing signal to the second ambulatory medicament pump, and transmit at least one of the therapy data associated with the delivery of the glucose control therapy or the glucose control parameter. | 2022-06-16 |
20220189604 | GLUCOSE LEVEL CONTROL SYSTEM WITH THERAPY CUSTOMIZATION - Systems and methods are disclosed herein for providing a configuration code for customizing a glucose level control system for at least an initial period. The configuration code can be based on one or more dosing parameters from a tracked medicament therapy administered to a subject over a tracking period by the glucose level control system. The configuration code includes encoded dosing parameters including a correction dosing parameter based on at least some of the correction boluses of medicament administered during the tracking period, a food intake dosing parameter comprising an indication of a food intake bolus size of medicament based on one or more food intake boluses provided during the tracking period, and a basal dosing parameter based on at least some of the basal doses of medicament administered during the tracking period. | 2022-06-16 |
20220189605 | INFUSION PUMP LINE CONFIRMATION - Methods, computer systems and computer readable media cause an infusion pump to provide a line check validation. A medical device that needs a line check validation is provided to a clinician via a graphical user interface. A selection of the medical device that needs the line check validation is received via the graphical user interface. The line check validation is automatically performed based on the selection. In aspects, the line check validation comprises establishing a first connection between a computing device associated with the graphical user interface and a second computing device associated with a patient. Further, the line check validation comprises establishing a second connection between the computing device and the medical device. As such, the medical device for the patient is automatically validated based on the first connection and the second connection. | 2022-06-16 |
20220189606 | INGESTIBLE EVENT MARKER DATA FRAMEWORK - The ingestible event marker data framework provides a uniform, comprehensive framework to enable various functions and utilities related to ingestible event marker data (IEM data). The functions and utilities include data and/or information having an aspect of data derived from, collected by, aggregated by, or otherwise associated with, an ingestion event. | 2022-06-16 |
20220189607 | METHODS AND APPARATUS FOR RECOMMENDING TAILORED WELLNESS ACTIVITIES BASED UPON NON-WELLNESS-RELATED DATA - Methods and apparatus for recommending tailored wellness activities based upon non-wellness-related data are disclosed. In an embodiment, a computer-implemented method for recommending wellness activities based upon non-wellness-related data includes accessing non-wellness-related data for a person from a datastore. The data is processed to determine a propensity score, the propensity score representing a likelihood that the person would perform a wellness activity. When the propensity score satisfies a condition, a wellness activity related to an aspect of the data is identified, and information regarding the wellness activity to the person is communicated via a network interface. | 2022-06-16 |
20220189608 | SELECTION OF A PREFERRED INTRAOCULAR LENS BASED ON RAY TRACING - A system and method for selecting a preferred intraocular lens, for implantation into an eye, includes a controller having a processor and a tangible, non-transitory memory on which instructions are recorded. The controller is in communication with a diagnostic module adapted to store pre-operative anatomic data of the eye as an eye model. The controller is configured to determine respective imputed post-operative variables for each of a plurality of intraocular lenses, via a projection module. A respective pseudophakic eye model is generated for each of the plurality of intraocular lenses by incorporating the respective imputed post-operative variables into the eye model. A ray tracing module is executed in the respective pseudophakic eye model to determine at least one respective metric for the plurality of intraocular lenses. The preferred intraocular lens is selected based on a comparison of the respective metric. | 2022-06-16 |