24th week of 2022 patent applcation highlights part 68 |
Patent application number | Title | Published |
20220189910 | METHOD FOR MANUFACTURING A STRUCTURE - A method for manufacturing a structure includes: supplying an active element provided with a front and rear face connected by a contour; assembling the front face and a main face of a support; filling a space of interconnections between the front face and the main face with glue. The method also includes, before the assembling, forming, by a method other than a plasma method, a first passivation layer covering the contour, and made from a first compound that makes it possible to limit the wetting of said contour by the glue regarding the front face and the main face. | 2022-06-16 |
20220189911 | AUTOMATED-POSITION-ALIGNING METHOD FOR TRANSFERRING CHIP AND SYSTEM USING THE METHOD - An automated-position-aligning method for transferring chips includes forming a chip-carrier base, applying a liquid, disposing a chip, transporting a carrier substrate and transferring the chip. A related system includes a carrier substrate, a liquid applying device, a chip disposing device, a carrier substrate transporting device and a chip transferring device. A carrier surface of the carrier substrate is crisscrossed by spacing grooves to form chip-carrier bases thereon. The carrier surface is hydrophilic, and the spacing grooves are hydrophobic. The liquid gathers on the chip-carrier bases. A plurality of chips are positioned and attached on the respective chip-carrier bases by surface free energy of the liquid. An electromagnetic wave radiates to the carrier substrate to heat and evaporate the liquid between each chip-carrier base and each chip such that the chips are released from the chip-carrier bases and fall to a receiving surface of a receiving substrate. | 2022-06-16 |
20220189912 | PROXIMITY SENSOR - A method of manufacturing a sensor device includes obtaining a semiconductor die structure comprising a transmitter and a receiver. Then, a first sacrificial stud is affixed to the transmitter and a second sacrificial stud is affixed to the receiver. The semiconductor die is affixed to a lead frame, and pads on the semiconductor die structure are wirebonded to the lead frame. The lead frame, the semiconductor die structure, and the wirebonds are encapsulated in a molding compound, while the tops of the first and second sacrificial studs are left exposed. The first and second sacrificial studs prevent the molding compound from encapsulating the transmitter and the receiver, and are removed to expose the transmitter in a first cavity and the receiver in a second cavity. In some examples, the semiconductor die structure includes a first semiconductor die comprising the transmitter and a second semiconductor die comprising the receiver. | 2022-06-16 |
20220189913 | TRANSISTORS, MEMORY CELLS, AND ARRANGEMENTS THEREOF - Disclosed herein are transistors, memory cells, and arrangements thereof. For example, in some embodiments, an integrated circuit (IC) structure may include a plurality of transistors, wherein the transistors are distributed in a hexagonally packed arrangement. In another example, in some embodiments, an IC structure may include a memory cell including an axially symmetric transistor coupled to an axially symmetric capacitor, wherein the axis of the transistor is aligned with the axis of the capacitor. | 2022-06-16 |
20220189914 | SEMICONDUCTOR PACKAGE INCLUDING STACKED SEMICONDUCTOR CHIPS - A semiconductor package including: a base layer; and a first chip stack and a second chip stack sequentially stacked over the base layer, each of the first and second chip stacks including first to fourth semiconductor chips which are offset stacked to expose chip pads at one side edge thereof, and the chip pads including stack identification pads for identifying the first chip stack and the second chip stack, and first and second chip identification pads for identifying the first to fourth semiconductor chips in each of the first and second chip stacks. | 2022-06-16 |
20220189915 | MEMORY CARD - A memory card includes an upper case, a lower case, and an integrated circuit package between the upper case and the lower case. The integrated circuit package includes a memory stacked chip on a panel substrate, and the memory stacked chip includes a base memory stacked chip and an additional memory stacked chip stacked on the base memory stacked chip. The integrated circuit package includes a frequency boosting interface chip on the panel substrate and electrically connected to the memory stacked chip, and a controller chip on the panel substrate and electrically connected to the memory stacked chip and the frequency boosting interface chip. | 2022-06-16 |
20220189916 | SEMICONDUCTOR PACKAGE - A semiconductor package comprising a package substrate that extends in a first direction and a second direction perpendicular to the first direction, a plurality of logic dies and a memory stack structure on the package substrate, and an interposer substrate mounted in the package substrate. The memory stack structure vertically overlaps the interposer substrate. Each of the logic dies includes a first part that is horizontally offset from the interposer substrate and a second part that vertically overlaps the interposer substrate. The interposer substrate includes an interlayer dielectric layer and a plurality of wiring lines in the interlayer dielectric layer. The memory stack structure is electrically connected to at least one of the logic dies through the wiring lines of the interposer substrate. | 2022-06-16 |
20220189917 | THROUGH-SILICON TRANSMISSION LINES AND OTHER STRUCTURES ENABLED BY SAME - One embodiment is a microelectronic assembly including an assembly support structure; a first die including a pair of hot via comprising through-substrate-via (TSVs) extending through the first die between first and second sides thereof and a plurality of ground vias surrounding the pair of hot vias and extending through the first die between the first and second sides thereof. The first die further includes a pair of signal interconnect structures electrically connected to the pair of hot vias disposed on the second side of the first die. The assembly further includes a second die between the assembly support structure and the first die the pair of signal interconnect structures disposed on the first side thereof. The first die is connected to the second die via a signal die-to-die (DTD) interconnect structure including the signal interconnect structures of the first and second dies. | 2022-06-16 |
20220189918 | PACKAGE STRUCTURE AND METHOD OF FABRICATING THE SAME - A structure including stacked substrates, a first semiconductor die, a second semiconductor die, and an insulating encapsulation is provided. The first semiconductor die is disposed over the stacked substrates. The second semiconductor die is stacked over the first semiconductor die. The insulating encapsulation includes a first encapsulation portion encapsulating the first semiconductor die and a second encapsulation portion encapsulating the second semiconductor die. | 2022-06-16 |
20220189919 | SEMICONDUCTOR PACKAGES INCLUDING PASSIVE DEVICES AND METHODS OF FORMING SAME - An embodiment is a structure including a first semiconductor device and a second semiconductor device, a first set of conductive connectors mechanically and electrically bonding the first semiconductor device and the second semiconductor device, a first underfill between the first and second semiconductor devices and surrounding the first set of conductive connectors, a first encapsulant on at least sidewalls of the first and second semiconductor devices and the first underfill, and a second set of conductive connectors electrically coupled to the first semiconductor device, the second set of conductive connectors being on an opposite side of the first semiconductor device as the first set of conductive connectors. | 2022-06-16 |
20220189920 | PACKAGE STRUCTURE - A package structure is provided. The package structure includes a first die and a second die, a dielectric layer, a bridge, an encapsulant, and a redistribution layer structure. The dielectric layer is disposed on the first die and the second die. The bridge is electrically connected to the first die and the second die, wherein the dielectric layer is spaced apart from the bridge. The encapsulant is disposed on the dielectric layer and laterally encapsulating the bridge. The redistribution layer structure is disposed over the encapsulant and the bridge. A top surface of the bridge is in contact with the RDL structure. | 2022-06-16 |
20220189921 | STACKED DIE CIRCUIT ROUTING SYSTEM AND METHOD - A stacked die system includes at least three dies. A first die has a same design as a second die. The first die includes a first circuit, and the second die includes a corresponding second circuit. A signal is received at the first die and sent to the third die via the second die. The signal is routed through either the first circuit or the second circuit but not both. Accordingly, an operation is performed on the signal prior to the signal reaching the third die but the operation is not performed by both the first circuit and the second circuit. | 2022-06-16 |
20220189922 | CREATE A PROTECTED LAYER FOR INTERCONNECTS AND DEVICES IN A PACKAGED QUANTUM STRUCTURE - A semiconductor device comprises a first chip layer, having a first chip layer front-side and a first chip layer back-side, a qubit chip layer, having a qubit chip layer front-side and a qubit chip layer back-side, the qubit chip layer front-side operatively coupled to the first chip layer front-side with a set of bump-bonds, a set of through-silicon vias (TSVs) connected to at least one of: the first chip layer back-side or the qubit chip layer back-side and a cap wafer metal bonded to at least one of: the qubit chip layer back-side or the first chip layer back-side. | 2022-06-16 |
20220189923 | CHIP PACKAGE STRUCTURE AND METHOD OF MANUFACTURING THE SAME - A chip package structure includes a wiring board, a first chip, a second chip, a thermally conductive material, a molding compound and a heat dissipation part. The wiring board includes a plurality of circuit pads. The first chip is mounted on the wiring board and is electrically connected to at least one of the circuit pads. The first chip is located between the second chip and the wiring board. The thermally conductive material is located on the wiring board and penetrates the second chip and the first chip to extend to the wiring board. The molding compound is disposed on the wiring board, and the heat dissipation part is disposed on the molding material and thermally coupled to the thermally conductive material. | 2022-06-16 |
20220189924 | SEMICONDUCTOR PACKAGE INCLUDING STACKED SEMICONDUCTOR CHIPS - A semiconductor package including: a base layer; a first chip stack and a second chip stack sequentially stacked over the base layer, each of the first and second chip stacks including a plurality of semiconductor chips which are offset stacked to expose chip pads at one side edge thereof, and the chip pads including stack identification pads for identifying the first chip stack and the second chip stack and chip identification pads for identifying the plurality of semiconductor chips in each of the first and second chip stacks; a first inter-chip wire and a second inter-chip wire connecting power-applied ones of the chip identification pads of the plurality of semiconductor chips of the first and second chip stacks; a first stack wire and second stack wire connecting the chip identification pad of a lowermost semiconductor chip of the first and second chip stacks to the base layer. | 2022-06-16 |
20220189925 | SEMICONDUCTOR DEVICE WITH SIDEWALL INTERCONNECTION STRUCTURE, METHOD OF MANUFACTURING THE SAME, AND ELECTRONIC APPARATUS - A semiconductor device, a method of manufacturing the semiconductor device, and an electronic apparatus including the semiconductor device are provided. The semiconductor device may include: a plurality of element stacks, wherein each element stack includes a plurality of stacked layers of semiconductor elements, each semiconductor element includes a gate electrode and source/drain regions on opposite sides of the gate electrode; and an interconnection structure between the plurality of element stacks. The interconnection structure includes an electrical isolation layer, and a conductive structure in the electrical isolation layer. At least one of the gate electrode and the source/drain regions of each of at least a part of the semiconductor elements is in contact with and therefore electrically connected to the conductive structure of the interconnection structure at a corresponding height in a lateral direction. | 2022-06-16 |
20220189926 | SEMICONDUCTOR DEVICE WITH SIDEWALL INTERCONNECTION STRUCTURE, METHOD OF MANUFACTURING THE SAME, AND ELECTRONIC APPARATUS - A method of manufacturing a semiconductor device includes: providing an element stack on a carrier substrate; forming an interconnection structure connecting the element stack laterally in an area on the carrier substrate adjacent to the element stack, wherein the interconnection structure includes an electrical isolation layer and a conductive structure in the electrical isolation layer; and controlling a height of the conductive structure in the interconnection structure, so that at least a part of components to be electrically connected in the element stack are in contact and therefore electrically connected to the conductive structure at the corresponding height. Forming the conductive structure includes: forming a conductive material layer in the area; forming a mask layer covering the conductive material layer; patterning the mask layer into a pattern corresponding to the conductive structure; and using the mask layer as an etching mask to selectively etch the conductive material layer. | 2022-06-16 |
20220189927 | DUAL-DIE SEMICONDUCTOR PACKAGE - The present application provides a semiconductor package and a manufacturing method thereof. The semiconductor package includes a package substrate, a bottom device die, an interposing package substrate and a top device die. The bottom device die is bonded to the package substrate. The interposing package substrate is located over the bottom device die and bonded to the package substrate. The top device die is bonded to the interposing package substrate form above the interposing package substrate. | 2022-06-16 |
20220189928 | Buffer Layer(s) on a Stacked Structure Having a Via - A structure includes first and second substrates, first and second stress buffer layers, and a post-passivation interconnect (PPI) structure. The first and second substrates include first and second semiconductor substrates and first and second interconnect structures on the first and second semiconductor substrates, respectively. The second interconnect structure is on a first side of the second semiconductor substrate. The first substrate is bonded to the second substrate at a bonding interface. A via extends at least through the second semiconductor substrate into the second interconnect structure. The first stress buffer layer is on a second side of the second semiconductor substrate opposite from the first side of the second semiconductor substrate. The PPI structure is on the first stress buffer layer and is electrically coupled to the via. The second stress buffer layer is on the PPI structure and the first stress buffer layer. | 2022-06-16 |
20220189929 | POWER MODULE PACKAGE - A power module package is provided. The power module package may include: a first substrate; a second substrate; a semiconductor chip disposed between the first substrate and the second substrate; and a mutual-connection layer that is formed between the semiconductor chip and the second substrate and provides conductive connection between the semiconductor chip and the second substrate. | 2022-06-16 |
20220189930 | MODULE - An electric circuit in which a first switching element and a first diode element are connected in antiparallel to form an upper arm and a second semiconductor element and a second diode element are connected in antiparallel to form a lower arm, and the upper arm and the lower arm are connected in series. A gate current path in one of the upper and lower arms and a reverse recovery path in the other one of the upper and lower arms are disposed close enough and extend at least partially in parallel to each other, so as to generate mutual inductance by the reverse recovery current flowing through the reverse recovery path and the gate current flowing through the gate current path. | 2022-06-16 |
20220189931 | DISPLAY TRANSFERRING STRUCTURE AND DISPLAY DEVICE INCLUDING THE SAME - A display transferring structure includes a transfer substrate including a plurality of recesses, each of the plurality of recesses including a first trap having a space in which a predetermined object can be moved and a second trap connected to the first trap and having a shape and size in which the object can be seated; and a micro-semiconductor chip positioned in the second trap. The micro-semiconductor chip may be self-aligned in a correct position by the display transferring structure. | 2022-06-16 |
20220189932 | Light Emitting Display with Improved Wide Angle Color Viewing - Disclosed are embodiments of apparatus and methods that provide light emitting displays with improved wide angle color viewing. A plurality of light emitting elements is arranged in a predetermined pattern and collectively creates a viewing plane. A portion of the light emitting elements are disposed in a primary orientation while the remainder of the light emitting element are disposed in a complementary orientation. Each light emitting element in a primary orientation is adjacent to a light emitting element in the complementary orientation. The spatial light emission pattern of the primary orientation is complementary to the spatial light emission pattern of the complementary orientation. Adjacent pairs of primary-complementary oriented light emitting elements cancel a substantial amount of color variation that would otherwise be seen when one varies the gaze angle upon the viewing plane. | 2022-06-16 |
20220189933 | DISPLAY FORMED BY CURING OF COLOR CONVERSION LAYER IN RECESS - A multi-color display includes a backplane having backplane circuitry, an array of micro-LEDs electrically integrated with backplane circuitry of the backplane, a cover layer spanning the LEDs and having a plurality of recesses, and first and second color conversion layers. Each recess of the plurality of recesses positioned over a corresponding micro-LED from the plurality of micro-LEDs, the first color conversion layer is in each recess over a first plurality of LEDs to convert the illumination from the first plurality of LEDs to light of a first color, and the second color conversion layer is in each recess over a second plurality of LEDs to convert the illumination from the second plurality of LEDs to light of a different second color. | 2022-06-16 |
20220189934 | Backside Interconnection Interface Die For Integrated Circuits Package - The technology relates to an integrated circuit (IC) package in which an interconnection interface chiplet and/or interconnection interface circuit are relocated, partitioned, and/or decoupled from a main or core IC die and/or high-bandwidth memory (HBM) components in an integrated component package. | 2022-06-16 |
20220189935 | DISPLAY DEVICE - A display device includes a first display panel, a second display panel, and an optical member. The first display panel includes a first substrate and a first cover member on the first substrate. The second display panel is coupled to a first side of the first display panel, and includes a second substrate and a second cover member on the second substrate. The optical member is in a groove defined by the first and second cover members at a boundary of the first and second display panels. | 2022-06-16 |
20220189936 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR MODULE - A semiconductor device includes first member that includes a switch made of a semiconductor element made from an elemental semiconductor. The first member is joined to a second member including a radio-frequency circuit including a semiconductor element made from a compound semiconductor. The switch and the radio-frequency circuit are connected by a path. The path includes an inter-member connection wire made of a metal pattern arranged on an interlayer insulating film extending from a surface of the second member to a surface of the first member or a conductive member allowing a current to flow in a direction crossing an interface where the first member and the second member are joined. | 2022-06-16 |
20220189937 | DISPLAY PANEL AND DISPLAY DEVICE - Provided are a display panel and a display device. The display panel includes a first display region, a second display region and a non-display region between the first display region and the second display region. The display panel further includes a third display region. The third display region and the non-display region at least partially overlap in the light emission direction of the display panel. In the preceding solution, the third display region is added in the display panel, and the third display region and the non-display region between the first display region and the second display region at least partially overlap in the light emission direction of the display panel, that is, the third display region covers at least part of the joint between the first display region and the second display region. | 2022-06-16 |
20220189938 | OPTICAL ENCLOSURES FOR LED MODULES - Various embodiments include combined lens and safety enclosure apparatuses and methods for forming the apparatuses. In one example a combined lens and safety enclosure apparatus for a light-emitting diode (LED) module is disclosed. The enclosure apparatus includes at least one plastic-material-based optical-lens element mounted over a plurality of LED elements, where a distance between the optical-lens element and any portion of any one of the plurality of LED elements is spaced away from each other by at least 0.8 mm. A driver-on-board (DoB) subsystem, including an electronic circuit configured to provide power to the plurality of LED elements, has a plastic-material-based optical enclosure mounted over the DoB subsystem. A distance between the optical enclosure and any portion of any of the electronic circuit is spaced away from optical enclosure by at least 0.8 mm. Other devices and methods are described. | 2022-06-16 |
20220189939 | DISPLAY DEVICE - A display device includes electrodes disposed on a substrate, extended in a first direction, and spaced apart from one another in a second direction intersecting the first direction, and light-emitting elements having ends disposed on the electrodes, wherein the electrodes include a first electrode having a first portion and a second portion, and a floating electrode adjacent to the first portion of the first electrode, and a width of the second portion is greater than a width of the first portion in the second direction. | 2022-06-16 |
20220189940 | SEMICONDUCTOR DEVICES - A semiconductor device includes a first substrate structure including a first substrate, gate electrodes stacked on the first substrate, and extended by different lengths to provide contact regions, cell contact plugs connected to the gate electrodes in the contact regions, and first bonding pads disposed on the cell contact plugs to be electrically connected to the cell contact plugs, respectively, and a second substrate structure, connected to the first substrate structure on the first substrate structure, and including a second substrate, circuit elements disposed on the second substrate, and a second bonding pad bonded to the first bonding pads, wherein, the contact regions include first regions having a first width and second regions, of which at least a portion overlaps the first bonding pads, and which have a second width greater than the first width, and the second width is greater than a width of the at least one first bonding pad. | 2022-06-16 |
20220189941 | STACKED DEVICES AND METHODS OF FABRICATION - Stacked devices and methods of fabrication are provided. Die-to-wafer (D2W) direct-bonding techniques join layers of dies of various physical sizes, form factors, and foundry nodes to a semiconductor wafer, to interposers, or to boards and panels, allowing mixing and matching of variegated dies in the fabrication of 3D stacked devices during wafer level packaging (WLP). Molding material fills in lateral spaces between dies to enable fan-out versions of 3D die stacks with fine pitch leads and capability of vertical through-vias throughout. Molding material is planarized to create direct-bonding surfaces between multiple layers of the variegated dies for high interconnect density and reduction of vertical height. Interposers with variegated dies on one or both sides can be created and bonded to wafers. Logic dies and image sensors from different fabrication nodes and different wafer sizes can be stacked during WLP, or logic dies and high bandwidth memory (HBM) of different geometries can be stacked during WLP. | 2022-06-16 |
20220189942 | Semiconductor Device Packages, Packaging Methods, and Packaged Semiconductor Devices - Semiconductor device packages, packaging methods, and packaged semiconductor devices are disclosed. In some embodiments, a package for a semiconductor device includes an integrated circuit die mounting region and a molding material disposed around the integrated circuit die mounting region. An interconnect structure is disposed over the molding material and the integrated circuit die mounting region. A protection pattern is disposed in a perimeter region of the package. The protection pattern includes a conductive feature. | 2022-06-16 |
20220189943 | LAYOUT FOR MEASURING OVERLAPPING STATE - A layout for measuring an overlapping state includes a layout region, a first dummy active area region, and dummy component regions. The first dummy active area region is located in the layout region. The dummy component regions are stacked in the layout region. At the moment when one of the dummy component regions is formed on the first dummy active area region, the one of the dummy component regions and the first dummy active area region have a first overlapping region, and the first overlapping region does not include other dummy component regions among the dummy component regions. | 2022-06-16 |
20220189944 | SEMICONDUCTOR DEVICES HAVING IMPROVED LAYOUT DESIGNS, AND METHODS OF DESIGNING AND FABRICATING THE SAME - A semiconductor device includes a first logic gate defined within a first unit cell footprint on a semiconductor substrate. The first logic gate includes a first field effect transistor including a first gate electrode and a first source/drain region, and a second field effect transistor including a second gate electrode and a second source/drain region. A first wiring pattern is provided, which extends in a first direction across a portion of the first unit cell footprint. The first wiring pattern is electrically connected to at least one of the first gate electrode and the second source/drain region, and has: (i) a first terminal end within a perimeter of the first unit cell footprint, and (ii) a second terminal end, which extends outside the perimeter of the first unit cell footprint but is not electrically connected to any current carrying region of any semiconductor device that is located outside the perimeter of the first unit cell footprint. | 2022-06-16 |
20220189945 | INTEGRATED CIRCUIT INCLUDING CONNECTION LINE - An integrated circuit includes: a first cell arranged in a first row extending in a first direction and performing a first function, a second cell arranged in the first row and performing a second function, a third cell arranged in a second row extending in the first direction and performing the first function, a fourth cell arranged in the second row and performing the second function, a first connection line connecting a first via in the first cell to a second via in the second cell, and a second connection line connecting a third via in the third cell to a fourth via in the fourth cell, wherein a length of the first connection line is different from a length of the second connection line. | 2022-06-16 |
20220189946 | ESD PROTECTION CIRCUIT WITH ISOLATED SCR FOR NEGATIVE VOLTAGE OPERATION - A semiconductor controlled rectifier (FIG. | 2022-06-16 |
20220189947 | SEMICONDUCTOR DEVICE AND OPERATION CIRCUIT - A semiconductor device including a substrate, a seed layer, a buffer layer, a channel layer, a barrier layer, a gate structure, a first source/drain structure, a second source/drain structure, and a contact is provided. The seed layer is disposed on the substrate. The buffer layer is disposed on the seed layer. The channel layer is disposed on the buffer layer. The barrier layer is disposed on the channel layer. The gate structure is disposed on the barrier layer. The first and second source/drain structures are disposed on opposite sides of the gate structure. The contact contacts the first source/drain structure. The distance between the gate structure and the contact is between 0.5 micrometers and 30 micrometers. | 2022-06-16 |
20220189948 | ELECTROSTATIC DISCHARGE PROTECTION WIRING, MANUFACTURING METHOD THEREOF, AND DISPLAY PANEL - An electrostatic discharge protection wiring is provided, and the electrostatic discharge protection wiring includes a gate signal line, a driving circuit, a gate connection line, and a source/drain. By disposing the bent gate connection line at an end of the gate signal line, the electrostatic discharge passes through the bent gate connection line to lose a part of current, thus reducing an effect of the electrostatic discharge to prevent bright spots at edges of panels caused by the weak electrostatic discharge. | 2022-06-16 |
20220189949 | HIGH RELIABILITY POLYSILICON COMPONENTS - The present disclosure introduces, among other things, an electronic device, e.g. an integrated circuit (IC). The IC includes a semiconductor substrate comprising a first doped layer of a first conductivity type. A second doped layer of the first conductivity type is located within the first doped layer. The second doped layer has first and second layer portions with a greater dopant concentration than the first doped layer, with the first layer portion being spaced apart from the second layer portion laterally with respect to a surface of the substrate. The IC further includes a lightly doped portion of the first doped layer, the lightly doped portion being located between the first and second layer portions. A dielectric isolation structure is located between the first and second layer portions, and directly contacts the lightly doped portion. | 2022-06-16 |
20220189950 | SEMICONDUCTOR DEVICE AND ELECTRONIC DEVICE - A semiconductor device in which a circuit and a power storage element are efficiently placed is provided. The semiconductor device includes a first transistor, a second transistor, and an electric double-layer capacitor. The first transistor, the second transistor, and the electric double-layer capacitor are provided over one substrate. A band gap of a semiconductor constituting a channel region of the second transistor is wider than a band gap of a semiconductor constituting a channel region of the first transistor. The electric double-layer capacitor includes a solid electrolyte. | 2022-06-16 |
20220189951 | SEMICONDUCTOR DEVICE - There is provided a semiconductor device including: an emitter region of a first conductivity type, a contact region of a second conductivity type, provided on the front surface side of the semiconductor substrate; one or more first trench portions which are electrically connected to a gate electrode and are in contact with emitter regions; a second trench portion which is adjacent to one of the one or more first trench portions, is electrically connected to the gate electrode, is in contact with the contact region of the second conductivity type, and is not in contact with the emitter region; and a dummy trench portion which is adjacent to one of the one or more first trench portions and is electrically connected to an emitter electrode, in which the contact region in contact with the second trench portion is in contact with the emitter electrode. | 2022-06-16 |
20220189952 | DEVICES INCLUDING CONTROL LOGIC STRUCTURES, AND RELATED METHODS - A semiconductor device includes a stack structure comprising decks. Each deck of the stack structure comprises a memory element level comprising memory elements and control logic level in electrical communication with the memory element level, the control logic level comprising a first subdeck structure comprising a first number of transistors comprising a P-type channel region or an N-type channel region and a second subdeck structure comprising a second number of transistors comprising the other of the P-type channel region or the N-type channel region overlying the first subdeck structure. Related semiconductor devices and methods of forming the semiconductor devices are disclosed. | 2022-06-16 |
20220189953 | NITRIDE SEMICONDUCTOR DEVICE - The present invention provides a nitride semiconductor device, including an insulating substrate, a substrate over the first surface of the insulating substrate, a first lateral transistor over a first region of the substrate, wherein the first lateral transistor includes a first nitride semiconductor layer formed over the substrate, and a first gate electrode, a first source electrode and a first drain electrode formed over the first nitride semiconductor layer, and a second lateral transistor over a second region of the substrate, wherein the second lateral transistor includes a second nitride semiconductor layer formed over the substrate, and a second gate electrode, a second source electrode and a second drain electrode formed over the second nitride semiconductor layer, and a separation trench formed over a third region, wherein the third region is between the first region and the second region. | 2022-06-16 |
20220189954 | SEMICONDUCTOR DEVICE WITH DIFFUSION SUPPRESSION AND LDD IMPLANTS AND AN EMBEDDED NON-LDD SEMICONDUCTOR DEVICE - The present disclosure provides a method for forming a semiconductor device containing MOS transistors both with and without source/drain extension regions in a semiconductor substrate having a semiconductor material on either side of a gate structure including a gate electrode on a gate dielectric formed in a semiconductor material. In devices with source/drain extensions, a diffusion suppression species of one or more of indium, carbon and a halogen are used. The diffusion suppression implant can be selectively provided only to the semiconductor devices with drain extensions while devices without drain extensions remain diffusion suppression implant free. | 2022-06-16 |
20220189955 | SEMICONDUCTOR DEVICE WITH CONTROLLABLE CHANNEL LENGTH AND MANUFACTURING METHOD THEREOF - A semiconductor device includes a ring-shaped gate electrode having an opening area disposed on a substrate, a source region and a bulk tap region disposed in the opening area, a well region disposed to overlap the ring-shaped gate electrode, a drift region disposed to be in contact with the well region, a first insulating isolation region disposed, on the drift region, to partially overlap the gate electrode, a second insulating isolation region enclosing the bulk tap region, a drain region disposed to be spaced apart from the ring-shaped gate electrode, and a deep trench isolation region disposed adjacent to the drain region. | 2022-06-16 |
20220189956 | FinFET Devices with Dummy Fins Having Multiple Dielectric Layers - A semiconductor device includes a substrate; semiconductor fins over the substrate and oriented lengthwise along a first direction; first multi-dielectric-layer (MDL) fins and second MDL fins over the substrate and oriented lengthwise along the first direction, wherein the first and the second MDL fins are intermixed with the semiconductor fins, wherein each of the first MDL fins and the second MDL fins includes an outer dielectric layer and an inner dielectric layer, wherein the outer dielectric layer and the inner dielectric layer have different dielectric materials; and gate structures oriented lengthwise along a second direction generally perpendicular to the first direction, wherein the gate structures are spaced from each other along the first direction, and are separated by the first MDL fins along the second direction, wherein the gate structures engage the semiconductor fins and the second MDL fins. | 2022-06-16 |
20220189957 | TRANSISTORS, MEMORY CELLS, AND ARRANGEMENTS THEREOF - Disclosed herein are transistors, memory cells, and arrangements thereof. For example, in some embodiments, an integrated circuit (IC) structure may include a plurality of transistors, wherein the transistors are distributed in a hexagonally packed arrangement. In another example, in some embodiments, an IC structure may include a memory cell including an axially symmetric transistor coupled to an axially symmetric capacitor, wherein the axis of the transistor is aligned with the axis of the capacitor. | 2022-06-16 |
20220189958 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR DEVICE - Provided herein may be a semiconductor device. The semiconductor device may include a first stacked body including a first stacked insulating layer and a first stacked conductive layer that are alternately stacked; a capacitor plug passing through the second stacked body; and a capacitor multi-layered layer configured to enclose the capacitor plug. The capacitor plug may include metal. | 2022-06-16 |
20220189959 | METHOD FOR MANUFACTURING SEMICONDUCTOR DIE WITH DECOUPLING CAPACITOR - The present application provides a method for manufacturing a semiconductor die. The method includes forming dielectric layers on a substrate; forming decoupling capacitors in the dielectric layers; forming first and second bonding pads on the dielectric layers, wherein the first bonding pads are coupled to a power supply voltage, the second bonding pads are coupled to a reference voltage, a group of the decoupling capacitors are located under one of the first bonding pads, first terminals of the group of the decoupling capacitors are electrically connected to the one of the first bonding pads, second terminals of the group of the decoupling capacitors are routed to one of the second bonding pads; and forming bond metals on the first and second bonding pads, wherein the decoupling capacitors are overlapped with the first and second bonding pads, and laterally surround portions of the dielectric layers overlapped with the bond metals. | 2022-06-16 |
20220189960 | APPARATUSES AND METHODS FOR CONTROLLING STRUCTURE OF BOTTOM ELECTRODES AND PROVIDING A TOP-SUPPORT THEREOF - An apparatus includes: a substrate; a plurality of pillar-shaped bottom electrodes provided over the substrate; and an upper electrode covering side and top surfaces of the pillar-shaped bottom electrodes with an intervening capacitor insulating film therebetween; wherein the pillar-shaped bottom electrodes have at least an upper portion and a lower portion, and the diameter of the upper portion is smaller than the diameter of the lower portion. | 2022-06-16 |
20220189961 | DRAM WITH SELECTIVE EPITAXIAL CELL TRANSISTOR - A method for manufacturing a dynamic random access memory device includes providing a semiconductor substrate and forming a highly doped diffusion region in a surface of the semiconductor substrate. A wordline structure is then deposited on the surface of the semiconductor substrate, where the wordline structure includes an electrically conductive gate layer. An opening is further formed in the wordline structure, where the opening is located at a first end of and extending to the highly doped diffusion region. A semiconductor pillar is then formed in the opening by selective epitaxial growth. An end of the semiconductor pillar is then doped and the doped end is connected with a memory element. | 2022-06-16 |
20220189962 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor memory device comprises a substrate, first and second lower electrode groups on the substrate and including a plurality of first and second lower electrodes, respectively, and first and second support patterns on side walls of and connecting each of the first and second lower electrodes, respectively. The first lower electrodes include a first center lower electrode arranged within a hexagonal shape defined by first edge lower electrodes. The second lower electrodes include a second center lower electrode arranged within a hexagonal shape defined by second edge lower electrodes. The first center lower electrode is spaced apart from each of the first edge lower electrodes in different first to third directions. The first support pattern is immediately adjacent to the second support pattern. The first center lower electrode is spaced apart from the second center lower electrode in a fourth direction different from the first to third directions. | 2022-06-16 |
20220189963 | SEMICONDUCTOR DEVICES AND METHOD OF MANUFACTURING THE SAME - A semiconductor device may include active pattern, a silicon liner, an insulation layer, an isolation pattern and a transistor. The active pattern may protrude from a substrate. The silicon liner having a crystalline structure may be formed conformally on surfaces of the active pattern and the substrate. The insulation layer may be formed on the silicon liner. The isolation pattern may be formed on the insulation layer to fill a trench adjacent to the active pattern. The transistor may include a gate structure and impurity regions. The gate structure may be disposed on the silicon liner, and the impurity regions may be formed at the silicon liner and the active pattern adjacent to both sides of the gate structure. | 2022-06-16 |
20220189964 | MEMORY STRUCTURE - A memory structure includes: a substrate including a memory array region and a peripheral circuit region; a plurality of bit line structures disposed in the memory array region of the substrate; a dummy bit line structure disposed on the substrate, wherein the dummy bit line structure is disposed in the memory array region and immediately adjacent to the peripheral circuit region; a plurality of contacts disposed between the bit line structures and in the memory array region; a dielectric layer disposed on the substrate and in the peripheral circuit region; and a protective structure disposed in the memory array region and immediately adjacent to the peripheral circuit region, wherein the protective structure includes the dummy bit line structure and a top surface of the protective structure is higher than top surfaces of the bit line structures. | 2022-06-16 |
20220189965 | METHODS OF FORMING SELF-ALIGNED CONTACTS - Electronic devices and methods of forming electronic devices using a reduced number of hardmask materials and reusing lithography reticles are described. Patterned substrates are formed using a combination of etch selective hardmask materials and reusing reticles to provide a pattern of repeating trapezoidal and rhomboidal openings. | 2022-06-16 |
20220189966 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor memory device comprises a substrate which includes a cell region, and a peri region defined around the cell region, the cell region including an active region defined by an element separation film, a storage pad connected to the active region of the cell region, a peri gate structure placed on the substrate of the peri region, a peri contact plug placed on both sides of the peri gate structure and connected to the substrate, a first interlayer insulating film which is placed on the storage pad and the pen contact plug, and includes a nitride-based insulating material, and an information storage unit connected to the storage pad, wherein a thickness of the first interlayer insulating film on an upper surface of the storage pad is smaller than a thickness of the first interlayer insulating film on an upper surface of the peri contact plug. | 2022-06-16 |
20220189967 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device may have a substrate including an active region in a memory cell region and a logic active region in a peripheral region, an element isolation structure between the active region and the logic active region, an insulating layer pattern covering the active region, and a support insulating layer. The insulating layer pattern may include an extension portion that extends along the element isolation structure, may be spaced apart from the element isolation structure, and may overhang over the element isolation structure. The support insulating layer may fill a recess space defined between the extension portion and the element isolation structure. | 2022-06-16 |
20220189968 | SEMICONDUCTOR MEMORY DEVICES - A semiconductor memory device includes a substrate comprising a memory cell region and a dummy cell region surrounding the memory cell region, the memory cell region including a plurality of memory cells, a plurality of active regions in the memory cell region, each of the plurality of active regions extending in a long axis direction, the long axis direction being a diagonal direction with respect to a first horizontal direction and a second horizontal direction orthogonal to the first horizontal direction, each of the plurality of active regions having a first width in a short axis direction orthogonal to the long axis direction, and a plurality of dummy active regions in the dummy cell region, each extending in the long axis direction, each of the plurality of dummy active regions having a second width greater than the first width in the short axis direction. | 2022-06-16 |
20220189969 | SEMICONDUCTOR DEVICES - A semiconductor device includes first and second trenches in respective first and second regions in a substrate, a first isolation structure having a first inner wall oxide pattern, a first liner, and a first filling insulation pattern sequentially stacked I the first trench, a second isolation structure having a second inner wall oxide pattern, a second liner, and a second filling insulation pattern sequentially stacked I the second trench, a first gate structure having a first high-k dielectric pattern, a first P-type metal pattern, and a first N-type metal pattern sequentially stacked on the first region, and a second gate structure having a second high-k dielectric pattern and a second N-type metal pattern sequentially stacked on the second region, wherein the first and second liners protrude above upper surfaces of the first and second inner wall oxide patterns and the first and second filling insulation patterns, respectively. | 2022-06-16 |
20220189970 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor device includes a substrate having a first memory cell and a second memory cell, the first and second memory cells being adjacent to each other in a first direction, first to fourth memory fins adjacent to each other in the first direction in the first memory cell, the first to fourth memory fins protruding from the substrate, fifth to eighth memory fins adjacent to each other in the first direction in the second memory cell, the fifth to eighth memory fins protruding from the substrate, and a first shallow device isolation layer between the fourth memory fin and the fifth memory fin, a sidewall of the first shallow device isolation layer having an inflection point. | 2022-06-16 |
20220189971 | MEMORY DEVICE - A memory device includes a first isolation cell, a first memory array of a first memory segment, a second memory array of a second memory segment, a first decoder cell of the first memory segment and a second decoder cell of the second memory segment. The first isolation cell extends in a first direction. The first memory array of the first memory segment abuts a first boundary of the first isolation cell in a second direction different from the first direction. The second memory array of the second memory segment abuts a second boundary, opposite to the first boundary, of the first isolation cell in the second direction. The first decoder cell of the first memory segment and the second decoder cell of the second memory segment are arranged on opposite sides of the first isolation cell. | 2022-06-16 |
20220189972 | SEMICONDUCTOR DEVICE INCLUDING FERROELECTRIC LAYER AND METHOD OF MANUFACTURING THE SAME - A semiconductor device according to an embodiment includes a substrate, a bit line structure and a source line structure respectively extending in a direction perpendicular to a surface of the substrate, a semiconductor layer disposed between the bit line structure and the source line structure on a plane parallel to the surface of the substrate, a first ferroelectric layer disposed on a first surface of the semiconductor layer, and a first gate electrode layer disposed on the first ferroelectric layer. | 2022-06-16 |
20220189973 | ONE-TRANSISTOR (1T) ONE-TIME PROGRAMMABLE (OTP) ANTI-FUSE BITCELL WITH REDUCED THRESHOLD VOLTAGE - A one-transistor (1T) one-time programmable (OTP) anti-fuse bitcell is provided. The 1T OTP anti-fuse bitcell includes a gate, a diffusion region including at least two sub-regions, and a gate oxide region located between the gate and the diffusion region, the gate oxide region including a thin gate oxide region and a thick gate oxide region. | 2022-06-16 |
20220189974 | SEMICONDUCTOR DEVICES COMPRISING CARBON-DOPED SILICON NITRIDE AND RELATED METHODS - A semiconductor device structure that comprises tiers of alternating dielectric levels and conductive levels and a carbon-doped silicon nitride over the tiers of the staircase structure. The carbon-doped silicon nitride excludes silicon carbon nitride. A method of forming the semiconductor device structure comprises forming stairs in a staircase structure comprising alternating dielectric levels and conductive levels. A carbon-doped silicon nitride is formed over the stairs, an oxide material is formed over the carbon-doped silicon nitride, and openings are formed in the oxide material. The openings extend to the carbon-doped silicon nitride. The carbon-doped silicon nitride is removed to extend the openings into the conductive levels of the staircase structure. Additional methods are disclosed. | 2022-06-16 |
20220189975 | SEMICONDUCTOR STRUCTURE AND THE FORMING METHOD THEREOF - A semiconductor structure is provided. The semiconductor structure includes a substrate, a gate structure, and a first spacer. The gate structure includes a floating gate structure disposed on the substrate, an inter-gate dielectric layer disposed on the floating gate structure, and a control gate structure disposed on the inter-gate dielectric layer. The control gate structure includes an electrode layer disposed on the inter-gate dielectric layer, a contact layer disposed on the electrode layer, and a cap layer disposed on the contact layer. The first spacer is disposed on a sidewall of the control gate structure and covering the electrode, the contact layer and the cap layer. A bottom surface of the first spacer is positioned between a bottom surface and a top surface of the electrode layer. | 2022-06-16 |
20220189976 | 3D MEMORY DEVICE WITH TOP WORDLINE CONTACT LOCATED IN PROTECTED REGION DURING PLANARIZATION - Embodiments of the present disclosure are directed towards a memory device including a top wordline contact located in a region that is protected from erosion during a planarization process, e.g., chemical mechanical polish (CMP). In embodiments, a plurality of wordlines are formed in a stack of multiple layers and a plurality of wordline contacts are formed to intersect with the plurality of wordlines. In embodiments, the stack forms a staircase and each of the plurality of wordline contacts lands on a corresponding each of the wordlines proximate to an edge of the staircase such that a top wordline contact lands in a region on a top wordline previously covered by a sacrificial layer. In some embodiments, the region is proximate to a raised notch at an edge of the staircase. Other embodiments may be described and claimed. | 2022-06-16 |
20220189977 | SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD OF THE SEMICONDUCTOR MEMORY DEVICE - There are provided a semiconductor memory device and a manufacturing method of the same. The semiconductor memory device includes: a peripheral circuit structure with a page buffer group; a net-shaped first source pattern disposed on the peripheral circuit structure, the net-shaped first source pattern with a plurality of openings; a memory cell array disposed on the net-shaped first source pattern; a second source pattern disposed between the net-shaped first source pattern and the memory cell array; and a cell-array-side pad pattern, disposed between the net-shaped first source pattern and the second source pattern, extending toward the net-shaped first source pattern from the second source pattern, the cell-array-side pad pattern being bonded directly to the net-shaped first source pattern. | 2022-06-16 |
20220189978 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - There are provided a semiconductor memory device and a method of manufacturing a semiconductor memory device. The semiconductor memory device includes a conductive pattern, an etch stop layer on the conductive pattern, a conductive bonding pattern including a contact portion connected to the conductive pattern, and a pad portion extending from the contact portion, a first dielectric layer disposed on the etch stop layer and spaced apart from the conductive bonding pattern, and a second dielectric layer including a first portion surrounding a sidewall of the contact portion of the conductive bonding pattern between the pad portion of the conductive bonding pattern and the etch stop layer, and a second portion extending from the first portion to cover an upper surface of the first dielectric layer. | 2022-06-16 |
20220189979 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - According to one embodiment, a semiconductor device includes a first region including a memory cell and a second region including a peripheral circuit. The second region includes a diffusion region provided on a surface of the semiconductor layer, a gate insulating film provided on the diffusion region, a gate electrode provided on the gate insulating film, an insulator layer provided on the diffusion region and surrounding the gate electrode, and an element isolation that is embedded in the semiconductor layer and surrounds the diffusion region. The element isolation includes a first region that is recessed below the surface of the diffusion region and a second region that is between the diffusion region and the first region and includes a protrusion protruding to a level higher than the first region. | 2022-06-16 |
20220189980 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - A semiconductor device includes: conductive layers and interlayer insulating layers, which are alternately stacked; a select conductor spaced apart from the conductive layers; cell plugs penetrating the conductive layers, the interlayer insulating layers, and the select conductor; and an auxiliary conductor in contact with the select conductor. | 2022-06-16 |
20220189981 | THREE-DIMENSIONAL MEMORY DEVICE WITH PLURAL CHANNELS PER MEMORY OPENING AND METHODS OF MAKING THE SAME - A three-dimensional memory device includes an alternating stacks of insulating layers and electrically conductive layers. Memory opening fill structures located in memory openings include a memory film and plural vertical semiconductor channels. | 2022-06-16 |
20220189982 | MICROELECTRONIC DEVICES INCLUDING STAIR STEP STRUCTURES, AND RELATED MEMORY DEVICES, ELECTRONIC SYSTEMS, AND METHODS - A microelectronic device comprises a stack structure comprising a vertically alternating sequence of conductive structures and insulative structures arranged in tiers, the stack structure divided into block structures separated from one another by slot structures, a staircase structure within the stack structure having steps comprising horizontal edges of the tiers, conductive contact structures in contact with the steps of the staircase structure, support pillar structures extending through the stack structure, and additional slot structures extending partially through the stack structure within one of the block structures, one of the additional slot structures extending between horizontally neighboring support pillar structures and closer to one of the horizontally neighboring support pillar structures than to an additional one of the horizontally neighboring support pillar structures. Related microelectronic devices, memory devices, and electronic systems are also described. | 2022-06-16 |
20220189983 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device, and a method of manufacturing the semiconductor device, includes a first source layer, a second source layer, a first insulating passivation layer partially interposed between the first source layer and the second source layer, and a gate structure located on the second source layer. The semiconductor device also includes a source contact structure passing through the gate structure, the second source layer, and the first insulating passivation layer. The source contact structure is coupled to the first source layer. | 2022-06-16 |
20220189984 | THREE-DIMENSIONAL MEMORY DEVICE INCLUDING TRENCH-ISOLATED MEMORY PLANES AND METHOD OF MAKING THE SAME - A three-dimensional memory device includes a first three-dimensional memory plane including first alternating stacks of first insulating layers and first word lines, and first bit lines electrically connected first vertical semiconductor channels, and a second three-dimensional memory plane including second alternating stacks of second insulating layers and second word lines and second bit lines electrically connected to second vertical channels. An inter-array backside trench laterally extend between the first three-dimensional memory plane and the second three-dimensional memory plane, and filled with an inter-array backside insulating material portion that provides electrical isolation between the three-dimensional memory planes. | 2022-06-16 |
20220189985 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device includes a stacked body including stacked insulating layers and stacked conductive layers; a cell plug; a connection contact structure; and a source layer coupled to the cell plug. The cell plug includes upper and lower portions, the connection contact structure includes a first connection contact disposed at substantially the same level as the lower portion of the cell plug, and a second connection contact disposed at substantially the same level as the upper portion thereof, a level at which the first and second connection contacts contact each other is substantially the same as a level at which the upper and lower portions of the cell plug contact each other, and a level of an uppermost portion of the second connection contact is higher than a level of a bottom surface of the source layer, and is lower than a level of a top surface thereof. | 2022-06-16 |
20220189986 | THREE-DIMENSIONAL MEMORY DEVICE WITH PLURAL CHANNELS PER MEMORY OPENING AND METHODS OF MAKING THE SAME - A three-dimensional memory device includes an alternating stacks of insulating layers and electrically conductive layers. Memory opening fill structures located in memory openings include a memory film and plural vertical semiconductor channels. | 2022-06-16 |
20220189987 | VERTICAL CHANNEL WITH CONDUCTIVE STRUCTURES TO IMPROVE STRING CURRENT - A vertical channel of a three-dimensional (3D) NAND has a recessed and filled drain/source pocket region for each memory cell to reduce resistance in a region that traditionally has high resistance. The vertical channel conducts current whose resistivity is controlled through a series of memory cells. The vertical channel can have a polysilicon material to conduct current past the memory cell gates and drain/sources region between the memory elements. The recess can extend the polysilicon away from a center of the vertical channel and closer to the control gates. The recess includes a structure to reduce resistance in the drain/source region along the vertical channel between memory cell gates. | 2022-06-16 |
20220189988 | SEMICONDUCTOR DEVICES AND DATA STORAGE SYSTEMS INCLUDING THE SAME - A semiconductor device includes a substrate having a first region, a second region, and a third region with gate electrodes spaced apart from each other in the first region and the second region. The semiconductor device also includes interlayer insulating layers alternately stacked with the gate electrodes, channel structures passing through the gate electrodes in the first region, first dummy structures passing through the gate electrodes in the second region, the first dummy structures disposed adjacent to the first region, second dummy structures passing through the gate electrodes in the second region, the second dummy structures disposed adjacent to the third region, and having different shapes from the first dummy structures, and support structures passing through the gate electrodes in the third region. A size of each of the second dummy structures is larger than a size of each of the support structures. | 2022-06-16 |
20220189989 | SEMICONDUCTOR DEVICE - A semiconductor device includes a stacked film of electrode layers and insulating layers. A charge storage layer is in a hole in the stacked film on a first insulating film. A channel layer is on the charge storage layer via a second insulating film. An adsorption promoting layer is on surfaces of a third insulating layer covering the insulating layers and the first insulating film facing the electrode layers. The third insulating film includes a first metal element and a first element, and the adsorption promoting layer includes a second element and a third element. The difference in electronegativity between the second element and the third element is larger than a difference in electronegativity between the first metal element and the first element. | 2022-06-16 |
20220189990 | 3D MEMORY SEMICONDUCTOR DEVICES AND STRUCTURES WITH BIT-LINE PILLARS - A 3D memory device, the device comprising: a plurality of memory cells, wherein each memory cell of said plurality of memory cells comprises at least one memory transistor, wherein each of said at least one memory transistor comprises a source, a drain, and a channel; a plurality of bit-line pillars, wherein each bit-line pillar of said plurality of bit-line pillars is directly connected to a plurality of said source or said drain, wherein said bit-line pillars are vertically oriented, wherein said channel is horizontally oriented, wherein said plurality of memory cells comprise a partially or fully metalized source, and/or, a partially or fully metalized drain, and wherein said plurality of bit-line pillars comprise a thermally conductive path from said plurality of memory cells to an external surface of said device. | 2022-06-16 |
20220189991 | THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE - A semiconductor device is provided. The semiconductor device includes a stack structure that includes a plurality of dielectric layers spaced apart from each other on a substrate, a plurality of electrodes interposed between the plurality of dielectric layers, and a plurality of stopper layers interposed between the plurality of dielectric layers; and a vertical channel structure that penetrates the stack structure. Each of the plurality of electrodes and the plurality of stopper layers is disposed in a corresponding empty space interposed between the plurality of dielectric layers, the plurality of stopper layers includes a first stopper layer and a second stopper layer that is interposed between the first stopper layer and the substrate, and at least one of the plurality of electrodes is interposed between the first stopper layer and the second stopper layer. | 2022-06-16 |
20220189992 | THREE-DIMENSIONAL MEMORY DEVICES AND METHODS FOR FORMING THE SAME - Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes a substrate having a first side and a second side opposite to the first side. The 3D memory device also includes a memory stack including interleaved conductive layers and dielectric layers at the first side of the substrate. The 3D memory device also includes a plurality of channel structures each extending vertically through the memory stack. The 3D memory device also includes a slit structure extending vertically through the memory stack and extending laterally to separate the plurality of channel structures into a plurality of blocks. The 3D memory device further includes a first doped region in the substrate and in contact with the slit structure. The 3D memory device further includes an insulating structure extending vertically from the second side of the substrate to the first doped region. The 3D memory device further includes a plurality of second doped regions in the substrate and separated by the insulating structure. | 2022-06-16 |
20220189993 | MULTIBIT FERROELECTRIC MEMORY CELLS AND METHODS FOR FORMING THE SAME - A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers and memory stack structures vertically extending through the alternating stack. Each of the memory stack structures includes a vertical semiconductor channel and a vertical stack of ferroelectric memory elements surrounding the vertical semiconductor channel and located at levels of the electrically conductive layers. Each of the ferroelectric memory elements includes a respective vertical stack of a first ferroelectric material portion and a second ferroelectric material portion that differs from the first ferroelectric material portion by at least one of a material composition and a lateral thickness. | 2022-06-16 |
20220189994 | RF SUBSTRATE STRUCTURE AND METHOD OF PRODUCTION - Producing a semiconductor or piezoelectric on-insulator type substrate for RF applications which is provided with a porous layer under the BOX layer and under a layer of polycrystalline semiconductor material. | 2022-06-16 |
20220189995 | DISPLAY DEVICE - A display device includes a metal layer disposed on a substrate; a transistor disposed on the metal layer; and a light emitting element electrically connected to the transistor, wherein the transistor includes a semiconductor layer at least partially overlapping the metal layer, the semiconductor layer includes a first region, a second region, and a channel region disposed between the first region and the second region, and the metal layer overlaps the second region and the channel region and is spaced apart from the first region in a plan view. | 2022-06-16 |
20220189996 | Wiring Layer And Manufacturing Method Therefor - To provide a miniaturized semiconductor device with low power consumption. A method for manufacturing a wiring layer includes the following steps: forming a second insulator over a first insulator; forming a third insulator over the second insulator; forming an opening in the third insulator so that it reaches the second insulator; forming a first conductor over the third insulator and in the opening; forming a second conductor over the first conductor; and after forming the second conductor, performing polishing treatment to remove portions of the first and second conductors above a top surface of the third insulator. An end of the first conductor is at a level lower than or equal to the top level of the opening. The top surface of the second conductor is at a level lower than or equal to that of the end of the first conductor. | 2022-06-16 |
20220189997 | MULTI-FUNCTION SUBSTRATE - The present disclosure relates an integrated chip. The integrated chip includes a polysilicon layer arranged on an upper surface of a base substrate. A dielectric layer is arranged over the polysilicon layer, and an active semiconductor layer is arranged over the dielectric layer. A semiconductor material is arranged vertically on the upper surface of the base substrate and laterally beside the active semiconductor layer. | 2022-06-16 |
20220189998 | SEMICONDUCTOR DEVICE - Reduction in power consumption of a semiconductor device is achieved. The semiconductor device includes: a first circuit operating at a first power supply voltage and a second circuit operating at a second power supply voltage and including a level shift unit and a switch unit, the first circuit is configured of a low-breakdown-voltage n-type transistor that is an SOTB transistor, and the switch unit is configured of an n-type transistor that is an SOTB transistor. A second power supply voltage is higher than a first power supply voltage, and an impurity concentration of a channel formation region of the n-type transistor is higher than an impurity concentration of a channel formation region of the low-breakdown-voltage n-type transistor. | 2022-06-16 |
20220189999 | ACTIVE MATRIX SUBSTRATE - An active matrix substrate is provided with a plurality of oxide semiconductor TFTs including a plurality of first TFTs. An oxide semiconductor layer of each oxide semiconductor TFT includes a channel region, a source contact region, and a drain contact region. In a view from a normal direction of the substrate, the channel region is a region located between the source contact region and the drain contact region and overlapping a gate electrode, and the channel region includes a first end portion and a second end portion that oppose each other and extend in a first direction from the source contact region side toward the drain contact region side, a source side end portion that is located on the source contact region side of the first and second end portions and extends in a second direction that intersects the first direction, and a drain side end portion that is located on the drain contact region side of the first and second end portions and extends in the second direction. Each first TFT further includes a light blocking layer located between the oxide semiconductor layer and the substrate. In a view from the normal direction of the substrate, the light blocking layer includes an opening region that overlaps part of the channel region and a light blocking region that overlaps another part of the channel region. In a view from the normal direction of the substrate, the light blocking region includes a first light blocking portion that extends in the first direction over the first end portion of the channel region and a second light blocking portion that extends in the first direction over the second end portion of the channel region; each of the first light blocking portion and the second light blocking portion includes a first edge portion and a second edge portion that oppose each other and extend in the first direction; at least part of the first edge portion overlaps the channel region; and the second edge portion is located on an outer side of the channel region and does not overlap the channel region. | 2022-06-16 |
20220190000 | DISPLAY DEVICE - A display device, includes: a first gate electrode; a lower insulating film; a lower gate insulating film including a metal oxide film; and an oxide semiconductor layer, all of which are provided on a substrate in a stated order; and a first transistor provided on the substrate and including the oxide semiconductor layer, the first transistor including one or more first transistors, the first transistor including: a first channel region; a first conductor region holding the first channel region; and the first gate electrode across the lower gate insulating film from the first channel region, and between the lower insulating film and the first gate electrode, a clearance being provided, and the clearance being filled with the lower gate insulating film. | 2022-06-16 |
20220190001 | ARRAY SUBSTRATE AND DISPLAY PANEL - The present application discloses an array substrate and a display panel, the array substrate including a substrate, and a first gate layer and a second gate layer formed on the substrate; the first gate layer includes a first gate line connecting a plurality of first gates, at least two of the second gates of the second gate layer connected to a same one of the first gates; or the second gate layer including a second gate line connecting the plurality of second gates, at least two of the first gates of the first gate layer connected to a same one of the second gates. | 2022-06-16 |
20220190002 | DISPLAY DEVICE AND MANUFACTURING METHOD - A display device includes a substrate; a semiconductor layer; a gate insulating film; a gate electrode; a first interlayer insulating film; a capacitance electrode; and a second interlayer insulating film. Each of a pixel circuits includes a drive transistor, a capacitor and a connection wiring line. The capacitance electrode is provided with a first opening and a second opening in portions of positions overlapping with the gate electrode in plan view. The first interlayer insulating film and the second interlayer insulating film include a contact hole provided at a position surrounded by the first opening and a hole provided at a position surrounded by the second opening. The connection wiring line is provided on the second interlayer insulating film and is connected to the gate electrode via the contact hole. The hole overlaps with a portion of a channel region in plan view. | 2022-06-16 |
20220190003 | THIN FILM TRANSISTOR SUBSTRATE AND DISPLAY USING THE SAME - The present disclosure relates to a thin film transistor substrate having two different types of thin film transistors on the same substrate. A thin film transistor substrate includes a substrate; a first thin film transistor disposed on the substrate, the first thin film transistor including a poly crystalline semiconductor layer, a first gate electrode over the poly crystalline semiconductor layer, a first source electrode, and a first drain electrode; a second thin film transistor disposed on the substrate, the second thin film transistor including a second gate electrode, an oxide semiconductor layer over the second gate electrode, a second source electrode, and a second drain electrode; and an intermediate insulating layer including a nitride layer and an oxide layer on the nitride layer, the intermediate insulating layer disposed over the first gate electrode and the second gate electrode and under the oxide semiconductor layer. | 2022-06-16 |
20220190004 | Array Of Capacitors, An Array Of Memory Cells, Method Used In Forming An Array Of Memory Cells, Methods Used In Forming An Array Of Capacitors, And Methods Used In Forming A Plurality Of Horizontally-Spaced Conductive Lines - A method used in forming an array of memory cells comprises forming a vertical stack comprising transistor material directly above insulator material. A mask is used to subtractively etch both the transistor material and thereafter the insulator material to form a plurality of pillars that individually comprise the transistor material and the insulator material. The insulator material is laterally-recessed from opposing lateral sides of individual of the pillars selectively relative to the transistor material of the individual pillars. The individual pillars are formed to comprise a first capacitor electrode that is in void space formed from the laterally recessing. Capacitors are formed that individually comprise the first capacitor electrode of the individual pillars. A capacitor insulator is aside the first capacitor electrode of the individual pillars and a second capacitor electrode is laterally-outward of the capacitor insulator. Vertical transistors are formed above the capacitors and individually comprise the transistor material of the individual pillars. Other aspects, including structure independent of method, are disclosed. | 2022-06-16 |
20220190005 | IMAGE SENSOR INCLUDING SHARED PIXELS - An image sensor may include a first shared pixel region and a first isolation layer on a substrate, the first isolation layer defining the first shared pixel region. The first shared pixel region may include photo-sensing devices in sub-pixel regions and a first floating diffusion region connected to the photo-sensing devices. The sub-pixel regions may include a first sub-pixel region and a second sub-pixel region that constitute a first pixel group region. The sub-pixel regions may include a third sub-pixel region and a fourth sub-pixel region that constitute a second pixel group region. The first shared pixel region may include first and second well regions doped with first conductivity type impurities. The second well region may be spaced apart from the first well region. The first pixel group region may share a first well region. The second pixel group region may share the second well region. | 2022-06-16 |
20220190006 | IMAGE SENSOR - An image sensor includes a pixel separation structure disposed in a semiconductor substrate and defining a plurality of pixel regions, a first photoelectric conversion region and a second photoelectric conversion region disposed in the semiconductor substrate and in each of the plurality of pixel regions, and a plurality of micro-lenses disposed on the semiconductor substrate and corresponding to the plurality of pixel regions. The semiconductor substrate includes a plurality of curved surfaces that is convex toward the plurality of micro-lenses, and the semiconductor substrate has a minimum thickness between the first photoelectric conversion region and the second photoelectric conversion region in each of the plurality of pixel regions, and has a maximum thickness at a boundary between the plurality of pixel regions. | 2022-06-16 |
20220190007 | IMAGE SENSOR AND METHOD OF MANUFACTURING THE SAME - An image sensor includes a substrate having first and second surfaces, pixel regions arranged in a direction parallel to the first surface, first and second photodiodes isolated from each other in each of the pixel regions, a first device isolation film between the pixel regions, a pair of second device isolation films between the first and second photodiodes and extending from the first device isolation film, a doped layer adjacent to the pair of second device isolation films and extending from the second surface to a predetermined depth and spaced apart from the first surface, the doped layer being isolated from the first device isolation film, and a barrier area between the pair of second device isolation films and having a potential greater than a potential of a portion of the substrate adjacent to the barrier area. | 2022-06-16 |
20220190008 | IMAGE SENSING DEVICE - An image sensing device includes a plurality of unit pixels, wherein each of the unit pixels includes a photoelectric conversion region disposed in a substrate, and configured to generate photocharges in response to incident light, a control region disposed in the substrate and configured to receive a control signal and generate a current in the substrate based on the control signal to carry and move the photocharges generated in the photoelectric conversion region, a detection region disposed in the substrate and configured to receive the current and to capture the photocharges carried by the current and a guard ring region configured to surround the control region, and wherein the hole current flows between the control region and the guard ring region. | 2022-06-16 |
20220190009 | FLICKER-MITIGATING PIXEL-ARRAY SUBSTRATE - A flicker-mitigating pixel-array substrate includes a semiconductor substrate and a metal layer. The semiconductor substrate includes a small-photodiode region. A back surface of the semiconductor substrate forms a trench surrounding the small-photodiode region in a cross-sectional plane parallel to a first back-surface region of the back surface above the small-photodiode region. The metal layer covers the first back-surface region, at least partially fills the trench, and surrounds the small-photodiode region in the cross-sectional plane. A method for fabricating a flicker-mitigating pixel-array substrate includes forming, on a back surface of a semiconductor substrate, a trench that surrounds a small-photodiode region of the semiconductor substrate in a cross-sectional plane parallel to a first back-surface region of the back surface above the small-photodiode region. The method also includes forming a metal layer on the first back-surface region and in the trench. | 2022-06-16 |