25th week of 2013 patent applcation highlights part 19 |
Patent application number | Title | Published |
20130154064 | GLASS COMPOSITION FOR PROTECTING SEMICONDUCTOR JUNCTION, METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - A glass composition for protecting a semiconductor junction contains at least SiO | 2013-06-20 |
20130154065 | PROCESS FOR TREATING A SUBSTRATE USING A LUMINOUS FLUX OF DETERMINED WAFELENGTH, AND CORRESPONDING SUBSTRATE - A substrate is treated by means of at least one pulse of a luminous flux of determined wavelength. The substrate comprises an embedded layer that absorbs the luminous flux independently of the temperature. The embedded layer is interleaved between a first treatment layer, layer and a second treatment layer. The first treatment layer has a coefficient of absorption of luminous flux that is low at ambient temperature and grows as the temperature rises. The luminous flux may be applied in several places of the surface of the first layer to heat regions of the embedded layer and generate a propagating thermal front in the first layer opposite the heated regions of the embedded layer, which generate constraints within the second layer. | 2013-06-20 |
20130154066 | SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF - A semiconductor package is presented which has a suitable structure for effectively shielding electromagnetic wave interference (EMI) in a cavity area to which a semiconductor chip is attached. The semiconductor package is assembled such that a lower substrate to which the semiconductor chip is attached is adhered to an EMI shielding & electric I/O body having various types of EMI shielding & electric I/O metal patterns by soldering. Further, the EMI shielding & electric I/O body is adhered to an upper substrate by soldering thereby simplifying assembling of the semiconductor package. | 2013-06-20 |
20130154067 | Semiconductor Device and Method of Forming Vertically Offset Bond on Trace Interconnect Structure on Leadframe - A semiconductor device has a vertically offset BOT interconnect structure. The vertical offset is achieved with a leadframe having a plurality of lead fingers around a die paddle. A first conductive layer is formed over the lead fingers. A second conductive layer is formed over the lead fingers. Each second conductive layer is positioned adjacent to the first conductive layer and each first conductive layer is positioned adjacent to the second conductive layer. The second conductive layer has a height greater than a height of the first conductive layer. The first and second conductive layers can have a side-by-side arrangement or staggered arrangement. Bumps are formed over the first and second conductive layers. Bond wires are electrically connected to the bumps. A semiconductor die is mounted over the die paddle of the leadframe and electrically connected to the bond wires and BOT interconnect structure. | 2013-06-20 |
20130154068 | PACKAGED LEADLESS SEMICONDUCTOR DEVICE - A packaged leadless semiconductor device ( | 2013-06-20 |
20130154069 | SEMICONDUCTOR PACKAGE - Disclosed herein is a semiconductor package, including: a first heat dissipation substrate; a first lead frame that is formed on the first heat dissipation substrate by patterning; a first semiconductor device formed on the first lead frame; a second semiconductor device that is stacked on the first semiconductor device; a second lead frame that is patterned and bonded to the second semiconductor device; and a second heat dissipation substrate formed on the first lead frame. | 2013-06-20 |
20130154070 | SEMICONDUCTOR PACKAGE - Disclosed herein is a semiconductor package. The semiconductor package includes: semiconductor elements, a first heat dissipation substrate formed under the semiconductor elements, a first lead frame electrically connecting the lower portions of the semiconductor elements to an upper portion of the first heat dissipation substrate, a second heat dissipation substrate formed over the semiconductor elements, and a second lead frame having a protrusion formed to be protruded from a lower surface thereof and electrically connecting the upper portions of the semiconductor elements to a lower portion of the second heat dissipation substrate. | 2013-06-20 |
20130154071 | Isolation Barrier Device and Methods of Use - Systems and methods pertaining to a digital signal isolator device are described. In one embodiment, the device includes an isolation barrier and two metal support paddles. The isolation barrier contains an organic and/or a semi-organic insulating material with at least one capacitor embedded inside. One of the two metal support paddles is located below a first portion of a bottom surface of the isolation barrier to provide support to the isolation barrier, while the other metal support paddle is located below a second portion of a bottom surface of the isolation barrier to provide support to the isolation barrier. | 2013-06-20 |
20130154072 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH PAD AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: forming a peripheral lead having a peripheral lead bottom side, a peripheral lead top side, a peripheral lead non-horizontal side, and a peripheral lead horizontal ridge protruding from the peripheral lead non-horizontal side; forming a first top distribution layer on the peripheral lead top side; connecting an integrated circuit to the first top distribution layer; and applying an insulation layer directly on a distribution layer bottom extent of the first top distribution layer and a peripheral lead ridge lower side of the peripheral lead horizontal ridge with a cavity in the portion of the insulation layer directly below the integrated circuit. | 2013-06-20 |
20130154073 | METHOD OF FORMING A SEMICONDUCTOR DEVICE AND LEADFRAME THEREFOR - In one embodiment, a leadframe for a semiconductor package includes a source connection area for one transistor and a drain connection point for a second transistor, and a common connection for using a connection clip to couple a drain of the first transistor to a source of the second transistor and to the common connection. | 2013-06-20 |
20130154074 | SEMICONDUCTOR STACK PACKAGES AND METHODS OF FABRICATING THE SAME - Semiconductor chip stacks are provided. The semiconductor chip stack includes a semiconductor chip stack including a plurality of first semiconductor chips vertically stacked on a top surface of the interposer, a second semiconductor chip stacked on a bottom surface of the interposer opposite to the semiconductor chip stack, and an external electrode attached to a top surface of the second semiconductor chip opposite to the interposer. Electronic systems including the semiconductor chip stack and related methods are also provided. | 2013-06-20 |
20130154075 | SEMICONDUCTOR DEVICE - In a QFP with a chip-stacked structure in which a lower surface of a die pad is exposed from a lower surface of a sealing member, a semiconductor chip having a BCB film, which is made of a polymeric material containing at least benzocyclobutene in its backbone as an organic monomer and formed on its surface, is mounted at a position (second stage) that is away from the die pad. As a result, even when moisture invades through the interface between the die pad and the sealing member, it is possible to prolong the time required for the moisture to reach the semiconductor chip, and subsequently to make moisture absorption defect less likely to occur. | 2013-06-20 |
20130154076 | Semiconductor Device and Method of Forming Leadframe Interposer Over Semiconductor Die and TSV Substrate for Vertical Electrical Interconnect - A semiconductor device has a substrate with a plurality of conductive vias formed through the substrate and first conductive layer formed over the substrate. A first semiconductor die is mounted over the substrate. A second semiconductor die can be mounted over the first semiconductor die. A leadframe interposer has a base plate and a plurality of base leads extending from the base plate. An etch-resistant conductive layer is formed over a surface of the base plate opposite the base leads. The leadframe is mounted to the substrate over the first semiconductor die. An encapsulant is deposited over the substrate and first semiconductor die. The base plate is removed while retaining the etch-resistant conductive layer and portion of the base plate opposite the base leads to electrically isolate the base leads. An interconnect structure is formed over a surface of the substrate opposite the base leads. | 2013-06-20 |
20130154077 | CHIP PACKAGE AND METHOD FOR FORMING THE SAME - A chip package includes: a substrate having a first and a second surfaces; a device region formed in or disposed on the substrate; a dielectric layer disposed on the first surface; at least one conducting pad disposed in the dielectric layer and electrically connected to the device region; a planar layer disposed on the dielectric layer, wherein a vertical distance between upper surfaces of the planar layer and the conducting pad is larger than about 2 μm; a transparent substrate disposed on the first surface; a first spacer layer disposed between the transparent substrate and the planar layer; and a second spacer layer disposed between the transparent substrate and the substrate and extending into an opening of the dielectric layer to contact with the conducting pad, wherein there is substantially no gap between the second spacer layer and the conducting pad. | 2013-06-20 |
20130154078 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH HEAT SLUG AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: mounting an integrated circuit over a package carrier; mounting a conductive connector over the package carrier; forming an encapsulation over the integrated circuit, the encapsulation having a recess exposing the conductive connector; and mounting a heat slug over the encapsulation, the heat slug having an opening with an opening width greater than a recess width of the recess, the opening exposing a portion of a top surface of the encapsulation. | 2013-06-20 |
20130154079 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH SUBSTRATE MOLD GATE AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a substrate; forming a mold gate on an upper surface of the substrate; mounting an integrated circuit to the substrate; and forming an encapsulant encapsulating the integrated circuit, the encapsulant having disruption patterns emanating from the mold gate and underneath a bottom plane of the integrated circuit. | 2013-06-20 |
20130154080 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH LEADS AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: forming a lead; forming an interior conductive layer having an interior top side and an interior bottom side, the interior bottom side directly on the lead; mounting an integrated circuit over the lead, the integrated circuit having an inactive side and an active side; forming an encapsulation directly on the inactive side and the interior top side; and forming an insulation layer directly on the active side and a portion of the interior bottom side. | 2013-06-20 |
20130154081 | SEMICONDUCTOR MODULE - A semiconductor module which includes a semiconductor device; a wiring member that is connected to the semiconductor device; a cooling plate that includes a first surface on a side of the semiconductor device and a second surface on a side opposite to the first surface and has a fastening portion at an end thereof in a first direction; and a molded portion that is formed by molding a resin on the semiconductor device, the wiring member and the cooling plate, wherein the fastening portion is exposed out of the molded portion, and a terminal portion of the wiring member is exposed out of the molded portion such that the terminal portion of the wiring member extends in a second direction which is substantially perpendicular to the first direction. | 2013-06-20 |
20130154082 | SEMICONDUCTOR DEVICE, SEMICONDUCTOR DEVICE MANUFACTURING METHOD, AND ELECTRONIC DEVICE - A semiconductor device includes an insulation layer, a first semiconductor element and a second semiconductor element which are disposed within the insulation layer, a frame which has higher thermal conductivity than the insulation layer and surrounds the first semiconductor element and the second semiconductor element via the insulation layer, and a wiring layer which is disposed over the insulation layer and includes an electrode which electrically connects the first semiconductor element and the second semiconductor element. | 2013-06-20 |
20130154083 | SEMICONDUCTOR PACKAGE - Disclosed herein is a semiconductor package. The semiconductor package includes a semiconductor module, a first heat dissipation unit, a second heat dissipation unit and a housing. The semiconductor module contains a semiconductor device. The first heat dissipation unit is provided under the semiconductor module. The first heat dissipation unit includes at least one first pipe through which first cooling water passes. A first rotator is rotatably disposed in the first pipe. The second heat dissipation unit is provided on the semiconductor module. The second heat dissipation unit includes at least one second pipe through which second cooling water passes. A second rotator is rotatably to disposed in the second pipe. The housing is provided on opposite sides of the semiconductor module, the first heat dissipation unit and the second heat dissipation unit and supports the semiconductor module, the first heat dissipation unit and the second heat dissipation unit. | 2013-06-20 |
20130154084 | SEMICONDUCTOR MODULE - A semiconductor module includes a semiconductor device; a metal plate portion that includes a first surface on a side of the semiconductor device and has a fastening portion at an end thereof; a molded portion that is formed by molding a resin on the semiconductor device and the metal plate portion, a cooling plate portion that is a separate member from the metal plate portion, is provided on a side opposite to the first surface on the side of the semiconductor device, and includes fins on a side opposite to the side of the metal plate portion; wherein the fastening portion of the metal plate portion is exposed out of the molded portion, and the cooling plate portion includes a fastening portion at a position that corresponds to a position of the fastening portion of the metal plate portion. | 2013-06-20 |
20130154085 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH HEAT CONDUCTION AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a substrate; mounting an integrated circuit over the substrate; mounting a lid base over the substrate, the lid base having a base indentation and a hole with the integrated circuit within the hole; and mounting a heat slug over the lid base, the heat slug having a slug non-horizontal side partially within the base indentation. | 2013-06-20 |
20130154086 | Exposing Connectors in Packages Through Selective Treatment - A method includes performing an etching step on a package. The package includes a package component, a connector on a top surface of the package component, a die bonded to the top surface of the package component, and a molding material molded over the top surface of the package component. The molding material covers the connector, wherein a portion of the molding material covering the connector is removed by the etching step, and the connector is exposed. | 2013-06-20 |
20130154087 | METHOD FOR FORMING INTERCONNECTION PATTERN AND SEMICONDUCTOR DEVICE - According to one embodiment, a method for forming an interconnection pattern includes forming an insulating pattern, forming a self-assembled film, and forming a conductive layer. The insulating pattern has a side surface on a major surface of a matrix. The self-assembled film has an affinity with a material of the insulating pattern on the side surface of the insulating pattern. The forming the conductive layer includes depositing a conductive material on a side surface of the self-assembled film. | 2013-06-20 |
20130154088 | Integrated Circuits with Components on Both Sides of a Selected Substrate and Methods of Fabrication - Novel integrated circuits (SOI ICs), and methods for making and mounting the ICs are disclosed. In one embodiment, an IC comprises a first circuit layer of the IC formed from an active layer of an SOI wafer. The first circuit layer is coupled to a first surface of buffer layer, and a second surface of the buffer layer is coupled to a selected substrate comprising an insulating material. The selected substrate may be selected, without limitation, from the following types: sapphire, quartz, silicon dioxide glass, piezoelectric materials, and ceramics. A second circuit layer of the IC are formed, coupled to a second surface of the selected substrate. In one embodiment of a mounted IC, the first circuit layer is coupled to contact pads on a package substrate via solder bumps or copper pillars. The second circuit layer is coupled to contact pads on the package substrate via wire bonds. | 2013-06-20 |
20130154089 | BUMP INCLUDING DIFFUSION BARRIER BI-LAYER AND MANUFACTURING METHOD THEREOF - Provided herein is a bump including a diffusion barrier bi-layer, the bump having: a conductive layer; a first diffusion barrier layer formed on or above the conductive layer, and comprising an alloy of nickel and phosphorus; a second diffusion barrier formed on or above the first diffusion barrier layer, and comprising copper; and a solder layer formed on or above the second diffusion barrier layer. A manufacturing method for producing a bump is also provided. | 2013-06-20 |
20130154090 | Semiconductor Device and Method of Forming Interconnect Structure with Conductive Pads Having Expanded Interconnect Surface Area for Enhanced Interconnection Properties - A semiconductor device has a substrate and first conductive pads formed over the substrate. An interconnect surface area of the first conductive pads is expanded by forming a plurality of recesses into the first conductive pads. The recesses can be an arrangement of concentric rings, arrangement of circular recesses, or arrangement of parallel linear trenches. Alternatively, the interconnect surface area of the first conductive pads is expanded by forming a second conductive pad over the first conductive pad. A semiconductor die has a plurality of interconnect structures formed over a surface of the semiconductor die. The semiconductor die is mounted to the substrate with the interconnect structures contacting the expanded interconnect surface area of the first conductive pads to increase bonding strength of the interconnect structure to the first conductive pads. A mold underfill material is deposited between the semiconductor die and substrate. | 2013-06-20 |
20130154091 | SEMICONDUCTOR DEVICE PACKAGING USING ENCAPSULATED CONDUCTIVE BALLS FOR PACKAGE-ON-PACKAGE BACK SIDE COUPLING - A semiconductor device package having an embedded three-dimensional interconnect structure and a process for making such a package is provided. One or more ball conductors are attached to a major surface of a substrate that provides at least an electrical conduit from the ball conductor to an opposite major surface of the substrate. The substrate can also provide an interconnect between solder balls. The combination of solder balls and substrate is encapsulated in the semiconductor device package. The ends of the signal conduits are exposed on one major surface of the device package, while a portion of the ball conductors is exposed on the opposite major surface of the device package. The ball conductors and signal conduits provide signal-bearing pathways between the major surfaces of the package. Contacts created by the back grinded ball conductors are used to form a package-on-package structure by coupling with contacts from another package. | 2013-06-20 |
20130154092 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH CONDUCTIVE PILLARS AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system including: providing a package carrier; mounting an integrated circuit to the package carrier; mounting a circuit interposer above the integrated circuit; mounting a mounting integrated circuit above the circuit interposer; forming a conductive pillar to the circuit interposer adjacent to the mounting integrated circuit; connecting the circuit interposer to the package carrier; and forming an encapsulation on the package carrier. | 2013-06-20 |
20130154093 | ANISOTROPIC CONDUCTIVE FILM COMPOSITION, ANISOTROPIC CONDUCTIVE FILM, AND SEMICONDUCTOR DEVICE BONDED BY THE SAME - An anisotropic conductive film composition for bonding an electronic device may include a hydrogenated bisphenol A epoxy monomer represented by Formula 1 or a hydrogenated bisphenol A epoxy oligomer represented by Formula 2: | 2013-06-20 |
20130154094 | ANISOTROPIC CONDUCTIVE FILM COMPOSITION, ANISOTROPIC CONDUCTIVE FILM, AND SEMICONDUCTOR DEVICE - A semiconductor device is bonded by an anisotropic conductive film composition. The anisotropic conductive film composition includes an ethylene-vinyl acetate copolymer, a polyurethane resin, and organic fine particles. The anisotropic conductive film composition has a melt viscosity of about 2,000 to about 8,000 Pa·s at 80° C. | 2013-06-20 |
20130154095 | SEMICONDUCTOR DEVICES CONNECTED BY ANISOTROPIC CONDUCTIVE FILM COMPRISING CONDUCTIVE MICROSPHERES - A semiconductor device includes an anisotropic conductive film for connecting the semiconductor device. The anisotropic conductive film includes a first conductive layer that has first conductive particles. The first conductive particles include cores containing silica or a silica composite, and have a 20% K-value ranging from about 7,000 N/mm | 2013-06-20 |
20130154096 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - In a manufacturing method of a barrier layer, a via hole is formed in an insulating layer that covers a conductive layer over a substrate, and then the barrier layer is formed in the via hole. The barrier layer is provided by forming a second titanium nitride film after forming a first titanium nitride film. The second titanium nitride film is formed using a method having a weak anisotropy than the first titanium nitride film. | 2013-06-20 |
20130154097 | SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD OF THE SAME - The present invention provides a semiconductor structure and a manufacturing method thereof. The method comprises: providing a semiconductor substrate comprising semiconductor devices; depositing a copper diffusion barrier layer on the semiconductor substrate; forming a copper composite layer on the copper diffusion barrier layer; decomposing the copper composite at corresponding positions, where copper interconnection is to be formed, into copper according to the shape of the copper interconnection; and etching off the undecomposed copper composite and the copper diffusion barrier layer underneath, to interconnect the semiconductor devices. The present invention is adaptive for manufacturing interconnection in integrated circuits. | 2013-06-20 |
20130154098 | LINER-FREE TUNGSTEN CONTACT - An electrical structure comprises a dielectric layer present on a semiconductor substrate. A contact opening is present through the dielectric layer. A nickel-tungsten alloy silicide is formed over the semiconductor substrate within the contact opening. A tungsten-containing nucleation layer formed within the contact opening covers the nickel-tungsten alloy silicide and at least a portion of a sidewall of the contact opening. A tungsten contact is formed within the contact opening and separated from the nickel-tungsten alloy silicide and at least a portion of the sidewall by the tungsten-containing nucleation layer. | 2013-06-20 |
20130154099 | PAD OVER INTERCONNECT PAD STRUCTURE DESIGN - A design rule checker that performs a maximum pattern density check in a first intermediary metallization layer that underlies a top metallization layer and a pad opening in an integrated circuit. The maximum pattern density check is performed at least under some circumstances if a modulus of the primary metallization material is less than a modulus of a surrounding dielectric material. The maximum pattern density check verifies that the pattern density within the underlying portion is below a maximum pattern density that depends on the thickness of the access pad. A maximum metal width check may also be performed in this portion. | 2013-06-20 |
20130154100 | METHOD OF PATTERNING A SEMICONDUCTOR DEVICE HAVING IMPROVED SPACING AND SHAPE CONTROL AND A SEMICONDUCTOR DEVICE - A pattern on a semiconductor substrate is formed using two separate etching processes. The first etching process removes a portion of an intermediate layer above an active region of the substrate. The second etching process exposes a portion of the active region of the substrate. A semiconductor device formed using the patterning method has a decreased mask error enhancement factor and increased critical dimension uniformity than the prior art. | 2013-06-20 |
20130154101 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device and a method for manufacturing the same are disclosed. In the semiconductor device, an upper part of a storage node contact plug is increased in size, and an area of overlap between a storage node formed in a subsequent process and a storage node contact plug is increased, such that resistance of the storage node contact plug is increased and device characteristics are improved. The semiconductor device includes at least one bit line formed over a semiconductor substrate, a first storage node contact plug formed between the bit lines and coupled to an upper part of the semiconductor substrate, and a second storage node contact plug formed over the first storage node contact plug, wherein a width of a lower part of the second storage node contact plug is larger than a width of an upper part thereof. | 2013-06-20 |
20130154102 | SEMICONDUCTOR DEVICE AND ITS MANUFACTURE METHOD - A support substrate includes a first surface and a second surface located above the level of the first surface. Chips are mounted on the first surface. A first insulating film is disposed over each chip. First conductive plugs are connected to the chip extending through each first insulating film. Filler material made of resin filling a space between chips. Wirings are disposed over the first insulating film and the filler material for interconnecting different chips. The second surface, an upper surface of the first insulating film and an upper surface of the filler material are located at the same level. | 2013-06-20 |
20130154103 | SEMICONDUCTOR PACKAGE HAVING MULTI PITCH BALL LAND - A semiconductor device having a printed circuit board and a semiconductor chip. The printed circuit board includes a chip region, a plurality of first ball lands adjacent to the chip region, and at least one second ball land adjacent to the first ball lands. The semiconductor chip is mounted on the chip region. The first ball lands are arranged to have a first pitch. One of the first ball lands which is nearest to the second ball land, and the second ball land have a second pitch greater than the first pitch. | 2013-06-20 |
20130154104 | INTEGRATED CIRCUITS AND METHODS OF FORMING CONDUCTIVE LINES AND CONDUCTIVE PADS THEREFOR - An integrated circuit includes circuitry, a first conductor coupled to the circuitry, a conductive pad coupled to the first conductor, and a second conductor coupled to the conductive pad. The second conductor would be floating but for its coupling to the conductive pad. The second conductor may be spaced apart from the first conductor by a distance that is substantially equal to a width of a merged spacer that was formed from a merging of single sidewall spacers over a conductive material from which the first and second conductors were formed. | 2013-06-20 |
20130154105 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH ROUTABLE TRACE AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing routable traces including a first routable trace with a top plate and a second routable trace; mounting an integrated circuit partially over a second routable trace; forming an encapsulation over and around the first routable trace and the integrated circuit; forming a hole through the encapsulation to the top plate; and forming a protective coat directly on the encapsulation with the first routable trace between and in contact with the protective coat and the encapsulation. | 2013-06-20 |
20130154106 | Stacked Packaging Using Reconstituted Wafers - An exemplary implementation of the present disclosure includes a stacked package having a top die from a top reconstituted wafer situated over a bottom die from a bottom reconstituted wafer. The top die and the bottom die are insulated from one another by an insulation arrangement. The top die and the bottom die are also interconnected through the insulation arrangement. The insulation arrangement can include a top molding compound that flanks the top die and a bottom molding compound that flanks the bottom die. The top die and the bottom die can be interconnected through at least the top molding compound. Furthermore, the top die and the bottom die can be interconnected through a conductive via that extends within the insulation arrangement. | 2013-06-20 |
20130154107 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH COUPLING FEATURES AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a wafer substrate having an active side containing a contact; forming a through silicon via extending through the wafer substrate electrically connected to the contact having a via width; forming a first coupling feature extending from a top side of the through silicon via; and forming a second coupling feature on the side of the through silicon via opposite the first coupling feature. | 2013-06-20 |
20130154108 | Semiconductor Device and Method of Forming Vertical Interconnect Structure with Conductive Micro Via Array for 3-D FO-WLCSP - A semiconductor device has a semiconductor die. An encapsulant is formed over the semiconductor die. A conductive micro via array is formed over the encapsulant outside a footprint of the semiconductor die. A first through-mold-hole having a step-through-hole structure is formed through the encapsulant to expose the conductive micro via array. In one embodiment, forming the conductive micro via array further includes forming an insulating layer over the encapsulant and the semiconductor die, forming a micro via array through the insulating layer outside the footprint of the semiconductor die, and forming a conductive layer over the insulating layer. In another embodiment, forming the conductive micro via array further includes forming a conductive ring. In another embodiment, an insulating layer is formed over the semiconductor die for structural support, a build-up interconnect structure is formed over the semiconductor die, and a conductive interconnect structure is formed within the first through-mold-hole. | 2013-06-20 |
20130154109 | METHOD OF LOWERING CAPACITANCES OF CONDUCTIVE APERTURES AND AN INTERPOSER CAPABLE OF BEING REVERSE BIASED TO ACHIEVE REDUCED CAPACITANCE - The disclosure provides an interposer with conductive paths, a three-dimensional integrated circuit (3D IC), a method of reducing capacitance associated with conductive paths in an interposer and a method of manufacturing an interposer. In one embodiment the interposer includes: (1) a semiconductor substrate that is doped with a dopant, (2) conductive paths located within said semiconductor substrate and configured to provide electrical routes therethrough and (3) an ohmic contact region located within said semiconductor substrate and configured to receive a back bias voltage. | 2013-06-20 |
20130154110 | DIRECT WRITE INTERCONNECTIONS AND METHOD OF MANUFACTURING THEREOF - A semiconductor device package having direct write interconnections and method of manufacturing thereof is disclosed. A device package is formed by providing a substrate structure, attaching at least one device to the substrate structure that each include a substrate and one or more connection pads formed on the substrate, depositing a dielectric layer over the at least one device and onto the substrate structure by way of a direct write application, the dielectric layer including vias formed therethrough, and forming an interconnect structure on the dielectric layer that is electrically coupled to the connection pads of the at least one device, the interconnect structure extending through the vias in the dielectric layer so as to be connected to the connection pads. | 2013-06-20 |
20130154111 | SEMICONDUCTOR DEVICE INCLUDING THROUGH ELECTRODE AND METHOD OF MANUFACTURING THE SAME AND STACKED PACKAGE INCLUDING SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device including a wafer having an upper surface and a lower surface, circuit layers formed on the upper surface and the lower surface of the wafer, respectively, and a through electrode formed to penetrate the wafer is presented. The through electrode can be configured to electrically coupled the circuit layers formed on the upper surface and the lower surface of the wafer. The semiconductor device can be stacked to form a stacked package. | 2013-06-20 |
20130154112 | Method for Forming Isolation Trenches in Micro-Bump Interconnect Structures and Devices Obtained Thereof - The disclosure is related to a substrate suitable for use in a stack of interconnected substrates, comprising: a base layer having a front side and a back side surface parallel to the plane of the base layer; one or more interconnect structures, each of said structures comprising: a via filled with an electrically conductive material, said via running through the complete thickness of the base layer, thereby forming an electrical connection between said front side and back side surfaces of the base layer, and on the back side surface of the base layer: a landing pad and a micro-bump in electrical connection with said filled via; characterized in that the backside surface of said base layer comprises one or more isolation ring trenches each of said trenches surrounding one or more of said interconnect structures. The disclosure is equally related to methods for producing said substrates and stacks of substrates. | 2013-06-20 |
20130154113 | PERFORATION PATTERNED ELECTRICAL INTERCONNECTS - This disclosure describes systems and methods for increasing the usable surface area of electrical contacts within a device, such as a thin film solid state device, through the implementation of electrically conductive interconnects. Embodiments described herein include the use of a plurality of electrically conductive interconnects that penetrate through a top contact layer, through one or more multiple layers, and into a bottom contact layer. The plurality of conductive interconnects may form horizontal and vertical cross-sectional patterns. The use of lasers to form the plurality of electrically conductive interconnects from reflowed layer material further aids in the manufacturing process of a device. | 2013-06-20 |
20130154114 | SEMICONDUCTOR DEVICE AND METHOD FOR MAKING SAME - A semiconductor circuit pattern includes an angled conductive pattern having a line portion and a pad portion at an end of the line portion extending normal to the line portion on a first side of the line portion. The pad portion has a width greater than a width of the line portion. A spacing has a first portion adjacent the first side of the pad portion, and a second portion adjacent a second side of the pad portion opposite the first side. The first portion of the spacing has a width greater than the width of the second portion of the spacing. | 2013-06-20 |
20130154115 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH LEADS AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: forming a lead having a lead bottom body, a lead top body, and a lead top conductive layer directly on the lead top body, the lead top conductive layer having a top protrusion and a top non-vertical portion, the lead bottom body having a horizontally contiguous structure; connecting an integrated circuit to the top protrusion; and forming an encapsulation covering the integrated circuit and exposing a top non-vertical upper side of the top non-vertical portion. | 2013-06-20 |
20130154116 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH PERIMETER ANTIWARPAGE STRUCTURE AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system comprising: providing a package carrier; mounting an integrated circuit to the package carrier; and forming a perimeter antiwarpage structure on and along a perimeter of the package carrier. | 2013-06-20 |
20130154117 | STACKED DIE IN DIE BGA PACKAGE - Die assemblies may include a first die abutting a substrate comprising a recess adjacent to the substrate. An adhesive element may be contained within the recess to attach the first die to the substrate. A height of the adhesive element may not contribute to an overall height of the die assembly. In some embodiments, a second die comprising a non-rectangular cross-sectional shape may be situated on the first die. Die assemblies ma also comprise a first die on a substrate and comprising a cavity on a side of the first die opposing a side on which the support substrate is located. A second die may be at least partially disposed in the cavity. Die assemblies may also comprise a first die secured to a substrate and partially inserted into a recess of a second die on a side opposing a side on which the substrate is located. | 2013-06-20 |
20130154118 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH CONTACTS AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: forming an isolated contact having a contact protrusion; forming a die paddle, adjacent to the isolated contact, having a die paddle contour; depositing a contact pad on the contact protrusion; coupling an integrated circuit die to the contact protrusion; molding an encapsulation on the integrated circuit die; and depositing an organic filler on and between the isolated contact and the die paddle, the contact protrusion extended past the organic filler. | 2013-06-20 |
20130154119 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH TERMINALS AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: forming a lead having a lead top side; forming a lower interior conductive layer directly on the lead top side; forming an interior insulation layer directly on the lower interior conductive layer; forming an upper interior conductive layer directly on the interior insulation layer; and mounting an integrated circuit over the upper interior conductive layer. | 2013-06-20 |
20130154120 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH PACKAGE-ON-PACKAGE AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: forming a peripheral lead; forming an interior conductive layer directly on the peripheral lead; forming a vertical connector directly on the interior conductive layer, the vertical connector having a connector top side; connecting an integrated circuit to the interior conductive layer; and forming an encapsulation over the integrated circuit, the encapsulation having an encapsulation top side coplanar with the connector top side. | 2013-06-20 |
20130154121 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH FILM ASSISTANCE MOLD AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a substrate; mounting an integrated circuit over the substrate, the integrated circuit having an inactive side and a non-horizontal side; mounting a mold chase having a buffer layer over the integrated circuit; forming an encapsulation between the substrate and the buffer; and removing the mold chase, leaving the encapsulation having a recess exposing a portion of the non-horizontal side. | 2013-06-20 |
20130154122 | SEMICONDUCTOR CHIP WITH UNDERFILL ANCHORS - Various semiconductor chips and methods of making the same are disclosed. In one aspect, a method of manufacturing is provided that includes forming a first opening in an insulating layer applied to a side of a semiconductor chip. The first opening does not extend through to the side. A second opening is formed in the insulating layer that exposes a portion of the side. | 2013-06-20 |
20130154123 | Semiconductor Device and Fabrication Method - In various embodiments, a semiconductor device may include: a carrier; a semiconductor chip disposed over a first side of the carrier; a layer stack disposed between the carrier and the semiconductor chip or over a second side of the carrier opposite the semiconductor chip, or both, the layer stack including at least a first electrically insulating layer, the first electrically insulating layer having a laminate having a first electrically insulating matrix material and a first mechanically stabilizing material embedded in the first electrically insulating matrix material. | 2013-06-20 |
20130154124 | METHOD FOR PACKAGING SEMICONDUCTORS AT A WAFER LEVEL - A package and method for packaging a semiconductor device formed in a surface portion of a semiconductor wafer. The package includes: a dielectric layer disposed on the surface portion of the semiconductor wafer having a device exposing opening to expose one of the devices and an electrical contacts pad opening to expose an electrical contact pad; and a porous material in the device exposing opening over said one of the devices. | 2013-06-20 |
20130154125 | ADHESIVE FILM AND ELECTRONIC DEVICE INCLUDING THE SAME - An adhesive film includes an amine curing agent and a phenolic curing agent, and has a ratio of a storage modulus at 170° C. after 80% or more curing to a storage modulus at 40° C. before curing in the range of about 1.5 to about 3.0. | 2013-06-20 |
20130154126 | SEMICONDUCTOR DEVICE - A semiconductor device is provided which can change electrode pads of a semiconductor chip which are allocated to balls without any increase in the number of wires and without any change in a substrate. The semiconductor device includes a semiconductor chip having first and second electrode pads, and a package substrate on which the semiconductor chip is mounted. The package substrate includes a first stitch having a width larger than widths of first and second wires, a second stitch having a width larger than the widths of the first and second wires, a ball that can be coupled with an external, the first wire that couples the first stitch and the ball, and the second wire that couples the first stitch and the second stitch. A first bonding wire couples the first stitch and the first electrode pad, or the second stitch and the second electrode pad. | 2013-06-20 |
20130154127 | Microspring Structures Adapted for Target Device Cooling - In a system for providing temporary or permanent connection of an integrated circuit die to a base substrate using electrical microsprings, a thermal element is provided that assists with cooling of the pad structure during use. The thermal element may be formed of the same material and my similar processes as the microsprings. The thermal element may be one or more block structures or one or more thermal microsprings. The thermal element may be provided with channels to contain and/or direct the flow of a thermal transfer fluid. Cooling of components associated with the pad structure (e.g., ICs) may be provided. | 2013-06-20 |
20130154128 | Automatic Place and Route Method for Electromigration Tolerant Power Distribution - The present disclosure relates to an electromigration tolerant power distribution network generated by an automatic place and route (APR) methodology. In some embodiments, an automatic place and route tool constructs a local power network having multi-level power rails. The multi-level power rails have interleaved segments of vertically adjacent metal layers, wherein each interleaved segment is shorter than a predetermined characteristic length corresponding to a Blech length. By limiting the length of the interleaved metallization segments, electromigration within the multi-level power rails is alleviated, allowing for the maximum current density requirement (J | 2013-06-20 |
20130154129 | ANISOTROPIC CONDUCTIVE FILM AND SEMICONDUCTOR DEVICE BONDED BY THE SAME - A semiconductor device bonded by an anisotropic conductive film and an anisotropic conductive film composition, the anisotropic conductive film including a reactive monomer having an epoxy equivalent weight of about 120 to about 180 g/eq; a hydrogenated epoxy resin; and a sulfonium cation curing catalyst. | 2013-06-20 |
20130154130 | METHOD FOR COATING AN OPTOELECTRONIC CHIP-ON-BOARD MODULE AND OPTOELECTRONIC CHIP-ON-BOARD MODULE - A method is provided for coating an optoelectronic chip-on-board module, including a flat substrate populated with one or more optoelectronic components, having a transparent, UV-resistant, and temperature-resistant coating made of one or more silicones. A corresponding optoelectronic chip-on-board module and a system having multiple optoelectronic chip-on-board modules are also provided. The method includes the following steps: a) preheating the substrate to be coated to a first temperature; b) applying on the preheated substrate a dam that encloses a surface area or partial area of the substrate to be coated, the dam being made of a first, heat-curable, highly reactive silicone that cures at the first temperature; c) filling the surface area or partial area of the substrate enclosed by the dam with a liquid second silicone; and d) curing the second silicone. | 2013-06-20 |
20130154131 | Air-cleaning decorative humidifier - An air-cleaning decorative humidifier, including mainly a support seat, a water receptacle, at least a shaft, a fan, and a water sub-receptacle; in which a base seat of the water receptacle is fixed to the bottom of the water receptacle; a first water opening is provided on the base seat of the water receptacle; a water valve is provided on the first water opening; the fan and the water sub-receptacle are provided in the support seat; a water level control rod is provided in the water sub-receptacle; the shaft is connected with at least a decoration directly or through a mechanism. | 2013-06-20 |
20130154132 | LIFTABLE AERATION ASSEMBLY AND METHODS OF PLACING AN AERATION ASSEMBLY INTO A RECEPTACLE - The disclosed apparatus aeration assembly is used for submersion in and aeration of wastewater contained in a receptacle. The assembly may comprise a non-floating planar grid supporting a plurality of gas diffuser panels. The supporting grid may have at least two ends; one or more gas inlets affixed to one of the at least two ends for supplying gas to the plurality of gas diffuser panels; and one or more lift lines of a predetermined length affixed to each of the at least two ends with all lift lines meeting at a juncture. The juncture may be positioned above a plane of the supporting grid so that the predetermined length of a line affixed to one of the at least two ends is unequal to the predetermined length of a line affixed to another of the at least two ends. | 2013-06-20 |
20130154133 | CARBURETOR FLOAT AND METHOD OF MANUFACTURING SAME - A method of making a carburetor float by first creating a homogeneous mixture of gas and polymer in a plastic injection machine. The gas/polymer mixture is injected into a tool having a mold cavity. A moveable portion of the mold cavity allows the gas/polymer mixture to expand in that area thus forming a foamed portion of the finished float. The portion of the mold that is stationary does not allow the gas/polymer mixture to foam and thus forms a portion of the finished float with a higher density that the foamed portion. The result is a float made of the homogeneous mixture with two differing densities in two different portion of the float. | 2013-06-20 |
20130154134 | Humidifier Having an Anti-Contamination System - A humidifier is provided having a base including a chamber for receiving water, at least one reservoir removably mounted on the base for providing water to the base chamber, and an atomizer provided in the base for aerosolizing water from the base chamber. A duct is removably mounted on the base, the duct enclosing the atomizer and venting humidified air from the humidifier. An anti-contamination system is in communication with the duct and includes a housing, an ultraviolet (UV) light source mounted within the housing for emitting UV light to interact with at least one of the aerosolized water and humidified air, and a window at least partially transparent to UV light provided between the anti-contamination system and the duct. Embodiments may include a reflective member provided within the housing for reflecting UV light through the window. | 2013-06-20 |
20130154135 | AIR-CONDITIONING SYSTEM - An air-conditioning system includes: a first duct through which air discharged from an electronic instrument passes; a water vapor retention chamber; an evaporator configured to be heated by the air passing through the first duct and thereby to generate water vapor inside the water vapor retention chamber; a desiccant rotor including an adsorbent to adsorb moisture and configured to be driven and rotated by a driving unit; a humidification chamber; a second duct configured to feed outdoor air introduced from an outdoor space into the humidification chamber; and a third duct configured to feed the air passing through the humidification chamber into a room where the electronic instrument is installed, wherein a portion of the desiccant rotor is located inside the water vapor retention chamber, and another portion of the desiccant rotor is located inside the humidification chamber. | 2013-06-20 |
20130154136 | METHOD AND DEVICE FOR FORMING REFLECTOR IN LIGHT EMITTING DEVICE PACKAGE - A method of forming a plurality of reflectors for a light emitting device (LED) package includes receiving a first fluid material at at least a first source opening of an upper mold of a transfer apparatus; passing the first fluid material through a transfer passageway of the upper mold; expelling the first fluid material from the transfer passageway through a plurality of openings in a lower internal surface of a transfer chamber of the transfer passageway; depositing the first fluid material on a lead frame, disposed on a lower mold of the transfer apparatus, through the plurality of openings; forming the first fluid material into a plurality of molded structures using the upper mold and the lower mold; and hardening each of the molded structures to form a plurality of reflectors. | 2013-06-20 |
20130154137 | OPTICAL ELEMENT AND METHOD FOR THE PRODUCTION THEREOF - Described is an optical element for guiding electromagnetic radiation. The optical element includes a base body and at least one film, wherein the film is configured to adhere to the base body to form an intimate connection with the base body without using an adhesion promoting interlayer and is arranged such that the electromagnetic radiation passes through it. | 2013-06-20 |
20130154138 | METHOD FOR PREPARING OF ALLICIN INJECTION AND LOW-TEMPERATURE CONTINUOUS STIRRING ULTRFILTRATION DEVICE THEREOF - The present invention provides a preparing method of an allicin injection and the low temperature continuous stirring ultrafiltration device thereof. Said preparing method consists of the following steps: extracting allicin; diluting the allicin with solvent precooled tol-4 in a clean environment, adding nitrogen gas or argon gas, and then encapsulating the solution to obtain allicin injection with different specifications. | 2013-06-20 |
20130154139 | PROCESS FOR PRODUCING CELLULOSE SHAPED ARTICLES - The present invention provides a process for producing cellulose shaped articles in which a) cellulose is at least partly dissolved at a temperature of about 100° C. or lower in a dope comprising an ionic liquid and a cosolvent to form a cellulose solution, wherein said cosolvent comprises a polar aprotic component, and b) cellulose shaped articles are cast from the cellulose solution. | 2013-06-20 |
20130154140 | Method for Manufacturing Dental Implant and Dental Implant - Herein is provide a dental implant for preventing elution of metal when the dental implant is applied within an oral cavity, and for preventing the occurrence of mismatching (bumpy occlusion or the like) when the dental implant is fixed in place. Also provided is a method for manufacturing the dental implant. The abutment manufacturing steps include a ceramic molded body production step for molding a ceramic molded body composition to obtain a ceramic molded body, an assembling step for assembling a titanium member and the ceramic molded body together to obtain an assembled body, a degreasing step for degreasing the assembled body so that the ceramic molded body is transformed into a ceramic degreased body, and a sintering step for sintering the assembled body to transform the ceramic degreased body into a ceramic member so that the ceramic member is firmly fixed to the titanium member. | 2013-06-20 |
20130154141 | PHOSPHOR, METHOD FOR PRODUCING THE SAME AND LIGHT-EMITTING DEVICE USING THE SAME - A method for providing a phosphor, including a kneading step in which a raw material is kneaded to provide a raw material mixture; a sintering step in which the raw material mixture is sintered; and a heat treatment step in which the sintered raw material mixture is heat-treated, wherein the raw material includes at least one or more M-containing materials selected from MSi | 2013-06-20 |
20130154142 | CONICITY CORRECTION FOR RUBBER COMPONENT EXTRUSION - A system for extruding one or more tread strips is described. The system includes an extruder having an outlet end connected to an extruder head for forming an elastomeric strip to a predetermined cross-sectional profile. The extruder head has an internal flow channel having an inlet end and an outlet end, wherein the flow channel has a first temperature zone and a second temperature zone. The temperature zones are used to adjust the conicity of the tread strips. | 2013-06-20 |
20130154143 | HIGH DYNAMIC TEMPERATURE CONTROL SYSTEM - A heating/cooling module for a molding system includes a mold surface forming a part of a mold cavity. A cooling unit is disposed adjacent to the mold surface for cooling the mold surface. A layered heater is disposed adjacent to the mold surface for heating the mold surface. | 2013-06-20 |
20130154144 | CONICITY CORRECTION FOR RUBBER COMPONENT EXTRUSION - A method for correcting the conicity of a tread strip is described. The method includes the steps of extruding a tread profile having a right hand side, a left hand side and a chimney; measuring the thickness of the tread profile at the right hand side and the left hand side; calculating the mass of the tread on the left hand side and the right hand side; and adjusting the location of the chimney incrementally towards the side which is least in mass. | 2013-06-20 |
20130154145 | BLOWN FILM SCANNING METHOD - A method is provided for measuring and controlling a cumulative physical property, such as the thickness, of a tubular blown film, wherein the tubular blown film is being extruded from a ring-shaped extruder having a plurality of film physical property controllers disposed around the ring-shaped extruder. Where the physical property is thickness, the method includes the steps of (1) collapsing the tubular film to create a two-ply web and slowly rotating the film while taking a plurality of thickness measurements across the two-play web at various sections of the film, (2) calculating initial estimates of the thickness of each section using a first algorithm, (3) refining the initial estimates of the thicknesses of each section by successive iterations using a second algorithm, and (4) optionally adjusting at least one film physical property controller to control the final estimate of the thicknesses of each longitudinal section. | 2013-06-20 |
20130154146 | SINTERING MACHINE AND METHOD OF MANUFACTURING SINTERED BODY - A sintering machine includes: a die configured to accommodate a processing object, and having a hole that extends from an outer side surface of the die toward inside of the die; a pressurizing member configured to apply a pressure on the processing object in the die; and a heating section configured to heat the processing object in the die. | 2013-06-20 |
20130154147 | Solid Oxide Fuel Cell Articles and Methods of Forming - A solid oxide fuel cell (SOFC) article including a SOFC unit cell having a functional layer of an average thickness of not greater than about 100 μm, wherein the functional layer has a first type of porosity having a vertical orientation, and the first type of porosity has an aspect ratio of length:width, the width substantially aligned with a dimension of thickness of the functional layer. | 2013-06-20 |
20130154148 | Electronic Device And Method Of Making - Circuits and methods of fabricating circuits are disclosed herein. A method of fabricating an electronic circuit includes placing an electronic component on a substrate. A ferromagnetic material is mixed into a mold compound to produce a mixed mold compound having an increased permeability over the mold compound. The mixed mold compound is applied to the substrate by way of a transfer mold process, wherein the mixed mold compound encapsulates the electronic component. | 2013-06-20 |
20130154149 | SYNTHETIC COMPOSITION OF MARBLE AND METHOD OF PRODUCTION - A method of producing a synthetic composition having properties of marble includes blending a polymer resin with a stone gravel bit to form a mixture. The method also includes processing the mixture of polymer resin with the stone gravel bit to produce a synthetic marble composition through a polymerization of the mixture that is cast in a casting cell. Further, the method may include preparing a mold to form a casting cell, removing air bubbles from the mixture of polymer resin with the stone gravel bit to enhance a physical property of the synthetic marble material, casting the mixture in the casting cell, polymerizing the cast mixture through an autoclave polymerization of the mixture at a pressure ranging from 1 to 10 atmospheres and a temperature ranging from 50° to 100° C. to prepare the synthetic marble material composition, and curing the synthetic marble sheet in an oven. | 2013-06-20 |
20130154150 | METHOD FOR PRODUCING MOLDED GASKET - In a method for producing a molded gasket having a surface treated layer on one surface of a substrate and integrally formed with a gasket body constructed by a rubber-like elastic body on the other surface, a first step of integrally molding the gasket body on the substrate, a second step of temporarily placing the molded piece on a placement stand, and a third step of removing a burr portion from a production portion by punching the molded piece are sequentially executed. For preventing foreign material attachment, pollution and scratching, the first step integrally forms a projecting leg portion constructed by a rubber-like elastic body at a position corresponding to the burr portion in the molded piece, the second step brings the molded piece into contact with the placement stand by the leg portion, and the third step removes the leg portion as a part of the burr portion. | 2013-06-20 |
20130154151 | Method for Forming a Thermoplastic Composition that Contains a Renewable Biopolymer - A method for forming a thermoplastic composition that contains a combination of a renewable biopolymer with a polyolefin is provided. The biopolymer and polyolefin are supplied to the extruder at a feed section. The plasticizer is directly injected into the extruder in the form of a liquid so that it forms a thermoplastic biopolymer in situ within the extruder and then a homogeneous blend. The in situ addition of the plasticizer is facilitated by the use of a compatibilizer that has a polar component with an affinity for the biopolymer and a non-polar component with an affinity for the polyolefin. | 2013-06-20 |
20130154152 | Precision Continuous Stamp Casting Method for Roll-Based Soft Lithography - Method for casting a continuous cylindrical polymer stamp. The method includes depositing a first layer of a fluid polymer on the inside of a rotatable drum and rotating the drum for a selected time and at a selected angular velocity. The polymer is cured to produce a uniform datum surface. A second layer of polymer is deposited on the first layer in the drum and the drum is rotated until solvent in the polymer has evaporated thereby forming a stable layer. The polymer is selectively exposed and developed to create a desired pattern. Thereafter, a polymer precursor is deposited on the patterned second layer and the polymer precursor is allowed to cure while the drum is rotating to produce a cured stamp. The cured stamp is removed from the drum. | 2013-06-20 |
20130154153 | MULTI-SHOT MOLDING METHOD WITH PRESSURE ACTIVATED EXPANSION LOCKS - A co-molding process includes molding a body between a “common cavity” and “first shot core” die halves, co-molding a soft plastic onto the first component to form a final part using the “common cavity” die half and a “second shot core” die half. The “second shot core” die half includes shallow formations forming expansion locks along an elongated edge of the final part on a non-show concave surface, the locks having a shallow depth and extending in a direction non-parallel a die pull direction such that the locks affirmatively prevent shifting of first component during the co-molding process. Also, the locks can be made to cause the final part to remain with the “second shot core” die half when dies are opened during a final step of the co-molding process. | 2013-06-20 |
20130154154 | COMPOSITE STRUCTURES HAVING CORED MEMBERS - A complex-shaped, three-dimensional fiber reinforced composite structure may be formed by using counteracting pressures applied to a structural lay-up of wetted fibers with cored members embedded there between. The wetted fibers are arranged on pressurizable members and may be configured to include internal structural features, such as shear webs. A reinforcement stiffener may be located adjacent to at least one of the pressurizable members and the wetted fibers that form the internal structural feature. The cored members may be selectively located on various interior and exterior regions or surfaces of the composite structure. | 2013-06-20 |
20130154155 | MANUFACTURING OF DSC TYPE ELECTRONIC DEVICES BY MEANS OF SPACER INSERT - A DSC type device manufacturing process includes placing a circuit assembly in a mold. The circuit assembly includes a first heat sink, a semiconductor chip mounted on the first heat sink, a second heat sink mounted on the semiconductor chip and a pin block electrically connected to the semiconductor chip. An outer surface of the first heat sink and an outer surface of the pin block are placed in contact with a first inner surface of the mold. A spacer insert is placed in contact with, and positioned between, a second inner surface of the mold and an outer surface of the second heat sink. The mold is filled with an insulating material that is subsequently hardened. After hardening, a resulting device is extracted from the mold with the outer surfaces of the first heat sink, the pin block and the second heat sink exposed. | 2013-06-20 |
20130154156 | GOLF BALL MOLD AND GOLF BALL MANUFACTURING METHOD - A golf ball mold body having a plurality of mold parts with a parting surface defining a parting line along an equator and removably mating to form a cavity having an inner wall with dimple-forming protrusions, and a support pin extendable into and retractable from the cavity, the support pin extending into the cavity to support a center sphere. An end face of the support pin defines a portion of the cavity inner wall when the support pin is retracted. The support pin has a shape satisfying certain conditions, and the support pin and mold body have a gap therebetween set within a specific range. The invention minimizes formation of uneven flash caused by deflection or shifting of support pins, appearance defects caused by damage to the cavity inner wall and contamination by rubbing debris, and the life of the mold is extended. | 2013-06-20 |
20130154157 | NOVEL MATERIAL AND PROCESS OF MANUFACTURE - A process for manufacturing a material including glass in particulate form and plastic, comprises the steps of heating the glass in particulate form and/or the plastic to a threshold temperature sufficient to change the state of the plastic from a solid to a viscous liquid, mixing together the glass and plastic to form a mixture, pressing the mixture into a desired shape and curing the pressed mixture. | 2013-06-20 |
20130154158 | METHOD AND MOLD FOR MANUFACTURING A TANK HAVING A SLIDE DRUM AND FOLLOWER PISTON - A method of manufacturing a fluid reservoir ( | 2013-06-20 |
20130154159 | Drilling Holes with Minimal Taper in Cured Silicone - A laser machining system is used to precision laser drill holes in an elastomeric material, preferably silicone rubber, to form holes to support miniature electronic components temporarily while they are being processed or tested. The holes are formed by directing laser pulses from a laser to a top surface of the elastomeric material in a plurality of passes in a direction proceeding from a non-zero inner diameter to the desired diameter or from the desired diameter to the inner diameter. The plurality of passes forms a first pattern such that a successive pass of the plurality of passes overlaps a previous pass of the plurality of passes. The first pattern is repeated without changing direction or the first pattern is repeated while reversing the direction until the hole is formed through a bottom surface of the elastomeric material. | 2013-06-20 |
20130154160 | Stereolithography Systems and Methods Using Internal Laser Modulation - Stereolithography systems ( | 2013-06-20 |
20130154161 | METHOD AND APPARATUS ASSOCIATED WITH ANISOTROPIC SHRINK IN SINTERED CERAMIC ITEMS - A manufacturing method for producing ceramic item from a photocurable ceramic filled material by stereolithography. The method compensates for the anisotropic shrinkage of the item during firing to produce a dimensionally accurate item. | 2013-06-20 |
20130154162 | System and Method of Optimizing a Composite System - The present application relates to a method and system for optimizing a composite system by electrically monitoring the reactive and physiological behavior of the resin binder in a composite system, so as to develop the desired properties of the resin during the cure process. A method of manufacturing a composite part can include assembling a composite preform with a resinous material and an open circuit. Further, the method can include subjecting the composite preform to a curing cycle so that a resin in the resinous material melts and closes the open circuit. Further, the method can include electrically monitoring a current through the resin during the curing cycle. Further, the method can include selectively controlling a manufacturing variable in response to the step of electrically monitoring the current through the resin. | 2013-06-20 |
20130154163 | METHOD AND APPARATUS FOR REPAIRING THE WALL OF A MANHOLE - The present invention comprises a method and means for repairing the wall of a manhole wherein a material capable of curing and hardening is adhered to the wall. An expandable bladder engages the curable and hardenable material and presses against and smoothes the material. The bladder may be chemically bonded to the curable and hardenable material or it may be mechanically bonded. | 2013-06-20 |