25th week of 2013 patent applcation highlights part 36 |
Patent application number | Title | Published |
20130155765 | PHASE CHANGE MEMORY DEVICE, OPERATION METHOD THEREOF, AND DATA STORAGE DEVICE HAVING THE SAME - A phase change memory device includes: a memory cell arranged at a region where a word line and a bit line cross each other; and a control logic including: a program control logic configured to control a program operation of the memory cell; a read control logic configured to control a read operation of the memory cell; and an operation complete signal transfer unit configured to adjust a transfer time point of an operation complete signal transferred between the program control logic and the read control logic. | 2013-06-20 |
20130155766 | PHASE CHANGE MEMORY DEVICES, METHOD FOR ENCODING, AND METHODS FOR STORING DATA - Phase change memory cells including a phase change media can be encoded using a source of energy that is not integral with the memory cell. External sources of energy include thermal heads, such as those used in direct thermal printing or thermal transfer printing and sources of electromagnetic radiation, such as lasers. Such types of phase change memory devices can be associated with substrates that include thermochromic materials or are suitable for thermal transfer printing so that the memory cells can be encoded and print media applied to the substrate using the same source of thermal energy. | 2013-06-20 |
20130155767 | APPARATUSES AND METHODS FOR SENSING A PHASE-CHANGE TEST CELL AND DETERMINING CHANGES TO THE TEST CELL RESISTANCE DUE TO THERMAL EXPOSURE - A phase change memory array may include at least one cell used to determine whether the array has been altered by thermal exposure over time. The cell may be the same or different from the other cells. In some embodiments, the cell is only read in response to an event. If, in response to that reading, it is determined that the cell has changed state or resistance, it may deduce whether the change is a result of thermal exposure. Corrective measures may then be taken. | 2013-06-20 |
20130155768 | Method for Operating a High Density Multi-Level Cell Non-Volatile Flash Memory Device - A localized trapping multi-level memory cell operating method includes the following steps. First, a localized trapping memory cell with the initial threshold voltage of ˜2.5V is provided. Next, an erasing operation is performed to obtain a negative threshold level which has the uniform distribution along the channel region. Taking into account the over-erasure issue in the erasing course, a programming operation is performed to precisely adjust the threshold voltage to a predetermined level of −2V˜−1V. Then, with the negative voltage as a new initial state, corresponding programming operation is performed and electrons are locally injected the storage layer. By controlling the quantity of injected electrons, the MLC storage is achieved. | 2013-06-20 |
20130155769 | Non-Volatile Memory And Method With Improved First Pass Programming - A nonvolatile memory with a multi-pass programming scheme enables a page of multi-level memory cells to be programmed with reduced floating-gate to floating-gate perturbations (Yuping effect). The memory cells operate within a common threshold voltage range or window, which is partitioned into multiple bands to denote a series of increasingly programmed states. The series is divided into two halves, a lower set and a higher set. The memory cells are programmed in a first, coarse programming pass such that the memory cells of the page with target states from the higher set are programmed to a staging area near midway in the threshold window. In particular, they are programmed closer to their targeted destinations than previous schemes, without incurring much performance penalty. Subsequent passes will then complete the programming more quickly. Yuping effect is reduced since the threshold voltage change in subsequent passes are reduced. | 2013-06-20 |
20130155770 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a memory cell array having a plurality of bit lines and a plurality of word lines intersecting each other and a plurality of nonvolatile memory cells; and a page buffer for each bit line including a latch configured to store one of data to be written to a first nonvolatile memory cell selected by each word line and data read from the first nonvolatile memory cell, wherein before reading out data, the page buffer configured to store in a replica capacitor a voltage value of a word line adjacent to the selected word line when a second nonvolatile memory cell is turned on, the replica capacitor including a first capacitor and a second capacitor connected in parallel, and the page buffer is configured to vary when the latch judges the data from the first nonvolatile memory cell according to the voltage value. | 2013-06-20 |
20130155771 | 3D NON-VOLATILE MEMORY DEVICE, MEMORY SYSTEM INCLUDING THE SAME, AND METHOD OF MANUFACTURING THE SAME - A three-dimensional 3D nonvolatile memory device includes vertical channel layers protruding from a substrate; interlayer insulating layers and conductive layer patterns alternately deposited along the vertical channel layers; a barrier metal pattern surrounding each of the conductive layer patterns; a charge blocking layer interposed between the vertical channel layers and the barrier metal patterns; and a diffusion barrier layer interposed between the barrier metal patterns and the charge blocking layer. | 2013-06-20 |
20130155772 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SAME - In a semiconductor memory device and a method of operating the same, a memory block including memory cells is divided into memory groups. A level of bit line voltage applied to a bit line coupled to the memory cells included in each of the memory groups varies according to a distance between a row decoder and each memory groups during a program operation. Characteristics of the threshold voltage distribution of the memory cells in the semiconductor memory device may be improved without deteriorating performance of the program. | 2013-06-20 |
20130155773 | NON-VOLATILE MEMORY DEVICE - A non-volatile memory device includes a memory cell array in which a plurality of bit lines intersect a plurality of word lines and a non-volatile memory cell is disposed at each intersection, a page buffer which is provided for each bit line and which includes a latch configured to store data to be written to a memory cell connected to a word line selected from among the plurality of word lines or data read from the memory cell, and a control circuit configured to control a data input time from the bit line to the page buffer and a data detection time of the latch according to a voltage level of a common source line connected to sources of the respective bit lines during an operation of reading data from the memory cell. | 2013-06-20 |
20130155774 | SEMICONDUCTOR DEVICE AND CONTROL METHOD OF THE SAME - The present invention provides a semiconductor memory and a control method therefor, the semiconductor device including a first current-voltage conversion circuit connected to a core cell provided in a nonvolatile memory cell array, a second current-voltage conversion circuit connected to a reference cell through a reference cell data line, a sense amplifier sensing an output from the first current-voltage conversion circuit and an output from the second current-voltage conversion circuit, a compare circuit comparing a voltage level at the reference cell data line with a predefined voltage level, and a charging circuit charging the reference cell data line, if the voltage level at the reference cell data line is lower than the predefined voltage level during pre-charging the reference cell data line. According to the present invention, the pre-charging period of the reference cell data line can be shortened, and the data read time can be shortened. | 2013-06-20 |
20130155775 | METHOD OF OPERATING SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device is operated by reading data stored in LSB and MSB pages of a first word line in response to a read command and storing the read data in first and second latches of a page buffer, outputting the data stored in the first latch externally and transferring the data, stored in the second latch, to a third latch of the page buffer, resetting the first and second latches, reading data stored in LSB and MSB pages of a second word line, and storing the read data in the first and second latches, and sequentially outputting the data stored in the first latch and the data stored in the third latch, resetting the third latch, and then transferring the data stored in the second latch to the third latch. | 2013-06-20 |
20130155776 | INTER-CELL INTERFERENCE CANCELLATION - A method includes selecting a first memory cell located along a first bit line and a first word line of a memory array. The method further includes selecting a second memory cell located along (i) the first word line, (ii) a second word line that is adjacent to the first word line, or (iii) a second bit line that is adjacent to the first bit line. A location of the second memory cell is selected based on a predetermined sequence of programming the memory cells. The method further includes writing data in the first memory cell, subsequently writing data in the second memory cell, and reading the first memory cell and the second memory cell. The method further includes detecting one or more states of the second memory causing interference to the first memory cell. | 2013-06-20 |
20130155777 | CURRENT SENSING TYPE SENSE AMPLIFIER AND METHOD THEREOF - The configurations of sense amplifier and methods thereof are provided. The proposed sense amplifier includes a switch circuit having a main control switch, a sensing switch and a holding switch, wherein the three switches have a first bias, a second bias and a third bias respectively, and an auxiliary control switch electrically connected to the holding switch to control an operation of the holding switch. | 2013-06-20 |
20130155778 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a nonvolatile semiconductor memory device comprises a semiconductor substrate, memory strings formed above the semiconductor substrate, and a control circuit configured to control voltages applied to the memory cells. In a read operation, when the control circuit precharges a first source line electrically connected to a selected memory string to a first voltage, the control circuit precharges a second source line electrically connected to an unselected memory string to a second voltage, the second voltage being higher than the first voltage, and after the second source line is precharged, the control circuit precharges a first bit line electrically connected to the selected memory string to the second voltage. | 2013-06-20 |
20130155779 | SEMICONDUCTOR STORAGE DEVICE, HOST CONTROLLING THE SAME, AND MEMORY SYSTEM INCLUDING THE SEMICONDUCTOR STORAGE DEVICE AND THE HOST - According to one embodiment, a semiconductor storage device includes a memory cell array, a data latch group. The memory cell array comprises a plurality of memory cells. The data latch group holds a first address or a second address of the memory cell and data. The data latch group comprises a first data latch unit and a second data latch unit, the first data latch unit holds write data to be written to any of the memory cells or read data read from the memory cell array and the first address or the second address, while the second data latch unit holds second write data or read data. | 2013-06-20 |
20130155780 | APPARATUSES AND METHODS FOR COMPARING A CURRENT REPRESENTATIVE OF A NUMBER OF FAILING MEMORY CELLS - Apparatuses and methods for comparing a sense current representative of a number of failing memory cells of a group of memory cells and a reference current representative of a reference number of failing memory cells is provided. One such apparatus includes a comparator configured to receive the sense current and to receive the reference current. The comparator includes a sense current buffer configured to buffer the sense current and the comparator is further configured to provide an output signal having a logic level indicative of a result of the comparison. | 2013-06-20 |
20130155781 | FAST-BYPASS MEMORY CIRCUIT - A memory circuit in which a level of a first data input appears promptly at an output in response to a clock pulse received. The circuit includes a flip-flop triggered by the clock pulse and configured to receive the first data input and drive a second data input. The circuit also includes a first control input driven by the clock pulse, a second control input driven by the flip-flop and selection logic configured to receive the first and second data inputs and the first and second control inputs. The selection logic is configured to drive the output of the memory circuit to the level of the first data input or of the second data input depending on the first and second control inputs. | 2013-06-20 |
20130155782 | RANDOM ACCESS MEMORY AND REFRESH CONTROLLER THEREOF - A random access memory and a refresh controller thereof are provided. The refresh controller includes a write action detector, a latch device, a reset circuit, and a refresh masking device. The write action detector is coupled to an address decoder of the random access memory, and is used to detect a write action in an address corresponding to the address decoder and generate a detection result. The latch device is coupled to the write action detector, and is used to receive and latch the detection result. The reset circuit is coupled to the latch device, receives a reset control signal, and resets the detection result according to the reset control signal. The refresh masking device is coupled to a corresponding word line control circuit and the latch device and is used to mask a refresh action on the word line control circuit according to the detection result. | 2013-06-20 |
20130155783 | FAST-BYPASS MEMORY CIRCUIT - A memory circuit that presents input data at a data output promptly on receiving a clock pulse includes upstream and downstream memory logic and selection logic. The upstream memory logic is configured to latch the input data on receiving the clock pulse. The downstream memory logic is configured to store the latched input data. The selection logic is configured to expose a logic level dependent on whether the upstream memory logic has latched the input data, the exposed logic level derived from the input data before the input data is latched, and from the latched input data after the input data is latched. | 2013-06-20 |
20130155784 | SEMICONDUCTOR MEMORY APPARATUS - A semiconductor memory apparatus includes: a first sense amplification unit including first and second inverters configured to be driven to voltage levels of a power driving signal and a ground driving signal and forming a latch structure between a bit line and a bit line bar; and a second sense amplification unit including first and second transistors configured to be driven to the voltage level of the ground driving signal and forming a latch structure between the bit line and the bit line bar when an activated switching signal is applied, wherein a threshold voltage of the second sense amplification unit is set lower than that of the first sense amplification unit. | 2013-06-20 |
20130155785 | MEMORY MACRO CONFIGURATION AND METHOD - A memory macro comprises a plurality of memory array segments, each having a predetermined number of data inputs and outputs. A segment decoder circuit is configured to: receive a first value indicating a number of memory partitions among which the memory array segments are to be divided, and output a plurality of signals for selectively activating one or more of the plurality of memory array segments to be accessed based on the first value. A plurality of output drivers are coupled to the segment decoder circuit and to respective ones of the outputs. The plurality of output drivers are configured to selectively output data from the respective outputs of each of the respective activated memory array segments. | 2013-06-20 |
20130155786 | DATA SENSING CIRCUIT AND MEMORY DEVICE INCLUDING THE SAME - A data sensing circuit includes: a current source configured to supply a reference current to an output line; a switching precharging unit configured to couple an input line with the output line during a precharge operation of the input line; and a current sinking unit configured to sink a current from the output line in response to a voltage level of the input line. | 2013-06-20 |
20130155787 | Digital Voltage Boost Circuit - A digital voltage boost circuit, optionally working in parallel with an analog voltage regulator, periodically injects a constant amount of current each cycle into the bit line of a high density memory array to eliminate the bias voltage reduction which would otherwise occur. This results in a much faster recovery time and reduces the semiconductor real estate required. A pulse generator in the boost circuit generates one or more current modulation signals which control corresponding current supply devices in a current source. The boost circuit drives a constant amount of current to the bias voltage node each memory cycle. | 2013-06-20 |
20130155788 | DDR 2D VREF TRAINING - A method is provided for performing memory operations in response to instructions to perform a double data rate (DDR) memory reference voltage training in the voltage domain by a processing device and determining a DDR memory reference voltage and a DDR memory delay time based upon the memory operation. Computer readable storage media are also provided. A circuit is provided that includes a communication interface portion coupled to a memory and to a processing device. The circuit also includes a circuit portion, coupled to the communication interface portion that has a hardware state machine or an algorithm. The state machine or algorithm provides instructions to the processing device to perform a double data rate (DDR) reference voltage training in the voltage domain. | 2013-06-20 |
20130155789 | DATA SENSING CIRCUIT AND MEMORY DEVICE INCLUDING THE SAME - An memory device includes a bit line, an NMOS transistor configured to supply a voltage of a pull-up voltage terminal to the bit line in response to a voltage level of the bit line and a PMOS transistor configured to supply a voltage of a pull-down voltage terminal to the bit line in response to the voltage level of the bit line. | 2013-06-20 |
20130155790 | STORAGE DEVICE - Noise attributed to signals of a word line, in first and second bit lines which are overlapped with the same word line in memory cells stacked in a three-dimensional manner is reduced in a storage device with a folded bit-line architecture. The storage device includes a driver circuit including a sense amplifier, and first and second memory cell arrays which are stacked each other. The first memory cell array includes a first memory cell electrically connected to the first bit line and a first word line, and the second memory cell array includes a second memory cell electrically connected to the second bit line and a second word line. The first and second bit lines are electrically connected to the sense amplifier in the folded bit-line architecture. The first word line, first bit line, second bit line, and second word line are disposed in this manner over the driver circuit. | 2013-06-20 |
20130155791 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes an internal signal generation unit configured to output a column select signal and a write enable signal in response to an external address, a write circuit unit configured to output internal data corresponding to external data in response to the write enable signal, a core unit configured to store the internal data in response to the column select signal, and an output timing control unit configured to control output timings of the internal signal generation unit and the write circuit unit in response to an external command, an internal synchronization signal, and preamble related information. | 2013-06-20 |
20130155792 | SEMICONDUCTOR DEVICE HAVING DATA TERMINAL SUPPLIED WITH PLURAL WRITE DATA IN SERIAL - Disclosed herein is a semiconductor device that includes: a frequency dividing circuit dividing a frequency of a first clock signal to generate second clock signals that are different in phase from one another; a multiplier circuit multiplying the second clock signals to generate a third clock signal; a data input/output terminal; data buses; and a data input/output circuit coupled between the data input/output terminal and the data buses. The data input/output circuit includes a data output circuit and a data input circuit. The data output circuit outputs read data supplied in parallel from the data buses to the data input/output terminal in serial in synchronism with the third clock signal. The data input circuit outputs write data supplied in serial from the data input/output terminal to the data buses in parallel in synchronism with a predetermined one of the second clock signals. | 2013-06-20 |
20130155793 | MEMORY ACCESS CONTROL SYSTEM AND METHOD - The present disclosure relates to a method and system for controlling memory access. In particular, a method for controlling memory access includes, in response to receiving a write request operative to write data to at least one memory cell of a plurality of memory cells, increasing a word line voltage above a nominal level after a predetermined delay following the receipt of the write request. A disclosed system includes a word line driver operative to increase a word line voltage above a nominal level during a write access after a predetermined delay in response to a write request. | 2013-06-20 |
20130155794 | REPAIRABLE MULTI-LAYER MEMORY CHIP STACK AND METHOD THEREOF - A repairable multi-layer memory chip stack is provided. Each of the memory chips of the chip stack includes a control unit, a decoding unit, a memory array module and a redundant repair unit comprising at least one redundant repair element. The decoding unit receives a memory address from an address bus, and correspondingly outputs a decoded address. The memory array module determines whether to allow a data bus to access the data of the memory array module corresponding to a decoded address in accordance with an activation signal of the control unit. The redundant repair element includes a valid field, a chip ID field, a faulty address field and a redundant memory. When the valid field is valid, the value of the chip ID field matches the ID code, and the value of the faulty address field matches the decoded address, the redundant memory is coupled to the data bus. | 2013-06-20 |
20130155795 | Methodology for Recovering Failed Bit Cells in an Integrated Circuit Memory - A method for recovering failed bit cells in an integrated circuit memory is disclosed. In one embodiment, the method includes stress testing an integrated circuit having a memory, wherein the memory includes a plurality of bit cells. The method further includes holding at least one internal node of the selected one of the plurality of bit cells at a first predetermined state for a period sufficient to cause a shift in a threshold voltage of a transistor in the selected one of the plurality of bit cells. | 2013-06-20 |
20130155796 | FABRICATION AND TESTING METHOD FOR NONVOLATILE MEMORY DEVICES - Provided is a plurality of master chips arranged in a row on the wafer, each master chip including a power supply circuit provides a power supply voltage, and a plurality of slave chips arranged in a column to at least one side of a corresponding master chip among the plurality of master chips, each slave chip including a memory cell array functionally operative in response to the power supply voltage provided by the corresponding master chip during wafer level testing. | 2013-06-20 |
20130155797 | USING A PRECHARGE CHARACTERISTICS OF A NODE TO VALIDATE A PREVIOUS DATA/SIGNAL VALUE REPRESENTED BY A DISCHARGE OF SAID NODE - An integrated circuit precharges a node | 2013-06-20 |
20130155798 | SEMICONDUCTOR DEVICE HAVING HIERARCHICAL BIT LINE STRUCTURE - A semiconductor device is disclosed which comprises first and second local bit lines coupled to a plurality of memory cells arranged in first and second areas, respectively, a differential type local sense amplifier amplifying a voltage difference between the first and second local bit lines, a global bit line arranged in an extending direction of the first and second local bit lines, and first and second switches controlling electrical connections between the first and second local bit lines and the global bit line, respectively. | 2013-06-20 |
20130155799 | ELECTRICAL FUSE MEMORY - A method of reading an eFuse in a column of eFuse memory cells includes electrically disconnecting a first end of the eFuse from a first electrical path. A second electrical path between a second end of the eFuse and a node is activated to bypass a third electrical path, where the third electrical path includes a diode device between the second end of the eFuse and the node. A footer coupled with the node is turned on. | 2013-06-20 |
20130155800 | Secondary Memory Units and Systems Including the Same - A secondary memory unit and a system including the same, the secondary memory unit including: a first substrate on which one or more non-volatile memory units to which power is supplied from an external device, are mounted; a second substrate on which one or more energy storage and supply mediums are mounted; and an energy transfer medium for electrically connecting the first substrate and the second substrate, wherein, when power from the external device to the one or more non-volatile memory units is cut off, the one or more energy storage and supply mediums are configured to supply power to the one or more non-volatile memory units. The secondary memory unit and the system including the same have high reliability and improved stability, and their product development and maintenance are convenient. | 2013-06-20 |
20130155801 | SUB WORD LINE DRIVER AND SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - A sub word line driver and a semiconductor integrated circuit device having the same are provided. The semiconductor integrated circuit device includes adjacent four sub word line drivers configured to drive four sub word lines in response to signals of four main word lines, wherein first and second sub word line drivers of adjacent sub word line drivers share one keeper transistor with each other, and third and fourth sub word line drivers of the adjacent sub word line drivers share one keeper transistor with each other. | 2013-06-20 |
20130155802 | COMPOSITIONS AND METHODS FOR PREPARING NANOFORMULATIONS AND SYSTEMS FOR NANO-DELIVERY USING FOCUSED ACOUSTICS - Focused ultrasonic acoustic processing is used to prepare formulations particles ranging between approximately 10 nm and approximately 50 microns (e.g., between 1 micron and 20 microns), or between approximately 10 nm approximately 400 nm (e.g., between 10 nm and 100 nm). Formulations (e.g., nanoformulations) may include a suspension (e.g., nanosuspension), an emulsion (e.g., nanoemulsion) or another small particle system. Formulations may be used as delivery systems for therapeutic agents, e.g., a formulation may include a bioactive agent and a carrier compound such as a surfactant that encapsulates the bioactive agent. | 2013-06-20 |
20130155803 | Electromagnetic Stirring Apparatus - The stirring apparatus is an electronic design that generates rotating magnetic fields to drive magnetic stir bars within vials placed above the cover of the stirring apparatus. Below the cover is a magnetics board containing multiple vial groups of four air core coils arranged in rectangular patterns. Each vial group has with two pairs of diagonal coils. The coils in each pair are wired in series and have opposite winding directions. Each pair is driven by a different phase of a stepper motor driver. The vial groups are spaced appropriately for placing one vial above each group. The adjacent coils of adjacent vial groups are driven by the same phase and have the same magnetic direction. The cover contains an array of pole standoffs that matches the coil pattern. The hollow center of each air core coil contains at least a portion of one pole standoff. | 2013-06-20 |
20130155804 | DEVICE FOR FROTHING A LIQUID | 2013-06-20 |
20130155805 | CONTROLLER AND METHOD FOR STEERING SOURCES - A marine acoustic source system and method for steering a seismic source array in a body of water during a seismic survey. The method includes measuring an actual position of the seismic source array; calculating a virtual position of the seismic source array, wherein the virtual position corresponds to a position of the seismic source array when towed with no adjustment from a source steering device; retrieving a pre-plot path that includes desired positions of the seismic source array for the seismic survey; and steering the vessel based on the virtual position so that the virtual position lies on the pre-plot path. | 2013-06-20 |
20130155806 | METHOD AND SYSTEM FOR MARINE SEISMIC SURVEY - A buoy is configured to record seismic signals while underwater. The buoy includes a body; a buoyancy system configured to control a buoyancy of the body to descend multiple times to a predetermined depth (H) and then resurface with a controlled speed; and a seismic sensor located in the body and configured to record the seismic signals. The seismic sensor is instructed to record the seismic signals as the buoy travels up and down between the water surface and the predetermined depth. | 2013-06-20 |
20130155807 | METHOD FOR DETERMINING POSITIONS OF SENSOR STREAMERS DURING GEOPHYSICAL SURVEYING - A method for determining geodetic position of at least one point on a geophysical sensor streamer towed by a vessel in a body of water includes determining geodetic positions of a plurality of locations along a first geophysical sensor streamer towed at a first depth in the body of water. A lateral offset is caused between the first geophysical sensor streamer and a second geophysical sensor streamer towed at a second depth in the body of water. A distance is measured between at least two selected points along the first geophysical sensor streamer and a selected point along the second geophysical sensor streamer. A depth is measured at at least one point along the second geophysical sensor streamer. A geodetic position is determined at a selected point along the second geophysical sensor using the depth measurement, a direction of the lateral offset and the measured distances. | 2013-06-20 |
20130155808 | Method and Device for Estimating an Inter-node Distance Between Nodes Arranged Along Towed Acoustic Linear Antennas - A method and apparatus are provided for estimating an inter-node distance between a sender node and a receiver node belonging to a network comprising a plurality of nodes arranged along towed acoustic linear antennas. An acoustic signal is transmitted from the sender node to the receiver node through an underwater acoustic channel. The method includes estimating the inter-node distance as a function of an estimate of a sound speed profile of the underwater acoustic channel, the sound speed profile depending on depth. | 2013-06-20 |
20130155809 | Method and Device for Managing the Acoustic Performances of a Network of Acoustic Nodes Arranged Along Towed Acoustic Linear Antennas - A method and apparatus are provided for managing the acoustic performances of a network of acoustic nodes arranged along towed acoustic linear antennas. The network of acoustic nodes is adapted to determine inter-node distances allowing to locate the acoustic linear antennas. The method includes: obtaining a determined layout of the network of acoustic nodes; obtaining at least one marine environment property relating to an area of performance of a survey with the network of acoustic nodes; and quantifying the acoustic performances of the network of acoustic nodes, using a sound propagation model, the at least one marine environment property and the determined layout. | 2013-06-20 |
20130155810 | METHOD AND DEVICE FOR SEPARATING SEISMIC SIGNALS FROM SEISMIC SOURCES - System and method for actuating first and second marine acoustic sources in a firing sequence, the firing sequence including at least a first actuation of the first source followed by a first actuation of the second source followed by a second actuation of the first source and a second actuation of the second source. The method includes towing the first source at a depth in water substantially equal to a depth of the second source; establishing a series of reference time instants; actuating the first source with a variable first time delay relative to the series of reference time instants; and actuating the second source with a variable second time delay relative to the series of reference time instants such that time intervals between consecutive activations of the first and second sources are also variable. | 2013-06-20 |
20130155811 | WAVE-FIELDS SEPARATION FOR SEISMIC RECORDERS DISTRIBUTED AT NON-FLAT RECORDING SURFACES - Apparatus, computer instructions and method for separating up-going and down-going wave fields (U, D) from seismic data recorded within or beneath a body of water, or in general below the surface of the earth. The method includes a step of receiving seismic data (P | 2013-06-20 |
20130155812 | Using Higher Order Harmonics to Determine Acoustic Impedance of Material Behind Borehole Casings - An acoustic logging tool emits a wideband acoustic pulse toward an inside surface of a borehole casing and an acoustic response is received. The acoustic response is analyzed at one or more higher order harmonics of the thickness mode resonance of the casing to determine the acoustic impedance of the material behind the casing. | 2013-06-20 |
20130155813 | ITERATIVE DIP-STEERING MEDIAN FILTER FOR SEISMIC DATA PROCESSING - An iterative dip-steering median filter is provided for random noise attenuation in seismic data where conflicting dips are indicated in the data. A number of dominant dips inside a processing window or sample of the data are identified by a Fourier-radial transform in the frequency-wavenumber domain. A median filter is then applied along the dominant dip to remove noise, and the remaining signal after filtering is retained for further median filter iterations. Iterations are repeated to apply the median filter along the most dominant dip in the remaining data. The processing continues in subsequent iterations until all selected dips have been processed. The remaining signal of each iteration is then summed for final output. | 2013-06-20 |
20130155814 | CRITICAL REFLECTION ILLUMINATIONS ANALYSIS - The illumination/imaging of a theorized target horizon that is below a theorized velocity contrast horizon where the velocity contrast horizon may represent the bottom of a salt dome by assessing the path of seismic energy for critical angle reflection/refraction and tabulates the successful paths and unsuccessful paths. For some subsurface locations, seismic energy will not reach the surface above the velocity contrast due to the shapes of the velocity contrast horizon and target horizon and the velocity model through which the studied waves propagate. Displays may be prepared and used for understanding illumination/imaging of the geology for drilling, reacquisition, and reprocessing to elicit information about subsurface geology that may have been overlooked or ignored. Future surveys avoid expensive surveying which cannot obtain useful seismic data as determined by the velocity contrast for the target locations due to the shapes of the horizons and the velocity model. | 2013-06-20 |
20130155815 | METHOD AND APPARATUS FOR VERIFYING INFORMATION ASSOCIATED WITH ELECTRONIC LABELS - Embodiments are directed to methods and apparatuses for determining and verifying a location of an electronic label. A host system exchange information with the electronic label via ultrasonic data communication. The host system also identifies a location of the electronic label using an ultrasonic location technique. The host system also verifies that the electronic label is correctly located by comparing a calculated location of the electronic label with a known location of merchandise associated with the electronic label. | 2013-06-20 |
20130155816 | SYSTEMS AND METHODS FOR PREDICTING AN EXPECTED BLOCKAGE OF A SIGNAL PATH OF AN ULTRASOUND SIGNAL - A method includes detecting a signal at a first set of receivers of a plurality of receivers of a device. The plurality of receivers includes the first set of receivers and a second set of receivers. The first set of receivers corresponds to selected receivers and the second set of receivers corresponds to non-selected receivers. The method includes predicting, based on the signal, an expected blockage of a signal path between a source of the signal and a first selected receiver of the first set of receivers, and selecting a particular receiver of the second set of receivers as a newly selected receiver in response to predicting the expected blockage. | 2013-06-20 |
20130155817 | CELL, ELEMENT OF ULTRASONIC TRANSDUCER, ULTRASONIC TRANSDUCER INCLUDING THE SAME, AND METHOD OF MANUFACTURING CELL OF ULTRASONIC TRANSDUCER - An element of an ultrasonic transducer includes a first substrate, at least one cell of the ultrasonic transducer arranged above the first substrate, and a second substrate arranged under the first substrate, in which a first power supply for applying an electric signal to the first substrate is formed. | 2013-06-20 |
20130155818 | ELECTRONIC DEVICE, STORAGE MEDIUM AND METHOD FOR CONTROLLING AN ALARM FUNCTION OF THE ELECTRONIC DEVICE - In a method for controlling an alarm function of an electronic device, an alarm time, an alarm mode, a plurality of control modes of the alarm function and a shaking frequency and an audio file corresponding to each of the control modes are set. If a current time matches the alarm time, the alarm function is started by activating the alarm mode and a monitor unit is enabled to monitor acceleration values of the electronic device. A first shaking frequency in a first predetermined time limit is recorded according to the acceleration values. The control mode corresponding to the first shaking frequency is confirmed, and the audio file corresponding to the confirmed control mode is output. The method further controls the alarm function according to the confirmed control mode. | 2013-06-20 |
20130155819 | TIMEPIECE MOVEMENT WITH LOW MAGNETIC SENSITIVITY - The invention relates to a timepiece movement ( | 2013-06-20 |
20130155820 | MECHANISM FOR ADVANCING A KARUSSEL CAGE BY PERIODIC JUMPS - A mechanism for advancing, by periodic jumps, a cage of an escapement mechanism, including: a pivoting retaining mechanism authorizing or preventing pivoting of the cage, depending on whether the retaining mechanism is moving or not; and a stopping mechanism cooperating with the retaining mechanism to allow or prevent the pivoting of the retaining mechanism according to the position of the stopping mechanism. The trajectory of the retaining mechanism interferes with that of the stopping mechanism, both being external to the cage, and the retaining mechanism includes a flirt pinion carrying a flirt arranged to cooperate with the stopping mechanism and whose trajectory interferes with the stopping mechanism, the flirt pinion cooperating with a toothing of the cage, via an inverter wheel set. | 2013-06-20 |
20130155821 | SWITCH DEVICE AND WRISTWATCH - A switch device of the present invention includes a case having a through hole; a cylindrical member attached to the through hole of the case; and an operating member having a shaft section inserted into the cylindrical member and an operating section provided in an outer end portion of the shaft section, wherein the operating member is provided with an engaging projected section, and has a spring member, wherein the cylindrical member is provided with, in an end portion in an outer direction of the case, a release groove where the engaging projected section is movable in an axial direction, and a restricting projected section which restricts movement to the outer direction of the engaging projected section, wherein the cylindrical member is provided with a lock groove which locks the spring member. | 2013-06-20 |
20130155822 | METHOD OF MANUFACTURING A DECORATIVE ARTICLE, A DECORATIVE ARTICLE, AND A TIMEPIECE - A method of manufacturing a decorative article, including a first coating formation step of forming a first coating of primarily TiN on a substrate; a second coating formation step of forming a second coating on the first coating by means of a dry plating method using a target containing 70.0 wt %≦85.0 wt % Au and 15.0 wt %≦30.0 wt % Cu; a heat treatment step of promoting formation of a solid solution of the constituents of the second coating by applying a heating process that heats the substrate on which the first coating and the second coating are disposed to 300° C.≦395° C. and then applying a cooling process; and an acid treatment step that, of the constituents of the second coating to which the heating process was applied, removes the constituents not forming a solid solution by applying an acid treatment. | 2013-06-20 |
20130155823 | SMOOTH TIMEPIECE BEARING - Smooth timepiece bearing ( | 2013-06-20 |
20130155824 | OPTICAL DISC DEVICE AND OPTICAL DISC RECORDING METHOD - On the occasion of providing a guard track and additionally recording data in an optical disc provided with a guide layer having a physical groove structure for carrying out tracking servo control and not having a land/groove structure in recording layers carrying out recording and playback, it has sometimes occurred that it was difficult to reposition a light spot. Given that there are a recorded area and an unrecorded area in a recording layer, recording with respect to the concerned recording layer is taken to be impossible to implement when the recording capacity of the unrecorded area is less than a prescribed value. | 2013-06-20 |
20130155825 | RECORDING MEDIUM FOR LONG-TERM DATA RETENTION, RECORDING METHOD, AND RECORDING/REPRODUCING APPARATUS - Provided are recording media, recording/reproducing apparatuses, and recording methods for use in long-term data retention. Recording medium information may be copied and stored in a new information zone in a data area. Accordingly, if medium recognition of a lead-in area and/or a lead-out area fails, a recording medium may be recognized using the data recorded in the new information zone. | 2013-06-20 |
20130155826 | Data Recording Medium, Method for Generating a Reference Clock Signal, and Data Storage Device - Various embodiments provide a recording medium. The recording medium may include: a dedicated servo layer for providing servo information, wherein the dedicated servo layer comprises a plurality of tracks, wherein a first track comprises a first servo signal of a first frequency, wherein a second track comprises a second servo signal of a second frequency, and wherein the first servo signal and the second servo signal comprise a common single tone signal. | 2013-06-20 |
20130155827 | METHOD AND SYSTEM FOR DETERMINING THE QUALITY OF A STORAGE SYSTEM - In accordance with an exemplary embodiment of the present invention, a method for measuring a quality parameter of an optical storage system comprising a non-diffraction-limited optical storage medium and a readout device, the method comprising the process of deriving an impulse response of the optical storage system, and the process of analyzing the impulse response to determine at least one of a width of the impulse response and a skewness of the impulse response as the quality parameter. | 2013-06-20 |
20130155828 | RECORDING METHOD AND RECORDING APPARATUS - A recording method includes: generating a laser driving pulse, of which the number depends on a length of a mark which is formed, and where a pulse level of a pulse column at least in an intermediate pulse besides the lead pulse and the last pulse is sequentially decreased; performing laser emission, based on the laser driving pulse; and performing mark formation using thermal recording by laser irradiation on a recording medium. | 2013-06-20 |
20130155829 | RECORDING APPARATUS AND METHOD - A recording apparatus characterized in that comprising a firmware configured to execute the following operation: performing a recording operation onto a rewritable optical recording medium with a recording speed selected from one of a plurality of recording speeds for an one-time optical recording medium; wherein the recording layer of the rewritable optical recording medium comprises at least four elements from Ge, In, Sb, Te, and Sn, wherein the component proportion of Sb/Te is ranged from 3 to 8, and the thickness of the recording layer is ranged from 3 nm to 25 nm. | 2013-06-20 |
20130155830 | COPY-PROTECTED OPTICAL RECORDING MEDIUM, METHOD FOR DRIVING THEREOF AND METHOD FOR MANUFACTURING THEREOF - A copy-protected optical recording medium, a method for driving thereof and a method for manufacturing thereof, wherein the optical recording medium includes at least one region whose address is designated to be said same with that of other region of the medium. | 2013-06-20 |
20130155831 | METHOD AND APPARATUS FOR DETECTING RADIO SIGNAL - In an aspect, a method for transmitting data in a wireless communication system is provided. A wireless device determines a subcarrier and a subcarrier group to which a data sequence is allocated. The wireless device modulates the data sequence by a transmit filter to generate a data stream. A waveform of the transmit filter is determined based on the subcarrier and the subcarrier group. The wireless device generates a transmission signal based on the data stream. The wireless device transmits the transmission signal through the subcarrier. The transmission signal is cyclostationary. | 2013-06-20 |
20130155832 | Method and terminal for transmitting uplink control information and method and apparatus for determining the number of coded symbol - The disclosure discloses a method and terminal for transmitting uplink control information. The method includes: coding the uplink control information required to be transmitted and data information corresponding to one or two transport blocks respectively, obtaining an encoded sequence according to a target length, and forming a corresponding coded modulation sequence from the encoded sequence according to a modulation mode ( | 2013-06-20 |
20130155833 | APPARATUS AND METHOD FOR I/Q OFFSET CANCELLATION IN SC-FDMA SYSTEM - The present invention relates to an apparatus and a method for eliminating I/Q offset in a receiver of a SC-FDMA system which improves performance of the system by accurate measurement and cancellation of I/Q offset in a receiver of a SC-FDMA system operating in a | 2013-06-20 |
20130155834 | METHODS AND SYSTEMS FOR SCHEDULING A PREDICTED FAULT SERVICE CALL - Disclosed is a fault prediction system and method that uses non-fatal event data received from a terminal to make predictions concerning future fatal faults for the terminal and to schedule a predicted service call. A complex fault pattern associated with a fault is applied to the non-fatal event data to predict the fault. A corrective action is provided for each predicted fault and historical data is used to predict a time to the predicted fault to govern the type of service response to create to prevent the fault. | 2013-06-20 |
20130155835 | APPLIANCE IN A MOBILE DATA NETWORK THAT SPANS MULTIPLE ENCLOSURES - Mobile network services are performed in an appliance in a mobile data network in a way that is transparent to most of the existing equipment in the mobile data network. The mobile data network includes a radio access network and a core network. The appliance in the radio access network breaks out data coming from a basestation, and performs one or more mobile network services at the edge of the mobile data network based on the broken out data. The appliance has defined interfaces and defined commands on each interface that allow performing all needed functions on the appliance without revealing details regarding the hardware and software used to implement the appliance. This appliance architecture allows performing new mobile network services at the edge of a mobile data network within the infrastructure of an existing mobile data network. | 2013-06-20 |
20130155836 | Method and System for an Optimized Retransmission of a Message in a Satellite Communications Context - A communications method for retransmission of at least one fragment of a lost or erroneous message from a terminal to a gateway over a communications network comprising a plurality of terminals, communicating over a demand assignment multiple access and comprising a control centre allocating the communications resource to the terminals, comprises: detection, by the gateway, of fragments of lost or erroneous messages and, when at least one fragment is detected, notification via the gateway to the control centre of the loss of at least one fragment; calculation, by the control centre, of a second allocation plan taking into account a new transmission of the fragment; notification by the gateway to the terminal of the loss of the fragment and notification by the control centre to the terminal of the second allocation plan; transmission by the terminal of the lost fragment according to the second allocation plan to the gateway. | 2013-06-20 |
20130155837 | Selecting a Master Processor From an Ambiguous Peer Group - A distributed switch may include a plurality of special-purpose processors that control the different functions of the switch. To enable some special services, however, the distributed switch may need one of these processors to perform the role of a master. When a processor is powered on, the processor may publish a corresponding unique ID. Before electing the master, the special-purpose processors may use a discovery process to identify the network topology of the switch and evaluate the published IDs to determine which processor should be the master. If all the processors nominate the same master processor, then that processor is elected as the master and may finish configuring the distributed switch to enable the special services. | 2013-06-20 |
20130155838 | SCALING CONTENT COMMUNICATED OVER A NETWORK - An architecture is provided that can scale content resolution in order to mitigate errors in a provisioned service of a communication network, such as a wireless service or a femtocell service that integrates with DSL or other broadband carriers. The architecture can identify fault conditions relating to e.g., bandwidth oversubscription or symbolization integrity. Based upon such identification, the architecture can alter encoding format codecs of certain types of content in order to reduce their resolution/quality, thereby mitigating bandwidth oversubscription fault conditions or freeing up space (without necessarily increasing bandwidth) to insert additional FEC code. | 2013-06-20 |
20130155839 | METHOD OF PROVIDING AN MMoIP COMMUNICATION SERVICE - One or more MMoIP packet streams are transmitted via a connection established between a first and second endpoint of an IP communication network. The one or more MMoIP packet streams include MMoIP payload data and/or control data. Control data directed to a processor is inserted in at least one MMoIP packet stream of the one or more MMoIP packet streams at the first endpoint and/or the second endpoint. The one or more MMoIP packet streams are transmitted via an MMoIP switch of the IP communication network. The MMoIP switch monitors the one or more MMoIP packet streams. The MMoIP switch detects the control data directed to the processor. The MMoIP switch forwards the detected control data to the processor. | 2013-06-20 |
20130155840 | Bandwidth management for MPLS fast rerouting - Certain exemplary embodiments provide a method comprising: in a network at a node located on a label switched path: selecting a backup path to respond to a failure; and for each link along the backup path, reserving a backup bandwidth, wherein the backup bandwidth is sufficient to reroute traffic around the failure. | 2013-06-20 |
20130155841 | SELECTING A MASTER PROCESSOR FROM AN AMBIGUOUS PEER GROUP - A distributed switch may include a plurality of special-purpose processors that control the different functions of the switch. To enable some special services, however, the distributed switch may need one of these processors to perform the role of a master. When a processor is powered on, the processor may publish a corresponding unique ID. Before electing the master, the special-purpose processors may use a discovery process to identify the network topology of the switch and evaluate the published IDs to determine which processor should be the master. If all the processors nominate the same master processor, then that processor is elected as the master and may finish configuring the distributed switch to enable the special services. | 2013-06-20 |
20130155842 | METHOD AND SYSTEM FOR PROVIDING MOBILE WIRELESS CALL FAILOVER - An approach for call failover to a packetized voice session is described. Impending signal failure is detected on a cellular link supporting a cellular call with a user device. A failover procedure is initiated in response to the detection, wherein the failover procedure includes detecting presence of a wireless data connection, and terminating the cellular call and concurrently activating a voice call application to establish a packetized voice session over the wireless data connection with the user device. | 2013-06-20 |
20130155843 | AUTONOMIC ERROR RECOVERY FOR A DATA BREAKOUT APPLIANCE AT THE EDGE OF A MOBILE DATA NETWORK - A mechanism provides autonomic recovery for a breakout appliance at the edge of a mobile data network from a variety of errors using a combination of hardware, software and network recovery actions. The recovery actions proceed upon a sliding scale depending on the severity of the problem to achieve the goals of minimizing disruption to traffic flowing through the NodeB while also maintaining an acceptable cost of ownership/maintenance of the system by automatically recovering from as many problems as possible. The error recovery functions within the breakout system hide the error recovery complexities from the management system upstream in the mobile data network. For critical, non-recoverable errors, the autonomic recovery mechanism works in conjunction with a fail-to-wire module to remove the breakout system in the event of a failure in such a way that the mobile data network functions as if the breakout system is no longer present. | 2013-06-20 |
20130155844 | PROTECTION SWITCHING METHOD, SYSTEM AND A NODE IN AN LTE NETWORK - The present invention relates to a protection switching method, system and a node in an LTE network. In one embodiment this is accomplished by a plurality of base transceiver station (BTS) linked by the network over which the base transceiver stations communicate, wherein the network includes at least one primary BTS and at least two secondary BTS, and wherein each BTS includes at least two bidirectional antennas, provisioning traffic to at least one secondary BTS as work BTS for backhauling the traffic, wherein the traffic includes user data traffic, control and signaling data traffic from the primary BTS, checking periodically for control signal by all the BTS, wherein the control signals are periodically transmitted and received by all the BTS directly or indirectly via another secondary BTS to check the status of wireless link, transparently and steering, upon failure of the work wireless X2 link between the primary BTS and the secondary BTS, the beam of the primary BTS appropriately to the next available BTS as protect BTS, wherein the steering is based on the computed pre-coder vector value at the primary BTS. | 2013-06-20 |
20130155845 | METHOD FOR PROVIDING BORDER GATEWAY PROTOCOL FAST CONVERGENCE ON AUTONOMOUS SYSTEM BORDER ROUTERS - Techniques are disclosed for providing fast convergence on Autonomous System Border Routers (ASBRs). In an embodiment, an ASBR receives first Virtual Private Network (VPN) route information including a first route target, a first route distinguisher, and a first network prefix and second VPN route information including a second route target, a second route distinguisher and a second network prefix. The second route distinguisher received by the ASBR is different than the first route distinguisher. The ASBR compares the first route target to the second route target and the first network prefix with the second network prefix. In response to determining that the first route target matches the second route target and the first network prefix matches the second network prefix, the ASBR associates, in a routing table, a first path based on the first VPN route information with a second path based on the second VPN route information. | 2013-06-20 |
20130155846 | Active Standby Virtual Port-Channels - An active-standby virtual port channel mechanism may be provided, where at any point only one virtual port channel link would be active. Upon failover of the active, a fast failover mechanism is employed to move active traffic to a standby port channel link. | 2013-06-20 |
20130155847 | METHODS AND APPARATUS TO ENHANCE RELIABILITY IN MILLIMETER WAVE WIDEBAND COMMUNICATIONS - A network node in a wireless network performs a method for enhancing reliability in wireless communication. The method includes determining, at a first network node, that a current link with a second network node is broken. The method also includes attempting, at the first network node, to recover the current link. The method further includes, upon a determination that the current link is not recoverable, establishing, at the first network node, a new link with the second network node according to one of a plurality of switching rules, the switching rules ordered according to a priority among the switching rules. | 2013-06-20 |
20130155848 | LINK ADAPTATION IN WIRELESS NETWORKS - An embodiment of a system for physical link adaptation in a wireless communication network such as e.g., a WLAN, selectively varies the physical mode of operation of the transmission channels serving the mobile stations in the network. The system includes an estimation module to evaluate transmission losses due to collisions as well as transmission losses due to channel errors over the transmission channel, and an adaptation module to select the physical mode of operation of the transmission channel as a function of the transmission losses due to collisions and to channel errors as evaluated by the estimation module. | 2013-06-20 |
20130155849 | SYSTEM AND METHOD FOR RESOURCE MANAGEMENT FOR OPERATOR SERVICES AND INTERNET - A method is provided in one example embodiment and includes providing a multi-radio connectivity service to a mobile subscriber, and managing the multi-radio connectivity service for the mobile subscriber. The managing can include: providing admission control; providing privileged subscriber access at a plurality of WiFi access points; providing signaling for quality of service (QoS) equivalence across a WiFi network and a mobile network; and distributing certain traffic based on a policy. | 2013-06-20 |
20130155850 | BUFFER OCCUPANCY BASED RANDOM SAMPLING FOR CONGESTION MANAGEMENT - A method for buffer occupancy based congestion management includes receiving, by a computing device, a data stream including a plurality of packets from a plurality of sources and storing the packets in a buffer that includes multiple storage units. The method also includes determining if the buffer is congested, responsive to determining that the buffer is congested randomly selecting an occupied unit of the buffer and determining the source of the packet stored in the occupied unit of the buffer and sending a congestion notification message to the source of the packet stored in the occupied unit of the buffer. | 2013-06-20 |
20130155851 | SYSTEM AND METHOD FOR RESOURCE MANAGEMENT FOR OPERATOR SERVICES AND INTERNET - A method is provided in one example embodiment and includes providing a multi-radio connectivity service to a mobile subscriber, and managing the multi-radio connectivity service for the mobile subscriber. The managing can include: providing admission control; providing privileged subscriber access at a plurality of WiFi access points; providing signaling for quality of service (QoS) equivalence across a WiFi network and a mobile network; and distributing certain traffic based on a policy. | 2013-06-20 |
20130155852 | Systems and Methods for Resource Booking for Admission Control and Scheduling Using DRX - Systems and methods provide for performing admission control in a communications network. The method includes: receiving a request for an entity or service for admission to the communications network; calculating resources, wherein the step of calculating resources includes: estimating a first future resource use for current entities and services in the communications network; and estimating a second future resource use for the entity or service received in the request; determining admission to the communications network of the received request based at least in part on the step of calculating resources; and using a partitionable booking window, if admission is allowed for the received request, for booking the first and second future resource uses based at least in part on the step of calculating resources. | 2013-06-20 |
20130155853 | HIERARCHICAL OCCUPANCY-BASED CONGESTION MANAGEMENT - A system for hierarchical occupancy based congestion management includes a buffer embodied in a computer readable storage medium including a plurality of buffer units for storing packets of a data flow received from sources. The system includes a buffer manager that stores information about the packets stored in the buffer, including a selection criterion associated with each of the plurality of sources and a congestion estimator that monitors a congestion level in the buffer. The system also includes a occupancy sampler that randomly selects at least two occupied buffer units from the plurality of buffer units and identifies the source of the packet stored in each of the occupied buffer units and a congestion notification message generator that generates a congestion notification message; wherein if the congestion level in the buffer exceeds a threshold value the congestion notification message is sent to the identified source with a higher selection criteria. | 2013-06-20 |
20130155854 | Multi-Tier Polling - A polling arrangement where polling frequency and/or rates may be adjusted according to activities of end stations or other elements being polled. The ability to adjust the polling activities may be used to facilitate reducing or otherwise controlling network resources allocated to the supporting the polling or other messaging depending operations. | 2013-06-20 |
20130155855 | Increasing Efficiency of Admission Control in a Network - An apparatus and a method is provided, by which a penetration of terminals supporting a congestion indication scheme in a network or a part of the network is determined, and a load threshold is dynamically adjusted according to the penetration of terminals supporting a congestion indication scheme, wherein the load threshold is used for controlling load in the network or the part of the network. | 2013-06-20 |
20130155856 | Method and Network Node For Handling TCP Traffic - The embodiments herein relate to a method in a network node ( | 2013-06-20 |
20130155857 | HYBRID ARRIVAL-OCCUPANCY BASED CONGESTION MANAGEMENT - A method for hybrid arrival-occupancy based congestion management includes increasing a recent arrivals counter associated with a data flow from one or more sources in response to receiving a data packet from one of the sources and storing the data packet in a buffer including multiple storage units. The method includes determining if a buffer is congested, randomly selecting an occupied unit of the buffer and determining the source of the packet stored in the occupied unit of the buffer, generating a congestion notification message, sending the congestion notification message to the source of the packet stored in the occupied unit of the buffer if the recent arrivals counter exceeds a threshold value and decreasing the recent arrivals counter associated with the source of the packet stored in the occupied unit of the buffer and discarding the congestion notification message if the recent arrivals counter has a zero value. | 2013-06-20 |
20130155858 | HIERARCHICAL OCCUPANCY-BASED CONGESTION MANAGEMENT - A method for hierarchical occupancy based congestion management includes receiving, by a computing device, a plurality of data flows, each of the plurality of data flows is received from a source and includes a plurality of data packets and storing the plurality of data packets in a buffer including multiple storage units. The method includes determining if the buffer is congested, responsive to determining the buffer is congested randomly selecting at least two occupied units of the buffer and identifying a source of each of the data packets stored in the occupied units of the buffer and generating a congestion notification message. The method also includes comparing a selection criterion associated with each identified source to determine which identified source has a higher selection criterion and sending the congestion notification message to the identified source with the higher selection criterion. | 2013-06-20 |
20130155859 | System and Method for Hierarchical Adaptive Dynamic Egress Port and Queue Buffer Management - A system and method for hierarchical adaptive dynamic egress port and queue buffer management. Efficient utilization of buffering resources in a commodity shared memory buffer switch is key to minimizing packet loss. Efficient utilization of buffering resources is enabled through adaptive queue limits that are derived from an adaptive port limit. | 2013-06-20 |
20130155860 | PACKET TRANSMISSION DEVICE AND METHOD OF TRANSMITTING PACKET - The inventive concept relates to a method of managing a packet being transmitted through a packet transmission network. The method may include distinguishing a buffer unit corresponding to the received data packet among a plurality of buffer units according to a type of a data packet received from the outside; comparing the number of packets stored in the distinguished buffer unit with a critical value; storing the received data packet in the distinguished buffer unit or a sub buffer unit corresponding to the distinguished buffer unit according to the comparing result; and transmitting the data packet stored in the distinguished buffer unit through a working path of the backbone network and transmitting the data packet stored in the sub buffer unit through a protection path of the backbone network. | 2013-06-20 |
20130155861 | CONTENT SERVICE AGGREGATION SYSTEM - A network content service apparatus includes a set of compute elements adapted to perform a set of network services; and a switching fabric coupling compute elements in said set of compute elements. The set of network services includes firewall protection, Network Address Translation, Internet Protocol forwarding, bandwidth management, Secure Sockets Layer operations, Web caching, Web switching, and virtual private networking. Code operable on the compute elements enables the network services, and the compute elements are provided on blades which further include at least one input/output port. | 2013-06-20 |
20130155862 | PERFORMING RATE LIMITING WITHIN A NETWORK - Methods and systems for performing rate limiting are provided. According to one embodiment, information is maintained regarding a set of virtual networks into which a network has been logically divided. Each virtual network comprises a loop-free switching path, reverse path learning network and provides a path through the network between a first and second component thereby collectively providing multiple paths between the first and second components. Packets are received by the first component that are associated with a flow sent by a source component. The packets are forwarded by the first component to the second component along a particular path defined by the set of virtual networks. A congestion metric is determined for the particular path and based thereon it is determined whether a congestion threshold has been reached. Responsive to an affirmative determination, the source component is instructed to limit the rate at which the packets are sent. | 2013-06-20 |
20130155863 | Adaptation of Quality of Service in Handling Network Traffic - For allowing differentiated handling of network traffic, a message is received by a traffic type detector. The traffic type detector extracts a network label, e.g. a domain name, a hostname, or a network address, from the message and compares this extracted network label to one or more stored network labels. On the basis of the comparison, adaptation of a quality of service level for a forwarding treatment of data packets associated with the message is initiated, e.g. by controlling a bearer used for communicating the data packets. | 2013-06-20 |
20130155864 | WIRELESS TERMINAL, WIRELESS COMMUNICATION METHOD, AND WIRELESS COMMUNICATION SYSTEM - There is provided a wireless terminal including a storage section that stores information on a plurality of wireless terminals forming a group in which the wireless terminal operates as a representative wireless terminal, a communication control section that controls random access to a base station before another wireless terminal in the group, and a transmitting section that transmits the information on the plurality of wireless terminals stored in the storage section to the base station. | 2013-06-20 |