25th week of 2019 patent applcation highlights part 66 |
Patent application number | Title | Published |
20190189555 | BINARY METALLIZATION STRUCTURE FOR NANOSCALE DUAL DAMASCENE INTERCONNECTS - A structure is provided that includes a lower interconnect level that includes a first interconnect dielectric material layer having an opening that contains a first bimetallization interconnect structure. An upper interconnect level is located above the lower interconnect level. The upper interconnect level includes a second interconnect dielectric material layer having a combined via/line opening, wherein the line portion of the combined via/line opening contains a second bimetallization interconnect structure. In accordance with the present application, the first and second bimetallization interconnect structures comprises a first electrically conductive structure composed of a first electrically conductive metal or metal alloy material having a first bulk resistivity surrounding a second electrically conductive structure composed of a second electrically conductive metal or metal alloy material having a second bulk resistivity that is less than the first bulk resistivity and a grain size greater than 10 nm. | 2019-06-20 |
20190189556 | VARIABLE INDUCTOR AND INTEGRATED CIRCUIT USING THE VARIABLE INDUCTOR - A variable inductor which comprises a primary conductor, first and second secondary conductors and one or more switch. The primary conductor has a first node and a second node, wherein the first node is used to connect a first external component and the second node is used to connect a second external component. The first and second secondary conductors magnetically couple to the primary conductor. The one or more switch has two sides connected to the first or second secondary conductor, respectively. The first and second secondary conductors are formed a single-loop structure with two or more changeable current paths which are operated by the states of the one or more switch. An integrated circuit using the variable inductor is also introduced. | 2019-06-20 |
20190189557 | TRANSFORMER, TRANSFORMER MANUFACTURING METHOD AND SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor substrate, an insulating layer, a transformer formed in the insulating layer, and a wiring. The transformer includes a primary winding conductor, and a secondary winding conductor. The primary winding conductor is provided in a quadrangle spiral shape having a first center axis extending in a direction parallel to the surface of the semiconductor substrate inside the insulating layer, and configured by one conductor film selected from a group consisting of a vacuum deposition film, a chemical vapor deposition film and a sputtered film. The secondary winding conductor is provided in a quadrangle spiral shape having a second center axis inside the insulating layer while being spaced from the primary winding conductor in plan view of the semiconductor substrate, magnetically coupled with the primary winding conductor and configured by a conductor film. | 2019-06-20 |
20190189558 | BEOL EMBEDDED HIGH DENSITY VERTICAL RESISTOR STRUCTURE - Embedded resistors which have tunable resistive values located between interconnect levels are provided. The embedded resistors have a pillar structure, i.e., they have a height that is greater than their width, thus they occupy less real estate as compared with conventional planar resistors that are typically employed in BEOL technology. | 2019-06-20 |
20190189559 | ANTI-FUSE DEVICE, MEMORY DEVICE INCLUDING THE SAME AND SEMICONDUCTOR DEVICE COMPRISING AN ANTI-FUSE DEVICE - An anti-fuse device includes a program transistor and a read transistor. The program transistor executes a program via insulation breakdown of a gate insulating layer. The read transistor is adjacent to the program transistor and reads the state of the program transistor. At least one of a first gate electrode of the program transistor or a second gate electrode of the read transistor is buried in a substrate. | 2019-06-20 |
20190189560 | HIGH BANDWIDTH ROUTING FOR DIE TO DIE INTERPOSER AND ON-CHIP APPLICATIONS - Routing structures including signal routing between die areas is described. In an embodiment, routing structures include signal lines with a characteristic thickness that is greater than a width. The signal lines may be twisted, and run directly underneath pads. | 2019-06-20 |
20190189561 | SEMICONDUCTOR DEVICE AND METHOD WITH MULTIPLE REDISTRIBUTION LAYER AND FINE LINE CAPABILITY - A semiconductor device includes a semiconductor die and a substrate having a first surface and a second surface. The semiconductor die is attached to the second surface. The substrate includes a layer of insulative material and an embedded conductive circuit in the layer of insulative material. The embedded conductive circuit includes an etched layer of a conductive material. The etched layer of the conductive material is located on the first surface of the substrate. The etched layer of the conductive material is made of a first metallic material and the embedded conductive circuit is made of a second metallic material that is different than the first metallic material. | 2019-06-20 |
20190189562 | SYSTEM ON INTEGRATED CHIPS AND METHODS OF FORMING THE SAME - A semiconductor device and methods of forming are provided. The method includes bonding a second die to a surface of a first die. The method includes encapsulating the second die in an isolation material, and forming a through via extending through the isolation material. The method also includes forming a first passive device in the isolation material. | 2019-06-20 |
20190189563 | PANEL LEVEL PACKAGING FOR MULTI-DIE PRODUCTS INTERCONNECTED WITH VERY HIGH DENSITY (VHD) INTERCONNECT LAYERS - A foundation layer and methods of forming a conductive via are described. A die pad is formed over a die. A seed layer is deposited over the die pad and the foundation layer. A first photoresist layer is deposited over the seed layer, and the first layer is patterned to form a conductive line opening over the die pad. A conductive material is deposited into the conductive line opening to form a conductive line. A second photoresist layer is deposited over the first layer, and the second layer is patterned to form a via opening over the conductive line. The conductive material is deposited into the via opening to form the conductive via, where the conductive material only deposits on portions of exposed conductive line. The second and first layers are removed. Portions of exposed seed layer are recessed, and then a top surface of the conductive via is exposed. | 2019-06-20 |
20190189564 | EMBEDDED DIE ON INTERPOSER PACKAGES - Integrated circuit (IC) packages having a through-via interposer with an embedded die, as well as related structures, devices, and methods, are disclosed herein. For example, in some embodiments, an IC package may include a through-via interposer with an embedded die, the through-via connections having front to back conductivity. In some embodiments, a die may be disposed on the back side of an IC package having a through-via interposer with an embedded die and may be electrically coupled to the embedded die. In some embodiments, a second IC package in a package-on-package (PoP) arrangement may be disposed on the back side of an IC package having a through-via interposer with an embedded die and may be electrically coupled to the conductive vias. | 2019-06-20 |
20190189565 | SEMICONDUCTOR DEVICE PACKAGE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device package includes a substrate, a first electronic component, a first package body, an electrical contact and a first conductive layer. The substrate has a first surface, a second surface and a lateral surface extending between the first surface and the second surface. The first electronic component is disposed on the first surface of the substrate. The first package body encapsulates the first electronic component. The electrical contact is disposed on the second surface of the substrate. The first conductive layer includes a first portion and a second portion. The first portion is disposed on the first package body and the lateral surface of the substrate. The second portion contacts the electrical contact. | 2019-06-20 |
20190189566 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE - An exemplary semiconductor device can comprise a die, a redistribution structure (RDS), an interconnect, a conductive strap, an encapsulant, and an EMI shield. The redistribution structure can comprise an RDS top surface coupled to the die bottom side. The interconnect can be coupled to the RDS bottom surface. The conductive strap can be coupled to the RDS, and can comprise a strap inner end coupled to the RDS bottom surface, and a strap outer end located lower than the RDS bottom surface. The encapsulant can encapsulate the conductive strap and the RDS bottom surface. The EMI shield can cover and contact the encapsulant sidewall and the strap outer end. Other examples and related methods are also disclosed herein. | 2019-06-20 |
20190189567 | ROBUST MOLD INTEGRATED SUBSTRATE - An apparatus, comprising an Integrated Circuit (IC) package comprising a dielectric, the IC package has a first surface and an opposing second-surface, wherein the first surface is separated from the second surface by a thickness of the IC package, wherein sidewalls extend along a perimeter and through the thickness between the first surface and the second surface, and a structure comprising a frame that extends at least partially along the perimeter of the IC package, wherein the structure extends at least through the thickness of the IC package and inwardly from the sidewalls of the IC package. | 2019-06-20 |
20190189568 | SEMICONDUCTOR CHIP - A semiconductor chip is provided. The semiconductor chip includes at least one interlayer dielectric layer, a transmission pattern and a stress absorption structure. The at least one interlayer dielectric layer is disposed on a substrate. The transmission pattern is disposed on the at least one interlayer dielectric layer and within a peripheral region of the semiconductor chip. The transmission pattern is electrically connected to an external signal source. The stress absorption structure is disposed in the at least one interlayer dielectric layer within the peripheral region, and electrically connected to the transmission pattern. The stress absorption structure is covered by the transmission pattern. | 2019-06-20 |
20190189569 | SEMICONDUCTOR PACKAGE HAVING HIGH MECHANICAL STRENGTH - A semiconductor wafer is singulated to form a plurality of semiconductor packages. The semiconductor wafer has a semiconductor substrate, a metal layer, an adhesive layer, a rigid supporting layer, a passivation layer and a plurality of contact pads. A semiconductor package has a semiconductor substrate, a metal layer, an adhesive layer, a rigid supporting layer, a passivation layer and a plurality of contact pads. A thickness of the rigid supporting layer is larger than a thickness of the semiconductor substrate. A thickness of the metal layer is thinner than the thickness of the semiconductor substrate. An entirety of the rigid supporting layer may be made of a single crystal silicon material or a poly-crystal silicon material. The single crystal silicon material or the poly-crystal silicon material may be fabricated from a reclaimed silicon wafer. An advantage of using a reclaimed silicon wafer is for a cost reduction. | 2019-06-20 |
20190189570 | CAPACITOR METAL GUARD RING FOR MOISTURE INGRESSION PREVENTION - A semiconductor die includes at least one electronic component. an at least partially moisture permeable material disposed on or about the at least one electronic component, at least one opening defining at least one path for moisture to migrate from an environment external to the die into the at least partially moisture permeable material, and a moisture impermeable shield disposed between the at least one electronic component and the at least one opening. | 2019-06-20 |
20190189571 | TIMING BASED CAMOUFLAGE CIRCUIT - In one embodiment, a chip comprising a circuit, the circuit comprising a plurality of components, wherein the circuit is adapted to perform a function that is dependent on timing behavior of the circuit, and wherein a geometry of a layout of the circuit is substantially the same as another geometry of another layout of another circuit adapted to perform another function that is dependent on different timing behavior. | 2019-06-20 |
20190189572 | MULTI-BAND ANTENNA PACKAGE STRUCTURE, MANUFACTURING METHOD THEREOF AND COMMUNICATION DEVICE - A multi-band antenna package structure includes a first redistribution layer; an integrated circuit layer, formed on the first redistribution layer, comprising at least one metal via, at least one metal pillar, an integrated circuit chip, and a molding layer, wherein the molding layer is used to fill openings formed by the metal via, the metal pillar and the integrated circuit chip which are disposed on the first redistribution layer, the metal via is electrically connected to one of the first metal patterns of the first redistribution layer; a second redistribution layer, formed on the integrated circuit layer; and a first antenna unit layer, comprising a first dielectric layer and third metal patterns formed in openings of the first dielectric layer, wherein at least one of the third metal patterns is electrically connected to one of the second metal patterns, and the third metal patterns form a first antenna unit. | 2019-06-20 |
20190189573 | DISPLAY SUBSTRATE, PRODUCTION METHOD THEREOF, AND DISPLAY APPARATUS - This disclosure provides a display substrate, a production method thereof, and a display apparatus. The display substrate comprises: a display area; and a pad area outside the display area. The pad area comprises at least one pad. The pad comprises: a metal layer, which comprises a first metal sublayer and a second metal sublayer laminated on the first metal sublayer, wherein a corrosion resistance of the second metal sublayer is stronger than that of the first metal sublayer; and a conductive material layer, which covers a side surface of the metal layer. | 2019-06-20 |
20190189574 | Semiconductor Chip and Method for Forming a Chip Pad - A semiconductor chip with different chip pads and a method for forming a semiconductor chip with different chip pads are disclosed. In some embodiments, a semiconductor chip includes a chip front side, a first chip pad located on the chip front side, a second chip pad located on the chip front side and an electrically insulating material located between the first chip pad and the second chip pad, wherein the first chip pad includes a surface layer predominantly comprising copper and the second chip pad includes a surface layer predominantly comprising aluminum. | 2019-06-20 |
20190189575 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE - A semiconductor device ( | 2019-06-20 |
20190189576 | SEMICONDUCTOR DEVICES HAVING DISCRETELY LOCATED PASSIVATION MATERIAL, AND ASSOCIATED SYSTEMS AND METHODS - Semiconductor devices having discretely located passivation material are disclosed herein. In one embodiment, a semiconductor device assembly can include a bond pad having a bonding surface with a process artifact. A passivation material can be positioned to at least partially fill a portion of the process artifact. A conductive structure can be positioned to extend across the bonding surface of the bond pad. | 2019-06-20 |
20190189577 | PACKAGE STRUCTURE AND METHOD FOR FORMING THE SAME - A package structure is provided. The package structure includes a first bump structure formed over a substrate, a solder joint formed over the first bump structure and a second bump structure formed over the solder joint. The first bump structure includes a first pillar layer formed over the substrate and a first barrier layer formed over the first pillar layer. The first barrier layer has a first protruding portion which extends away from a sidewall surface of the first pillar layer, and a distance between the sidewall surface of the first pillar layer and a sidewall surface of the first barrier layer is in a range from about 0.5 μm to about 3 μm. The second bump structure includes a second barrier layer formed over the solder joint and a second pillar layer formed over the second barrier layer, wherein the second barrier layer has a second protruding portion which extends away from a sidewall surface of the second pillar layer. | 2019-06-20 |
20190189578 | FINGERPRINT CHIP PACKAGING METHOD AND FINGERPRINT CHIP PACKAGE - A fingerprint chip packaging method and a fingerprint chip package are provided. During a process of packaging a fingerprint chip, the fingerprint chip is directly packaged and protected by a mold compound layer to form a thin package. With the fingerprint chip packaging method and the fingerprint chip package, the thickness of the package is greatly reduced, which facilitates miniaturization of the electronic device. Further, since the mold compound layer formed after curing of a mold compound material has a great mechanical strength, the mold compound layer can serve as a carrier substrate for mounting other electronic components of the electronic device, such that the integration of the electronic device is greatly improved, the space of the circuit board is saved, thereby facilitating the miniaturization of the electronic device. | 2019-06-20 |
20190189579 | SEMICONDUCTOR PACKAGE - A semiconductor package includes: a connection member having a first surface and a second surface opposing each other in a stacking direction of the semiconductor package and including an insulating member and a redistribution layer formed on the insulating member and having a redistribution via; a semiconductor chip disposed on the first surface of the connection member and having connection pads connected to the redistribution layer; an encapsulant disposed on the first surface of the connection member and encapsulating the semiconductor chip; a passivation layer disposed on the second surface of the connection member; UBM pads disposed on the passivation layer and overlapping the redistribution vias in the stacking direction; and UBM vias connecting the UBM pads to the redistribution layer through the passivation layer, not overlapping the redistribution vias with respect to the stacking direction, and having a non-circular cross section. | 2019-06-20 |
20190189580 | THERMAL SHUNTS AND THERMAL MANAGEMENT IN MONOLITHIC MICROWAVE INTEGRATED CIRCUITS - A method for fabricating an electronic device includes fabricating a plurality of electronic components on a substrate; fabricating a plurality of posts on the plurality of electronic components; depositing filling material between the plurality of posts; and depositing a plurality of top layers, with each top layer disposed on a respective post, thereby fabricating the electronic device. Each top layer is composed of a metal. The step of fabricating the posts includes: fabricating the posts to have identical heights above the substrate. Each post is thermally-conductive, and may be composed of gold. The filling material is composed of MgO, which may be electron beam evaporated to be disposed between the posts. The step of depositing the filling material includes: controlling a thickness of the MgO being deposited by controlling an evaporation rate of the MgO. | 2019-06-20 |
20190189581 | DUAL SOLDER METHODOLOGIES FOR ULTRAHIGH DENSITY FIRST LEVEL INTERCONNECTIONS - An apparatus, comprising an integrated circuit (IC) package having at least one solder bond pad, a die having at least one solder bond pad, wherein the die is bonded to the IC package by at least one solder joint between the at least one solder bond pad of the die, and the at least one solder bond pad of the IC package, and an underfill material between the IC package and the die, wherein the at least one solder joint is embedded in the underfill material, and wherein the at least one solder joint comprises a first metallurgy and a second metallurgy. | 2019-06-20 |
20190189582 | INDIUM SOLDER METALLURGY TO CONTROL ELECTRO-MIGRATION - Embodiments are generally directed to indium solder metallurgy to control electro-migration. An embodiment of an electronic device includes a die; and a package substrate, wherein the die is bonded to the package substrate by an interconnection. The interconnection includes multiple interconnects, and wherein the interconnection includes a solder. The solder for the interconnection includes a combination of tin (Sn), copper (Cu), and indium (In). | 2019-06-20 |
20190189583 | SEMICONDUCTOR PACKAGE - A semiconductor package includes a core member having a cavity penetrating through first and second surfaces, a semiconductor chip disposed in the cavity and having an active surface having connection, a passive component module disposed in the cavity, including a plurality of passive components and a resin portion encapsulating the plurality of passive components, and having a mounting surface from which connection terminals of the passive components are exposed, a connection member on the second surface and including a redistribution layer connected to the connection pads of the semiconductor chip and connection terminals of some of the plurality of passive components, connection terminals of the others of the plurality of passive components not being connected to the redistribution layer. | 2019-06-20 |
20190189584 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - According to one embodiment, semiconductor device includes a semiconductor layer, an electrode provided on the semiconductor layer, and a bonding wire connected to the electrode, wherein the electrode comprises a first metal layer containing copper, a second metal layer containing aluminum, provided between the first metal layer and the semiconductor layer, and a third metal layer provided between the first metal layer and the second metal layer, the third metal layer comprising a material different from those of the first metal layer and the second metal layer, and the thickness of the first metal layer is larger than the thickness of the second metal layer and larger than the thickness of the third metal layer. | 2019-06-20 |
20190189585 | OVERLAPPING STACKED DIE PACKAGE WITH VERTICAL COLUMNS - Some forms relate to an electronic assembly that includes a die that includes an upper surface and a conductive column extending from the upper surface such that the conductive column is not surrounded by any material other than where the conductive column engages the die. Other forms relate to an electronic package that includes a stack of electronic assemblies where each electronic assembly includes a die that having an upper surface and a plurality of conductive columns extending from the upper surface such that each conductive column is not surrounded by any material other than where the conductive column engages the die, and wherein the stack of electronic assemblies is arranged in an overlapping configuration such the plurality of conductive columns on each electronic assembly are not covered by another electronic assembly. | 2019-06-20 |
20190189586 | COMPONENT JOINING APPARATUS, COMPONENT JOINING METHOD AND MOUNTED STRUCTURE - A component joining apparatus, which can realize positioning between a component and a substrate with high accuracy by avoiding influence of thermal expansion of the substrate at the time of joining the component to the substrate by heating at a high temperature, includes a component supply head holding a component and a heating stage heating and holding a substrate, in which a heating region where the heating stage contacts the substrate includes a joining region of the substrate in which the component is joined, and the substrate is larger than the heating stage and a peripheral part of the substrate does not contact the heating stage. | 2019-06-20 |
20190189587 | BONDING DEVICE - A bonding device ( | 2019-06-20 |
20190189588 | DIE PROCESSING - Representative implementations provide techniques and systems for processing integrated circuit (IC) dies. Dies being prepared for intimate surface bonding (to other dies, to substrates, to another surface, etc.) may be processed with a minimum of handling, to prevent contamination of the surfaces or the edges of the dies. The techniques include processing dies while the dies are on a dicing sheet or other device processing film or surface. Systems include integrated cleaning components arranged to perform multiple cleaning processes simultaneously. | 2019-06-20 |
20190189589 | FAN-OUT SEMICONDUCTOR PACKAGE - A fan-out semiconductor package includes: a core member having a first through-hole and including first and second wiring layer disposed on different levels; a first semiconductor chip disposed in the first through-hole; a second semiconductor chip disposed on the first semiconductor chip in the first through-hole so that a second inactive surface faces a first inactive surface; conductive wires disposed on the core member and a second active surface and electrically connecting second connection pads and the second wiring layer to each other; an encapsulant covering at least portions of the core member, the first semiconductor chip, the second semiconductor chip, and the conductive wires and filling at least portions of the first through-hole; and a connection member disposed on the core member and a first active surface and electrically connecting first connection pads and the first wiring layer to each other. | 2019-06-20 |
20190189590 | STACKED DIES AND DUMMY COMPONENTS FOR IMPROVED THERMAL PERFORMANCE - Various semiconductor chip devices with stacked chips are disclosed. In one aspect, a semiconductor chip device includes a stack of plural semiconductor chips. Each two adjacent semiconductor chips of the plural semiconductor chips is electrically connected by plural interconnects and physically connected by a first insulating bonding layer. A first stack of dummy chips is positioned opposite a first side of the stack of semiconductor chips and separated from the plural semiconductor chips by a first gap. Each two adjacent of the first dummy chips are physically connected by a second insulating bonding layer. A second stack of dummy chips is positioned opposite a second side of the stack of semiconductor chips and separated from the plural semiconductor chips by a second gap. Each two adjacent of the second dummy chips are physically connected by a third insulating bonding layer. The first, second and third insulating bonding layers include a first insulating layer and a second insulating layer bonded to the first insulating layer. An insulating layer is in the first gap and another insulating layer is in the second gap. | 2019-06-20 |
20190189591 | SEMICONDUCTOR STORAGE CUBE WITH ENHANCED SIDEWALL PLANARITY - A semiconductor cube is disclosed including one or more highly planar vertical sidewalls on which to form a pattern of electrical traces. The semiconductor cube may be fabricated from a semiconductor cube assembly including a vertical semiconductor die stack and a pair of wire bond landing blocks. The vertical semiconductor die stack may be wire bonded off of first and second opposed edges to different levels of the first and second wire bond landing blocks. Once all wire bonds are formed, the semiconductor cube assembly may be encapsulated in mold compound. The mold compound may then be cut to separate the semiconductor die stack from the wire bond landing blocks, leaving the wire bonds exposed in a sidewall of the semiconductor cube. | 2019-06-20 |
20190189592 | SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF - A semiconductor package includes a first layer including a first semiconductor chip and a first through via, a first redistribution layer disposed on a surface of the first layer, and including a first-first wiring and a second-first wiring, and a second layer including a second semiconductor chip, and stacked on the first layer. The first semiconductor chip includes a first-first buffer, and the first-first buffer is electrically connected between the first-first wiring and the second-first wiring. | 2019-06-20 |
20190189593 | SUBSTRATE BONDING APPARATUS - A substrate bonding apparatus and a method of bonding substrates, the apparatus including an upper chuck securing a first substrate onto a lower surface thereof such that the first substrate is downwardly deformed into a concave surface profile; a lower chuck arranged under the upper chuck and securing a second substrate onto an upper surface thereof such that the second substrate is upwardly deformed into a convex surface profile; and a chuck controller controlling the upper chuck and the lower chuck to secure the first substrate and the second substrate, respectively, and generating a shape parameter for changing a shape of the second substrate to the convex surface profile from a flat surface profile. | 2019-06-20 |
20190189594 | Semiconductor Device and Method of Manufacture - An integrated fan out package on package architecture is utilized along with a reference via in order to provide a reference voltage that extends through the InFO-POP architecture. If desired, the reference via may be exposed and then connected to a shield coating that can be used to shield the InFO-POP architecture. The reference via may be exposed by exposing either a top surface or a sidewall of the reference via using one or more singulation processes. | 2019-06-20 |
20190189595 | LIGHT EMITTING DEVICE PACKAGE AND DISPLAY DEVICE USING THE SAME - A light emitting device package includes a first wavelength conversion portion and a second wavelength conversion portion to provide a wavelength of incident light to provide light having a converted wavelength, a light-transmissive partition structure extending along side surfaces of the first and second wavelength conversion portions along a thickness direction to separate the first and second wavelength conversion portions part from each other along a direction crossing the thickness direction, and a cell array including a first light emitting device, a second light emitting device and a third light emitting device, overlapping the first wavelength conversion portion, the second wavelength conversion portion and the light-transmissive partition structure, respectively, along the thickness direction. | 2019-06-20 |
20190189596 | LED UNIT FOR DISPLAY AND DISPLAY APPARATUS HAVING THE SAME - A light emitting device for a display includes first LED sub-unit, second LED, and third LED sub-units, an insulating layer substantially covering the first, second, and third LED sub-units, and electrode pads electrically connected to the first, second, and third LED sub-units, in which the first LED sub-unit is disposed on a partial region of the second LED sub-unit, the second LED sub-unit is disposed on a partial region of the third LED sub-unit, the insulating layer has openings for electrical connection between the electrode pads, a common electrode pad is connected to the first, second, and third LED sub-units through the openings in the insulating layer, first, second, and third electrode pads are connected to the first, second, and third LED sub-units, respectively, through at least one of the openings, and the first, second, and third LED sub-units are configured to be independently driven using the electrode pads. | 2019-06-20 |
20190189597 | DISCONTINUOUS PATTERNED BONDS FOR SEMICONDUCTOR DEVICES AND ASSOCIATED SYSTEMS AND METHODS - Discontinuous bonds for semiconductor devices are disclosed herein. A device in accordance with a particular embodiment includes a first substrate and a second substrate, with at least one of the first substrate and the second substrate having a plurality of solid-state transducers. The second substrate can include a plurality of projections and a plurality of intermediate regions and can be bonded to the first substrate with a discontinuous bond. Individual solid-state transducers can be disposed at least partially within corresponding intermediate regions and the discontinuous bond can include bonding material bonding the individual solid-state transducers to blind ends of corresponding intermediate regions. Associated methods and systems of discontinuous bonds for semiconductor devices are disclosed herein. | 2019-06-20 |
20190189598 | Multi-Chip Module - A multi-chip module is disclosed. In an embodiment, a multi-chip module includes a first carrier including a mold material and at least two light-emitting diode chips embedded at least by side faces in the first carrier, wherein the light-emitting diode chips have first electrical contacts on a front side and second electrical contacts on a rear side, wherein the front side is configured as a radiation side, wherein the first electrical contacts are connected to control lines, wherein the control lines are arranged on a front side of the first carrier, wherein the second electrical contacts are connected to a collective line, and wherein the collective line is led to a rear side of the first carrier. | 2019-06-20 |
20190189599 | SEMICONDUCTOR DEVICE WITH INTEGRATED HEAT DISTRIBUTION AND MANUFACTURING METHOD THEREOF - A semiconductor package having an internal heat distribution layer and methods of forming the semiconductor package are provided. The semiconductor package can include a first semiconductor device, a second semiconductor device, and an external heat distribution layer. The first semiconductor device can comprise a first semiconductor die and an external surface comprising a top surface, a bottom surface, and a side surface joining the bottom surface to the tope surface. The second semiconductor device can comprise a second semiconductor die and can be stacked on the top surface of the first semiconductor device. The external heat distribution layer can cover an external surface of the second semiconductor device and the side surface of the first semiconductor device. The external heat distribution layer further contacts an internal heat distribution layer on a top surface of the first semiconductor die. | 2019-06-20 |
20190189600 | FAN-OUT SEMICONDUCTOR PACKAGE AND PACKAGE ON PACKAGE INCLUDING THE SAME - The fan-out semiconductor package includes: a metal member including a metal plate having a first through-hole and second through-holes and metal posts disposed in the second through-holes; a semiconductor chip disposed in the first through-hole; an encapsulant covering at least portion of each of the metal member and the semiconductor chip and filling at least portions of each of the first and second through-holes; a wiring layer disposed on the encapsulant; first vias electrically connecting the wiring layer and the connection pads to each other; and second vias electrically connecting the wiring layer and the metal posts to each other, wherein a height of the second vias is greater than that of the first vias or a thickness of the metal plate is the same as that of the metal post. | 2019-06-20 |
20190189601 | ELECTRONIC DEVICE AND ELECTRONIC EQUIPMENT - The characteristics of an electronic device can be improved. The electronic device includes a first redistribution layer formed over an upper surface US of a sealing body, and a second redistribution layer formed below a bottom surface of the sealing body. The thickness of the second redistribution layer is smaller than the thickness of the first redistribution layer. | 2019-06-20 |
20190189602 | STRUCTURE WITH MICRO DEVICE - A structure with micro device includes a substrate, a plurality of micro devices, and a plurality of holding structures. The micro devices are disposed on the substrate and arranged in multiple rows. Each of the micro devices has a top surface. The holding structures are respectively disposed on the top surface of each of the micro devices and extend to the substrate. Distances between the holding structure on the micro devices on any one of the rows and the holding structures on the micro devices on two adjacent rows are different. | 2019-06-20 |
20190189603 | DIRECT-BONDED OPTOELECTRONIC INTERCONNECT FOR HIGH-DENSITY INTEGRATED PHOTONICS - Direct-bonded optoelectronic interconnects for high-density integrated photonics are provided. A combined electrical and optical interconnect enables direct-bonding of fully-processed optoelectronic dies or wafers to wafers with optoelectronic driver circuitry. The photonic devices may be III-V semiconductor devices. Direct-bonding to silicon or silicon-on-insulator (SOI) wafers enables the integration of photonics with high-density CMOS and other microelectronics packages. Each bonding surface has an optical window to be coupled by direct-bonding. Coplanar electrical contacts lie to the outside, or may circumscribe the respective optical windows and are also direct-bonded across the interface using metal-to-metal direct-bonding, without interfering with the optical windows. Direct hybrid bonding can accomplish both optical and electrical bonding in one overall operation, to mass-produce mLED video displays. The adhesive-free dielectric-to-dielectric direct bonding and solder-free metal-to-metal direct bonding creates high-density electrical interconnects on the same bonding interface as the bonded optical interconnect. Known-good-dies may be used, which is not possible conventionally, and photolithography over their top surfaces can scale to high density. | 2019-06-20 |
20190189604 | MICRO LIGHT-EMITTING-DIODE DISPLAY PANEL AND MANUFACTURING METHOD THEREOF - The present invention provides a micro light emitting-diode display panel and a manufacturing method thereof. The first electrode contact and the second electrode contact are alternatively disposed on the base substrate of the micro light-emitting-diode display panel, and the first electrode contact and the second electrode contact are respectively connected with the bottom electrode and the connection electrode of the micro light-emitting-diode. The connection electrode is also connected the top electrode of the micro light-emitting-diode, and the micro light-emitting-diodes can be immediately inspected after the micro-light-emitting-diode is transferred, to reduce the difficulty of detection and product repair, and to improve the product yield. | 2019-06-20 |
20190189605 | ARRANGEMENT HAVING A CARRIER AND AN OPTOELECTRONIC COMPONENT - An arrangement includes a carrier; an optoelectronic component arranged on the carrier; and a material arranged on the carrier, wherein the carrier includes at least one structural element that hinders flow of the material in a flow direction, the structural element extends transversely to the flow direction, and the structural element has a rounding radius in a plane perpendicular to the transverse extent of the structural element less than | 2019-06-20 |
20190189606 | MULTI-DIE ARRAY DEVICE - Embodiments are provided that include a method for fabricating a multi-die package including: placing a plurality of flip chip dies and splitter dies on the sacrificial carrier; performing solder reflow to join solder bumps of each flip chip die and each splitter die to the sacrificial carrier that includes test probe circuitry; testing the flip chip and splitter dies; replacing any faulty dies; overmolding the flip chip and splitter dies on the sacrificial carrier to form a panel of embedded dies; planarizing the panel of embedded dies to expose back surfaces of the embedded dies; forming a metallization layer across the back surface of the panel of embedded dies; and removing the sacrificial carrier to expose a front surface of the panel of embedded dies, wherein a contact surface of each solder bump of each flip chip die and splitter die is exposed in the front surface. | 2019-06-20 |
20190189607 | STACKED DIES AND METHODS FOR FORMING BONDED STRUCTURES - In various embodiments, a method for forming a bonded structure is disclosed. The method can comprise mounting a first integrated device die to a carrier. After mounting, the first integrated device die can be thinned. The method can include providing a first layer on an exposed surface of the first integrated device die. At least a portion of the first layer can be removed. A second integrated device die can be directly bonded to the first integrated device die without an intervening adhesive. | 2019-06-20 |
20190189608 | CAPACITOR ARRAY OVERLAPPED BY ON-CHIP INDUCTOR/TRANSFORMER - An integrated circuit (IC) includes a capacitor array in at least one first back-end-of-line (BEOL) interconnect level. The capacitor array includes a pair of capacitor manifolds coupled to parallel capacitor routing traces and capacitors coupled between each pair of parallel capacitor routing traces. The IC also includes an inductor trace having at least one turn in at least one second BEOL interconnect level. The inductor trace defines a perimeter to overlap at least a portion of the capacitor array. | 2019-06-20 |
20190189609 | SEMICONDUCTOR DEVICE HAVING FIN STRUCTURE - A semiconductor device includes a fin structure, a first conductive line, a second conductive line and a first conductive rail. The fin structure is disposed on a substrate. The first conductive line is arranged to wrap a first portion of the fin structure. The second conductive line is attached on a second portion of the fin structure. The second portion is different from the first portion. The first conductive rail is disposed in a same layer as the first conductive line and the second conductive line on the substrate. The first conductive rail is attached on one end of the first conductive line and one end of the second conductive line for electrically connecting the first conductive line and the second conductive line. | 2019-06-20 |
20190189610 | SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit includes: a p | 2019-06-20 |
20190189611 | PN DIODES AND CONNECTED GROUP III-N DEVICES AND THEIR METHODS OF FABRICATION - A semiconductor structure including a group III-N semiconductor material is disposed on a silicon substrate. A group III-N transistor structure is disposed on the group III-N semiconductor material. A well is disposed in the silicon substrate. The well has a first conductivity type. A doped region is disposed in the well. The doped region has a second conductivity type that is opposite to the first conductivity type. A first electrode is connected to the well of the second conductivity type and a second electrode is connected to the doped region having a first conductivity type. The well and the doped region form a PN diode. The well or the doped region is connected to the raised drain structure of the group III-N transistor. | 2019-06-20 |
20190189613 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a substrate having an active region, and first to third transistors on the active region of the substrate, each of the first to third transistors including a dielectric layer on the substrate, a metal layer on the dielectric layer, a barrier layer between the dielectric layer and the metal layer, and a work function layer between the dielectric layer and the barrier layer, wherein the barrier layer of the third transistor is in contact with the dielectric layer of the third transistor, and wherein a threshold voltage of the second transistor is greater than a threshold voltage of the first transistor and less than a threshold voltage of the third transistor. | 2019-06-20 |
20190189614 | METHOD OF FORMING SEMICONDUCTOR STRUCTURE - A method includes forming a first fin on a semiconductor substrate, forming an isolation dielectric material over the first fin, and planarizing the isolation dielectric material. A top surface of the first fin is covered by the isolation dielectric material after planarizing the isolation dielectric material. The method further includes etching back the isolation dielectric material until the first fin protrudes from the isolation dielectric material. | 2019-06-20 |
20190189615 | SEMICONDUCTOR DEVICES INCLUDING CAPACITORS AND METHODS OF MANUFACTURING THE SAME - A semiconductor device includes a substrate, a conductive pattern on the substrate, a lower electrode electrically connected to the conductive pattern, a dielectric layer covering a surface of the lower electrode, a first upper electrode on the dielectric layer, a diffusion barrier on an upper surface of the first upper electrode, and a second upper electrode covering the diffusion barrier, the second upper electrode including a different material from that of the first upper electrode. | 2019-06-20 |
20190189616 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - According to example embodiments, a semiconductor device may include a substrate having an upper surface defining a groove and an active region, a device isolation layer in the groove, and a contact structure on the active region. The device isolation exposes the active region and may have a top surface that is higher than a top surface of the active region. The contact structure may include a first portion filling a gap region delimited by a sidewall of the device isolation layer and the top surface of the active region, the contact structure may include and a second portion on the device isolation layer so the second portion overlaps with the device isolation layer in a plan view. | 2019-06-20 |
20190189617 | INTEGRATED CIRCUIT DEVICE AND METHOD OF MANUFACTURING THE SAME - An integrated circuit device may include a support pattern over a substrate, a lower electrode pattern and a dielectric structure over the substrate, and an upper electrode structure on the dielectric structure. The support pattern may include a first support structure extending in a vertical direction. The lower electrode pattern may be between the support pattern and the dielectric structure. The lower electrode pattern may include a first group of N (e.g., an integer of 4 or more) lower electrodes that are spaced apart from each other and may extend in the vertical direction to a first level above the substrate. The dielectric structure may include a first dielectric protrusion that extends in the vertical direction and surrounds the first support structure and the first group of N lower electrodes. The upper electrode structure may include a first upper electrode protrusion that surrounds the first dielectric protrusion. | 2019-06-20 |
20190189618 | MEMORY CELL - A memory cell includes a curved gate channel transistor, a buried bit line, a word line and a capacitor. The curved gate channel transistor has a first doped region located in a substrate, a second doped region and a third doped region located on the substrate, wherein the second doped region is directly on the first doped region and the third doped region is right next to the second doped region, thereby constituting a curved gate channel. The buried bit line is located below the first doped region. The word line covers the second doped region. The capacitor is located above the curved gate channel transistor and in electrical contact with the third doped region. The present invention also provides a memory cell having a vertical gate channel transistor, and the vertical gate channel has current flowing downward. | 2019-06-20 |
20190189619 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device is provided. The semiconductor device includes a substrate which includes a cell region including first and second regions, and a peri region more adjacent to the second region than adjacent to the first region, first and second lower electrodes disposed in the first and second regions, respectively, first and second lower support patterns disposed on outer walls of the first and second lower electrodes, respectively, an upper support pattern disposed on outer walls of the first and second lower electrodes, and being on and spaced apart from the first and second lower support patterns, a dielectric layer disposed on surfaces of the first and second lower electrodes, the first and second lower support patterns, and the upper support pattern, and an upper electrode disposed on a surface of the dielectric layer, wherein thickness of the first lower support pattern is smaller than thickness of the second lower support pattern. | 2019-06-20 |
20190189620 | METHOD OF FORMING A MEMORY DEVICE - A method for forming a memory device is disclosed, including providing a substrate, forming an isolation structure and plural active regions in the substrate, forming a plurality of island features on the substrate respectively covering two of the terminal portions of the active regions, using the island features as an etching mask to etch the substrate to perform a first etching process to define a first recessed region and plural island structures on the substrate. The island structures respectively comprise the two terminal portions of the active regions and the first recessed region comprises the central portions of the active regions. | 2019-06-20 |
20190189621 | SEMICONDUCTOR DEVICE - The present invention provides a semiconductor device including a semiconductor substrate with a memory cell region and a peripheral region, a gate line in the peripheral region, an etch-stop layer covering the gate line and the semiconductor substrate, a first insulating layer covering the etch-stop layer, two contact plugs disposed on the semiconductor substrate in the peripheral region, two pads disposed on the contact plugs respectively, and a second insulating layer disposed between the pads. The contact plugs are located at two sides of the gate line respectively, and the contact plugs penetrate through the etch-stop layer and the first insulating layer to contact the semiconductor substrate. The second insulating layer is not in contact with the etch-stop layer. | 2019-06-20 |
20190189622 | SEMICONDUCTOR DEVICE - [Problem] To provide a semiconductor device suitable for miniaturization. To provide a highly reliable semiconductor device. To provide a semiconductor device with improved operating speed. | 2019-06-20 |
20190189623 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - Provided is a semiconductor device which has a non-volatile memory including: a semiconductor substrate; a tunnel insulating film formed on a surface of the semiconductor device; a floating gate formed on the tunnel insulating film; a memory cell transistor drain region and a memory cell transistor source region formed from the surface to an inside of the semiconductor substrate in a vicinity of both ends of the floating gate; a first interface formed between the semiconductor substrate and the tunnel insulating film; and a second interface formed between the floating gate and the tunnel insulating film. The first interface and the second interface form an uneven structure having a curvature that changes at an identical period with respect to a place in sectional view. | 2019-06-20 |
20190189624 | EMBEDDED NON-VOLATILE MEMORY - A semiconductor device includes a semiconductor substrate and a pair of memory device structures. The semiconductor substrate includes a common source/drain region and a pair of individual source/drain regions, in which the common source/drain region is between the individual source/drain regions. The memory device structures each corresponds to one of the individual source/drain regions. Each memory device structure includes a trap storage structure, a control gate, a cap structure, and a word line. The trap storage structure is between the common source/drain region and the corresponding individual source/drain region. The control gate is over the trap storage structure. The cap structure is over the control gate, in which the cap structure comprises a nitride layer over the control gate and an oxide layer over the nitride layer. The word line is over the semiconductor substrate and laterally spaced from the control gate. | 2019-06-20 |
20190189625 | PROGRAMMABLE DEVICE COMPATIBLE WITH VERTICAL TRANSISTOR FLOW - The present disclosure relates to a programmable device. The programmable device comprises a first vertical transistor; and a second vertical transistor coupled to the first vertical transistor via a shared terminal, wherein: a first gate dielectric of the first vertical transistor has a first thickness and a second gate dielectric of the second vertical transistor has a second thickness, the first thickness being greater than the second thickness, and the second gate dielectric breaks down based on an application of a gate voltage that is lower than a first breakdown voltage of the first gate dielectric and higher than a second breakdown voltage of the second gate dielectric. | 2019-06-20 |
20190189626 | Memory Cells - A memory cell includes a select device and a capacitor electrically coupled in series with the select device. The capacitor includes two conductive capacitor electrodes having ferroelectric material there-between. The capacitor has an intrinsic current leakage path from one of the capacitor electrodes to the other through the ferroelectric material. There is a parallel current leakage path from the one capacitor electrode to the other. The parallel current leakage path is circuit-parallel the intrinsic path and of lower total resistance than the intrinsic path. Other aspects are disclosed. | 2019-06-20 |
20190189627 | FERROELECTRIC MEMORY CELLS INCLUDING FERROELECTRIC CRYSTALLINE MATERIALS HAVING POLAR AND CHIRAL CRYSTAL STRUCTURES, AND RELATED MEMORY DEVICES - A ferroelectric memory device includes a plurality of memory cells. Each of the memory cells comprises at least one electrode and a ferroelectric crystalline material disposed proximate the at least one electrode. The ferroelectric crystalline material is polarizable by an electric field capable of being generated by electrically charging the at least one electrode. The ferroelectric crystalline material comprises a polar and chiral crystal structure without inversion symmetry through an inversion center. The ferroelectric crystalline material does not consist essentially of an oxide of at least one of hafnium (Hf) and zirconium (Zr). | 2019-06-20 |
20190189628 | TWO-TERMINAL NON-VOLATILE MEMRISTOR AND MEMORY - The present disclosure provides a vertical tunneling random access memory comprising: a first electrode disposed on a base substrate; a second electrode vertically spaced from the first electrode; a floating gate disposed between the first electrode and the second electrode and configured to charge or discharge charges; a tunneling insulating layer disposed between the first electrode and the floating gate; a barrier insulating layer disposed between the floating gate and the second electrode; a contact hole passing through the tunneling insulating layer and the barrier insulating layer for partially exposing the first electrode; a semiconductor pattern extending from the second electrode, along and on a portion of a side wall face defining the contact hole, to the first electrode such that one end of the semiconductor pattern is in contact with the first electrode and the other end of the pattern is in contact with the second electrode. | 2019-06-20 |
20190189629 | Integrated Assemblies Having Anchoring Structures Proximate Stacked Memory Cells, and Methods of Forming Integrated Assemblies - Some embodiments include an assembly having channel material structures extending upwardly from a conductive structure. Anchor structures are laterally offset from the channel material structures and penetrate into the conductive structure to a depth sufficient to provide mechanical stability to at least a portion of the assembly. The conductive structure may include a first conductive material over a second conductive material, and may be a source line of a three-dimensional NAND configuration. Some embodiments include methods of forming assemblies to have channel material structures and anchor structures. | 2019-06-20 |
20190189630 | Methods of Filling Openings with Conductive Material, and Assemblies Having Vertically-Stacked Conductive Structures - Some embodiments include a method in which an assembly is formed to have voids within a stack, and to have slits adjacent the voids. Peripheral boundaries of the voids have proximal regions near the slits and distal regions adjacent the proximal regions. A material is deposited within the voids under conditions which cause the material to form to a greater thickness along the distal regions than along the proximal regions. Some embodiments include an assembly having a stack of alternating first and second levels. The second levels include conductive material. Panel structures extend through the stack. The conductive material within the second levels has outer edges with proximal regions near the panel structures and distal regions adjacent the proximal regions. Interface material is along the outer edges of the conductive material and has a different composition along the proximal regions than along the distal regions. | 2019-06-20 |
20190189631 | COMPOSITION FOR ETCHING AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE USING THE SAME - The present invention provides a composition for etching a silicon nitride film and a manufacturing method of a semiconductor device using the same, wherein the composition for etching a silicon nitride film comprises phosphoric acid, metaphosphoric acid, an ammonium salt-based compound, and water. | 2019-06-20 |
20190189632 | MEMORY DEVICES WITH THREE-DIMENSIONAL STRUCTURE - A memory device includes a substrate, a first memory structure including a plurality of first word lines stacked on the substrate in a direction perpendicular to a top surface of the substrate, an inter-metal layer on the first memory structure and including a plurality of intermediate pads connected with separate, respective first word lines of the plurality of first word lines, a second memory structure including a plurality of second word lines stacked on the inter-metal layer in the direction perpendicular to the top surface of the substrate, and an upper metal layer on the second memory structure and including a plurality of upper pads connected with separate, respective second word lines of the plurality of second word lines. | 2019-06-20 |
20190189633 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes a first semiconductor layer, a second semiconductor layer spaced apart from the first semiconductor layer and disposed on the first semiconductor layer, a gate stack structure disposed on the second semiconductor layer, a third semiconductor layer positioned between the first and second semiconductor layers, and a channel pillar passing through the gate stack structure, the second semiconductor layer and the third semiconductor layer and extending into the first semiconductor layer. | 2019-06-20 |
20190189634 | VERTICAL MEMORY DEVICES - A vertical memory device includes a substrate, a plurality of channels extending in a first direction substantially vertical to a top surface of the substrate, a plurality of gate lines surrounding a predetermined number of channels from among the channels, a plurality of common wirings electrically connected to the gate lines, and a plurality of signal wirings electrically connected to the gate lines via the common wirings. The gate lines are arranged and spaced apart from one another along the first direction. Each common wiring is electrically connected to a corresponding gate line at a same level of the corresponding gate line via a corresponding contact. | 2019-06-20 |
20190189635 | INVERTED STAIRCASE CONTACT FOR DENSITY IMPROVEMENT TO 3D STACKED DEVICES - A semiconductor stacked device include a first plurality of device layers separated from one another by a first plurality of dielectric layers, a first electrically conductive via coupled to a contact portion of a device layer of the first plurality of the device layers, a second plurality of device layers separated from one another by a second plurality of dielectric layers, and a second electronically conductive via coupled to a contact portion of a device layer of the second plurality of the device layers. The first electronically conductive via extends to a frontside of the semiconductor stacked device and the second electrically conductive via extends to a backside of the semiconductor stacked device. The first plurality of device layers form a stair pattern in a first direction and the second plurality of device layers form a stair pattern in a second direction inverted from the first direction | 2019-06-20 |
20190189636 | DISPLAY DEVICE AND METHOD OF MANUFACTURING THE SAME - A display device includes a substrate defining a display area having a plurality of pixels therein and a non-display area; a gate electrode in the display area; a panel identification layer in a panel identification area of the non-display area; a gate insulation layer on the gate electrode; a first passivation layer on the gate insulation layer; a planarization layer on the first passivation layer; and a second passivation layer on the planarization layer, wherein the second passivation layer and the planarization layer are absent in a portion of the panel identification area such that a portion of the first passivation layer is not covered by the second passivation layer and the planarization layer. | 2019-06-20 |
20190189637 | ELECTRONIC DEVICE - An electronic device includes a first substrate, a second substrate, a plurality of first metal line segments and a shielding layer. The second substrate is opposite to the first substrate. The first metal line segments are disposed on the first substrate and extend along a first direction, wherein at least one of the first metal line segments includes a first alignment part and a first trace part, a width of the first alignment part is larger than a width of the first trace part, and the first alignment parts are arranged along a second direction. The shielding layer is disposed on the second substrate, and the shielding layer includes a plurality of first alignment structures, wherein one of the first alignment parts is aligned with one of the first alignment structures in a normal vector of the first substrate. | 2019-06-20 |
20190189638 | ARRAY SUBSTRATE AND DISPLAY PANEL - An array substrate includes a plurality of pixel units arranged in an array. Each of the pixel units includes a common electrode, a first insulation layer, a sub pixel electrode, a second insulation layer, and a conductor plate that are sequentially stacked. The conductor plate is electrically connected to the common electrode. The common electrode and the sub pixel electrode collectively form therebetween a first confronting area and the conductor plate and the sub pixel electrode collectively form therebetween a second confronting area, such that a storage capacitor is formed, collectively, between the common electrode and the sub pixel electrode and between the conductor plate and the sub pixel electrode. The above-described array substrate provides a relatively large storage capacitor. Also disclosed is a display panel. | 2019-06-20 |
20190189639 | SUBSTRATE AND MANUFACTURING METHOD THEREOF AND DISPLAY DEVICE - A substrate and a manufacturing method thereof and a display device are provided. The substrate includes: a base including a bendable region; an interlayer on the base and in the bendable region; and a signal line at a side, facing away from the base, of the interlayer. In the bendable region, an orthographic projection of the signal line on the base is within an orthographic projection of the interlayer on the base; and in the bendable region, the interlayer is provided with a groove on at least one side of a portion, corresponding to the signal line, of the interlayer. | 2019-06-20 |
20190189640 | ARRAY SUBSTRATE, MANUFACTURING METHOD THEREOF AND DISPLAY PANEL - An array substrate, a manufacturing method thereof and a display panel are provided. The array substrate includes a base substrate and a wiring layer. The base substrate includes a peripheral region, a bending region and a driving circuit region. The bending region is arranged between the driving circuit region and the peripheral region. A portion of the base substrate at the bending region is a stress buffer member arranged at an end of the bending region adjacent to the peripheral region, connected to a portion of the base substrate at the peripheral region, and spaced apart from a portion of the base substrate at the driving circuit region. | 2019-06-20 |
20190189641 | SEMICONDUCTOR DEVICE AND DISPLAY DEVICE - A semiconductor device including a circuit which does not easily deteriorate is provided. The semiconductor device includes a first transistor, a second transistor, a first switch, a second switch, and a third switch. A first terminal of the first transistor is connected to a first wiring. A second terminal of the first transistor is connected to a second wiring. A gate and a first terminal of the second transistor are connected to the first wiring. A second terminal of the second transistor is connected to a gate of the first transistor. The first switch is connected between the second wiring and a third wiring. The second switch is connected between the second wiring and the third wiring. The third switch is connected between the gate of the first transistor and the third wiring. | 2019-06-20 |
20190189642 | Display Device Fabricated with Fewer Masks and Method of Manufacturing the Same - A display device includes: a substrate including first and second light-blocking areas, and a pixel area; a light-blocking pattern at least partially at the first light-blocking area; a data line at the second light-blocking area; a first insulating layer on the light-blocking pattern and the data line; a semiconductor layer on the first insulating layer and overlapping the light-blocking pattern on a plane; a second insulating layer on the semiconductor layer; a color filter on the second insulating layer at least partially at the pixel area; a third insulating layer on the second insulating layer and the color filter; a gate line on the third insulating layer at the first light-blocking area; a pixel electrode at least partially at the pixel area; and a bridge electrode at least partially at the first light-blocking area. The second and third insulating layers directly contact one another over the semiconductor layer. | 2019-06-20 |
20190189643 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SEMICONDUCTOR DEVICE - First to third insulators are successively formed in this order over a first conductor over a semiconductor substrate; a hard mask with a first opening is formed thereover; a resist mask with a second opening is formed thereover; a third opening is formed in the third insulator; a fourth opening is formed in the second insulator; the resist mask is removed; a fifth opening is formed in the first to third insulators; a second conductor is formed to cover an inner wall and a bottom surface of the fifth opening; a third conductor is formed thereover; polishing treatment is performed so that the hard mask is removed, and that levels of top surfaces of the second and third conductors and the third insulator are substantially equal to each other; and an oxide semiconductor is formed thereover. The second insulator is less permeable to hydrogen than the first and third insulators, the second conductor is less permeable to hydrogen than the third conductor. | 2019-06-20 |
20190189644 | ARRAY SUBSTRATE FOR DISPLAY ASSEMBLY, DISPLAY ASSEMBLY AND ELECTRONIC EQUIPMENT - In one embodiment, there is provided an array substrate for a display assembly. The display assembly includes a display region and a non-display region. The array substrate includes a first portion located in the display region and a second portion located in the non-display region, wherein a touch key subassembly is provided within the second portion. There is also provided a display assembly including the abovementioned array substrate and an electronic equipment including the display assembly. | 2019-06-20 |
20190189645 | ARRAY SUBSTRATE AND DISPLAY DEVICE - An array substrate includes: a base substrate; at least one first connection terminal, at least one second connection terminal, and at least one connection line, which are disposed on the base substrate and located in a non-display area of the array substrate, the at least one connection line being connected with the at least one first connection terminal and the at least one second connection terminal; at least one gate line disposed on the base substrate and located in a display area of the array substrate. The first connection terminal is for connecting with an IC, and the second connection terminal is for connecting with a flexible circuit board. A resistivity of at least a part of each of at least one of the at least one connection line is less than a resistivity of the at least one gate line. | 2019-06-20 |
20190189646 | DISPLAY DEVICE AND ELECTRONIC APPARATUS - To provide a display device and an electronic apparatus that prevent the occurrence of failure in the connection between a mounting substrate and an electronic component. The display device includes: an interconnection layer ( | 2019-06-20 |
20190189647 | THIN FILM TRANSISTOR, MANUFACTURING METHOD THEREOF, AND DISPLAY DEVICE HAVING THE SAME - A thin film transistor includes a first blocking layer disposed on a substrate, and an active pattern disposed on the first blocking layer. The active pattern includes a source region, a drain region, and a channel region disposed between the source region and the drain region. The thin film transistor further includes a gate electrode disposed on the active pattern. The channel region corresponds to a portion of the active pattern overlapped by the gate electrode. The thin film transistor additionally includes a source electrode connected to the source region, and a drain electrode connected to the drain region. The active pattern includes a first part and a second part. The first part partially overlaps with the first blocking layer, and the first part and the second part have different thicknesses from each other. | 2019-06-20 |
20190189648 | METHOD FOR FABRICATING ARRAY SUBSTRATE, ARRAY SUBSTRATE, AND DISPLAY DEVICE - A method for fabricating an array substrate includes: forming a first metal layer on a base substrate; forming an insulating layer of a silicon-containing organic material on the first metal layer; forming a second metal layer on the insulating layer; patterning the second metal layer by adopting an oxygen ion etching process to partially cover the insulating layer; and forming a silicon oxide layer, by the oxygen ion etching process, on a surface of the insulating layer not covered by the second metal layer. | 2019-06-20 |
20190189649 | DISPLAY DEVICE, TRANSFLECTIVE ARRAY SUBSTRATE, AND MANUFACTURING METHOD THEREOF - The present disclosure relates to a display device and a manufacturing method of a transflective array substrate. The transflective array substrate includes: a plurality of scanning lines, a plurality of data lines, and a plurality of pixel cells. Each of the pixel cells includes a thin film transistor (TFT), a photoresist layer, and at least one pixel electrode. The photoresist layer is configured on the TFT. Each of the pixel cells includes a reflective area configured above the photoresist layer. As such, light-reflection efficiency and brightness of the display device may be improved, so as to provide better user experience. | 2019-06-20 |
20190189650 | ARRAY SUBSTRATE, MANUFACTURING METHOD THEREFOR, DISPLAY DEVICE - A method for manufacturing an array substrate, including: forming a semiconductor material film on a substrate, the method further including: forming a metal film covering the semiconductor material film; and performing a single patterning process on the metal film and the semiconductor material film to form an active layer, a semiconductor material remained pattern and a first electrode of a storage capacitor. The semiconductor material remained pattern is in a same layer as the active layer; and the first electrode of the storage capacitor is formed of the metal film and is on a side, away from the substrate, of the semiconductor material remained pattern. An array substrate and a display device are also provided. | 2019-06-20 |
20190189651 | METHOD AND SYSTEM FOR AGING PROCESS ON TRANSISTORS IN A DISPLAY PANEL - The present disclosure relates to a method and system for performing aging process on the transistor in the display panel. A method for performing aging process on a transistor in a display panel, comprising: obtaining an initial characteristic curve of the transistor; determining an initial cutoff voltage range of the transistor according to the obtained initial characteristic curve; determining a gate-source voltage and a drain-source voltage required by the transistor according to the initial cutoff voltage range, so as to increase an cutoff voltage range of the transistor; and performing aging process on the transistor according to the determined required gate-source voltage and drain-source voltage. | 2019-06-20 |
20190189652 | CMOS IMAGE SENSOR WITH BURIED SUPERLATTICE LAYER TO REDUCE CROSSTALK - A CMOS image sensor may include a semiconductor substrate having a first conductivity type, and a superlattice on the semiconductor substrate including a plurality of stacked groups of layers. Each group of layers may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and a non-semiconductor monolayer(s) constrained within a crystal lattice of adjacent base semiconductor portions. The image sensor may further include a plurality of laterally adjacent photodiodes on the superlattice. Each photodiode may include a semiconductor layer on the superlattice and having a first conductivity type dopant and with a lower dopant concentration than the semiconductor substrate, a retrograde well extending downward into the semiconductor layer from a surface thereof and having a second conductivity type, a first well around a periphery of the retrograde well having the first conductivity type, and a second well within the retrograde well having the first conductivity type. | 2019-06-20 |
20190189653 | IMAGE SENSOR AND MANUFACTURING METHOD THEREOF - An image sensor includes a semiconductor layer, a plurality of light sensing regions, a first pixel isolation layer, a light shielding layer, and a wiring layer. The semiconductor layer has a first surface and a second surface opposite to the first surface. The plurality of light sensing regions is formed in the semiconductor layer. The first pixel isolation layer is disposed between adjacent light sensing regions from among the plurality of light sensing regions. The first pixel isolation layer is buried in an isolation trench formed between the first surface and the second surface. The light shielding layer is formed on the second surface of the semiconductor layer and on some of the adjacent light sensing regions. The wiring layer is formed on the first surface of the semiconductor layer. | 2019-06-20 |
20190189654 | BONDING PAD ARCHITECTURE USING CAPACITIVE DEEP TRENCH ISOLATION (CDTI) STRUCTURES FOR ELECTRICAL CONNECTION - A semiconductor substrate has a back side surface and a front side surface. Metallization levels are provide at the front side surface. Capacitive deep trench isolation structures extend completely through the semiconductor substrate from the front side surface to the back side surface. Each capacitive deep trench isolation structure includes a conductive region insulated from the semiconductor substrate by an insulating liner. The conductive regions at first ends of the plurality of capacitive deep trench isolation structures are electrically connected to a first metallization level by electrical contacts. A bonding pad structure is located at the back side surface of the semiconductor substrate in direct physical and electrical connection to the conductive regions at second ends of the capacitive deep trench isolation structures. | 2019-06-20 |
20190189655 | METHOD FOR MAKING CMOS IMAGE SENSOR INCLUDING STACKED SEMICONDUCTOR CHIPS AND READOUT CIRCUITRY INCLUDING A SUPERLATTICE - A method for making a CMOS image sensor may include forming a first semiconductor chip including an array of image sensor pixels and readout circuitry electrically connected thereto, forming a second semiconductor chip comprising image processing circuitry electrically connected to the readout circuitry, and coupling the first semiconductor chip and the second semiconductor chip together in a stack. The readout circuitry may include a plurality of transistors each including spaced apart source and drain regions, a superlattice channel extending between the source and drain regions, and a gate including a gate insulating layer on the superlattice channel and a gate electrode on the gate insulating layer. | 2019-06-20 |