25th week of 2017 patent applcation highlights part 69 |
Patent application number | Title | Published |
20170178866 | APPARATUS AND TECHNIQUES FOR TIME MODULATED EXTRACTION OF AN ION BEAM - A plasma processing apparatus may include: a plasma chamber; a power source to generate a plasma in the plasma chamber; an extraction voltage supply coupled to the plasma chamber to apply a pulsed extraction voltage between the plasma chamber and a substrate; an extraction assembly disposed along a side of the plasma chamber between the plasma chamber and the substrate, the extraction assembly having at least one aperture, the at least one aperture defining a first ion beam when the plasma is present in the plasma chamber and the pulsed extraction voltage is applied; a deflection electrode adjacent the extraction assembly; and a controller to synchronize application of the pulsed extraction voltage with application of a pulsed deflection voltage to the deflection electrode. | 2017-06-22 |
20170178867 | GAS DIFFUSER HAVING GROOVED HOLLOW CATHODES - In one embodiment, a diffuser for a deposition chamber includes a plate having edge regions and a center region, and plurality of gas passages comprising an upstream bore and an orifice hole fluidly coupled to the upstream bore that are formed between an upstream side and a downstream side of the plate, and a plurality of grooves surrounding the gas passages, wherein a depth of the grooves varies from the edge regions to the center region of the plate. | 2017-06-22 |
20170178868 | UPPER ELECTRODE FOR PLASMA PROCESSING APPARATUS AND PLASMA PROCESSING APPARATUS HAVING THE SAME - An upper electrode for a plasma processing apparatus includes a body portion having a plurality of through-holes, a showerhead disposed below the body portion and having a plurality of jet holes connected to the plurality of through-holes, and a buffer layer interposed between the body portion and the showerhead. | 2017-06-22 |
20170178869 | HOLLOW CATHODE ION SOURCE - An ion source includes a chamber. The ion source further includes a first hollow cathode having a first hollow cathode cavity and a first plasma exit orifice and a second hollow cathode having a second hollow cathode cavity and a second plasma exit orifice. The first and second hollow cathodes are disposed adjacently in the chamber. The ion source further includes a first ion accelerator between and in communication with the first plasma exit orifice and the chamber. The first ion accelerator forms a first ion acceleration cavity. The ion source further includes a second ion accelerator between and in communication with the second plasma orifice and the chamber. The second ion accelerator forms a second ion acceleration cavity. The first hollow cathode and the second hollow cathode are configured to alternatively function as electrode and counter-electrode to generate a plasma. Each of the first ion acceleration cavity and the second ion acceleration cavity are sufficient to enable the extraction and acceleration of ions. | 2017-06-22 |
20170178870 | METHOD OF EXTRACTING AND ACCELERATING IONS - A method of extracting and accelerating ions is provided. The method includes providing a ion source. The ion source includes a chamber. The ion source further includes a first hollow cathode having a first hollow cathode cavity and a first plasma exit orifice and a second hollow cathode having a second hollow cathode cavity and a second plasma exit orifice, the first and second hollow cathodes being disposed adjacently in the chamber. The ion source further includes a first ion accelerator between and in communication with the first plasma exit orifice and the chamber. The first ion accelerator forms a first ion acceleration cavity. The ion source further includes a second ion accelerator between and in communication with the second plasma orifice and the chamber. The second ion accelerator forms a second ion acceleration cavity. The method further includes generating a plasma using the first hollow cathode and the second hollow cathode. The first hollow cathode and the second hollow cathode are configured to alternatively function as electrode and counter-electrode. The method further includes extracting and accelerating ions. Each of the first ion acceleration cavity and the second ion acceleration cavity are sufficient to enable the extraction and acceleration of ions. | 2017-06-22 |
20170178871 | PLASMA PROCESSING APPARATUS AND METHOD THEREFOR - A dry etching apparatus plasma processes a wafer held by a carrier having a frame and an holding sheet. The carrier is placed on an electrode unit of a stage provided in a chamber. The electrode unit is cooled by a cooling section configured to cool the electrode unit. An upper face of the electrode unit is at least as large as the back side of the carrier. The holding sheet and the frame are cooled effectively by the heat transfer to the stage. | 2017-06-22 |
20170178872 | PLASMA PROCESSING METHOD AND PLASMA PROCESSING APPARATUS - A plasma processing apparatus | 2017-06-22 |
20170178873 | Determining A Malfunctioning Device in A Plasma System - Systems and methods for determining a malfunctioning device in a plasma system, are described. One of the methods includes receiving an indication whether plasma is generated within a plasma chamber of the plasma system. The plasma system includes a processing portion and a power delivery portion. The method further includes determining whether the plasma system operates within constraints in response to receiving the indication that the plasma is generated, determining a value of a variable at an output of the power delivery portion when the processing portion is decoupled from the power delivery portion, and comparing the determined value with a pre-recorded value of the variable. The method includes determining whether the determined value is outside a range of the pre-recorded value and determining that the malfunctioning device within the power delivery portion upon determining that the determined value is outside the range of the pre-recorded value. | 2017-06-22 |
20170178874 | PLASMA PROCESSING APPARATUS AND OPERATING METHOD OF PLASMA PROCESSING APPARATUS - A plasma processing device performing etching processing to a sample disposed in a processing chamber disposed in a vacuum vessel by using plasma formed in the processing chamber includes a light detector, a component detector, and a determination unit. The light detector detects light intensity of a plurality of wavelengths from the inside of the processing chamber at a plurality of times during the sample processing. The component detector detects, by using a result of a principal component analysis of time-series data, a highly correlated component between the time-series data of a plurality of the wavelengths at a certain time in a plurality of the times obtained from output of the light detector. The determination unit determines an amount or an end point of the etching processing based on a change in light intensity of at least one of a plurality of the wavelengths detected by using the time-series data from which the highly correlated component is removed. | 2017-06-22 |
20170178875 | INSULATOR TARGET - There is provided an insulator target which, when mounted on a sputtering apparatus and supplied with AC power, is capable of preventing the discharging from occurring in a clearance between a shield and the target. The insulator target for the sputtering apparatus according to this invention, around which is disposed a shield at the time of assembling the insulator target on the sputtering apparatus, is made up of: a plate-shaped target material to be enclosed by the shield; and, suppose that one surface of the target material is defined as a sputtering surface to be subjected to sputtering, an annular supporting material coupled to an outer peripheral portion of the opposite surface of the target material. The supporting material has an extended portion which is extended outward from a peripheral surface of the target material and which keeps a predetermined clearance to the shield. | 2017-06-22 |
20170178876 | Cu-Ga ALLOY SPUTTERING TARGET AND METHOD FOR MANUFACTURING SAME - A Cu—Ga alloy sputtering target includes, as a component composition, Ga: 0.1 to 40.0 at % and a balance including Cu and inevitable impurities, in which a porosity is 3.0% or lower, an average diameter of circumscribed circles of pores is 150 μm or less, and an average crystal grain size of Cu—Ga alloy particles is 50 μm or less. | 2017-06-22 |
20170178877 | METHODS AND APPARATUS FOR PROCESSING A SUBSTRATE - Methods and apparatus for processing a substrate are disclosed herein. In some embodiments, a process chamber includes: a chamber body defining an interior volume; a substrate support to support a substrate within the interior volume; a plurality of cathodes coupled to the chamber body and having a corresponding plurality of targets to be sputtered onto the substrate; and a shield rotatably coupled to an upper portion of the chamber body and having at least one hole to expose at least one of the plurality of targets to be sputtered and at least one pocket disposed in a backside of the shield to accommodate and cover at least another one of the plurality of targets not to be sputtered, wherein the shield is configured to rotate about and linearly move along a central axis of the process chamber. | 2017-06-22 |
20170178878 | Electrically and Magnetically Enhanced Ionized Physical Vapor Deposition Unbalanced Sputtering Source - An electrically and magnetically enhanced ionized physical vapor deposition (I-PVD) magnetron apparatus and method is provided for sputtering material from a cathode target on a substrate, and in particular, for sputtering ceramic and diamond-like coatings. The electrically and magnetically enhanced magnetron sputtering source has unbalanced magnetic fields that couple the cathode target and additional electrode together. The additional electrode is electrically isolated from ground and connected to a power supply that can generate positive, negative, or bipolar high frequency voltages, and is preferably a radio frequency (RF) power supply. RF discharge near the additional electrode increases plasma density and a degree of ionization of sputtered material atoms. | 2017-06-22 |
20170178879 | Sputtering System And Method Including An Arc Detection - A sputtering system that includes a sputtering chamber having a target material serving as a cathode, and an anode and a work piece. A direct current (DC) power supply supplies electrical power to the anode and the cathode sufficient to generate a plasma within the sputtering chamber. A detection module detects the occurrence of an arc in the sputtering chamber by monitoring an electrical characteristic of the plasma. In one embodiment the electrical characteristic monitored is the impedance of the plasma. In another embodiment the electrical characteristic is the conductance of the plasma. | 2017-06-22 |
20170178880 | Two Dimensional MS/MS Acquisition Modes - A method of mass spectrometry is disclosed comprising performing a plurality of experimental runs, wherein each experimental run comprises: periodically mass analysing fragment or product ions at a plurality of time intervals, wherein a delay time is provided between the start of the experimental run and the first time interval at which the fragment or product ions are mass analysed. Different delay times are provided in different ones of the experimental runs and fragment or product ions that have been analysed in the same time interval in at least one of said experimental runs and that have been analysed in different time intervals in at least one other of said experimental runs are identified as fragment or product ions of interest. These fragment or product ions are thus determined to relate to different precursor ions and are used to identify their respective precursor ions. | 2017-06-22 |
20170178881 | ANALYZER - An analyzer ( | 2017-06-22 |
20170178882 | APPARATUS AND METHOD FOR SUB-MICROMETER ELEMENTAL IMAGE ANALYSIS BY MASS SPECTROMETRY - A mass spectrometer system for elemental analysis of a planar sample is provided. In some embodiments, the mass spectrometer system comprises: a primary ion source capable of irradiating a segment on planar sample with a beam of primary ions that is less than 1 mm in diameter, c) an orthogonal ion mass-to-charge ratio analyzer positioned downstream of sample interface, the analyzer being configured to separate secondary elemental atomic ions according to their mass-to-charge ratio by time of flight; d) an ion detector for detecting the secondary elemental atomic ions and producing mass spectra measurements; and e) a synchronizer, wherein the system is configured so that so that the beam of primary ions scans across the planar sample in two dimensions and the synchronizer associates the mass spectra measurements with positions on the planar sample. | 2017-06-22 |
20170178883 | Method to Remove Ion Interferences - A method of mass spectrometry is disclosed comprising mass analysing an eluent from a chromatography device and obtaining parent ion data sets and corresponding product ion data sets, and determining whether, in a first product ion data set, one or more product ions are present that are related to one or more parent ions in a corresponding first parent ion data set, based on the mass or mass to charge ratio and/or intensity of the one or more product ions and the one or more parent ions. If it is determined that the one or more product ions are present, the method further comprises removing the one or more product ions from one or more second product ion data sets to produce one or more second modified product ion data sets and/or removing ions other than the one or more product ions from the first product ion data set to produce a first modified product ion data set. | 2017-06-22 |
20170178884 | Liquid Sample Introduction System and Method, for Analytical Plasma Spectrometer - A liquid sample introduction system for a plasma spectrometer includes a sample container for holding a liquid sample, a surface acoustic wave (SAW) nebulizer, arranged to receive a liquid sample from the sample container, an electronic controller for supplying electrical power to the SAW nebulizer so as to produce a surface acoustic wave on a surface of the SAW nebulizer, for generating an aerosol from the supplied sample liquid, and an aerosol transport arrangement for receiving the aerosol from the SAW nebulizer and carrying it into a plasma or flame of a spectrometer. The electronic controller is further configured to control the electrical power to the SAW nebulizer so as to permit adjustment of the aerosol parameters, and to control the aerosol transport arrangement so as to permit adjustment of the aerosol delivery into the plasma or flame of the spectrometer. | 2017-06-22 |
20170178885 | RF ION GUIDE WITH AXIAL FIELDS - RF ion guides are configured as an array of elongate electrodes arranged symmetrically about a central axis, to which RF voltages are applied. The RF electrodes include at least a portion of their length that is semi-transparent to electric fields. Auxiliary electrodes are then provided proximal to the RF electrodes distal to the ion guide axis, such that application of DC voltages to the auxiliary electrodes causes an auxiliary electric field to form between the auxiliary electrodes and the ion guide RF electrodes. A portion of this auxiliary electric field penetrates through the semi-transparent portions of the RF electrodes, such that the potentials within the ion guide are modified. The auxiliary electrode structures and voltages can be configured so that a potential gradient develops along the ion guide axis due to this field penetration, which provides an axial motive force for collision damped ions. | 2017-06-22 |
20170178886 | Ion Guide Construction Method - A method of constructing an ion guide is disclosed comprising providing an elongated spine member and a plurality of plates. Each plate comprises an aperture therethrough for receiving the spine member and at least one electrode for use in guiding ions. The apertures of the plates are arranged around the spine member and the plates are arranged along the spine member. The plates are then locked in position on the spine member such that the plates are fixed axially with respect to the spine member and so that the electrodes of the plates are arranged so as to form an array of electrodes for use in guiding ions. | 2017-06-22 |
20170178887 | TRIPLE QUADRUPOLE MASS SPECTROMETRY COUPLED TO TRAPPED ION MOBILITY SEPARATION - The invention provides a method for acquiring fragment ion spectra of substances in complex substance mixtures wherein a trapped ion mobility spectrometer (“TIMS”) is used as the ion mobility separation device coupled to a triple quadrupole mass filter assembly. The fragment ion spectra may be used for the identification of high numbers of proteins in complex mixtures, or for a safe quantification of some substances, by their fragment ion mass spectra in a mass spectrometer with upstream substance separator. TIMS, in particular equipped with parallel accumulation, provides the unique possibility to prolong the ion accumulation duration to find more detectable ion species without decreasing the measuring capacity for fragment ion mass spectra. The high measurement capacity for fragment ion mass spectra permits the repeated measurement of low abundance ion species such as to improve the quality of the fragment ion spectra. | 2017-06-22 |
20170178888 | METHOD FOR POLISHING SEMICONDUCTOR SUBSTRATE - Proposed is a method for polishing a semiconductor substrate including an intermediate polishing step of polishing in such a way that the number of surface defects having heights of less than 3 nm is 45% or more of the total number of the surface defects on the surface of a semiconductor substrate, and a final polishing step of finish-polishing the semiconductor substrate after the intermediate polishing step. | 2017-06-22 |
20170178889 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device may include: performing a cycle a predetermined number of times to form an oxynitride film on a substrate, the cycle including: (a) supplying a source gas to the substrate via a first nozzle; and (b) supplying a nitriding gas and an oxidizing gas to the substrate via a second nozzle different from the first nozzle, wherein (a) and (b) are performed non-simultaneously, wherein (b) may include: (b-1) supplying only the oxidizing gas while suspending a supply of the nitriding gas; and (b-2) simultaneously supplying the nitriding gas and the oxidizing gas, wherein (b-1) and (b-2) are consecutively performed. | 2017-06-22 |
20170178890 | SEMICONDUCTOR SUBSTRATE POLISHING METHODS WITH DYNAMIC CONTROL - Methods for polishing semiconductor substrates are disclosed. The finish polishing sequence is adjusted based on a measured edge roll-off of an analyzed substrate. | 2017-06-22 |
20170178891 | Methods for Improving Wafer Planarity and Bonded Wafer Assemblies Made from the Methods - A method to improve the planarity of a semiconductor wafer and an assembly made from the method. In a preferred embodiment of the method, a compressive PECVD oxide layer such as SiO | 2017-06-22 |
20170178892 | SUBSTRATE PROCESSING APPARATUS AND SUBSTRATE PROCESSING METHOD - In one embodiment, a substrate processing apparatus includes a substrate retainer and a substrate rotator to retain and rotate a substrate, liquid feeders to supply a cleaning liquid, a rinse liquid and a first coating liquid to a first face of the substrate, a heater to heat the substrate from a second face of the substrate, and a controller to control processing of the substrate. The controller supplies the first coating liquid to the first face while rotating the substrate at a first number of revolution. The controller heats the substrate from the second face while rotating the substrate at a second number of revolution that is different from the first number of revolution after the first coating liquid is supplied, to evaporate a solvent from the first coating liquid to form a coating film containing a solute of the first coating liquid on the first face. | 2017-06-22 |
20170178893 | METHOD FOR RINSING COMPOUND SEMICONDUCTOR, SOLUTION FOR RINSING COMPOUND SEMICONDUCTOR CONTAINING GALLIUM AS CONSTITUENT ELEMENT, METHOD FOR FABRICATING COMPOUND SEMICONDUCTOR DEVICE, METHOD FOR FABRICATING GALLIUM NITRIDE SUBSTRATE, AND GALLIUM NITRIDE SUBSTRATE - A method for rinsing a compound semiconductor, the method including a step of rinsing a compound semiconductor at a temperature of 80 degrees centigrade or higher with an aqueous solution of sulfuric acid of 50 wt % or less in purified water, the aqueous solution having a hydrogen ion concentration of pH 2 or less and an oxidation-reduction potential of 0.6 volts or higher, the compound semiconductor containing gallium as a constituent element, and the compound semiconductor having a surface of gallium nitride (GaN). | 2017-06-22 |
20170178894 | CLEANING METHOD - Implementations of the present disclosure generally relate to methods and apparatuses for epitaxial deposition on substrate surfaces. More particularly, implementations of the present disclosure generally relate to methods and apparatuses for surface preparation prior to epitaxial deposition. In one implementation, a method of processing a substrate is provided. The method comprises etching a surface of a silicon-containing substrate by use of a plasma etch process to form an etched surface of the silicon-containing substrate and forming an epitaxial layer on the etched surface of the silicon-containing substrate. The plasma etch process comprises flowing an etchant gas mixture comprising a fluorine-containing precursor and a hydrogen-containing precursor into a substrate-processing region of a first processing chamber and forming a plasma from the etchant gas mixture flowed into the substrate-processing region. | 2017-06-22 |
20170178895 | METHOD FOR CLEANING SUBSTRATE - A method for cleaning a substrate is provided. The method includes providing a substrate. Metal compound residues are formed over the substrate. The method includes exposing the substrate to an organic plasma to volatilize the metal compound residues. The organic plasma is generated from a gas. The gas includes an organic gas, and the organic gas is made of a hydrocarbon compound or an alcohol compound. | 2017-06-22 |
20170178896 | PATTERN FORMING METHOD - A pattern forming method includes forming a guide pattern on a substrate including first and second regions and applying a directed self-assembly material including a first and a second polymer portion to the substrate. The first region is irradiated with an energy beam. The substrate is subjected to a heating process after irradiation and the directed self-assembly material in the second region separates into a first polymer phase and a second polymer phase. The directed self-assembly material is removed from the first region after irradiation. | 2017-06-22 |
20170178897 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - The reliability of a semiconductor device is improved. In a manufacturing method, a film to be processed is formed over a circular semiconductor substrate, and a resist layer whose surface has a water-repellent property is formed thereover. Subsequently, the water-repellent property of the resist layer in the outer peripheral region of the circular semiconductor substrate is lowered by selectively performing first wafer edge exposure on the outer peripheral region of the semiconductor substrate, and then liquid immersion exposure is performed on the resist layer. Subsequently, second wafer edge exposure is performed on the outer peripheral region of the circular semiconductor substrate, and then the resist layer, on which the first wafer edge exposure, the liquid immersion exposure, and the second wafer edge exposure have been performed, is developed, so that the film to be processed is etched by using the developed resist layer. | 2017-06-22 |
20170178898 | VARIABLE TEMPERATURE HARDWARE AND METHODS FOR REDUCTION OF WAFER BACKSIDE DEPOSITION - A process tuning kit for use in a chemical deposition apparatus wherein the process tuning kit includes a carrier ring, horseshoes and shims. The horseshoes have the same dimensions and the shims are provided in sets with different thicknesses to control the height of the horseshoes with respect to an upper surface of a pedestal assembly on which the horseshoes and shims are mounted. A semiconductor substrate is transported into a vacuum chamber of the chemical deposition apparatus by the carrier ring which is placed on the horseshoes such that minimum contact area supports lift the substrate from the carrier ring and support the substrate at a predetermined offset with respect to an upper surface of the pedestal assembly. During processing of the substrate, backside deposition can be reduced by using shims of desired thickness to control the predetermined offset. | 2017-06-22 |
20170178899 | DIRECTIONAL DEPOSITION ON PATTERNED STRUCTURES - Provided herein are methods and related apparatus that facilitate patterning by performing highly non-conformal (directional) deposition on patterned structures. The methods involve depositing films on a patterned structure, such as a hard mask. The deposition may be both substrate-selective such that the films have high etch selectivity with respect to an underlying material to be etched and pattern-selective such that the films are directionally deposited to replicate the pattern of the patterned structure. In some embodiments, the deposition is performed in the same chamber as a subsequent etch is performed. In some embodiments, the deposition may be performed in a separate chamber (e.g., a PECVD deposition chamber) that is connected to the etch chamber by a vacuum transfer chamber. The deposition may be performed prior to or at selected intermittences during at etch process. In some embodiments, the deposition involves multiple cycles of a deposition and treatment process. | 2017-06-22 |
20170178900 | TECHNIQUES FOR CONTROLLING ION/NEUTRAL RATIO OF A PLASMA SOURCE - Approaches herein increase a ratio of reactive ions to a neutral species in a plasma processing apparatus. Exemplary approaches include providing a processing apparatus having a plasma source chamber including a first gas inlet, and a deposition chamber coupled to the plasma source chamber, wherein the deposition chamber includes a second gas inlet for delivering a point of use (POU) gas to an area proximate a substrate disposed within the deposition chamber. Exemplary approaches further include generating an ion beam for delivery to the substrate, and modifying a pressure within the deposition chamber in the area proximate the substrate to increase an amount of reactive ions present for impacting the substrate when the ion beam is delivered to the substrate. | 2017-06-22 |
20170178901 | METHOD OF IMPROVING ADHESION - A method is for improving adhesion between a semiconductor substrate and a dielectric layer. The method includes depositing a silicon dioxide adhesion layer onto the semiconductor substrate by a first plasma enhanced chemical vapor deposition (PECVD) process, and depositing the dielectric layer onto the adhesion layer by a second PECVD process. The first PECVD process is performed in a gaseous atmosphere comprising tetraethyl orthosilicate (TEOS) either in the absence of O | 2017-06-22 |
20170178902 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, SUBSTRATE PROCESSING APPARATUS, AND RECORDING MEDIUM - A method of manufacturing a semiconductor device includes: providing a substrate having an oxide film; performing, a predetermined number of times, a cycle of non-simultaneously performing supplying a precursor gas to the substrate, supplying a carbon-containing gas to the substrate, and supplying a nitrogen-containing gas to the substrate, or performing, a predetermined number of times, a cycle of non-simultaneously performing supplying a precursor gas to the substrate and supplying a gas containing carbon and nitrogen to the substrate, or performing, a predetermined number of times, a cycle of non-simultaneously performing supplying a precursor gas containing carbon to the substrate and supplying a nitrogen-containing gas to the substrate, the oxide film being used as an oxygen source to form a nitride layer containing oxygen and carbon as a seed layer; and forming a nitride film containing no oxygen and carbon as a first film on the seed layer. | 2017-06-22 |
20170178903 | Single Crystal Rhombohedral Epitaxy of SiGe on Sapphire at 450.degree.C - 500.degree.C Substrate Temperatures - Various embodiments may provide a low temperature (i.e., less than 850° C.) method of Silicon-Germanium (SiGe) on sapphire (Al | 2017-06-22 |
20170178904 | METHOD FOR MANUFACTURING SPUTTERING TARGET, METHOD FOR FORMING OXIDE FILM, AND TRANSISTOR - A method for manufacturing a sputtering target with which an oxide semiconductor film with a small amount of defects can be formed is provided. Alternatively, an oxide semiconductor film with a small amount of defects is formed. A method for manufacturing a sputtering target is provided, which includes the steps of: forming a polycrystalline In-M-Zn oxide (M represents a metal chosen among aluminum, titanium, gallium, yttrium, zirconium, lanthanum, cesium, neodymium, and hafnium) powder by mixing, sintering, and grinding indium oxide, an oxide of the metal, and zinc oxide; forming a mixture by mixing the polycrystalline In-M-Zn oxide powder and a zinc oxide powder; forming a compact by compacting the mixture; and sintering the compact. | 2017-06-22 |
20170178905 | Method of Forming a Feature of a Target Material on a Substrate - A method is provided for forming a feature of a target material on a substrate. The method including:
| 2017-06-22 |
20170178906 | METHOD FOR FORMING POLYSILICON FILM - Provided is a method for forming a silicon film, and more particularly, to a method for forming a polycrystalline silicon film including pretreatment process in a process for forming a silicon film. According to an embodiment of the present invention, a method for forming a polycrystalline silicon film by annealing a amorphous silicon film deposited on a base, the method includes a pretreatment process of allowing a pretreatment gas including at least one of N, C, O and B to flow. | 2017-06-22 |
20170178907 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor device includes line patterns extending in a first direction, and separated from each other in a second direction perpendicular to the first direction. The plurality of line patterns includes at least two line sets, and each of the line sets includes four line patterns consecutively disposed in the second direction and having a length which varies based on location, and the at least two line sets have substantially an identical length. | 2017-06-22 |
20170178908 | DAMAGE FREE ENHANCEMENT OF DOPANT DIFFUSION INTO A SUBSTRATE - A method of doping a substrate. The method may include implanting a dose of a helium species into the substrate through a surface of the substrate at an implant temperature of 300 ° C. or greater. The method may further include depositing a doping layer containing a dopant on the surface of the substrate, and annealing the substrate at an anneal temperature, the anneal temperature being greater than the implant temperature. | 2017-06-22 |
20170178909 | A METHOD FOR PROCESSING A CARRIER, A CARRIER, AN ELECTRONIC DEVICE AND A LITHOGRAPHIC MASK - Various embodiments provide a method for processing a carrier, the method including changing the three-dimensional structure of a mask layer arranged over the carrier so that at least two mask layer regions are formed having different mask layer thicknesses; and applying an ion implantation process to the at least two mask layer regions to form at least two implanted regions in the carrier having different implantation depth profiles. | 2017-06-22 |
20170178910 | Method for Differential Heating of Elongate Nano-Scaled Structures - The present disclosure is related to a method of fabricating a semiconductor device involving the production of at least two non-parallel nano-scaled structures on a substrate. These structures are heated to different temperatures by exposing them simultaneously to polarized light having a wavelength and polarization such that a difference in absorption of light occurs in the first and second nanostructure. In some cases the light is polarized in a plane that is parallel to one of the structures. The present disclosure may provide differential heating of semiconductor structures of different materials, such as Ge and Si fins. | 2017-06-22 |
20170178911 | ION IMPLANTATION FOR IMPROVED CONTACT HOLE CRITICAL DIMENSION UNIFORMITY - Provided herein are approaches for patterning a semiconductor device. In an exemplary approach, a method includes providing a set of contact openings through a photoresist formed atop a substrate, and implanting ions into just a sidewall surface of the set of contact openings. In an exemplary approach, the ions are implanted at an implant angle nonparallel with the sidewall surface to prevent the ions from implanting a surface of the substrate within the set of contact openings, and to form a treated layer along an entire height of the contact opening. The method further includes etching the substrate within the set of contact openings after the ions are implanted into the sidewall surface. As a result, by using an angled ion implantation to the contact opening sidewall surface as a pretreatment prior to etching, local critical dimension uniformity is improved. | 2017-06-22 |
20170178912 | Capacitive Coupled Plasma Source for Sputtering and Resputtering - An ionized physical vapor deposition (I-PVD) source includes an electrically and magnetically enhanced radio frequency (RF) diode, which has magnetic field lines directed substantially perpendicular to a cathode that terminate on an electrode positioned between an anode around the cathode. The anode forms a gap and the electrode is positioned behind the gap. An RF power supply connected to the cathode generates RF discharge. The cathode is inductively grounded to prevent forming a constant voltage bias during RF discharge. The electrons drift between the cathode and the gap, thereby producing ionization and forming high density plasma. The electrons drift and energy are controlled by applying different voltage potentials to the electrode. The I-PVD source is positioned in a vacuum chamber to form an I-PVD apparatus that generates ions from sputtered target material atoms and deposition. During sputtering, the substrate is biased. The I-PVD source performs chemically enhanced ionized physical vapor deposition (CE-IPVD). | 2017-06-22 |
20170178913 | ASYMMETRIC HIGH-K DIELECTRIC FOR REDUCING GATE INDUCED DRAIN LEAKAGE - An asymmetric high-k dielectric for reduced gate induced drain leakage in high-k MOSFETs and methods of manufacture are disclosed. The method includes performing an implant process on a high-k dielectric sidewall of a gate structure. The method further includes performing an oxygen annealing process to grow an oxide region on a drain side of the gate structure, while inhibiting oxide growth on a source side of the gate structure adjacent to a source region. | 2017-06-22 |
20170178914 | Etch Rate Modulation Through Ion Implantation - As etching processes become more aggressive, increased etch resistivity of the hard mask is desirable. Methods of modulating the etch rate of the mask and optionally the underlying material are disclosed. An etch rate modifying species is implanted into the hard mask after the mask etching process is completed. This etch rate modifying species increases the difference between the etch rate of the mask and the etch rate of the underlying material to help preserve the integrity of the mask during a subsequent etching process. In some embodiments, the etch rate of the mask is decreased by the etch rate modifying species. In certain embodiments, the etch rate of the underlying material is increased by the etch rate modifying species. | 2017-06-22 |
20170178915 | METHODS FOR SELECTIVE ETCHING OF A SILICON MATERIAL USING HF GAS WITHOUT NITROGEN ETCHANTS - The present disclosure provides methods for etching a silicon material in a device structure in semiconductor applications. In one example, a method for etching features in a silicon material includes performing a remote plasma process formed from an etching gas mixture including HF gas without nitrogen etchants to remove a silicon material disposed on a substrate. | 2017-06-22 |
20170178916 | ENHANCED LATERAL CAVITY ETCH - A cavity is formed in a semiconductor substrate wherein the width of the cavity is greater than the depth of the cavity and wherein the depth of the cavity is non uniform across the width of the cavity. The cavity may be formed under an electronic device in the semiconductor substrate. The cavity is formed in the substrate by performing a first cavity etch followed by repeated cycles of polymer deposition, cavity etch, and polymer removal. | 2017-06-22 |
20170178917 | SELF LIMITING LATERAL ATOMIC LAYER ETCH - Methods of and apparatuses for laterally etching semiconductor substrates using an atomic layer etch process involving exposing an oxidized surface of a semiconductor substrate to a fluorine-containing etch gas and heating the substrate to remove non-volatile etch byproducts by a sublimation mechanism are provided herein. Methods also including additionally pulsing a hydrogen-containing gas when pulsing the fluorine-containing etch gas. Apparatuses also include an ammonia mixing manifold suitable for separately preparing and mixing ammonia for use in various tools. | 2017-06-22 |
20170178918 | POST-POLISH WAFER CLEANING - An apparatus for semiconductor wafer treatment is provided including a polishing stage configured for polishing a surface of the semiconductor wafer, a rinse stage configured for cleaning the surface of the semiconductor wafer and a mixer connected with the rinse stage and configured for supplying a mixture of at least deionized water and an inert gas to the rinse stage. | 2017-06-22 |
20170178919 | SURFACE MACHINING METHOD FOR SINGLE CRYSTAL SIC SUBSTRATE, MANUFACTURING METHOD THEREOF, AND GRINDING PLATE FOR SURFACE MACHINING SINGLE CRYSTAL SIC SUBSTRATE - A surface machining method for a single crystal SiC substrate, including: a step of mounting a grinding plate which includes a soft pad and a hard pad sequentially attached onto a base metal having a flat surface, a step of generating an oxidation product by using the grinding plate, and a step of grinding the surface while removing the oxidation product, wherein abrasive grains made of at least one metallic oxide that is softer than single crystal SiC and has a bandgap are fixed to the surface of the hard pad. | 2017-06-22 |
20170178920 | TECHNIQUE TO TUNE SIDEWALL PASSIVATION DEPOSITION CONFORMALITY FOR HIGH ASPECT RATIO CYLINDER ETCH - Methods, apparatus and systems for forming a recessed feature in dielectric material on a semiconductor substrate are provided. Separate etching and deposition operations are employed in a cyclic manner. Each etching operation partially etches the feature. Each deposition operation forms a protective film on the sidewalls of the feature to prevent lateral etch of the dielectric material during the etching operations. The protective film may be deposited under different conditions (e.g., pressure, duration of reactant delivery, duration of plasma exposure, RF power, and/or RF duty cycle, etc.) in different deposition operations. Such conditions may affect the degree of conformality at which the protective film forms. In various embodiments, one or more protective films may be sub-conformal. In these or other embodiments, one or more other protective films may be conformal. | 2017-06-22 |
20170178921 | ETCHING METHOD - An etching method performed by an etching apparatus includes a first process of causing a first high-frequency power supply to output a first high-frequency power with a first frequency and causing a second high-frequency power supply to output a second high-frequency power with a second frequency lower than the first frequency in a cryogenic environment where the temperature of a wafer is −35° C. or lower, to generate plasma from a hydrogen-containing gas and a fluorine-containing gas and to etch, with the plasma, a multi-layer film of silicon dioxide and silicon nitride and a single-layer film of silicon dioxide that are formed on the wafer; and a second process of stopping the output of the second high-frequency power supply. The first process and the second process are repeated multiple times, and the first process is shorter in time than the second process. | 2017-06-22 |
20170178922 | ETCHING METHOD - An etching method for etching a silicon oxide film is provided that includes generating a plasma from a gas including a hydrogen-containing gas and a fluorine-containing gas using a high frequency power for plasma generation, and etching the silicon oxide film using the generated plasma. The fluorine-containing gas includes a hydrofluorocarbon gas, and the sticking coefficient of radicals generated from the hydrofluorocarbon gas is higher than the sticking coefficient of radicals generated from carbon tetrafluoride (CF | 2017-06-22 |
20170178923 | IODINE-CONTAINING COMPOUNDS FOR ETCHING SEMICONDUCTOR STRUCTURES - A method for etching silicon-containing films is disclosed. The method includes the steps of introducing a vapor of an iodine-containing etching compound into a reaction chamber containing a silicon-containing film on a substrate, wherein the iodine-containing etching compound has the formula C | 2017-06-22 |
20170178924 | OXIDE ETCH SELECTIVITY ENHANCEMENT - A method of etching exposed silicon oxide on patterned heterogeneous structures is described and includes a gas phase etch using plasma effluents formed in a remote plasma. The remote plasma excites a fluorine-containing precursor in combination with an oxygen-containing precursor. Plasma effluents within the remote plasma are flowed into a substrate processing region where the plasma effluents combine with water vapor or an alcohol. The combination react with the patterned heterogeneous structures to remove an exposed silicon oxide portion faster than an exposed silicon nitride portion. The inclusion of the oxygen-containing precursor may suppress the silicon nitride etch rate and result in unprecedented silicon oxide etch selectivity. | 2017-06-22 |
20170178925 | PLASMA PROCESSING METHOD - To provide a plasma processing device, a plasma processing method and a method of manufacturing electronic devices capable of performing high-speed processing as well as using the plasma stably. In an inductively-coupled plasma, torch unit, a coil, a first ceramic block and a second ceramic block are arranged in parallel, and a long chamber has an annular shape. Plasma generated in the chamber is ejected from an opening in the chamber toward a substrate. The substrate is processed by moving the long chamber and the substrate mounting table relatively in a direction perpendicular to a longitudinal direction of the opening. A discharge suppression gas is introduced into a space between the inductively-coupled plasma torch unit and the substrate inside the chamber through a discharge suppression gas supply hole, thereby generating long plasma stably. | 2017-06-22 |
20170178926 | POLISHING COMPOSITION AND POLISHING METHOD - The present invention relates to a polishing composition including water and silica, wherein the silica has a BET specific surface area of 30 m | 2017-06-22 |
20170178927 | Methods Of Treating Nitride Films - Methods for reducing oxygen content in an oxidized annealed metal nitride film comprising exposing the film to a plasma. | 2017-06-22 |
20170178928 | Method Of Fabricating Low-Profile Footed Power Package - A method is disclosed of fabricating a power package which includes a heat tab extending from a die pad exposed on the underside of the package, which facilitates the removal of heat from the die to the PCB or other surface on which the package is mounted. The heat tab has a bottom surface coplanar with the flat bottom surface of the die pad and bottom surface of a lead. The lead includes a horizontal foot segment, a vertical columnar segment, and a horizontal cantilever segment facing the die pad. The heat tab may also have a foot. A die containing a power device is mounted on a top surface of the die pad and may be electrically connected to the lead using a bonding wire or clip. The die may be mounted on the die pad with as electrically conductive material, and the package may also include a lead that extends from the die pad and is thus electrically tied to the bottom of the die. The result is a package with a minimal footprint that is suitable for the technique known as “wave soldering” that is used in relatively low-cost printed circuit board assembly factories. | 2017-06-22 |
20170178929 | A Method For Low Temperature Bonding Of Wafers - A method for bonding wafers is provided. The method comprises the steps of providing a first wafer having an exposed first layer, the first layer comprising a first metal; and providing a second wafer having an exposed second layer, the second layer comprising a second metal, the first metal and the second metal capable of forming a eutectic mixture having a eutectic melting temperature. The method further comprises the steps of contacting the first layer with the second layer; and applying a predetermined pressure at a predetermined temperature to form a solid-state diffusion bond between the first layer and the second layer, wherein the predetermined temperature is below the eutectic melting temperature. | 2017-06-22 |
20170178930 | SUBSTRATE ALIGNING METHOD, SUBSTRATE RECEIVING METHOD, SUBSTRATE LIQUID PROCESSING METHOD, SUBSTRATE ALIGNING APPARATUS, SUBSTRATE RECEIVING APPARATUS, SUBSTRATE LIQUID PROCESSING APPARATUS, AND SUBSTRATE PROCESSING SYSTEM - A substrate aligning method includes receiving a substrate by moving a substrate support from an outside of an outer periphery toward a central portion of the substrate along the substrate; and aligning the substrate such that the substrate support moves from a position different from a position partially upwardly warped along an outer peripheral edge of the substrate and a position partially downwardly warped along the outer peripheral edge of the substrate toward the central portion of the substrate so as to receive the substrate. | 2017-06-22 |
20170178931 | Substrate Chuck and Substrate Bonding System Including the Same - Provided are a substrate chuck and a substrate bonding system including the substrate chuck. The substrate bonding system includes a lower substrate chuck and an upper substrate chuck disposed on the lower substrate chuck. The lower substrate chuck has a non-flat lower substrate contact surface, and the upper substrate chuck has a flat upper substrate contact surface. | 2017-06-22 |
20170178932 | METHODS AND APPARATUS FOR INTERACTIVELY AND DYNAMICALLY UPDATING A SCHEMATIC OVERLAY - A computer implemented method of dynamically updating an interactive diagnostic schematic overlay comprises displaying a first drawing comprising a plurality of static graphical objects, each static graphical object corresponding to a design element of a complex system and identifying a diagnostic schematic overlay comprising a plurality of dynamic graphical objects, wherein each dynamic graphical object is aligned with a static graphical object of the plurality of static graphical objects. In an embodiment, the diagnostic schematic overlay further includes a plurality of fields, wherein each field may be populated with one or more dynamic graphical objects, and the method further includes determining a design element operating state and/or a design element operating parameter for at least some of the static graphical objects at a first instance in time and displaying, together with the first drawing, determined operating states and determined operating parameters as an updated diagnostic schematic overlay. | 2017-06-22 |
20170178933 | HIGH THROUGHPUT SERIAL WAFER HANDLING END STATION - An ion implantation apparatus, system, and method are provided for transferring a plurality of workpieces between vacuum and atmospheric pressures, wherein an alignment mechanism is operable to align a plurality of workpieces for generally simultaneous transportation to a dual-workpiece load lock chamber. The alignment mechanism comprises a characterization device, an elevator, and two vertically-aligned workpiece supports for supporting two workpieces. First and second atmospheric robots are configured to generally simultaneously transfer two workpieces at a time between load lock modules, the alignment mechanism, and a FOUP. Third and fourth vacuum robots are configured to transfer one workpiece at a time between the load lock modules and a process module. | 2017-06-22 |
20170178934 | Adaptive Alignment Methods and Systems - Adaptive alignment methods and systems are disclosed. An adaptive alignment system may include a scanner configured to align a wafer and an analyzer in communication with the scanner. The analyzer may be configured to: recognize at least one defined analysis area; determine whether any perturbations exist within the analysis area; and in response to at least one perturbation determined to be within the analysis area, invoke a fall back alignment strategy or report the at least one perturbation to the scanner. | 2017-06-22 |
20170178935 | SUBSTRATE TRANSFER METHOD AND STORAGE MEDIUM - A substrate transfer method is provided. The substrate transfer method comprises: loading the transfer container to a load port, and separating the cover body from the container main body; detecting an accommodation status of the substrate in the container main body by a detection unit; correcting, by a correction device, the accommodation status of the substrate in the container main body in which the accommodation status of the substrate detected by the detection unit is abnormal; and allowing a substrate transfer device to enter the container main body in which the accommodation status of the substrate is corrected, and unloading the substrate from the container main body. | 2017-06-22 |
20170178936 | WAFER PROCESSING SYSTEM AND WAFER PROCESSING METHOD USING SAME - A system for processing a wafer may use a wafer identification (ID) assigned by a wafer manufacturing company as an ID code of the wafer in managing the wafer by a semiconductor manufacturing company. | 2017-06-22 |
20170178937 | INTERLOCKING NEST WAFER PROTECTOR - An interlocking ring wafer separator for reducing particles during shipment of integrated circuit wafers has a wafer shelf, an interlocking tab which prevents the edge of the wafer from coming into contact with the inner wall of the wafer shipping container, and an interlocking slot into which the interlocking tab of a second interlocking ring wafer separator may be inserted locking the two interlocking ring wafer separators together in the coin stacked wafers. | 2017-06-22 |
20170178938 | ROBOT SYSTEM AND CARRYING METHOD - A robot system includes a robot including a first hand, a second hand, an arm mechanism, and an elevator. The first hand is to hold a substrate. The second hand is to hold the substrate. The arm mechanism supports the first hand and the second hand to provide a height difference between the first hand and the second hand in a height direction of the robot. The elevator is to move the arm mechanism in the height direction within a moving range larger than the height difference. Both the first hand and the second hand put the substrate in the holder. Circuitry is configured to control the robot to move the arm mechanism in the height direction by the elevator to pass the substrate from the first hand to the second hand via the holder. | 2017-06-22 |
20170178939 | SUBSTRATE TRANSPORT DEVICE AND SUBSTRATE PROCESSING APPARATUS - A substrate transport device includes a shaft, a first moving part for moving the shaft in a vertical direction and in a rotational direction, at least one rotation arm attached to the shaft, and a supporting part having an upper surface waved as seen front view, wherein the rotation arm includes a contact rotation arm which directly or indirectly contacts the upper surface of the supporting part. | 2017-06-22 |
20170178940 | SUBSTRATE TRANSFER APPARATUS AND SUBSTRATE TRANSFER METHOD - Disclosed is a substrate transfer apparatus including: a pair of hands facing with each other; an opening/closing mechanism configured to move the pair of hands symmetrically in an opening/closing direction; a driving unit configured to transmit a power to the opening/closing mechanism; and a controller configured to control an operation of the driving unit. The opening/closing mechanism includes: a rotating body configured to rotate depending on a moving amount of the pair of hands in the opening/closing direction, and a sensor configured to detect a rotating amount of the rotating body. The controller controls an operation of the driving unit based on a signal from the sensor. | 2017-06-22 |
20170178941 | APPARATUS, METHOD AND NON-TRANSITORY STORAGE MEDIUM FOR ACCOMODATING AND PROCESSING A SUBSTRATE - A substrate accommodating and processing apparatus is provided with a cassette mounting table, a processing part, a substrate transfer mechanism, a partition wall, a cassette stage, and a lid attaching/detaching mechanism. The lid attaching/detaching mechanism is provided with a key configured to be engaged with a key hole installed in the lid, and configured to switch a latch between locking and unlocking positions. The mechanism is also provided with a lid abnormality detecting sensor, a lid attaching/detaching mechanism closing sensor, a lid attaching/detaching mechanism opening sensor, a pressure sensor and a control part. | 2017-06-22 |
20170178942 | LOAD PORT AND LOAD PORT ATMOSPHERE REPLACING METHOD - Provided is a load port capable of loading and unloading a substrate by a transfer robot in a state where a purge gas atmosphere is maintained inside a substrate storage space. After the lid of the substrate storage container is opened, an opening portion of the substrate storage container is closed by a frame sealing a peripheral edge of the opening portion of the substrate storage container and a shutter portion where a plurality of shielding plates are disposed in a vertical direction at a third position which is further moved forward from a release position. The shutter portion can locally move all or a portion of the shielding plates to form a narrow opening portion (third opening portion), and transferring of the substrate in the state where an atmosphere of the substrate storage space is replaced is performed through the narrow opening portion (third opening portion). | 2017-06-22 |
20170178943 | ELECTROSTATIC HEATING SUBSTRATE HOLDER WHICH IS POLARISED AT HIGH VOLTAGE - The present invention relates to a support comprising:
| 2017-06-22 |
20170178944 | ELECTROSTATIC CHUCK - An electrostatic chuck includes: a ceramic dielectric substrate having a first major surface, a second major surface, and a through-hole; a metallic base plate which has a gas introduction path that communicates with the through-hole; and a bonding layer which is provided between the ceramic dielectric substrate and the base plate and includes a resin material. The bonding layer has a space which is provided between an opening of the through-hole in the second major surface and the gas introduction path and is larger than the opening in a horizontal direction, and a first area in which an end face of the bonding layer on a side of the space intersects with the second major surface being recessed from the opening further than a second area of the end face which is different from the first area. | 2017-06-22 |
20170178945 | SUBSTRATE PROCESSING SYSTEM AND SUBSTRATE PROCESSING METHOD - A substrate processing system includes an index module including wafer carriers. First and second heat processing units are disposed adjacent to the index module. Each of the first and second heat processing units includes a plurality of first heat processing plates sequentially stacked. First and second transfer robots are disposed adjacent to the first and second heat processing units, respectively. Each of the first and second transfer robots is movable along a vertical transfer path and to rotate. First and second coating units are disposed adjacent to first sides of the first and second transfer robots, respectively. Each of the first and second coating units includes a plurality of coating devices sequentially stacked. First and second bake units are disposed adjacent to second sides of the first and second transfer robots, respectively. Each of the first and second bake units includes a plurality of second heat processing plates sequentially stacked. | 2017-06-22 |
20170178946 | PULSED-MODE DIRECT-WRITE LASER METALLIZATION - A method for manufacturing includes coating a substrate ( | 2017-06-22 |
20170178947 | Trench Separation Diffusion for High Voltage Device - A manufacturable and economically viable edge termination structure allows a semiconductor device to withstand a very high reverse blocking voltage (for example, 8500 volts) without suffering breakdown. A P type peripheral aluminum diffusion region extends around the bottom periphery of a thick die. The peripheral aluminum diffusion region extends upward from the bottom surface of the die, extending into N− type bulk silicon. A deep peripheral trench extends around the upper periphery of the die. The deep trench extends from the topside of the die down toward the peripheral aluminum diffusion region. A P type sidewall doped region extends laterally inward from the inner sidewall of the trench, and extends laterally outward from the outer sidewall of the trench. The P type sidewall doped region joins with the P type peripheral aluminum diffusion region, thereby forming a separation edge diffusion structure that surrounds the active area of the die. | 2017-06-22 |
20170178948 | INTERLEVEL AIRGAP DIELECTRIC - A method of forming a semiconductor device includes: forming a lower trace in a lower dielectric layer; reducing a height of the lower trace a distance equal to gap height (g) to form an initial void region; filling the initial void region with an amorphous carbon layer; forming an upper dielectric layer above the amorphous carbon layer; covering the amorphous carbon layer with at least an oxide layer and a nitride layer; forming a hole in the oxide and nitride layers to expose a portion of the amorphous carbon layer; exposing the amorphous carbon layer to oxygen plasma to remove the amorphous carbon layer; sputtering a metal layer over the oxide layer and into a void created removal of the amorphous carbon layer to divide the void such that it includes an airgap; and forming an upper trace over the airgap. | 2017-06-22 |
20170178949 | SEMICONDUCTOR DEVICES - A semiconductor device may include a substrate, a first interlayered insulating layer on the substrate having openings, conductive patterns provided in the openings, first to fourth insulating patterns stacked on the substrate provided with the conductive patterns, and a second interlayered insulating layer provided on the fourth insulating pattern. | 2017-06-22 |
20170178950 | FABRICATION METHOD OF A STACK OF ELECTRONIC DEVICES - This method includes the following steps: a) providing a first structure successively including a substrate, an electronic device, a dielectric layer, and a first semiconductor layer; b) providing a second structure successively including a substrate, an active layer, a dielectric layer, and a second semiconductor layer, the active layer being designed to form an electronic device; c) bonding the first and second structures by direct bonding between the first and second semiconductor layers so as to form a bonding interface; d) removing the substrate of the second structure so as to expose the active layer; e) introducing dopants into the first and second semiconductor layers so as to form a ground plane. | 2017-06-22 |
20170178951 | Via Corner Engineering in Trench-First Dual Damascene Process - An integrated circuit structure includes a first dielectric layer, an etch stop layer over the first dielectric layer, and a second dielectric layer over the etch stop layer. A via is disposed in the first dielectric layer and the etch stop layer. A metal line is disposed in the second dielectric layer, wherein the metal line is connected to the via. The etch stop layer includes a first portion having an edge contacting an edge of the via, wherein the first portion has a first chemical composition, and a second portion in contact with the first portion. The second portion is spaced apart from the via by the first portion, and wherein the second portion has a second chemical composition different from the first composition. | 2017-06-22 |
20170178952 | METHOD FOR MANUFACTURING DUAL DAMASCENE STRUCTURE - A method for manufacturing a semiconductor device include forming a dielectric layer over an underlying layer; forming an etch barrier over the dielectric layer, wherein a partial via opening is formed in the etch barrier and exposes a lower portion of the etch barrier; forming an assist-etch barrier over the etch barrier to fill the partial via opening; patterning the assist-etch barrier to form an initial trench opening in the assist-etch barrier, wherein the initial trench opening communicates with the partial via opening; patterning the lower portion of the etch barrier exposed by the partial via opening to form a final via opening in the etch barrier; patterning the dielectric layer exposed by the final via opening to form an initial via hole in the dielectric layer; patterning the etch barrier exposed by the initial trench opening to form a final trench opening in the etch barrier; patterning a lower portion of the dielectric layer exposed by the initial via hole to form a final via hole in the dielectric layer; and patterning a upper portion of the dielectric layer exposed by the final trench opening to form a trench, wherein the trench communicates the final via hole. | 2017-06-22 |
20170178953 | METHODS AND DEVICES FOR BACK END OF LINE VIA FORMATION - Back end of line via formation for semiconductor devices and methods of fabricating the semiconductor devices. One method includes, for instance: obtaining a wafer with a substrate and at least one contact in the substrate; depositing at least one lithography stack over the substrate; performing lithography to pattern at least one via opening; depositing a block co-polymer coating over the wafer into the at least one via opening; performing an ashing to remove excess block co-polymer material and form block co-polymer caps; and performing a thermal bake to separate the block co-polymer caps into a first material and a second material. An intermediate semiconductor device is also disclosed. | 2017-06-22 |
20170178954 | INTERCONNECTION STRUCTURE AND MANUFACTURING METHOD THEREOF - An interconnection structure includes a first dielectric layer, a bottom conductive feature present in the first dielectric layer, a second dielectric layer present on the first dielectric layer, an aluminum-containing etch stop layer present between the first dielectric layer and the second dielectric layer, an upper conductive via present at least in the second dielectric layer and electrically connected to the bottom conductive feature, and at least one aluminum-containing fragment present at least at a bottom corner of the upper conductive via. | 2017-06-22 |
20170178955 | LOW DAMAGE LOW-K DIELECTRIC ETCH - A method of forming an interconnect structure for an integrated circuit. A dielectric stack is formed on the substrate including an etch-stop layer, a low-k or ULK dielectric layer, and a hard mask layer. The low-k or ULK dielectric is etched using at least two etching processes wherein each etching process is followed by an etch repair process where the etch repair process includes flowing at least one hydrocarbon into the reactor and generating a plasma. The photoresist may be removed using at least two ashing processes wherein each ashing process is followed by an ash repair process where the etch repair process includes flowing at least one hydrocarbon into the reactor and generating a plasma. | 2017-06-22 |
20170178956 | METHOD AND APPARATUS FOR DEPOSITING COBALT IN A FEATURE - Methods and apparatus for depositing a cobalt layer in a feature, such as, a word line formed in a substrate, are provided herein. In some embodiments, method of processing a substrate includes: exposing a substrate at a first temperature to a cobalt containing precursor to deposit a cobalt layer within a word line feature formed in the substrate, wherein the word line feature is part of a 3D NAND device; and annealing the substrate to remove contaminants from the cobalt layer and to reflow the cobalt layer into the word line feature, wherein the substrate is at a second temperature greater than the first temperature during the annealing. | 2017-06-22 |
20170178957 | TRENCH LINER FOR REMOVING IMPURITIES IN A NON-COPPER TRENCH - The present disclosure involves a method of fabricating a semiconductor device in a semiconductor technology node that is 5-nanometer or smaller. An opening is formed that extends through a plurality of layers over a substrate. A barrier layer is formed on surfaces of the opening. A liner layer is formed over the barrier layer in the opening. The barrier layer and the liner layer have different material compositions. The opening is filled with a non-copper metal material. The non-copper material is formed over the liner layer. In some embodiments, the non-copper metal material includes cobalt. | 2017-06-22 |
20170178958 | METHOD AND STRUCTURES FOR VIA SUBSTRATE REPAIR AND ASSEMBLY - A component can include a substrate having an opening extending between first and second surfaces thereof, and an electrically conductive via having first and second portions. The first portion can include a first layer structure extending within the opening and at least partially along an inner wall of the opening, and a first principal conductor extending within the opening and at least partially overlying the first layer structure. The first portion can be exposed at the first surface and can have a lower surface located between the first and second surfaces. The second portion can include a second layer structure extending within the opening and at least partially along the lower surface of the first portion, and a second principal conductor extending within the opening and at least partially overlying the second layer structure. The second portion can be exposed at the second surface. | 2017-06-22 |
20170178959 | VERTICAL FETS WITH VARIABLE BOTTOM SPACER RECESS - A method of forming a variable spacer in a vertical transistor device includes forming a first source/drain of a first transistor on a substrate; forming a second source/drain of a second transistor on the substrate adjacent to the first source/drain, an isolation region arranged in the substrate between the first source/drain and the second source/drain; depositing a spacer material on the first source/drain; depositing the spacer material on the second source/drain; forming a first channel extending from the first source drain and through the spacer material; forming a second channel extending from the second source/drain and through the spacer material; wherein the spacer material on the first source/drain forms a first spacer and the spacer material on the second source/drain forms a second spacer, the first spacer being different in thickness than the second spacer. | 2017-06-22 |
20170178960 | SELECTIVE REMOVAL OF SEMICONDUCTOR FINS - An array of semiconductor fins is formed on a top surface of a substrate. A dielectric material liner is formed on the surfaces of the array of semiconductor fins. A photoresist layer is applied and patterned such that sidewalls of an opening in the photoresist layer are parallel to the lengthwise direction of the semiconductor fins, and are asymmetrically laterally offset from a lengthwise direction passing through the center of mass of a semiconductor fin to be subsequently removed. An angled ion implantation is performed to convert a top portion of dielectric material liner into a compound material portion. The compound material portion is removed selective to the remaining dielectric material liner, and the physically exposed semiconductor fin can be removed by an etch or converted into a dielectric material portion by a conversion process. The dielectric material liner can be removed after removal of the semiconductor fin. | 2017-06-22 |
20170178961 | TANTALUM COMPOUND AND METHODS OF FORMING THIN FILM AND FABRICATING INTEGRATED CIRCUIT DEVICE BY USING THE SAME - A tantalum compound, a method of forming a thin film, and a method of fabricating an integrated circuit device, the tantalum compound being represented by the following General Formula (I): | 2017-06-22 |
20170178962 | METHOD TO GROW THIN EPITAXIAL FILMS AT LOW TEMPERATURE - Implementations of the present disclosure generally relate to methods for epitaxial growth of a silicon material on an epitaxial film. In one implementation, the method includes forming an epitaxial film over a semiconductor fin, wherein the epitaxial film includes a top surface having a first facet and a second facet, and forming an epitaxial layer on at least the top surface of the epitaxial film by alternatingly exposing the top surface to a first precursor gas comprising one or more silanes and a second precursor gas comprising one or more chlorinated silanes at a temperature of about 375° C. to about 450° C. and a chamber pressure of about 5 Torr to about 20 Torr. | 2017-06-22 |
20170178963 | SRAM DESIGN TO FACILITATE SINGLE FIN CUT IN DOUBLE SIDEWALL IMAGE TRANSFER PROCESS - A double sidewall image transfer process for forming FinFET structures having a fin pitch of less than 40 nm generates paired fins with a spacing determined by the width of a sidewall spacer that forms a second mandrel. Here, the fin pairs are created at two different spacings without requiring the minimum space for the standard sidewall structure. An enlarged space between paired fins is created by placing two first mandrel shapes close enough so as to overlap or merge two sidewall spacer shapes so as to form a wider second mandrel upon further processing. The fin pair created from the wider second mandrel is spaced at about 2 times the fin pair created from the narrower second mandrel. For some circuits, such as an SRAM bitcell, the wider second mandrel can be utilized to form an inactive fin not utilized in the circuit structure, which can be removed. In some embodiments, all dummy inactive fins are eliminated for a simpler process | 2017-06-22 |
20170178964 | GATE DEVICE OVER STRAINED FIN STRUCTURE - A method for forming a semiconductor device includes forming a fin structure on a substrate, forming a shallow trench isolation region adjacent the fin structure so that an upper portion of the fin structure is exposed, forming a dummy gate over the exposed fin structure, forming an interlayer dielectric layer around the dummy gate, removing the dummy gate to expose the fin structure, and after removing the dummy gate, introducing a strain into a crystalline structure of the exposed fin structure. | 2017-06-22 |
20170178965 | INTEGRATING A PLANAR FIELD EFFECT TRANSISTOR (FET) WITH A VERTICAL FET - One embodiment provides a method of integrating a planar field-effect transistor (FET) with a vertical FET. The method comprises masking and etching a semiconductor of the vertical FET to form a fin, and providing additional masking, additional etching, doping and depositions to isolate a bottom source/drain (S/D) region. A dielectric is formed on the bottom S/D region to form a spacer. The method further comprises depositing gate metals, etching a vertical gate for the vertical FET and a planar gate for the planar FET using a shared gate mask, depositing dielectric, etching the dielectric to expose one or more portions of the fin, growing epitaxy on a top S/D region, masking and etching S/D contact openings for the bottom S/D region, forming silicide regions in S/D regions, depositing contact metal in the silicide regions to form contacts, and planarizing the contacts. | 2017-06-22 |