25th week of 2017 patent applcation highlights part 72 |
Patent application number | Title | Published |
20170179166 | ARRAY SUBSTRATE AND MANUFACTURING METHOD THEREOF AND DISPLAY APPARATUS - The present invention relates to an array substrate, which comprises: a display region and a drive circuit region; the drive circuit region comprises GOA units, the GOA unit comprising a substrate, a gate electrode layer, an insulation layer, an active layer and a source/drain electrode layer, and the drive circuit region further comprises a gate wire connecting to the gate electrode layer, and a source/drain layer wire at the same layer with the source/drain electrode layer, wherein the area between the portions of the gate wire and the source/drain layer wire which intercross with each other is only formed with the insulation layer. The invention further relates to a manufacturing method of an array substrate and a display apparatus comprising the array substrate. | 2017-06-22 |
20170179167 | SEMICONDUCTOR DEVICE - Solved is a problem of attenuation of output amplitude due to a threshold value of a TFT when manufacturing a circuit with TFTs of a single polarity. In a capacitor ( | 2017-06-22 |
20170179168 | DISPLAY DEVICE - According to one embodiment, a display device includes an insulating substrate, display function layer disposed above the insulating substrate, reflective electrode disposed between the insulating substrate and the display function layer, to which a potential for image display is applied, and antenna having a band shape disposed between the insulating substrate and the reflective electrode. | 2017-06-22 |
20170179169 | DIRECT INTEGRATION OF PHOTOVOLTAIC DEVICE INTO CIRCUIT BOARD - Aspects relate to a system and a method of manufacturing an integrated device. The method includes providing a circuit board, configuring an upper surface of the circuit board as a substrate, integrally depositing photovoltaic device layers that include at least a semi-conductor absorber layer, a buffer layer, and a top electrode layer on the upper surface of the circuit board to form a photovoltaic device using the upper surface of the circuit board as a photovoltaic device substrate, wherein the buffer layer is integrally deposited between the semi-conductor absorber layer and the top electrode, and electrically connecting the photovoltaic device to one or more on-board electronic components. | 2017-06-22 |
20170179170 | PIXEL FOR CMOS IMAGE SENSOR AND IMAGE SENSOR INCLUDING THE SAME - A pixel of a complementary metal-oxide-semiconductor (CMOS) image sensor includes a semiconductor substrate having a first surface and a third surface formed by removing part of the semiconductor substrate from a second surface, an active region which is formed between the first surface and the third surface and which contains a photoelectric conversion element generating charges in response to light incident on the substrate at the third surface, and a trench-type isolation region formed from either of the first and third surfaces to isolate the active region from an adjacent active region. The trench-type isolation region is filled with first material in a process that leaves a void in the material, the void is filled or partially filled with second material, and then a layer of third material is formed over the resulting structure composed of the first and second materials. | 2017-06-22 |
20170179171 | SOLID-STATE IMAGING DEVICE AND ELECTRONIC APPARATUS - A solid-state imaging device includes a semiconductor layer on which a plurality of pixels are arranged along a light-receiving surface being a main surface of the semiconductor layer, photoelectric conversion units provided for the respective pixels in the semiconductor layer, and a trench element isolation area formed by providing an insulating layer in a trench pattern formed on a light-receiving surface side of the semiconductor layer, the trench element isolation area being provided at a position displaced from a pixel boundary between the pixels. | 2017-06-22 |
20170179172 | SOLID-STATE IMAGING DEVICE, PRODUCTION METHOD OF THE SAME, AND IMAGING APPARATUS - A solid-state imaging device in which a pixel circuit formed on the first surface side of a semiconductor substrate is shared by a plurality of light reception regions and second surface side of the semiconductor substrate is the light incident side of the light reception regions. The second surface side regions of the light reception regions are arranged at approximately even intervals and the first surface side regions of the light reception regions e are arranged at uneven intervals. Respective second surface side regions and first surface side regions are joined in the semiconductor substrate so that the light reception regions extend from the second surface side to the first surface side of the semiconductor substrate. | 2017-06-22 |
20170179173 | SPAD ARRAY WITH PIXEL-LEVEL BIAS CONTROL - A sensing device includes an array of sensing elements. Each sensing element includes a photodiode, including a p-n junction, and a local biasing circuit, coupled to reverse-bias the p-n junction at a bias voltage greater than a breakdown voltage of the p-n junction by a margin sufficient so that a single photon incident on the p-n junction triggers an avalanche pulse output from the sensing element. A bias control circuit is coupled to set the bias voltage in different ones of the sensing elements to different, respective values that are greater than the breakdown voltage. | 2017-06-22 |
20170179174 | IMAGE SENSOR INCLUDING VERTICAL TRANSFER GATE - An image sensor includes a photoelectric conversion element, including a first impurity region and a second impurity region, wherein the first impurity region contacts a first surface of a substrate, wherein the second impurity region has conductivity complementary to the first impurity region and is formed in the substrate and below the first impurity region; a pillar formed over the photoelectric conversion element; a transfer gate formed over the photoelectric conversion element to surround the pillar; and a channel layer formed between the transfer gate and the pillar and contacting the photoelectric conversion element, wherein the channel layer contacts the first impurity region and has the same conductivity as the second impurity region. | 2017-06-22 |
20170179175 | SOLID-STATE IMAGE SENSOR - A solid-state image sensor includes: a pixel array that includes first pixels, each having first and second photoelectric conversion units, and second pixels, each having third and fourth photoelectric conversion units; first to fourth transfer gates via which a signal charge respectively generated in the first to fourth photoelectric conversion units is respectively transferred to first to fourth charge voltage conversion units. At least one of a gate width, a gate length and an installation position of at least one transfer gate among the first to fourth transfer gates is altered to achieve uniformity in voltage conversion efficiency at the first to fourth charge voltage conversion units. | 2017-06-22 |
20170179176 | IMAGING SYSTEMS WITH THROUGH-OXIDE VIA CONNECTIONS - An imaging system may include an image sensor package with through-oxide via connections between the image sensor die and the digital signal processing die in the image sensor package. The image sensor die and the digital signal processing die may be attached to each other. The through-oxide via may connect a bond pad on the image sensor die with metal routing paths in the image sensor and digital signal processing dies. The through-oxide via may simultaneously couple the image sensor die to the digital signal processing die. The through-oxide via may be formed through a shallow trench isolation structure in the image sensor die. The through-oxide via may be formed through selective etching of the image sensor and digital signal processing dies. | 2017-06-22 |
20170179177 | SOLID STATE IMAGE SENSOR WITH EXTENDED SPECTRAL RESPONSE - Various embodiments are directed to an image sensor that includes a first sensor portion and a second sensor portion coupled to the first sensor portion. The second sensor portion may be positioned relative to the first sensor portion so that the second sensor portion may initially detect light entering the image sensor, and some of that light passes through the second sensor portion and is be detected by the first sensor portion. In some embodiments, the second sensor portion may be configured to have a thickness suitable for sensing visible light. The first sensor portion may be configured to have a thickness suitable for sensing IR or NIR light. As a result of the arrangement and structure of the second sensor portion and the first sensor portion, the image sensor captures substantially more light from the light source. | 2017-06-22 |
20170179178 | COLOR SEPARATION ELEMENT ARRAY, IMAGE SENSOR INCLUDING THE SAME, AND ELECTRONIC DEVICE - A color separation element array, an image sensor including the color separation element array, and an electronic device including the color separation element array are provided. The color separation element array includes a plurality of color separation elements configured to separate an incident light into a color light according to wavelength bands in a transparent layer, the plurality of color separation elements including a first element and a second element having different refractive indices, and the first element and second element being arranged in a horizontal direction. | 2017-06-22 |
20170179179 | IMAGE SENSOR AND ELECTRONIC DEVICE INCLUDING THE SAME - An image sensor includes a semiconductor substrate integrated with at least one first photo-sensing device sensing light in a first wavelength region and at least one second photo-sensing device sensing light in a second wavelength region shorter than the first wavelength region, a photoelectric device including a pair of electrodes facing each other and a light absorption layer between the electrodes, the photoelectric device selectively absorbing light in a third wavelength region between the first wavelength region and the second wavelength region, and a nanostructural body between the semiconductor substrate and the photoelectric device, the nanostructural body including at least two parts having different optical paths. | 2017-06-22 |
20170179180 | LIGHT FIELD IMAGING DEVICE AND METHOD FOR FABRICATING THE SAME - A light field imaging device includes an image sensor having a plurality of pixels arranged two-dimensionally therein; a microlens array formed over the image sensor, the microlens array having a plurality of microlenses arranged two-dimensionally therein; and a plurality of support structures formed between the image sensor and the microlens array for providing an air gap therebetween. | 2017-06-22 |
20170179181 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a first semiconductor substrate having a first wiring layer which includes a first conductive pad, a second semiconductor substrate disposed on the first semiconductor substrate and including a second wiring layer which includes a second conductive pad, a first oxide layer disposed on the second semiconductor substrate and containing a second end of an intermediate connection which extends vertically through the second semiconductor substrate and has a first end electrically connected to the second conductive pad, and a third semiconductor substrate disposed on the first oxide layer and including a third wiring layer which includes a third conductive pad. The second end of the intermediate connection layer is electrically connected to the third conductive pad via a metal bond. | 2017-06-22 |
20170179182 | SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME - A semiconductor package is disclosed. The semiconductor package a circuit substrate, a semiconductor chip mounted on and electrically connected to the circuit substrate, an optoelectronic chip mounted on the semiconductor chip, and an adhesive part interposed between the semiconductor chip and optoelectronic chip. | 2017-06-22 |
20170179183 | SEMICONDUCTOR DEVICE FOR WAFER-SCALE INTEGRATION - The semiconductor device comprises a semiconductor wafer with an integrated circuit, formed by a plurality of dies, a further semiconductor wafer, which differs from the semiconductor wafer in diameter and semiconductor material, the semiconductor wafer and the further semiconductor wafer being bonded to one another by means of a bonding layer, and an electrically conductive contact layer arranged on the further semiconductor wafer opposite to the bonding layer. | 2017-06-22 |
20170179184 | PHOTO RELAY - A photo relay includes an illuminating unit, a photoelectric conversion IC, a first MOS IC and a second MOS IC. The illuminating unit receives an input signal to generate an illuminating signal. The photoelectric conversion IC receives the illuminating signal to generate a voltage control signal accordingly. The second MOS IC is reversely stacked on the first MOS IC, such that the source electrodes of the two MOS ICs are electrically connected, and the gate electrodes of the two MOS ICs are electrically connected through a gate connection structure for receiving the voltage control signal, and the drain electrodes of the two MOS ICs generate an output signal according to the received voltage control signal. | 2017-06-22 |
20170179185 | SEMICONDUCTOR DEVICE - A semiconductor device is disclosed, which includes: at least one device layer being a crystallized layer for example including: a superlattice layer and/or a layer of group III-V semiconductor materials; and a passivation structure comprising one or more layers wherein at least one layer of the passivation structure is a passivation layer grown in-situ in a crystallized form on top of the device layer, and at least one of the one or more layers of the passivation structure includes material having a high density of surface states which forces surface pinning of an equilibrium Fermi level within a certain band gap of the device layer, away from its conduction and valence bands. | 2017-06-22 |
20170179186 | RADIATION DETECTOR FOR USE AS AN IMAGE INTENSIFIER - A flat panel detector is provided having a circular active area. The flat panel detector is built using complementary metal-oxide-semiconductor (CMOS) tiles. In one implementation, the flat panel detector having a circular active area can be used as a replacement for a conventional image intensifier, including an image intensifier used in a fluoroscopy system. | 2017-06-22 |
20170179187 | DIGITAL X-RAY DETECTOR AND METHOD FOR REPAIRING A BAD PIXEL THEREOF - Provided herein is a digital x-ray detector and a method for repairing a bad pixel thereof, the detector including a substrate; a gate line and a data line formed on the substrate such that the gate line and the data line intersect each other to form a pixel domain; a thin film transistor formed within the pixel domain such that the thin film transistor is adjacent to a portion where the gate line and the data line intersect each other, the thin film transistor including a gate electrode, an active layer, a source electrode and a drain electrode; a PIN diode which is formed within the pixel domain and which includes a lower electrode connected to the source electrode of the thin film transistor, a PIN layer formed on the lower electrode, and an upper electrode formed on the PIN layer; a bias line connected to the upper electrode of the PIN diode; and a scintillator arranged above the PIN diode, wherein on at least one of a surface of the drain electrode which faces the PIN diode and a surface of the PIN diode which faces the drain electrode, a groove is formed such that it expands a distance between the drain electrode and the PIN diode. | 2017-06-22 |
20170179188 | PHOTOELECTRIC CONVERSION DEVICE, IMAGE PICKUP SYSTEM, AND DRIVING METHOD OF THE PHOTOELECTRIC CONVERSION DEVICE - A photoelectric conversion device has a pixel area including an effective pixel row and a reference pixel row, the reference pixel row containing a plurality of reference pixel pairs, each pair composed of a first reference pixel and a second reference pixel arranged adjacent to each other. The first and second reference pixels output reference signals having different signal levels and independent of the quantity of incident light. | 2017-06-22 |
20170179189 | CURVED IMAGE SENSOR - An image sensor includes a plurality of photodiodes arranged in an array and disposed in a semiconductor material with pinning wells disposed between individual photodiodes in the plurality of photodiodes. The image sensor also includes a microlens layer. The microlens layer is disposed proximate to the semiconductor material and is optically aligned with the plurality of photodiodes. A spacer layer disposed between the semiconductor material and the microlens layer. The spacer layer has a concave cross-sectional profile across the array, and the microlens layer is conformal with the concave cross-sectional profile of the spacer layer. | 2017-06-22 |
20170179190 | METHOD OF MANUFACTURING IMAGE SENSOR FOR REDUCING CROSSTALK CHARACTERISTIC - An image sensor includes a plurality of photoelectric detectors, a plurality of color filters, and at least one pixel isolation region between adjacent ones of the photoelectric detectors. The color filters include a white color filter, and the color filters correspond to respective ones of the photoelectric detectors. The at least one pixel isolation region serves to physically and at least partially optically separate the photoelectric detectors from one another. | 2017-06-22 |
20170179191 | IMAGING DEVICE MANUFACTURING METHOD - There is provided an imaging device manufacturing method contributing to improved reliability and yield. The method includes forming a first insulating film on a polysilicon film and then removing a portion of the first insulating film formed on a second main surface and a portion of the first insulating film formed on a side surface of the substrate to expose a polysilicon film. After the polysilicon film is exposed, a second insulating film is formed on the first main surface by a plasma chemical vapor deposition (CVD) method. | 2017-06-22 |
20170179192 | Semiconductor Devices with Integrated Thin-Film Transistor Circuitry - Various embodiments include a semiconductor device with thin-film transistor (TFT) circuitry monolithically integrated with other non-TFT functional devices. One example is an integrated LED display panel, in which an array of LEDs is integrated with corresponding TFT driver circuitry. The TFT driver circuitry typically is an array of pixel drivers that drive the LEDs. | 2017-06-22 |
20170179193 | DOUBLE-MASKING TECHNIQUE FOR INCREASING FABRICATION YIELD IN SUPERCONDUCTING ELECTRONICS - An improved microfabrication technique for Josephson junctions in superconducting integrated circuits, based on the use of a double-layer lithographic mask for partial anodization of the side-walls and base electrode of the junctions. The top layer of the mask is a resist material, and the bottom layer is a dielectric material chosen so to maximize adhesion between the resist and the underlying superconducting layer, be etch-compatible with the underlying superconducting layer, and be insoluble in the resist and anodization processing chemistries. The superconductor is preferably niobium, under a silicon dioxide layer, with a conventional photoresist or electron-beam resist as the top layer. This combination results in a substantial increase in the fabrication yield of high-density superconducting integrated circuits, increase in junction uniformity and reduction in defect density. A dry etch more compatible with microlithography may be employed. | 2017-06-22 |
20170179194 | LOW TEMPERATURE ENCAPSULATION FOR MAGNETIC TUNNEL JUNCTION - A method of making a magnetic random access memory device comprises forming a magnetic tunnel junction on an electrode, the magnetic tunnel junction comprising a reference layer positioned in contact with the electrode, a tunnel barrier layer arranged on the reference layer, and a free layer arranged on the tunnel barrier layer; and depositing an encapsulating layer on and along sidewalls of the magnetic tunnel junction at a temperature of 40 to 60° C. using remote microwave plasma deposition wherein the encapsulation layer comprises silicon and nitrogen. An MRAM device made by the aforementioned method is also disclosed. | 2017-06-22 |
20170179195 | DEVICE SWITCHING USING LAYERED DEVICE STRUCTURE - A resistive switching device. The device includes a first electrode comprising a first metal material overlying the first dielectric material and a switching material comprising an amorphous silicon material. The device includes a second electrode comprising at least a second metal material. In a specific embodiment, the device includes a buffer material disposed between the first electrode and the switching material. The buffer material provides a blocking region between the switching material and the first electrode so that the blocking region is substantially free from metal particles from the second metal material when a first voltage is applied to the second electrode. | 2017-06-22 |
20170179196 | INTEGRATED CIRCUIT COINTEGRATING A FET TRANSISTOR AND A RRAM MEMORY POINT - The invention relates to an integrated circuit ( | 2017-06-22 |
20170179197 | MEMORY ELEMENT WITH A REACTIVE METAL LAYER - A re-writeable non-volatile memory device including a re-writeable non-volatile two-terminal memory element (ME) having tantalum. The ME including a first terminal, a second terminal, a first layer of a conductive metal oxide (CMO), and a second layer in direct contact with the first layer. The second layer and the first layer being operative to store at least one-bit of data as a plurality of resistive states, and the first and second layer are electrically in series with each other and with the first and second terminals. | 2017-06-22 |
20170179198 | TANDEM ORGANIC PHOTOVOLTAIC DEVICES THAT INCLUDE A METALLIC NANOSTRUCTURE RECOMBINATION LAYER - An intermediate layer ( | 2017-06-22 |
20170179199 | METHOD OF SCREEN PRINTING IN MANUFACTURING AN IMAGE SENSOR DEVICE - A method of manufacturing an image sensor device includes providing a metalized thin film transistor layer on a glass substrate; forming an inter-layer dielectric layer on the metalized thin film transistor layer; forming a via through the inter-layer dielectric layer; forming a metal layer on the inter-layer dielectric for contacting the metalized thin film transistor layer; forming a bank layer on the metal layer and the inter-layer dielectric layer; forming a via through the bank layer; forming an electron transport layer on the bank layer and within the bank layer via for contacting an upper surface of the metal layer; forming a bulk hetero-junction layer on the electron transport layer; forming a hole transport layer on the bulk hetero-junction layer; and forming a top contact layer on the hole transport layer. The bulk hetero-junction layer and/or the top contact layer are applied using a screen printing technique. | 2017-06-22 |
20170179200 | TEST STRUCTURES FOR MANUFACTURING PROCESS OF ORGANIC PHOTO DIODE IMAGING ARRAY - A test structure for characterizing an organic photodiode image sensor includes, on a common substrate, at least one of a cathode sheet resistance portion; a diode capacitance portion; an OPD sheet resistance portion; a contact resistance portion; a step coverage portion; a quantum efficiency portion; a film adhesion portion; and an inkjet printing portion. | 2017-06-22 |
20170179201 | PROCESSES FOR FABRICATING ORGANIC PHOTODETECTORS AND RELATED PHOTODETECTORS AND SYSTEMS - A process for fabricating an organic photodetector is presented. The process includes providing an array of thin film transistor assemblies, each thin film transistor assembly including a first electrode disposed on a thin film transistor; disposing an organic semiconductor layer on the array; disposing a second electrode layer including a first inorganic material on the organic semiconductor layer through a shadow mask to form a first etch stop layer; and removing portions of the organic semiconductor layer unprotected by the first etch stop layer using a dry etching process to form a multilayered structure. An organic photodetector, for example an organic x-ray detector fabricated by the process is further presented. An x-ray system including the organic x-ray detector is also presented. | 2017-06-22 |
20170179202 | ORGANIC LIGHT EMITTING DIODE DISPLAY DEVICE - The present disclosure provides an organic light emitting diode display device including: first to third color filter layers disposed corresponding to red, green, and blue sub-pixels, respectively; and a fourth color filter layer alternately arranged including a color layer having the same color as any one of the first to third color filter layers in a white sub-pixel in each of a plurality of pixels, and having a smaller height than the first to third color filter layers. Additional color filter layers may also be included. The display device of the present disclosure has lower reflectance and enhanced black color expression. | 2017-06-22 |
20170179203 | ORGANIC LIGHT-EMITTING DIODE TOUCH DISPLAY PANEL, METHOD FOR FABRICATING THE SAME, AND DISPLAY APPARATUS CONTAINING THE SAME - The present disclosure provides an organic light-emitting diode (OLED) touch display panel. The OLED touch display panel includes a packaging substrate, having a touch sensing region and a touch pin line region on a first surface of the packaging substrate, the touch sensing region including a plurality of touch electrodes, the touch pin line region including a plurality of touch lines forming one-to-one electrical connections with the touch electrodes; and an array substrate, having a display region, a connecting region, and a packaging region on a first surface of the array substrate, the display region having an OLED structure, the connecting region having a plurality of conductive lines connectable to a touch control chip. The first surface of the packaging substrate and the first surface of the array substrate are facing each other, the conductive lines forming one-to-one connection with the touch lines through a plurality of via holes. | 2017-06-22 |
20170179204 | ORGANIC LIGHT-EMITTING DEVICE - An organic light-emitting device including: a first electrode; a second electrode facing the first electrode; an emission layer between the first electrode and the second electrode; a hole transport region between the first electrode and the emission layer; and an electron transport region between the emission layer and the second electrode, wherein at least one selected from the hole transport region and the emission layer includes a first compound represented by Formula 1A or 1B, and at least one selected from the hole transport region and the electron transport region includes a second compound represented by Formula 2: | 2017-06-22 |
20170179205 | ORGANIC LIGHT-EMITTING DISPLAY APPARATUS AND METHOD OF MANUFACTURING THE SAME - An organic light-emitting display apparatus includes a thin film transistor on a substrate; a pixel electrode electrically connected to the thin film transistor; an insulating first lower intermediate layer that includes a first region that covers an edge part of the pixel electrode, and a second region that covers a central part of the pixel electrode: an adhesive layer disposed on at least a portion of the first lower intermediate layer and that is lyophilic with respect to the first lower intermediate layer; a second lower intermediate layer disposed on the adhesive layer; a light-emitting layer disposed on the second lower intermediate layer; and a counter electrode disposed on the light-emitting layer. | 2017-06-22 |
20170179206 | DISPLAY DEVICE - In a display device, light emitting areas and colored areas each have a predetermined planar shape having no rotational symmetry so that rotation of the area by an angle greater than or equal to 0° but smaller than 360° does not produce an initial shape of the area and are so arranged as to have different types of rotation angle. The colored areas are grouped based on a set of the colored areas of colors different from one another to forma plurality of full-color pixels. The full-color pixels are so arranged that the rotation angle of the colored areas of the same color have different types. In the full-color pixels of the same type, the colored areas of the same color have the same rotation angle. In the full-color pixels of different types, the colored areas of the same color have different rotation angles. | 2017-06-22 |
20170179207 | DISPLAY DEVICE AND METHOD FOR MANUFACTURING THE SAME - How a flat panel display is bent by external forces is controlled. A display panel | 2017-06-22 |
20170179208 | ORGANIC LIGHT EMITTING DISPLAY DEVICE AND METHOD OF MANUFACTURING THE SAME - An organic light emitting display device can include a substrate; an anode electrode on the substrate; an organic emitting layer on the anode electrode; a cathode electrode on the organic emitting layer; an auxiliary electrode connected with the cathode electrode; a first bank on an upper surface of the auxiliary electrode; and a second bank disposed between the auxiliary electrode and the anode electrode, in which the second bank is formed of a same material as the first bank, and the first and second banks are spaced apart from each other, and a width of an upper surface of the first bank is larger than a width of a lower surface of the first bank, and the cathode electrode is connected with the auxiliary electrode via a gap space between the first bank and the second bank. | 2017-06-22 |
20170179209 | ORGANIC LIGHT EMITTING DISPLAY DEVICE - An organic light emitting display device includes, a light emitting structure, a pixel defining structure that includes first and second pixel defining layers, and a first wiring. The light emitting structure is disposed on a substrate and includes a pixel electrode, an organic light emitting layer and an opposite electrode. The first pixel defining layer is disposed on the substrate and partially covers the pixel electrode. The second pixel defining layer is disposed on the first pixel defining layer. The first wiring is disposed on the substrate and is in contact with the first pixel defining layer and the second pixel defining layer. An adhesive strength between the second pixel defining layer and the first wiring is greater than an adhesive strength between the second pixel defining layer and the first pixel defining layer. | 2017-06-22 |
20170179210 | DISPLAY DEVICE - A display device includes: a flexible substrate; a pixel over the flexible substrate, the pixel including a transistor and a display element; a first wiring for transmitting a signal to the pixel, the first wiring extending in a first direction; a second wiring extending in a second direction intersecting the first direction; an inorganic insulating layer on a higher level than the first wiring or the second wiring; and an organic insulating layer on a higher level than the inorganic insulating layer, wherein the inorganic insulating layer has an opening exposing a part of the upper surface of the first wiring or the second wiring is exposed, and the organic insulating layer is provided in such a way as to fill the opening. | 2017-06-22 |
20170179211 | ORGANIC EL DISPLAY DEVICE - Provided is a display device including a pixel. The pixel has: a conductive film; an interlayer insulating film over the conductive film; a first electrode over the interlayer insulating film; an insulating film over the first electrode; an organic layer over the first electrode and the insulating film; and a second electrode over the organic layer. The interlayer insulating film has a first opening portion overlapping with the conductive film. The insulating film covers the first opening portion. A first region of the organic layer in contact with the first electrode surrounds the insulating film. An area defined by a periphery of the first region has at least two symmetry axes in a direction parallel to a surface of the substrate. | 2017-06-22 |
20170179212 | ORGANIC LIGHT-EMITTING DISPLAY DEVICE - An organic light-emitting display device includes a substrate having a display region and a peripheral region, a plurality of pixels on the substrate in the display region, a first wiring and a second wiring on the substrate in the peripheral region, a compensation layer on the first and second wirings, the compensation layer surrounding a top surface and a sidewall of each of the first and second wirings, and an encapsulation layer on the plurality of pixels and on the compensation layer. | 2017-06-22 |
20170179213 | Display Device and Manufacturing Method Thereof - A display device in which light leakage in a monitor element portion is prevented without increasing the number of steps and cost is provided. The display device includes a monitor element for suppressing influence on a light-emitting element due to temperature change and change over time and a TFT for driving the monitor element, in which the TFT for driving the monitor element is provided so as not to overlap the monitor element. Furthermore, the display device includes a first light shielding film and a second light shielding film, in which the first light shielding film is provided so as to overlap a first electrode of the monitor element and the second light shielding film is electrically connect to the first light shielding film through a contact hole formed in an interlayer insulating film. The contact hole is formed so as to surround the outer edge of the first electrode of the monitor element. | 2017-06-22 |
20170179214 | ORGANIC LIGHT EMITTING DIODE DISPLAY - An organic light emitting diode (“OLED”) display includes: a substrate divided into a pixel area, and a peripheral area enclosing the pixel area; an OLED in the pixel area and including a first electrode, an organic emission layer and a second electrode; a common voltage line in the peripheral area and transmitting a common voltage to the second electrode; and a reaction blocking part overlapping the common voltage line. | 2017-06-22 |
20170179215 | Flexible Display Device with Space Reducing Wire Configuration and Manufacturing Method for the Same - There is provided a flexible display having a plurality of innovations configured to allow bending of a portion or portions to reduce apparent border size and/or utilize the side surface of an assembled flexible display. | 2017-06-22 |
20170179216 | Adjustable Multi-Turn Magnetic Coupling Device - According to some embodiments, an integrated circuit device is disclosed. The integrated circuit device include at least one inductor having at least one turn, a magnetic coupling ring positioned adjacent to the at least one inductor, the magnetic coupling ring comprising at least two magnetic coupling turns, the at least two magnetic coupling turns are disposed adjacent to the at least one turn to enable magnetic coupling between the at least two magnetic coupling turns and the at least one turn The integrated circuit device also includes a power electrode and a ground electrode, wherein the power electrode and the ground electrode are coupled to the at least one inductor and the magnetic coupling ring to provide a first current in the at least one inductor having a direction opposite to a second current in the magnetic coupling ring to cancel at least a portion of a magnetic field generated by the at least one inductor. | 2017-06-22 |
20170179217 | CHIP RESISTOR - A chip resistor includes a substrate having first and second electrodes disposed on one surface thereof to be separated from each other. A first resistor electrically connects the first electrode to the second electrode, and a second resistor electrically connects the first electrode to the second electrode. When temperatures of the first electrode and the second electrode are different from each other, thermo electromotive force generated from the first resistor is less than thermo electromotive force generated from the second resistor, and a temperature coefficient of resistivity (TCR) of the second resistor is lower than the TCR of the first resistor. | 2017-06-22 |
20170179218 | HEAD RESISTANCE BUFFER - An integrated circuit with first and second resistors comprised of resistor bodies, resistor heads, and resistor buffer regions wherein the resistor buffer regions are disposed between the resistor body and the resistor heads. The width of the first and second resistors is different. The length of the first and second resistor buffer regions is different. The total head resistance which is equal to the resistor head resistance plus the resistor buffer region is equal for both the first and second resistors. A method is described for forming an integrated circuit with first and second resistors comprised of resistor bodies, resistor heads, and resistor buffer regions disposed between the resistor body and the resistor head wherein the width of the first and second resistors is different, wherein the length of the resistor buffer regions of the first and second resistors is different, and wherein the total head resistance which is equal to the resistor head resistance plus the resistor buffer region is equal for both the first and second resistors. A method is described for calculating the length of a resistor buffer region as a function of resistor width so that the resistance of the resistor head plus the resistor buffer region remains the same as resistor body width changes. | 2017-06-22 |
20170179219 | LOWER ELECTRODE OF DRAM CAPACITOR AND MANUFACTURING METHOD THEREOF - A lower electrode is made of a TiN-based material and provided at a base of a dielectric film in a DRAM capacitor. The lower electrode includes first TiON films provided at opposite outer sides, the first TiON films having a relatively low oxygen concentration, and a second TiON film provided between the first TiON films, the second TiON film having a relatively high oxygen concentration. | 2017-06-22 |
20170179220 | Horizontal Current Bipolar Transistors with Improved Breakdown Voltages - A horizontal current bipolar transistor comprises a substrate of first conductivity type, defining a wafer plane parallel to said substrate; a collector drift region above said substrate, having a second, opposite conductivity type, forming a first metallurgical pn-junction with said substrate; a collector contact region having second conductivity type above said substrate and adjacent to said collector drift region; a base region comprising a sidewall at an acute angle to said wafer plane, having first conductivity type, and forming a second metallurgical pn-junction with said collector drift region; and a buried region having first conductivity type between said substrate and said collector drift region forming a third metallurgical pn-junction with the collector drift region. An intercept between an isometric projection of said base region on said wafer plane and an isometric projection of said buried region on said wafer plane is smaller than said isometric projection of said base region. | 2017-06-22 |
20170179221 | SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING THE SAME - A semiconductor device according to one embodiment of the present invention comprises: a semiconductor substrate having a main surface; a noise source element formed at the main surface of the semiconductor substrate; a protection target element formed at the main surface of the semiconductor substrate; an n type region disposed between the noise source element and the protection target element; and a p type region disposed between the noise source element and the protection target element and electrically connected to the n type region. The n type region and the p type region are adjacent to each other on the main surface of the semiconductor substrate in a direction intersecting a direction from the noise source element toward the protection target element. | 2017-06-22 |
20170179222 | SEMICONDUCTOR DEVICE - A semiconductor device includes a wall-like first guard ring structure that is formed to surround a periphery of an element formation region on a semiconductor substrate and that extends in a thickness direction of the substrate through an insulating film; and a wall-like second guard ring structure that is formed to surround the periphery of the element formation region between the element formation region on the semiconductor substrate and the first guard ring structure and that extends in the thickness direction of the substrate through the insulating films. The first and second guard ring structures are formed of a conductive material, and the first guard ring structure is provided in a state of being insulated from the semiconductor substrate, the element formation region and the second guard ring structure. | 2017-06-22 |
20170179223 | SEMICONDUCTOR DEVICE, AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - [Object] To provide a semiconductor device capable of improving a discharge starting voltage when measuring electric characteristics, and widening a pad area of a surface electrode or increasing the number of semiconductor devices (number of chips) to be obtained from one wafer, and a method for manufacturing the same. | 2017-06-22 |
20170179224 | POWER SEMICONDUCTOR DEVICES, SEMICONDUCTOR DEVICES AND A METHOD FOR ADJUSTING A NUMBER OF CHARGE CARRIERS - A power semiconductor device includes a semiconductor substrate including at least one electrical structure. The at least one electrical structure has a blocking voltage of more than 20V. Further, the power semiconductor device includes an electrically insulating layer structure formed over at least a portion of a lateral surface of the semiconductor substrate. The electrically insulating layer structure embeds one or more local regions for storing charge carriers. Further, the one or more local regions includes in at least one direction a dimension of less than 200 nm. | 2017-06-22 |
20170179225 | SEMICONDUCTOR DEVICE HAVING A SUPER JUNCTION STRUCTURE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device having a super junction and a method of manufacturing the semiconductor device capable of obtaining a high breakdown voltage are provided, whereby charge balance of the super junction is further accurately controlled in the semiconductor device that is implemented by an N-type pillar and a P-type pillar. The semiconductor device includes a semiconductor substrate; and a blocking layer including a first conductive type pillar and a second conductive type pillar that extend in a vertical direction on the semiconductor substrate and that are alternately arrayed in a horizontal direction, wherein, in the blocking layer, a density profile of a first conductive type dopant may be uniform in the horizontal direction, and the density profile of the first conductive type dopant may vary in the vertical direction. | 2017-06-22 |
20170179226 | ULTRASOUND T/R ISOLTATION DISOLATOR WITH FAST RECOVERY TIME ON SOI - A semiconductor disolator device is provided. The device may include a silicon-on-insulator (SOI) substrate, a body layer disposed on the SOI substrate, a first p-type well disposed on the body layer, a first n-type well disposed on the first p-type well to form a first p-n junction, and a second p-type well that is spaced a predetermined distance from at least one of the first p-type well and first n-type well. | 2017-06-22 |
20170179227 | DIELECTRICALLY ISOLATED SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - The present disclosure relates to a dielectrically isolated semiconductor device and a method for manufacturing the same. The dielectrically isolated semiconductor device includes a semiconductor substrate, a first semiconductor layer above the semiconductor substrate, a second semiconductor layer above the first semiconductor layer, a semiconductor island in the second semiconductor layer, and a first dielectric isolation layer surrounding a bottom and sidewalls of the semiconductor island. The first dielectric isolation layer includes a first portion which is formed from a portion of the first semiconductor layer and extending along the bottom of the semiconductor island, and a second portion which is formed from a portion of the second semiconductor layer and extending along the sidewalls of the semiconductor island. The dielectrically isolated semiconductor devices needs no an SOI wafer and reduces manufacturing cost. | 2017-06-22 |
20170179228 | STRAIN COMPENSATION IN TRANSISTORS - Transistor structures having channel regions comprising alternating layers of compressively and tensilely strained epitaxial materials are provided. The alternating epitaxial layers can form channel regions in single and multigate transistor structures. In alternate embodiments, one of the two alternating layers is selectively etched away to form nanoribbons or nanowires of the remaining material. The resulting strained nanoribbons or nanowires form the channel regions of transistor structures. Also provided are computing devices comprising transistors comprising channel regions comprised of alternating compressively and tensilely strained epitaxial layers and computing devices comprising transistors comprising channel regions comprised of strained nanoribbons or nanowires. | 2017-06-22 |
20170179229 | SUPERLATTICE LATERAL BIPOLAR JUNCTION TRANSISTOR - A bipolar junction transistor includes an intrinsic base formed on a substrate. The intrinsic base includes a superlattice stack including a plurality of alternating layers of semiconductor material. A collector and emitter are formed adjacent to the intrinsic base on opposite sides of the base. An extrinsic base structure is formed on the intrinsic base. | 2017-06-22 |
20170179230 | JUNCTION INTERLAYER DIELECTRIC FOR REDUCING LEAKAGE CURRENT IN SEMICONDUCTOR DEVICES - A semiconductor device includes a substrate and a p-doped layer including a doped III-V material on the substrate. A dielectric interlayer is formed on the p-doped layer. An n-type layer is formed on the dielectric interlayer, the n-type layer including a high band gap II-VI material to form an electronic device. | 2017-06-22 |
20170179231 | PROTECTING TRANSISTOR ELEMENTS AGAINST DEGRADING SPECIES - A technique comprising: providing a stack of layers defining at least (a) source and drain electrodes, (b) gate electrode, and (c) semiconductor channel of at least one transistor; depositing one or more organic insulating layers over the stack; removing at least part of the stack in one or more selected regions by an ablation technique; depositing conductor material over the stack in at least the one or more ablated regions and one or more border regions immediately surrounding a respective ablated region; and depositing inorganic insulating material over the stack at least in the ablated regions and the border regions to cover the ablated regions and make direct contact with said conductor material in said one or more border regions all around the respective ablated region. | 2017-06-22 |
20170179232 | III-V TRANSISTOR DEVICE WITH DOPED BOTTOM BARRIER - A method for forming a semiconductor device comprising forming a sacrificial gate stack on a channel region of first layer of a substrate, forming a spacer adjacent to the sacrificial gate stack, forming a raised source/drain region on the first layer of the substrate adjacent to the spacer, forming a dielectric layer over the raised source/drain region, removing the sacrificial gate stack to expose the channel region of the first layer of the substrate, and implanting dopants in a second layer of the substrate to form an implant region in the second layer below the channel region of the first layer of the substrate, where the first layer of the substrate is arranged on the second layer of the substrate. | 2017-06-22 |
20170179233 | High Mobility Transport Layer Structures for Rhombohedral Si/Ge/SiGe Devices - An electronic device includes a trigonal crystal substrate defining a (0001) C-plane. The substrate may comprise Sapphire or other suitable material. A plurality of rhombohedrally aligned SiGe (111)-oriented crystals are disposed on the (0001) C-plane of the crystal substrate. A first region of material is disposed on the rhombohedrally aligned SiGe layer. The first region comprises an intrinsic or doped Si, Ge, or SiGe layer. The first region can be layered between two secondary regions comprising n+doped SiGe or n+doped Ge, whereby the first region collects electrons from the two secondary regions. | 2017-06-22 |
20170179234 | MULTILAYER GRAPHENE, METHOD OF FORMING THE SAME, DEVICE INCLUDING THE MULTILAYER GRAPHENE, AND METHOD OF MANUFACTURING THE DEVICE - A multilayer graphene, a method of forming the same, a device including the multilayer graphene, and a method of manufacturing the device are provided. In the method of forming the multilayer graphene, a first graphene is formed on an underlayer, and then a multilayer graphene is formed by exposing two adjacent areas on the first graphene to a source gas. By differentiating temperatures and source gasses, the multilayer graphene has different electrical characteristics in the two adjacent areas. | 2017-06-22 |
20170179235 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device includes an n | 2017-06-22 |
20170179236 | METHOD OF PRODUCING SILICON CARBIDE EPITAXIAL SUBSTRATE, SILICON CARBIDE EPITAXIAL SUBSTRATE, AND SILICON CARBIDE SEMICONDUCTOR DEVICE - A method of producing a silicon carbide epitaxial substrate includes steps of: preparing a silicon carbide substrate; and forming a silicon carbide layer on the silicon carbide substrate. In this production method, in the step of forming the silicon carbide layer, a step of growing an epitaxial layer and a step of polishing a surface of the epitaxial layer are repeated twice or more. | 2017-06-22 |
20170179237 | III-V FIELD EFFECT TRANSISTOR ON A DIELECTRIC LAYER - An electrical device comprising a base semiconductor layer of a silicon including material; a dielectric layer present on the base semiconductor layer; a first III-V semiconductor material area present in a trench in the dielectric layer, wherein a via of the III-V semiconductor material extends from the trench through the dielectric layer into contact with the base semiconductor layer; a second semiconductor material area present in the trench in the dielectric layer wherein the second III-V semiconductor material area does not have a via extending through the dielectric layer into contact with the base semiconductor layer; and a semiconductor device present on the second III-V semiconductor material area, wherein the first III-V semiconductor material area and the second III-V semiconductor material area are separated by a low aspect ratio trench extending to the dielectric layer. | 2017-06-22 |
20170179238 | III-V FIELD EFFECT TRANSISTOR ON A DIELECTRIC LAYER - An electrical device comprising a base semiconductor layer of a silicon including material; a dielectric layer present on the base semiconductor layer; a first III-V semiconductor material area present in a trench in the dielectric layer, wherein a via of the III-V semiconductor material extends from the trench through the dielectric layer into contact with the base semiconductor layer; a second semiconductor material area present in the trench in the dielectric layer wherein the second III-V semiconductor material area does not have a via extending through the dielectric layer into contact with the base semiconductor layer; and a semiconductor device present on the second III-V semiconductor material area, wherein the first III-V semiconductor material area and the second III-V semiconductor material area are separated by a low aspect ratio trench extending to the dielectric layer. | 2017-06-22 |
20170179239 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes a P-type semiconductor substrate, a plurality of N-type buried diffusion layers that are arranged in the semiconductor substrate, an N-type first semiconductor layer that is arranged in a first region on a first buried diffusion layer, an N-type second semiconductor layer that is arranged in a second region on a second buried diffusion layer, an N-type first impurity diffusion region that surrounds the first region in plan view, a P-type second impurity diffusion region that is arranged in the second semiconductor layer, an N-type third impurity diffusion region that is arranged in the second semiconductor layer, an N-type fourth impurity diffusion region that is arranged in the first semiconductor layer. The second region is a region in which an N-type impurity diffusion region that has a higher impurity concentration than the second semiconductor layer cannot be arranged. | 2017-06-22 |
20170179240 | METHOD FOR REDUCED SOURCE AND DRAIN CONTACT TO GATE STACK CAPACITANCE - A structure and method for fabricating a semiconductor device is described. A device structure including a gate structure, a source region and a drain region is disposed on a first surface of a substrate. Contact holes are etched through the source and drain regions and through a first portion of the substrate. The contact holes are filled with a conductive material to produce contact studs coupled to the source and drain regions. A second portion of the substrate is removed. A surface of the contact studs is exposed through a second surface of the substrate opposite to the gate structure for connection to a wiring layer disposed over the second surface of the substrate. | 2017-06-22 |
20170179241 | SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF - A semiconductor structure includes a substrate, at least one first gate structure, at least one first spacer, at least one source drain structure, and a conductive plug. The first gate structure is present on the substrate. The first spacer is present on at least one sidewall of the first gate structure. The source drain structure is present adjacent to the first spacer. The conductive plug is electrically connected to the source drain structure while leaving a gap between the conductive plug and the spacer. | 2017-06-22 |
20170179242 | SEMICONDUCTOR STRUCTURE HAVING A GAS-FILLED GAP - A semiconductor structure includes a substrate, at least one first gate structure, at least one source drain structure, at least one bottom conductor, and a first dielectric layer. The first gate structure is present on the substrate. The source drain structure is present on the substrate. The bottom conductor is electrically connected to the source drain structure. The bottom conductor has an upper portion and a lower portion between the upper portion and the source drain structure, and a gap is at least present between the upper portion of the bottom conductor and the first gate structure. The first dielectric layer is at least present between the lower portion of the bottom conductor and the first gate structure. | 2017-06-22 |
20170179243 | STRUCTURE FOR REDUCED SOURCE AND DRAIN CONTACT TO GATE STACK CAPACITANCE - A structure of a semiconductor device is described. A semiconductor device includes a transistor which further includes a gate structure, a source region and a drain region disposed on a first surface of a substrate. A wiring layer of conductive material is disposed over a second surface of the substrate. The second surface of the substrate is located opposite to the first surface of the substrate. A set of contact studs including a first contact stud which extends completely through the source region and through the substrate to a first respective portion of the wiring layer. The set of contact studs also includes a second contact stud which extends completely through the drain region and through the substrate to a second respective portion of the wiring layer. | 2017-06-22 |
20170179244 | STRUCTURE FOR REDUCED SOURCE AND DRAIN CONTACT TO GATE STACK CAPACITANCE - A structure of a semiconductor device is described. In one aspect of the invention, a FinFET semiconductor device includes a FinFET transistor which includes a source region and a drain region disposed in a fin on a first surface of a substrate. A gate structure is disposed over a central portion of the fin. A wiring layer of conductive material is disposed over a second surface of the substrate which is opposite to the first surface of the substrate. A set of contact studs include a first contact stud which extends completely through the height of the fin in the source region and the substrate to the wiring layer. The set of contact studs also includes a second contact stud which extends completely through the height of the fin in the drain region and the substrate to the wiring layer. In other aspects of the invention, the device is a Nanosheet device or an inverter. | 2017-06-22 |
20170179245 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device having a composite barrier structure over a transistor and a method for manufacturing the same is disclosed. The method includes a series of steps including: forming a transistor having source/drain regions within a fin structure and adjacent to a gate structure across over the fin structure; forming first source/drain contacts right above and electrically connected to the source/drain regions; depositing a composite barrier structure over the transistor and the first source/drain contacts; and forming second source/drain contacts right above and electrically connected to the first source/drain contacts. The method further includes depositing a second etch-stop layer before depositing the composite barrier structure and forming second source/drain contacts right above and electrically connected to the first source/drain contacts. The method also includes forming contacts over and electrically connected to the second source/drain contacts. | 2017-06-22 |
20170179246 | METHODS OF FORMING A PROTECTION LAYER ON A SEMICONDUCTOR DEVICE AND THE RESULTING DEVICE - One illustrative example of a transistor device disclosed herein includes, among other things, a gate structure, first and second spacers positioned adjacent opposite sides of the gate structure, and a multi-layer gate cap structure positioned above the gate structure and the upper surface of the spacers. The multi-layer gate cap structure includes a first gate cap material layer positioned on an upper surface of the gate structure and on the upper surfaces of the first and second spacers, a first high-k protection layer positioned on an upper surface of the first gate cap material layer and a second gate cap material layer positioned on an upper surface of the high-k protection layer. The first and second gate cap layers comprise different materials than the first high-k protection layer. | 2017-06-22 |
20170179247 | METHOD FOR PRODUCING A HIGH-VOLTAGE TRANSISTOR WITH REDUCED FOOTPRINT, AND CORRESPONDING INTEGRATED CIRCUIT - An integrated MOS transistor is formed in a substrate. The transistor includes a gate region buried in a trench of the substrate. The gate region is surrounded by a dielectric region covering internal walls of the trench. A source region and drain region are situated in the substrate on opposite sides of the trench. The dielectric region includes an upper dielectric zone situated at least partially between an upper part of the gate region and the source and drain regions. The dielectric region further includes a lower dielectric zone that is less thick than the upper dielectric zone and is situated between a lower part of the gate region and the substrate. | 2017-06-22 |
20170179248 | HORIZONTAL GATE ALL AROUND NANOWIRE TRANSISTOR BOTTOM ISOLATION - A method of forming a GAA MOSFET includes providing a substrate having source, drain and channel regions, the substrate doped with one of a p-type and an n-type dopant. Disposing an etch stop-electric well (ESEW) layer over the substrate, the ESEW layer doped with the other of the p-type and the n-type dopant. Disposing a sacrificial layer over the ESEW layer, the sacrificial layer doped with the same type dopant as the substrate. Disposing a channel layer over the sacrificial layer. Patterning a fin out of the ESEW layer, sacrificial layer and channel layer in the channel region. Selectively etching away only the sacrificial layer of the fin to form a nanowire from the channel layer of the fin while the ESEW layer of the fin functions as an etch stop barrier to prevent etching of trenches in the substrate. | 2017-06-22 |
20170179249 | SEMICONDUCTOR DEVICE - A semiconductor device is provided that is excellent in semiconductor properties and Schottky characteristics. A semiconductor device includes: a semiconductor layer containing a crystalline oxide semiconductor with a corundum structure as a major component; and a Schottky electrode on the semiconductor layer, wherein the Schottky electrode is formed by containing a metal of Groups 4-9 of the periodic table, thereby manufacturing a semiconductor device excellent in semiconductor properties and Schottky characteristics without impairing the semiconductor properties to use the semiconductor device thus obtained for a power device and the like. | 2017-06-22 |
20170179250 | PROCESS FOR FORMING A LAYER OF EQUIAXED TITANIUM NITRIDE AND A MOSFET DEVICE HAVING A METAL GATE ELECTRODE INCLUDING A LAYER OF EQUIAXED TITANIUM NITRIDE - Local variability of the grain size of work function metal, as well as its crystal orientation, induces a variable work function and local variability of transistor threshold voltage. If the metal nitride for the work function metal of the transistor gate is deposited using a radio frequency physical vapor deposition, equiaxed grains are produced. The substantially equiaxed structure for the metal nitride work function metal layer (such as with TiN) reduces local variability in threshold voltage. | 2017-06-22 |
20170179251 | NANOWIRE SEMICONDUCTOR DEVICE - A method for forming a nanowire device comprises depositing a hard mask on portions of a silicon substrate having a <110> orientation wherein the hard mask is oriented in the <112> direction, etching the silicon substrate to form a mandrel having (111) faceted sidewalls; forming a layer of insulator material on the substrate; forming a sacrificial stack comprising alternating layers of sacrificial material and dielectric material disposed on the layer of insulator material and adjacent to the mandrel; patterning and etching the sacrificial stack to form a modified sacrificial stack adjacent to the mandrel and extending from the mandrel; removing the sacrificial material from the modified sacrificial stack to form growth channels; epitaxially forming semiconductor in the growth channels; and etching the semiconductor to align with the end of the growth channels and form a semiconductor stack comprising alternating layers of dielectric material and semiconductor material. | 2017-06-22 |
20170179252 | MULTI-THRESHOLD VOLTAGE STRUCTURES WITH A LANTHANUM NITRIDE FILM AND METHODS OF FORMATION THEREOF - Semiconductor devices incorporating multi-threshold voltage structures and methods of forming such semiconductor devices are provided herein. In some embodiments of the present disclosure, a semiconductor device having a multi-threshold voltage structure includes: a substrate; a gate dielectric layer atop the substrate, wherein the gate dielectric layer comprises an interface layer and a high-k dielectric layer atop the interface layer; a lanthanum nitride layer deposited atop the high-k dielectric layer; an interface of the interface layer and the high-k dielectric layer comprising lanthanum species from the lanthanum nitride layer; and a gate electrode layer atop the lanthanum nitride layer. | 2017-06-22 |
20170179253 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A method for fabricating a semiconductor device may include: preparing a semiconductor substrate including a doping region; performing tilt implantation using a first additional dopant to form an amorphous region in the doping region; doping a second additional dopant in the amorphous region; forming a metal layer on the doped amorphous region; and reacting the doped amorphous region with the metal layer to form metal silicide | 2017-06-22 |
20170179254 | CHANNEL REPLACEMENT AND BIMODAL DOPING SCHEME FOR BULK FINFET THRESHOLD VOLTAGE MODULATION WITH REDUCED PERFORMANCE PENALTY - A method includes removing a top portion of a substrate after implantation of a punch through stopper into the substrate; epitaxially growing undoped material on the substrate, thereby forming a channel; filling a top portion of the channel with an intermediate implant forming a vertically bi-modal dopant distribution, with one doping concentration peak in the top portion of the channel and another doping concentration peak in the punch through stopper; and patterning fins into the channel and the punch though stopper to form a finFET structure. | 2017-06-22 |
20170179255 | GAP FILL OF METAL STACK IN REPLACEMENT GATE PROCESS - A method for fabricating a semiconductor device comprises forming a replacement gate structure on a semiconductor layer of a substrate. The replacement gate structure at least including a polysilicon layer. After forming the replacement gate structure, a gate spacer is formed on the replacement gate structure. Atoms are implanted in an upper portion of the polysilicon layer. The implanting expands the upper portion of the polysilicon layer and a corresponding upper portion of the gate spacer in at least a lateral direction beyond a lower portion of the polysilicon layer and a lower portion of the spacer, respectively. After the atoms have been implanted, the polysilicon layer is removed to form a gate cavity. A metal gate stack is formed within the gate cavity. The metal gate stack includes an upper portion having a width that is greater than a width of a lower portion of the metal gate stack. | 2017-06-22 |
20170179256 | IMPROVING GAP FILL OF METAL STACK IN REPLACEMENT GATE PROCESS - A method for fabricating a semiconductor device comprises forming a replacement gate structure on a semiconductor layer of a substrate. The replacement gate structure at least including a polysilicon layer. After forming the replacement gate structure, a gate spacer is formed on the replacement gate structure. Atoms are implanted in an upper portion of the polysilicon layer. The implanting expands the upper portion of the polysilicon layer and a corresponding upper portion of the gate spacer in at least a lateral direction beyond a lower portion of the polysilicon layer and a lower portion of the spacer, respectively. After the atoms have been implanted, the polysilicon layer is removed to form a gate cavity. A metal gate stack is formed within the gate cavity. The metal gate stack includes an upper portion having a width that is greater than a width of a lower portion of the metal gate stack. | 2017-06-22 |
20170179257 | JUNCTION BUTTING STRUCTURE USING NONUNIFORM TRENCH SHAPE - The present invention relates generally to semiconductor devices and more particularly, to a structure and method of forming a partially depleted semiconductor-on-insulator (SOI) junction isolation structure using a nonuniform trench shape formed by reactive ion etching (RIE) and crystallographic wet etching. The nonuniform trench shape may reduce back channel leakage by providing an effective channel directly below a gate stack having a width that is less than a width of an effective back channel directly above the isolation layer. | 2017-06-22 |
20170179258 | CHANNEL-LAST REPLACEMENT METAL-GATE VERTICAL FIELD EFFECT TRANSISTOR - A method of making a vertical transistor includes forming a doped source on a substrate; depositing a sacrificial gate material on the source; forming a trench in the sacrificial gate material to expose the doped source; growing an epitaxial layer within the trench to form a channel region extending from the doped source and through the sacrificial gate material; performing an epitaxial growth process to grow an epitaxial layer on a portion of the channel region to form a drain over the sacrificial gate material; depositing a dielectric material on the drain to form a spacer that protects the epitaxial growth; and removing the sacrificial gate material and replacing the sacrificial gate material with a gate stack that surrounds the channel region between the doped source and the drain. | 2017-06-22 |
20170179259 | VERTICAL TRANSISTOR FABRICATION AND DEVICES - A method of fabricating a vertical field effect transistor including forming a first recess in a substrate; epitaxially growing a first drain from the first bottom surface of the first recess; epitaxially growing a second drain from the second bottom surface of a second recess formed in the substrate; growing a channel material epitaxially on the first drain and the second drain; forming troughs in the channel material to form one or more fin channels on the first drain and one or more fin channels on the second drain, wherein the troughs over the first drain extend to the surface of the first drain, and the troughs over the second drain extend to the surface of the second drain; forming a gate structure on each of the one or more fin channels; and growing sources on each of the fin channels associated with the first and second drains. | 2017-06-22 |
20170179260 | LDMOS DEVICE WITH GRADED BODY DOPING - A laterally diffused MOS (LDMOS) device includes a substrate having a p-epi layer thereon. A p-body region is in the p-epi layer. An ndrift (NDRIFT) region is within the p-body region providing a drain extension region, and a gate dielectric layer is formed over a channel region in the p-body region adjacent to and on respective sides of a junction with the NDRIFT region, and a patterned gate electrode on the gate dielectric. A DWELL region is within the p-body region, sidewall spacers are on sidewalls of the gate electrode, a source region is within the DWELL region, and a drain region is within the NDRIFT region. The p-body region includes a portion being at least one 0.5 μm wide that has a net p-type doping level above a doping level of the p-epi layer and a net p-type doping profile gradient of at least 5/μm. | 2017-06-22 |
20170179261 | METHODS OF FORMING A DEVICE INCLUDING AN INTERFACIAL DIPOLE LAYER - A method of forming an electronic device includes forming an oxygen scavenging layer proximate to a dielectric layer in a gate region of a field effect transistor (FET). The interface layer is between the dielectric layer and a substrate of the FET. The method further includes forming a dipole layer by annealing the oxygen scavenging layer, the dielectric layer, and the interface layer. | 2017-06-22 |
20170179262 | THIN FILM TRANSISTOR ARRAY PANEL AND METHOD OF MANUFACTURING THE SAME - A thin film transistor array panel that includes: a substrate; a gate electrode disposed on the substrate; a semiconductor layer disposed on the substrate; a gate insulating layer disposed between the gate electrode and the semiconductor layer; a source electrode disposed on the semiconductor layer and a drain electrode facing the source electrode; a metal oxide layer covering the source electrode and the drain electrode; and a passivation layer covering the source electrode, the drain electrode, and the metal oxide layer, wherein the source electrode and the drain electrode include a first material and a second material which is added to the first material and metal included in the metal oxide layer is formed by diffusing the second material. | 2017-06-22 |
20170179263 | TWO-DIMENSIONAL MATERIAL SEMICONDUCTOR DEVICE - A semiconductor device comprises a two-dimensional (2D) material layer, the 2D material layer comprising a channel region in between a source region and a drain region; a first gate stack and a second gate stack in contact with the 2D material layer, the first and second gate stack being spaced apart over a distance; the first gate stack located on the channel region of the 2D material layer and in between the source region and the second gate stack, the first gate stack arranged to control the injection of carriers from the source region to the channel region and the second gate stack located on the channel region of the 2D material layer; the second gate stack arranged to control the conduction of the channel region. | 2017-06-22 |
20170179264 | Bipolar Transistor - A bipolar transistor and a method for fabricating a bipolar transistor are disclosed. In one embodiment the bipolar transistor includes a semiconductor body including a collector region and a base region arranged on top of the collector region, the collector region being doped with dopants of a second doping type and the base region being at least partly doped with dopants of a first doping type and an insulating spacers arranged on top of the base region. The semiconductor body further includes a semiconductor layer including an emitter region arranged on the base region and laterally enclosed by the spacers, the emitter region being doped with dopants of the second doping type forming a pn-junction with the base region, wherein the emitter region is fully located above a horizontal plane through a bottom side of the spacers | 2017-06-22 |
20170179265 | POWER SEMICONDUCTOR DEVICE - An object is to provide a technique that enables suppression of oscillation of a gate signal waveform. A power semiconductor device includes a power semiconductor chip, a plurality of collector main terminals and a plurality of emitter main terminals electrically connected to the power semiconductor chip, and a signal line. The plurality of collector main terminals and the plurality of emitter main terminals have protrusion portions which protrude from a disposition surface of the power semiconductor chip, respectively, and the signal line surrounds, with respect to these protrusion portions, an entire circumference of all the protrusion portions and is spaced apart therefrom in plan view. | 2017-06-22 |