25th week of 2011 patent applcation highlights part 57 |
Patent application number | Title | Published |
20110151576 | METHOD TO ASSESS MULTIPHASE FLUID COMPOSITIONS - A method for the assessment of a multiphase (aqueous and organic) sample phase, the method comprising adding at least one detection molecule to the multiphase sample; detecting a signal emitted from the detection molecule/multiphase sample mixture, the signal being detectably different when the at least one detection molecule is present in one of either an organic phase, an aqueous phase or an interface between said organic phase and said aqueous phase of the multiphase sample; and analysing the detected signal to assess the properties of a phase or an interface between phases. A system for use in such a method, use of at least one detection molecule for the assessment of a multiphase sample, and a composition for use in the assessment of a multiphase sample are also disclosed. | 2011-06-23 |
20110151577 | DISPOSABLE DEVICE FOR AUTOMATED BIOLOGICAL SAMPLE PREPARATION - A device and a process for preparing biological test samples are presented. The device has a disposable device with a connection mechanism for connecting to a closed sonication tube together with a filter capture unit to capture samples and to handle the samples without requiring additional tubes. With the device and/or method, samples are sonicated in the closed sonication tube that prevents aerosol contamination. | 2011-06-23 |
20110151578 | VALVES AND OTHER FLOW CONTROL IN FLUIDIC SYSTEMS INCLUDING MICROFLUIDIC SYSTEMS - Articles and methods for controlling flow in fluidic Systems, especially in microfluidic Systems, are provided. A microfluidic System includes a configuration such that the actuation of a single valve can allow the switching of fluids from a first fluid path (e.g., a first channel section) to a second fluid path (e.g., a second channel section). This may be achieved by incorporating a valve ( | 2011-06-23 |
20110151579 | Secreted Epithelial Stromal-1 Molecules and Uses Thereof - The present invention provides novel Secreted Epithelial Colon Stromal-1 (Secs-1) polypeptides and nucleic acid molecules encoding the same. The invention also provides selective binding agents, vectors, host cells, and methods for producing Secs-1 polypeptides. The invention further provides pharmaceutical compositions and methods for the diagnosis, treatment, amelioration, and/or prevention of diseases, disorders, and conditions associated with Secs-1 polypeptides. | 2011-06-23 |
20110151580 | METHOD FOR THE DETECTION OF BREAST CANCER BY DETERMINING ALCAM AND/OR BCAM LEVELS IN A PATIENT - The present application describes biomarkers and methods useful for screening for, diagnosing or detecting the presence and severity of breast cancer in a subject. The present application also provides methods for determining the prognosis of a subject with breast cancer as well as methods for monitoring the therapeutic response to a breast cancer treatment or therapy. | 2011-06-23 |
20110151581 | TRIGGER ASSAY FOR DIFFERENTIATING BETWEEN RHEUMATIC AND NON-RHEUMATIC DISORDERS - The present invention provides for a method for excluding a non-rheumatic disorder as cause of a musculoskeletal complaint of a subject including determining as to whether at least one autoantibody or antigen which is indicative for at least one rheumatic disorder is present in a sample obtained from the subject, wherein the presence of the autoantibody or antigen allows to exclude a non-rheumatic disorder as cause of a musculoskeletal complaint of a subject. Accordingly, it provides for a method that triggers the next steps in diagnosing the cause of a musculoskeletal complaint of a subject—either further diagnosis of a rheumatic disorder or of a non-rheumatic disorder to confirm the initial diagnosis. Also provided is a kit for excluding a non-rheumatic disorder as cause of a musculoskeletal complaint of a subject as well as uses of the kit. | 2011-06-23 |
20110151582 | METHOD FOR DETECTION OF ANTIGEN-SPECIFIC ANTIBODIES IN BIOLOGICAL SAMPLES - Disclosed herein is a rapid and universal assay for the detection of antigen-specific antibodies in biological samples. The assay allows for the detection of antigen-specific antibodies in any species, including species for which secondary antibodies or antisera have not been developed or are not available. Biological samples to be tested are directly labeled, such as with biotin, and contacted with antigen-bound microparticles. The presence of antigen-specific antibodies in the biological samples is detected using a binding partner for the label, such as a biotin binding partner, conjugated to a detectable label, such as a fluorophore. This improved test provides a total antibody assay that is capable of detecting all classes of antibodies simultaneously. | 2011-06-23 |
20110151583 | METHOD FOR EVALUATING MYOCARDIAL ISCHEMIC STATE USING BLOOD SAMPLE - The present invention provides a method and an index capable of less-invasively determining myocardial ischemia such as ischemic heart disease or restenosis after percutaneous coronary intervention. The present invention also provides an index that allows the cardiovascular disease other than heart failure to be determined even from a blood sample showing a BNP value from which the cardiovascular disease other than heart failure cannot be determined by a conventional method. A method for determining myocardial ischemia comprising subjecting a blood sample which is derived from a test subject and which contains a BNP molecular group containing at least two selected from the group consisting of BNP 1-32 molecule, BNP 3-32 molecule, BNP 4-32 molecule, BNP 5-32 molecule, and a molecule having a mass number larger than that of BNP 5-32 molecule by 16 Da to a detection process capable of distinguishing and quantifying the individual BNP molecules different in mass number to detect the BNP molecular group, wherein myocardial ischemia in the test subject is determined using, as an index, a ratio between a detected intensity of at least one molecule selected from the BNP molecular group and a detected intensity of at least one other molecule selected from the BNP molecular group. | 2011-06-23 |
20110151584 | Dual Path Immunoassay Device - The systems of the invention include test cells with a first sorbent material defining a first flow path for a solution, a second sorbent material defining a second flow path distinct from the first flow path for a sample, and a test site with immobilized antigens or antibodies or other ligand binding molecules such as aptamers, nucleic acids, etc. located at the junction of the first and second sorbent materials for identifying one or more ligands. The first and second sorbent strips touch each other at the test site location. The test cell may be used to test for pregnancy, HIV (including different HIV antigens or peptides), tuberculosis, prion, urin-analysis/drug, cardiac markers, cancer markers, Chagas, Chlamydia, dental bacteria (SM/LC), influenza A, influenza B, adenovirus, rotavirus, strep A, other bacteria or viruses, etc., and veterinary applications such as CPV, FIV, FeLV, heartworm, etc., although it is not limited to those applications. | 2011-06-23 |
20110151585 | DUAL INLET MICROCHANNEL DEVICE AND METHOD FOR USING SAME - A dual inlet microchannel device and a method for using the device to perform a flow-through kinetic assay are described. A microplate having an array of the dual inlet microchannel devices and in particular their specially configured flow chambers is also described. Several embodiments of the dual inlet microchannel devices and specially configured flow chambers are also described. | 2011-06-23 |
20110151586 | POLYMER ENCAPSULATED PARTICLES AS SURFACE ENHANCED RAMAN SCATTERING PROBES - The present invention refers to a Raman active composite material comprising a metal particle; a coating layer of a Raman active molecule bound to the metal particle; and an encapsulating layer of an amphiphilic polymer bound to the metal particle. The present invention also refers to methods of manufacturing a Raman active composite material described herein and their uses. | 2011-06-23 |
20110151587 | METHOD OF PRODUCING AN INTEGRATED MICROMAGNET SENSOR ASSEMBLY - A method of integrating a permanent bias magnet within a magnetoresistance sensor comprising depositing an alternating pattern of a metal material and a semiconductor material on or within a surface of an insulating substrate; depositing a mask on the surface of the insulating substrate to create an opening above the alternating pattern of metal material and semiconductor material; applying a magnetic paste within the opening above the alternating pattern of metal material and semiconductor material; curing the magnetic paste to form a hardened bias magnet; removing the mask; and magnetizing the hardened bias magnet by applying a strong magnetic field to the hardened bias magnet at a desired orientation. | 2011-06-23 |
20110151588 | METHOD AND MAGNETIC TRANSFER STAMP FOR TRANSFERRING SEMICONDUCTOR DICE USING MAGNETIC TRANSFER PRINTING TECHNIQUES - Releasable semiconductor dice are deposited with a magnetic layer and held by magnetic forces to a magnetic or electromagnetic transfer stamp for the transfer of the dice from a host substrate directly or indirectly to a target substrate. | 2011-06-23 |
20110151589 | PRODUCTION OF A DEVICE COMPRISING MAGNETIC STRUCTURES FORMED ON ONE AND THE SAME SUBSTRATE AND HAVING RESPECTIVE DIFFERENT MAGNETIZATION ORIENTATIONS - The invention relates to a method for producing a device comprising magnetic blocks magnetized in different directions, comprising steps of:
| 2011-06-23 |
20110151590 | APPARATUS AND METHOD FOR LOW-K DIELECTRIC REPAIR - A method, a system and a computer readable medium for integrated in-vacuo repair of low-k dielectric thin films damaged by etch and/or strip processing. A repair chamber is integrated onto a same platform as a plasma etch and/or strip chamber to repair a low-k dielectric thin film without breaking vacuum between the damage event and the repair event. UV radiation may be provided on the integrated etch/repair platform in any combination of before, after, or during the low-k repair treatment to increase efficacy of the repair treatment and/or stability of repair. | 2011-06-23 |
20110151591 | PHOTOVOLTAIC CELL MANUFACTURING METHOD - The present invention provides a photovoltaic cell manufacturing method, the photovoltaic cell including: a photoelectric converter in which at least a first electrode layer, a semiconductor layer, and a second electrode layer are stacked in layers in this order being formed on a face of a substrate; and a connection portion of the first electrode layer and the second electrode layer, the photoelectric converter having a plurality of compartment elements which are electrically separated by a predetermined size using scribing lines at which the semiconductor layer and the second electrode layer are removed, adjacent compartment elements being electrically connected to each other, the photovoltaic cell manufacturing method comprising: a defect region specifying step in which a region at which the structural defect exists is specified in the photoelectric converter; and a repairing step in which at least three repair lines in which the semiconductor layer and the second electrode layer are removed are formed by irradiating the photoelectric converter with a laser, the region at which the structural defect exists is surrounded by at least three repair lines described above and one of the scribing lines, and the structural defect is removed or separated off, wherein one of at least three repair lines described above are formed at a region between the structural defect and the connection portion and at a region α including a contact portion of the semiconductor layer and the substrate in the photoelectric converter. | 2011-06-23 |
20110151592 | METHODS FOR MONITORING THE AMOUNT OF CONTAMINATION IMPARTED INTO SEMICONDUCTOR WAFERS DURING WAFER PROCESSING - Methods are disclosed for monitoring the amount of metal contamination imparted during wafer processing operations such as polishing and cleaning. The methods include subjecting a silicon-on-insulator structure to the semiconductor process, precipitating metal contamination in the structure and delineating the metal contaminants. | 2011-06-23 |
20110151593 | MANUFACTURING METHOD OF SEMICONDUCTOR SUBSTRATE - A surface of a single crystal semiconductor substrate is irradiated with ions to form a damaged region, an insulating layer is formed over the surface of the single crystal semiconductor substrate, and a surface of a substrate having an insulating surface is made to be in contact with a surface of the insulating layer to bond the substrate having an insulating surface to the single crystal semiconductor substrate. Then, the single crystal semiconductor substrate is separated at the damaged region by performing heat treatment to form a single crystal semiconductor layer over the substrate having an insulating surface, and the single crystal semiconductor layer is patterned to form a plurality of island-shaped semiconductor layers. One of the island-shaped semiconductor layers is irradiated with a laser beam which is shaped to entirely cover the island-shaped semiconductor layer. | 2011-06-23 |
20110151594 | METHOD AND SYSTEM FOR CONTROLLED ISOTROPIC ETCHING ON A PLURALITY OF ETCH SYSTEMS - A method for forming identical isotropic etch patterns in an etch system is disclosed. The method comprises providing a wafer paddle, a wafer, a plurality of identical etch systems, utilizing identical etch recipes within each of the plurality of etch systems, providing a fixed temperature stability time FTST for each system so that the heat transfer from the paddle to the wafer is constant, wherein the FTST is the same on each of the plurality of etch systems; and utilizing the plurality of identical etch systems to produce identical etches on each of the wafers based upon the FTST, wherein a five-second preheat step in the etch process is not utilized. | 2011-06-23 |
20110151595 | Fabrication method for semiconductor device - A semiconductor device fabrication method can improve yield of semiconductor devices and decrease (or prevent) waste of non-defective semiconductor chips. This fabrication method has a step of performing characteristic inspection after packaging a semiconductor chip every time a semiconductor chip layer is formed. The fabrication method makes another semiconductor chip layer on this semiconductor chip layer only when the inspection indicates that the semiconductor chip is a non-defective product. | 2011-06-23 |
20110151596 | Cascaded-Based De-embedding Methodology - An embodiment is a method for de-embedding. The method comprises forming a primary structure in a semiconductor chip and forming an auxiliary structure in the semiconductor chip. The auxiliary structure replicates a first portion of the primary structure. The method further comprises determining a transmission matrix for each of the primary structure and the auxiliary structure based on measurements and extracting a transmission matrix of a first component of the primary structure by determining a product of the transmission matrix of the primary structure and an inverse of the transmission matrix of the auxiliary structure. | 2011-06-23 |
20110151597 | Analysis method for semiconductor device - An analysis method for a semiconductor device is described. The semiconductor device having an abnormal region is provided. Thereafter, a focused ion beam microscope analysis process is performed to the abnormal region, wherein the result of the focused ion beam microscope analysis process shows that the abnormal region has a defect therein. After the focused ion beam microscope analysis process, an electrical property measurement step is performed to the abnormal region, so as to determine whether the defect in the abnormal region is a device failure root cause or not. | 2011-06-23 |
20110151598 | METHOD FOR MANUFACTURING A SUBSTRATE FOR LIQUID-EJECTING HEADS AND A LIQUID-EJECTING HEAD - A method for manufacturing a substrate for liquid-ejecting heads includes etching a surface of a silicon substrate using a first etchant, with a silicon oxide layer as a mask, to form a depression as a part of a liquid supply port, and subsequently etching at least the silicon oxide layer and the thickness sandwiched between the depression and the etched surface of the silicon substrate with a second etchant to form the liquid supply port. | 2011-06-23 |
20110151599 | Vapor deposition apparatus having improved carrier gas supplying structure and method of manufacturing an organic light emitting display apparatus by using the vapor deposition apparatus - A vapor deposition apparatus includes a canister configured to contain a vapor deposition source, the canister including a gas inlet and a gas outlet opposite to each other, a heater configured to heat the canister, a chamber in fluid communication with the canister, the chamber being configured to contain a vapor deposition target, and a carrier gas supplying unit configured to supply a carrier gas into the canister. | 2011-06-23 |
20110151600 | METHOD OF MANUFACTURING DISPLAY DEVICE - In a method of manufacturing a display device, a first insulating layer is formed on a semiconductor pattern. Ions of a first concentration are injected into source and drain domains of the semiconductor pattern and a lower electrode of the semiconductor pattern by using a mask pattern that selectively overlaps a channel domain of the semiconductor pattern and is positioned on the top of the first insulating layer. The mask pattern is removed. An ion injection process of injecting ions of a second concentration lower than the first concentration into the semiconductor pattern of the channel domain is directly performed in the first insulating layer. A gate electrode that overlaps the channel domain is formed on the top of the first insulating layer. An upper electrode that overlaps the lower electrode is formed on the top of the first insulating layer. | 2011-06-23 |
20110151601 | CRYSTALLIZATION METHOD, METHOD OF MANUFACTURING THIN FILM TRANSISTOR, AND METHOD OF MANUFACTURING DISPLAY DEVICE - A crystallization method, a method of manufacturing a thin-film transistor, and a method of manufacturing a display device are provided. The crystallization method comprises: forming a backup amorphous silicon layer on a substrate, forming nickel particles on the backup amorphous silicon layer, converting the backup amorphous silicon layer into an amorphous silicon layer by thermally processing the backup amorphous silicon layer so as to diffuse the nickel particles throughout said backup amorphous silicon layer; and irradiating the amorphous silicon layer with energy from a laser. | 2011-06-23 |
20110151602 | METHOD OF MANUFACTURING TRANSFERABLE ELEMENTS INCORPORATING RADIATION ENABLED LIFT OFF FOR ALLOWING TRANSFER FROM HOST SUBSTRATE - Semiconductor material is formed on a host substrate of a material exhibiting optical transparency with an intervening radiation lift off layer. A transfer device, intermediate substrate or target substrate is brought into adhesive contact with the semiconductor material and the radiation lift off layer is irradiated to weaken it, allowing the semiconductor material to be transferred off the host substrate. Electronic devices may be formed in the semiconductor layer while it is attached to the host substrate or the intermediate substrate. | 2011-06-23 |
20110151603 | LIGHT EMITTING APPARATUS AND METHOD OF MANUFACTURING THE SAME - A light-emitting apparatus of the present invention includes: a first electrode formed on an insulating surface; a first insulating layer covering an end portion of the first electrode and having a tapered edge; a second insulating layer formed on the first electrode and the first insulating layer and formed of one kind or a plurality of kinds selected from the group consisting of silicon oxide, silicon nitride, and silicon oxynitride; an organic compound layer formed on the second insulating layer; and a second electrode formed on the organic compound layer. | 2011-06-23 |
20110151604 | LED PACKAGING METHOD - An LED packaging method provides a package that includes a substrate, a LED chip, a carbon naonotube thin film and an adhesive layer. The LED chip includes an anode and a cathode. The carbon naonotube thin film includes at least two electrically conductive areas spaced from each other. The anode and the cathode are electrically connected to the adjacent electrically conductive areas. The adhesive layer is coated on the LED chip and the carbon nanotube thin film. | 2011-06-23 |
20110151605 | METHOD FOR FABRICATING COLOR FILTER USING SURFACE PLASMON AND METHOD FOR FABRICATING LIQUID CRYSTAL DISPLAY DEVICE - Discussed are methods for fabricating a color filter using a surface plasmon and a liquid crystal display (LCD) device capable of enhancing a transmittance ratio of an LC panel and simplifying entire processes, by forming a transmissive pattern consisting of a plurality of sub-wavelength holes having a period on a metal layer, and by implementing colors by selectively transmitting light of specific wavelengths with using a surface plasmon phenomenon. | 2011-06-23 |
20110151606 | LIGHT EMITTING DEVICE AND METHOD OF MANUFACTURE - A method of making a light emitting device includes forming an active layer between first and semiconductor layers of different conductivity types, and forming a transparent conductive layer adjacent the second semiconductor layer. The transparent conductive layer includes a first transparent conductive region contacting a first region of the second semiconductor layer and a second transparent conductive region contacting a second region of the second semiconductor layer. An electrode is formed adjacent the first semiconductor layer in vertical alignment with the second region. | 2011-06-23 |
20110151607 | METHOD FOR MANUFACTURING A METAL AND DIELECTRIC NANOSTRUCTURES ELECTRODE FOR COLORED FILTERING IN AN OLED AND METHOD FOR MANUFACTURING AN OLED - A method for manufacturing an OLED and an electrode for an OLED, said electrode comprising a surface comprising a first dielectric nanostructuration and a second metal nanostructuration, on a substrate, wherein the following successive steps are carried out:
| 2011-06-23 |
20110151608 | CAPACITIVE MICROMACHINED ULTRASONIC TRANSDUCER AND MANUFACTURING METHOD - The integrated circuit/transducer device of the preferred embodiment includes a substrate, a complementary-metal-oxide-semiconductor (CMOS) circuit that is fabricated on the substrate, and a capacitive micromachined ultrasonic transducer (cMUT) element that is also fabricated on the substrate. The CMOS circuit and cMUT element are fabricated during the same foundry process and are connected. The cMUT includes a lower electrode, an upper electrode, a membrane structure that support the upper electrode, and a cavity between the upper electrode and lower electrode. | 2011-06-23 |
20110151609 | Method for Forming Thin Film Heat Dissipater - The present invention discloses a method of forming Peltier diodes comprising providing a substrate and forming a conductive pattern over the substrate. An isolation layer is formed over the conductive pattern; followed by forming cavities in the isolation layer and refilling a semiconductor layer into the cavities, thereby forming a first and a second semiconductors, wherein the first and second semiconductors are formed by silicon or III-V group material; A Peltier junction is formed on the isolation layer to connect the first and the second semiconductors, thereby forming the Peltier diodes, wherein electricity is applied to the Peltier diodes for transferring heat. | 2011-06-23 |
20110151610 | WORKPIECE PATTERNING WITH PLASMA SHEATH MODULATION - Methods to texture or fabricate workpieces are disclosed. The workpiece may be, for example, a solar cell. This texturing may involve etching or localized sputtering using a plasma where a shape of a boundary between the plasma and the plasma sheath is modified with an insulating modifier. The workpiece may be rotated in between etching or sputtering steps to form pyramids. Regions of the workpiece also may be etched or sputtered with ions formed from a plasma adjusted by an insulating modifier and doped. A metal layer may be formed on these doped regions. | 2011-06-23 |
20110151611 | METHOD FOR MANUFACTURING SOLAR CELLS - Disclosure herein is a method for manufacturing a solar cell. The method comprises the following steps. A substrate is provided. An article having a plurality of protrusions touches the surface of the substrate and thereby forming a plurality of indentations thereon. Subsequently, a transparent conductive layer is formed on the indented surface of the substrate, a photovoltaic layer is formed on the transparent conductive layer, and then a back electrode is form above the photovoltaic layer. | 2011-06-23 |
20110151612 | Method For Manufacturing An Oled Or A blank For Forming An Oled As Well As Such A Blank Or Oled - Method for manufacturing an organic light emitting device or a blank for forming therefrom an organic light emitting device as well as such a OLED or blank, the organic light emitting device having a light emitting area with two opposite first sides and two opposite second sides, the method comprising at least the following steps: providing a substrate; depositing and partly removing a layer of transparent conductive material on the substrate for forming parallel anode lines which extend between the first sides; depositing and partly removing at least one conductive layer for forming contacts which are connected anode lines; wherein a photoresist layer is deposited so that it fully extends over contacts adjacent the at least one second side except for at least one contact position per cathode line, via which an electric contact between a respective cathode line to be formed and a respective contact is established. | 2011-06-23 |
20110151613 | Solid-state image capturing element, method for manufacturing the solid-state image capturing element, and electronic information device - A solid-state image capturing element according to the present invention is provided, in which one or a plurality of light receiving sections for photoelectrically converting an incident light to generate a signal charge is provided on a surface of a semiconductor area or a surface of a semiconductor substrate and a peripheral circuit with a transistor is provided, where a reflection preventing film provided above the light receiving sections and a gate sidewall film of the transistor are formed with a common nitride film that is formed simultaneously. | 2011-06-23 |
20110151614 | PROCESS FOR PRODUCING ELECTRODES FOR SOLAR CELLS - The invention relates to a process for producing electrodes for solar cells, the electrode being configured as an electrically conductive layer on a substrate ( | 2011-06-23 |
20110151615 | BICYCLIC GUANIDINES, METAL COMPLEXES THEREOF AND THEIR USE IN VAPOR DEPOSITION - Bicyclic guanidine compounds are described. Metal bicyclic guanidinate and its use in vapor deposition processes to deposit a metal-containing thin film are also described. Methods of making alkaline earth metal N,N′dialkylacetamidinates or bicyclic guanidinates including dissolution of alkaline earth metal into liquid ammonia followed by addition of a solution of an amidine or guanidine ligand in the free base from are provided. | 2011-06-23 |
20110151616 | MBE GROWTH TECHNIQUE FOR GROUP II-VI INVERTED MULTIJUNCTION SOLAR CELLS - A method of forming a Group II-VI multijunction semiconductor device comprises providing a Group IV substrate, forming a first subcell from a first Group II-VI semiconductor material, forming a second subcell from a second Group II-VI semiconductor material, and removing the substrate. The first subcell is formed over the substrate and has a first bandgap, while the second subcell is formed over the first subcell and has a second bandgap which is smaller than the first bandgap. Additional subcells may be formed over the second subcell with the bandgap of each subcell smaller than that of the preceding subcell and with each subcell preferably separated from the preceding subcell by a tunnel junction. Prior to the removal of the substrate, a support layer is affixed to the last-formed subcell in opposition to the substrate. | 2011-06-23 |
20110151617 | Memory and methods of forming the same to enhance scalability of non-volatile two-terminal memory cells - Embodiments of the invention relate generally to semiconductors and memory technology, and more particularly, to systems, integrated circuits, and methods to scale memory elements, such as implemented in BEOL third dimensional memory technology, independent of operational characteristics. In at least some embodiments, a method to fabricate a non-volatile two-terminal memory device includes depositing a first electrode at a first temperature in a first region in relation to a substrate (e.g., a silicon wafer) that includes active circuitry that was previously fabricated FEOL on the substrate, fabricating a memory element coupled to the first electrode, and optionally, forming at least a portion of a non-ohmic device electrically coupled with the memory element. Further, the method can include depositing a second electrode at a second temperature in a second region in relation to the substrate. In some embodiments, the second temperature is approximately equal to or greater than the first temperature. | 2011-06-23 |
20110151618 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - An oxide semiconductor layer with excellent crystallinity is formed to enable manufacture of transistors with excellent electrical characteristics for practical application of a large display device, a high-performance semiconductor device, etc. By first heat treatment, a first oxide semiconductor layer is crystallized. A second oxide semiconductor layer is formed over the first oxide semiconductor layer. By second heat treatment, an oxide semiconductor layer including a crystal region having the c-axis oriented substantially perpendicular to a surface is efficiently formed and oxygen vacancies are efficiently filled. An oxide insulating layer is formed over and in contact with the oxide semiconductor layer. By third heat treatment, oxygen is supplied again to the oxide semiconductor layer. A nitride insulating layer containing hydrogen is formed over the oxide insulating layer. By fourth heat treatment, hydrogen is supplied at least to an interface between the second oxide semiconductor layer and the oxide insulating layer. | 2011-06-23 |
20110151619 | METHOD OF FORMING METAL OXIDE FILM AND APPARATUS FOR FORMING METAL OXIDE FILM - A method of forming a metal oxide film, which can lower a temperature of a heat treatment of a substrate and also can form a metal oxide film having a low resistance value without limiting the kind of the metal oxide film to be formed. The method of forming a metal oxide film includes (A) converting a solution containing a metal into mist, (B) heating a substrate, and (C) supplying the solution converted into mist, and ozone to a first main surface of the substrate under heating. | 2011-06-23 |
20110151620 | METHOD FOR MANUFACTURING CHIPS - A method for manufacturing chips ( | 2011-06-23 |
20110151621 | MICROFEATURE WORKPIECES HAVING INTERCONNECTS AND CONDUCTIVE BACKPLANES, AND ASSOCIATED SYSTEMS AND METHODS - Microfeature workpieces having interconnects and conductive backplanes and associated systems and methods are disclosed herein. One such device includes a semiconductor substrate having integrated circuitry and terminals electrically coupled to the integrated circuitry. The device also includes electrically conductive interconnects extending through at least a portion of the semiconductor substrate and electrically coupled to corresponding terminals. The device further includes a conductive backplane assembly having a conductive layer at a back side of the semiconductor substrate. One or more of the interconnects are electrically coupled to the conductive layer at the back side of the semiconductor substrate. | 2011-06-23 |
20110151622 | Method of manufacturing semiconductor device - The present invention provides a method of manufacturing a semiconductor device in which a plurality of wires are connected to the same electrode on a semiconductor chip, the method making it possible to inhibit an increase in electrode area. First, ball bonding is performed to compressively bond a first ball to an electrode on a semiconductor chip to form a first connection portion. Wedge bonding is then performed on an inner lead. Subsequently, ball bonding is performed to compress a second ball against the first connection portion from immediately above to bond the second ball to form a second connection portion. Wedge bonding is then performed on the inner lead. | 2011-06-23 |
20110151623 | EXPOSED MOLD - A method for forming a semiconductor device can include providing a patterned layer of mold compound having a plurality of individual mold compound structures overlying a base film. The plurality of mold compound structures are aligned with a plurality of semiconductor dice to interpose the individual mold compound structures between the plurality of semiconductor dice. A pressure is applied to the individual mold compound structures to fill spaces between each of the plurality of semiconductor dice with the mold compound. The mold compound structures can be formed on the base film using a photosensitive mold compound. The mold compound structures can also be formed through the use of a patterned mask and a screen printing process. | 2011-06-23 |
20110151624 | Coating for a microelectronic device, treatment comprising same, and method of managing a thermal profile of a microelectronic die - A coating for a microelectronic device comprises a polymer film ( | 2011-06-23 |
20110151625 | HEAT-RESISTANT ADHESIVE SHEET FOR SUBSTRATELESS SEMICONDUCTOR PACKAGE FABRICATION AND METHOD FOR FABRICATING SUBSTRATELESS SEMICONDUCTOR PACKAGE USING THE ADHESIVE SHEET - The present invention is intended to solve the following problems with a method for fabricating a substrateless semiconductor package using an adhesive sheet as a temporary fixing supporter. A chip can be displaced from a specified position by pressure during resin encapsulation because the chip is not properly held by the adhesive sheet. If such displacement occurs, the relative positional relationship between the chip and an interconnect to be connected to a specified position in a subsequent wiring step also changes by the displacement of the chip from the specified position. Another problem is that if adhesive deposits occur during peeling of the adhesive sheet and the surface of a package is contaminated with the adhesive deposits, adhesive components left on the surface of the chip can inhibit connection between the interconnect and the chip in a subsequent wiring step. To solve these problems, the present invention provides an adhesive sheet for semiconductor device fabrication that is attached to a substrateless semiconductor chip when the chip is encapsulated with resin. The adhesive sheet includes a base material layer and an adhesive layer. The adhesive layer has a specific adhesion strength and peel strength. | 2011-06-23 |
20110151626 | METHOD OF MAKING A SEMICONDUCTOR CHIP ASSEMBLY WITH A POST/BASE/POST HEAT SPREADER AND ASYMMETRIC POSTS - A method of making a semiconductor chip assembly includes providing first and second posts, first and second adhesives and a base, wherein the first post extends from the base in a first vertical direction into a first opening in the first adhesive and is located within a periphery of the second post, the second post extends from the base in a second vertical direction into a second opening in the second adhesive and the base is sandwiched between and extends laterally from the posts, then flowing and solidifying the adhesives, then providing a conductive trace that includes a pad and a terminal, wherein the pad extends beyond the base in the first vertical direction and the terminal extends beyond the base in the second vertical direction, providing a heat spreader that includes the posts and the base, then mounting a semiconductor device on the first post, electrically connecting the semiconductor device to the conductive trace and thermally connecting the semiconductor device to the heat spreader. | 2011-06-23 |
20110151627 | OVERCOMING LAMINATE WARPAGE AND MISALIGNMENT IN FLIP-CHIP PACKAGES - An apparatus, system, and method are disclosed for connecting an integrated circuit device to a substrate. A plurality of standard diameter pillars and three or more increased diameter pillars are disposed on an integrated circuit device. The increased diameter pillars have a diameter that is greater than the standard diameter pillars and a height that is similar to the standard diameter pillars. The standard diameter pillars and the increased diameter pillars form a pattern on the integrated circuit device that corresponds to contact pads on a substrate opposite the integrated circuit device. A first group of solder bumps is disposed between the standard diameter pillars and the contact pads. A second group of solder bumps is disposed between the increased diameter pillars and the contact pads. The second group of solder bumps has pre-connection heights that are greater than pre-connection heights of the first group of solder bumps. | 2011-06-23 |
20110151628 | Configuration of gate to drain (GD) clamp and ESD protection circuit for power device breakdown protection - A semiconductor power device supported on a semiconductor substrate comprising a plurality of transistor cells each having a source and a drain with a gate to control an electric current transmitted between the source and the drain. The semiconductor further includes a gate-to-drain (GD) clamp termination connected in series between the gate and the drain further includes a plurality of back-to-back polysilicon diodes connected in series to a silicon diode includes parallel doped columns in the semiconductor substrate wherein the parallel doped columns having a predefined gap. The doped columns further include a U-shaped bend column connect together the ends of parallel doped columns with a deep doped well disposed below and engulfing the U-shaped bend. | 2011-06-23 |
20110151629 | Recessed Channel Negative Differential Resistance-Based Memory Cell - Disclosed herein is an improved recessed thyristor-based memory cell. The disclosed cell comprises in one embodiment a conductive plug recessed into the bulk of the substrate, which is coupled to or comprises the enable gate of the cell. Vertically disposed around this recessed gate is a thyristor, whose anode (source; p-type region) is connected to the bit line and cathode (drain; n-type region) is connected to the word line. Aside from the recessed enable gate, the disclosed cell comprises no other gate, such as an access transistor, and hence is essentially a one-transistor device. As a result, and as facilitated by the vertical disposition of the thyristor, the disclosed cell takes up a small amount of area on an integrated circuit when compared to a traditional DRAM cell. Moreover, the disclosed cell is simple to manufacture in its various embodiments, and is easy to configure into an array of cells. Isolation underneath the cell, while not required in all useful embodiments, assists in improving the data retention of the cell and extends the time needed between cell refresh. | 2011-06-23 |
20110151630 | Display element manufacturing method and manufacturing apparatus, thin film transistor manufacturing method and manufacturing apparatus, and circuit forming apparatus - The thin film transistor manufacturing apparatus comprises a surface modification layer forming means, which forms a surface modification layer on a substrate, an illuminating part, which irradiates light that includes ultraviolet rays, a mask, on which the patterns of the source electrode and the drain electrode are drawn, a projection optical system, which illuminates a mask using light from the illuminating part and projects the pattern of the mask to the substrate as a pattern image, and a coating part, which coats a fluid electrode material to a region in which the surface modification layer has been modified by projection of the pattern image in order to form the source electrode and the drain electrode. | 2011-06-23 |
20110151631 | THIN FILM TRANSISTOR SUBSTRATE AND METHOD OF MANUFACTURING THEREOF - A thin film transistor substrate and a method of manufacturing the thin film transistor substrate comprises forming a gate line and a data line intersecting each other with a gate insulating layer interposed and defining a pixel area on the substrate, a thin film transistor electrically connected to the gate line and the data line, and a stepped-structure occurring pattern overlapping at least one of the gate line and the data line; forming a passivation layer having a stepped-structure portion formed by the stepped-structure occurring pattern on the substrate; forming a photoresist pattern having a second stepped-structure portion corresponding to the stepped-structure portion on the passivation layer; patterning the passivation layer using the photoresist pattern as a mask; forming a transparent conductive layer on the substrate; and removing the photoresist pattern where the transparent conductive layer is covered by a stripper penetrating through the stepped-structure portion of the photoresist pattern and forming a pixel electrode connected to the thin film transistor. | 2011-06-23 |
20110151632 | METHOD FOR FORMING SEMICONDUCTOR DEVICE - A method for forming a semiconductor device includes: etching a hard mask layer and a conductive layer formed on a semiconductor substrate, a lower structure being formed on the semiconductor substrate; forming a sacrificial insulating layer at upper parts of the etched hard mask layer and the etched conductive layer of a peripheral circuit region; forming an isolation insulating layer at an upper part of an isolation insulating layer of a cell region; forming spacers at sidewalls of the etched hard mask layer, the etched conductive layer, and the isolation insulating layer of the cell region, respectively; forming storage electrode contact plugs at both sides of each of the spacers, respectively; and removing the sacrificial insulating layer to expose the semiconductor substrate of the peripheral circuit region, and etching the lower structure to expose the semiconductor substrate of the peripheral circuit region. | 2011-06-23 |
20110151633 | METHODS OF FORMING A CONDUCTIVE LAYER STRUCTURE AND METHODS OF MANUFACTURING A RECESSED CHANNEL TRANSISTOR INCLUDING THE SAME - In a method of forming a conductive layer structure and a method of manufacturing a recess channel transistor, a first insulating layer and a first conductive layer are sequentially formed on a substrate having a first region a second region and the substrate is exposed in a recess-forming area in the first region. A recess is formed in the recess-forming-area by etching the exposed region of the substrate. A second insulating layer is conformally formed on a sidewall and a bottom of the recess. A second conductive layer pattern is formed on the second insulating layer to fill up a portion of the recess. A spacer is formed on the second conductive layer pattern and on the second insulating layer on the sidewall of the recess. A third conductive layer pattern is formed on the second conductive layer pattern and the spacer to fill up the recess. | 2011-06-23 |
20110151634 | LATERAL DRAIN-EXTENDED MOSFET HAVING CHANNEL ALONG SIDEWALL OF DRAIN EXTENSION DIELECTRIC - An integrated circuit ( | 2011-06-23 |
20110151635 | HIGH TEMPERATURE GATE REPLACEMENT PROCESS - A method for fabricating an integrated circuit device is disclosed. An exemplary method comprises performing a gate replacement process to form a gate structure, wherein the gate replacement process includes an annealing process; after the annealing process, removing portions of a dielectric material layer to form a contact opening, wherein a portion of the substrate is exposed; forming a silicide feature on the exposed portion of the substrate through the contact opening; and filling the contact opening to form a contact to the exposed portion of the substrate. | 2011-06-23 |
20110151636 | Method For Angular Doping Of Source And Drain Regions For Odd And Even NAND Blocks - A method for creating NAND flash memory. Source implantations are performed at a first implantation angle to areas between stacked gate structures of a NAND string. Drain implantations are performed at a second implantation angle to areas between the stacked gate structures. The source implantation can include n-type and p-type materials implanted under different angles, and the drain implantation can include n-type and p-type materials implanted under different angles. Or, the source implantation can include multiple n-type implantations under different angles, and the drain implantation can include multiple n-type implantations under different angles. | 2011-06-23 |
20110151637 | Method for Improving the Thermal Stability of Silicide - An embodiment of the invention is a method of making a transistor by performing an ion implant on a gate electrode layer | 2011-06-23 |
20110151638 | Method of fabricating semiconductor device - There is provided a method of fabricating a semiconductor including: forming a first and a second bipolar transistors on a semiconductor substrate; forming a dummy layer on, or on the periphery of, at least one region of the emitter region, the base region, or the collector region of the second bipolar transistor and on an area surrounding a contact region for establishing an electrical connection to the outside in the at least one of the emitter region, the base region, or the collector region; forming an insulation layer so as to cover the first bipolar transistor, the second bipolar transistor, and the dummy layer; forming, together with the insulation layer and in a contact region of each region of the first bipolar transistor and the second bipolar transistor, a contact hole for establishing contact with each of those regions; and embedding a conductive member in the contact holes. | 2011-06-23 |
20110151639 | SEMICONDUCTOR DEVICE, METHOD OF FABRICATING THE SAME, SEMICONDUCTOR MODULE, ELECTRONIC CIRCUIT BOARD, AND ELECTRONIC SYSTEM INCLUDING THE DEVICE - Provided are a semiconductor device, a method of fabricating the same, and a semiconductor module, an electronic circuit board, and an electronic system including the device. The semiconductor device includes a lower electrode, a rutile state lower vanadium dioxide layer on the lower electrode, a rutile state titanium oxide on the lower vanadium dioxide layer, and an upper electrode on the titanium oxide layer. | 2011-06-23 |
20110151640 | COMPOUND FOR FILLING SMALL GAPS IN A SEMICONDUCTOR DEVICE, COMPOSITION INCLUDING THE COMPOUND, AND METHOD OF FABRICATING A SEMICONDUCTOR CAPACITOR - A compound for filling small gaps in a semiconductor device, a composition for filling small gaps in a semiconductor device, and a method of fabricating a semiconductor capacitor, the compound including hydrolysates prepared by hydrolysis, in the presence of an acid catalyst, of compounds represented by Formulae 1, 2, and 3: | 2011-06-23 |
20110151641 | METHOD OF FORMING A SEMICONDUCTOR DEVICE - A method of forming a semiconductor device includes the following processes. A first groove is formed in a semiconductor substrate. An insulating film is formed in the first groove. An interlayer insulating film is formed over the semiconductor substrate. A removing process is performed to remove a part of the interlayer insulating film and a part of the insulating film to form an alignment mark in the first groove. | 2011-06-23 |
20110151642 | SEMICONDUCTOR DEVICE INCLUDING HIGH VOLTAGE AND LOW VOLTAGE MOS DEVICES - Methods and devices for forming both high-voltage and low-voltage transistors on a common substrate using a reduced number of processing steps are disclosed. An exemplary method includes forming at least a first high-voltage transistor well and a first low-voltage transistor well on a common substrate separated by an isolation structure extending a first depth into the substrate, using a first mask and first implantation process to simultaneously implant a doping material of a first conductivity type into a channel region of the low-voltage transistor well and a drain region for the high-voltage transistor well. | 2011-06-23 |
20110151643 | METHOD FOR MANUFACTURING BONDED WAFER - A method for manufacturing a bonded wafer by forming an ion implanted layer in a bond wafer; bonding an ion implanted surface of the bond wafer to a surface of a base wafer directly or through a silicon oxide film; and performing a delamination heat treatment. After the formation of the ion implanted layer and before the bonding, a plasma treatment is carried out with respect to a bonding surface of at least one of the bond wafer and the base wafer. The delamination heat treatment is carried out at a fixed temperature by directly putting the bonded wafer into a heat-treating furnace whose furnace temperature is set to the fixed temperature less than 475° C. without a temperature increasing step. | 2011-06-23 |
20110151644 | PROCESS FOR FABRICATING A HETEROSTRUCTURE WITH MINIMIZED STRESS - A process for fabricating a heterostructure by bonding a first wafer to a second wafer, with the first wafer having a thermal expansion coefficient that is lower than the thermal expansion coefficient of the second wafer, and conducting at least one bond-strengthening annealing step. After the bonding step and before the bond-strengthening annealing step, at least one trimming step is conducted in which the first wafer is at least partially trimmed. | 2011-06-23 |
20110151645 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - A manufacturing method of a semiconductor device, including a first step of forming a first electrode pad at an external edge part of a semiconductor chip mounting area of a supporting board; a second step of fixing a rear surface of a semiconductor chip having a main surface, the main surface where a second electrode pad is formed, to an inside of an area of the main surface of the supporting board, the area where the first electrode pad is formed; a third step of forming a first internal connecting terminal on the first electrode pad, and forming a second internal connecting terminal on the second electrode pad; and a fourth step of forming a first insulation layer on the main surface of the supporting board. | 2011-06-23 |
20110151646 | MICROWAVE ANNEALING METHOD FOR DEVICE PROCESSING WITH PLASTIC SUBSTRATE - The present invention provides a microwave annealing method for a plastic substrate. The method comprises pulsed microwave annealing to an organic photo-voltaic device to avoid warpage and degradation of the plastic substrate. Utilizing pulsed microwave annealing method can improve the wettability of the organic layer on the plastic substrate verified by contact angle measurement, and achieving the organic solar cell fabricated with higher power conversion efficiency. | 2011-06-23 |
20110151647 | Semiconductor substrate, semiconductor device, and manufacturing methods thereof - Exemplary embodiments of the present invention provide a method of fabricating a semiconductor substrate, the method including forming a first semiconductor layer on a substrate, forming a metallic material layer on the first semiconductor layer, forming a second semiconductor layer on the first semiconductor layer and the metallic material layer, etching the substrate using a solution to remove the metallic material layer and a portion of the first semiconductor layer, and forming a cavity in the first semiconductor layer under where the metallic material layer was removed. | 2011-06-23 |
20110151648 | Apparatus and method for transformation of substrate - A method is disclosed for forming a layer of a wide bandgap material in a non-wide bandgap material. The method comprises providing a substrate of a non-wide bandgap material and converting a layer of the non-wide bandgap material into a layer of a wide bandgap material. An improved component such as wide bandgap semiconductor device may be formed within the wide bandgap material through a further conversion process. | 2011-06-23 |
20110151649 | METHOD FOR FABRICATING A SEMICONDUCTOR DEVICE - A method for fabricating a semiconductor device includes forming a first semiconductor layer on a front side of the semiconductor substrate. Additional semiconductor layers may be formed on a font side of the first semiconductor layer. The substrate is subsequently removed. In some embodiments, one or more additional semiconductor layers may be formed on the back side of the first semiconductor layer after the semiconductor substrate has been removed. Additionally, in some embodiments, a portion of the first semiconductor layer is removed along with the semiconductor substrate. In such embodiments, the first semiconductor layer is subsequently etched to a known thickness. Source regions and device electrodes may be then be formed. | 2011-06-23 |
20110151650 | SEMICONDUCTOR LAYER STRUCTURE AND METHOD FOR FABRICATING A SEMICONDUCTOR LAYER STRUCTURE - Semiconductor layer structure and a method for producing a structure are provided, including a substrate made of semiconductor material, on which a layer made of a second semiconductor material is situated, furthermore a region ( | 2011-06-23 |
20110151651 | METHOD FOR FORMING INTEGRATED CIRCUITS WITH ALIGNED (100) NMOS AND (110) PMOS FINFET SIDEWALL CHANNELS - A method of forming an integrated circuit device that includes a plurality of multiple gate FinFETs (MuGFETs) is disclosed. Fins of different crystal orientations for PMOS and NMOS MuGFETs are formed through amorphization and crystal regrowth on a direct silicon bonded (DSB) hybrid orientation technology (HOT) substrate. PMOS MuGFET fins are formed with channels defined by fin sidewall surfaces having (110) crystal orientations. NMOS MuGFET fins are formed with channels defined by fin sidewall surfaces having (100) crystal orientations in a Manhattan layout with the sidewall channels of the different PMOS and NMOS MuGFETs aligned at 0° or 90° rotations. | 2011-06-23 |
20110151652 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE AND PLASMA DOPING SYSTEM - An impurity is introduced into a fin-type semiconductor region ( | 2011-06-23 |
20110151653 | SPIN-ON FORMULATION AND METHOD FOR STRIPPING AN ION IMPLANTED PHOTORESIST - A spin-on formulation that is useful in stripping an ion implanted photoresist is provided that includes an aqueous solution of a water soluble polymer containing at least one acidic functional group, and at least one lanthanide metal-containing oxidant. The spin-on formulation is applied to an ion implanted photoresist and baked to form a modified photoresist. The modified photoresist is soluble in aqueous, acid or organic solvents. As such one of the aforementioned solvents can be used to completely strip the ion implanted photoresist as well as any photoresist residue that may be present. A rinse step can follow the stripping of the modified photoresist. | 2011-06-23 |
20110151654 | SEMICONDUCTOR DEVICE MANUFACTURING METHOD - First, a first layer made of Ni or an alloy including Ni may be formed on an upper surface of a semiconductor layer. Next, a second layer made of silicon oxide may be formed on an upper surface of the first layer. Next, a part, which corresponds to a semiconductor region, of the second layer may be removed. Next, second conductive type ion impurities may be injected from upper sides of the first and second layers to the semiconductor layer after the removing step. | 2011-06-23 |
20110151655 | METAL GATE FILL AND METHOD OF MAKING - The present disclosure provides various methods of fabricating a semiconductor device. A method of fabricating a semiconductor device includes providing a semiconductor substrate and forming a gate structure over the substrate. The gate structure includes a first spacer and a second spacer formed apart from the first spacer. The gate structure also includes a dummy gate formed between the first and second spacers. The method also includes removing a portion of the dummy gate from the gate structure thereby forming a partial trench. Additionally, the method includes removing a portion of the first spacer and a portion of the second spacer adjacent the partial trench thereby forming a widened portion of the partial trench. In addition, the method includes removing a remaining portion of the dummy gate from the gate structure thereby forming a full trench. A high k film and a metal gate are formed in the full trench. | 2011-06-23 |
20110151656 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A method of forming a semiconductor device, the method including the following processes. A groove is formed in a semiconductor substrate. A gate electrode is formed in the groove. A boron-phosphorus silicate glass film is formed over the gate electrode. An etching process is performed using the boron-phosphorus silicate glass film as an etching stopper for preventing the gate electrode from being removed. | 2011-06-23 |
20110151657 | METHOD FOR FABRICATING ELECTRICAL BONDING PADS ON A WAFER - A method for fabricating electrical bonding pads on the electrical contact areas of a wafer includes producing first blocks made of a solder material, producing second blocks made of a solder material on these first blocks, and passing the blocks through an oven so as to shape the blocks into approximately domed electrical bonding pads. | 2011-06-23 |
20110151658 | Methods of Forming a Semiconductor Device Having a Contact Structure - A method of forming a semiconductor device having a contact structure includes forming an insulating layer on a semiconductor substrate, and selectively implanting impurity ions into a predetermined region of the insulating layer to generate lattice defects in the predetermined region of the insulating layer. A thermal treatment, such as quenching the insulating layer at a temperature change rate of at least −20° C./minute, is performed on the insulating layer having the lattice defects to accelerate generation of the lattice defects in the predetermined region such that a conductive region results from the generated lattice defects to provide current paths in the predetermined region. | 2011-06-23 |
20110151659 | MULTILAYERED THROUGH A VIA - A method for forming a through substrate via (TSV) comprises forming an opening within a substrate. An adhesion layer of titanium is formed within the via opening, a nucleation layer of titanium nitride is formed over the adhesion layer, and a tungsten layer is deposited over the nucleation layer, the tungsten layer having a thickness less than or equal to a critical film thickness sufficient to provide for film integrity and adhesion stability. A stress relief layer of titanium nitride is formed over the tungsten layer and a subsequent tungsten layer is deposited over the stress relief layer. The subsequent tungsten layer has a thickness less than or equal to the critical film thickness. The method further includes planarizing to expose the interlevel dielectric layer and a top of the TSV and backgrinding a bottom surface of the substrate sufficient to expose a bottom portion of the TSV. | 2011-06-23 |
20110151660 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, METHOD OF PROCESSING SUBSTRATE AND SUBSTRATE PROCESSING APPARATUS - A method of manufacturing a semiconductor device capable of minimally preventing the property deterioration caused by the oxidation of a metal film, and a substrate processing apparatus are provided. The method of manufacturing a semiconductor device includes: (a) loading a substrate into a processing container; (b) forming a metal film on the substrate using a chemical deposition method by supplying a processing gas into the processing container and exhausting the processing gas; (c) forming an aluminum nitride film on the metal film using the chemical deposition method by supplying an aluminum-containing source gas and a nitrogen-containing gas into the processing container and exhausting the aluminum-containing source gas and the nitrogen-containing gas; and (d) unloading the substrate from the processing container after forming the metal film and the aluminum nitride film, wherein the step (b) and the step (c) are continuously performed while maintaining an inside of the processing container to have an oxygen-free atmosphere. | 2011-06-23 |
20110151661 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A first film containing a first metal material having a diffusion preventing function for copper, a second film containing oxygen-contained copper film, a third film containing copper and a second metal material which exhibits a diffusion preventing function for copper by bonding with oxygen, and a fourth film of copper as the main material are formed in an opening formed in an insulating film, and then a barrier layer containing the first metal material, the second metal material and oxygen is formed by thermal processing between the insulating film and the fourth film. | 2011-06-23 |
20110151662 | MANUFACTURE METHOD FOR SEMICONDUCTOR DEVICE HAVING IMPROVED COPPER DIFFUSION PREVENTIVE FUNCTION OF PLUGS AND WIRINGS MADE OF COPPER OR COPPER ALLOY AND SEMICONDUCTOR DEVICE OF THIS KIND - (a) A copper alloy film containing at least two types of metal elements in addition to copper is formed on the surface of an insulator containing oxygen and formed on a semiconductor substrate. (b) A metal film made of pure copper or copper alloy is formed on the copper alloy film. (c) After the step (a) or (b), heat treatment is performed under the condition that a metal oxide film is formed on a surface of the insulator through reaction between the oxygen in the insulator and the metal elements in the copper alloy film. | 2011-06-23 |
20110151663 | METHOD TO FORM A VIA - A method for forming a via, comprising (a) providing a structure comprising a mask ( | 2011-06-23 |
20110151664 | METHOD OF MANUFACTURING MULTI-LEVEL METAL THIN FILM AND APPARATUS FOR MANUFACTURING THE SAME - Provided are methods and apparatuses for manufacturing a multilayer metal thin film without additional heat treatment processes. The method of manufacturing a multilayer metal thin film including steps of: (a) forming a first metal layer on a substrate by flowing a first metal precursor into a first reaction container; and (b) forming a second metal layer on the first metal layer by flowing a second metal precursor into a second reaction container, wherein the step (b) is performed in a range of a heat treatment temperature of the first metal layer so that the second metal layer is formed as the first metal layer is heat-treated. | 2011-06-23 |
20110151665 | METHOD FOR NON-CONTACT MATERIALS DEPOSITION - Embodiments of the invention are directed to a method of printing lines. The method may include depositing material on a substrate from a plurality of nozzles to form a multi-layered line of a desired cross section area or a desired height by dispensing the material in at least two layers in a single scan. Each layer may be printed by different nozzles and the number of layers in the line is determined based on the desired cross section area or height. | 2011-06-23 |
20110151666 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A method for fabricating a semiconductor device includes etching a substrate to form a plurality of trenches, forming first liner layers over bottom surfaces and inner sidewalls of the trenches to a first height, forming sacrificial liner layers on one of the inner sidewalls of the trenches where the first liner layers are formed, forming third sacrificial layers to a second height, so that the third sacrificial layers are buried over the trenches where the sacrificial liner layers are formed, removing portions of the sacrificial liner layers exposed by the third sacrificial layers to form sacrificial patterns, forming second liner layers on the inner sidewalls of the trenches exposed by the third sacrificial layers, and removing the third sacrificial layers to form side contact regions opening one of the inner sidewalls of the trenches in a line form. | 2011-06-23 |
20110151667 | Methods of Manufacturing Three-Dimensional Semiconductor Devices and Related Devices - A three-dimensional semiconductor device may include a substrate including wiring and contact regions and a thin film structure on the wiring and contact regions of the substrate. The thin-film structure may include a plurality of alternating wiring layers and inter-layer insulating layers defining a terraced structure in the contact region so that each of the wiring layers includes a contact surface in the contact region that extends beyond others of the wiring layers more distant from the substrate. A plurality of contact structures may extend in a direction perpendicular to a surface of the substrate with each of the contact structures being electrically connected to a contact surface of a respective one of the wiring layers. Related methods are also discussed. | 2011-06-23 |
20110151668 | PITCH DIVISION PATTERNING TECHNIQUES - Embodiments of the invention comprise pitch division techniques to extend the capabilities of lithographic techniques beyond their minimum pitch. The pitch division techniques described herein employ additional processing to ensure pitch divided lines have the spatial isolation necessary to prevent shorting problems. The pitch division techniques described herein further employ processing acts to increase the structural robustness of high aspect ratio features. | 2011-06-23 |
20110151669 | Release Accumulative Charges by Tuning ESC Voltages in Via-Etchers - A method of forming an integrated circuit structure on a wafer includes providing a first etcher comprising a first electrostatic chuck (ESC); placing the wafer on the first ESC; and forming a via opening in the wafer using the first etcher. After the step of forming the via opening, a first reverse de-chuck voltage is applied to the first ESC to release the wafer. The method further includes placing the wafer on a second ESC of a second etcher; and performing an etching step to form an additional opening in the wafer using the second etcher. After the step of forming the additional opening, a second reverse de-chuck voltage is applied to the second ESC to release the wafer. The second reverse de-chuck voltage is different from the first reverse de-chuck voltage. | 2011-06-23 |
20110151670 | METHOD OF CONTROLLING ETCH MICROLOADING FOR A TUNGSTEN-CONTAINING LAYER - A method for etching features of different aspect ratios in a tungsten containing layer is provided. An etch gas is provided containing a tungsten etch component and a deposition component. A plasma is formed from the provided etch gas. A tungsten containing layer patterned with wide and narrow features is etched with the provided plasma. | 2011-06-23 |
20110151671 | METHOD OF TEXTURING SEMICONDUCTOR SUBSTRATES - Semiconductor substrates are cleaned and subsequently oxidized. After the semiconductor is oxidized it is textured to reduce incident light reflectance. The textured semiconductors can be used in the manufacture of photovoltaic devices. | 2011-06-23 |
20110151672 | Method of Etching Oxide Layer and Nitride Layer - An exemplary method of patterning oxide layer and removing residual nitride includes steps of forming a first oxide layer, a nitride layer, a second oxide layer and a complex hard mask on a substrate in turn. The first oxide layer covers an insulating structure. The second oxide layer, the complex hard mask and the nitride layer are etched by utilizing a patterned photoresist as an etching mask, so as to expose the first oxide layer. In addition, the part of the nitride layer covering the insulating structure can be further removed. Accordingly, the present invention can effectively control layout patterns of material layers and doped regions and thereby can improve the performance of a narrow width device. | 2011-06-23 |
20110151673 | PLASMA ETCHING METHOD, PLASMA ETCHING DEVICE, AND METHOD FOR PRODUCING PHOTONIC CRYSTAL - A plasma etching method capable of oblique etching with a high aspect ratio and high uniformity is provided. In the plasma etching method, a base body is etched with a high aspect ratio by the following process: An electric-field control device having an ion-introducing orifice penetrating therethrough in a direction inclined from the normal to the surface of a base body is placed on or above the surface of this base body. Plasma is generated on the surface of the base body on or above which the electric-field control is placed. A potential difference is formed between the plasma and the base body so as to attract ions in the plasma toward the base body. | 2011-06-23 |
20110151674 | SMOOTH SICONI ETCH FOR SILICON-CONTAINING FILMS - A method of etching silicon-containing material is described and includes a SiConi™ etch having a greater or lesser flow ratio of hydrogen compared to fluorine than that found in the prior art. Modifying the flow rate ratios in this way has been found to reduce roughness of the post-etch surface and to reduce the difference in etch-rate between densely and sparsely patterned areas. Alternative means of reducing post-etch surface roughness include pulsing the flows of the precursors and/or the plasma power, maintaining a relatively high substrate temperature and performing the SiConi™ in multiple steps. Each of these approaches, either alone or in combination, serve to reduce the roughness of the etched surface by limiting solid residue grain size. | 2011-06-23 |
20110151675 | DEVICE AND PROCESS FOR LIQUID TREATMENT OF A WAFER SHAPED ARTICLE - A spin chuck in an apparatus for single wafer wet processing has structures at its periphery that, in combination with a supported wafer, form a series of annular nozzles that direct flowing gas from a chuck-facing surface of the wafer, around the edge of the wafer, and exhaust the gas away from the non-chuck-facing surface of the wafer, thereby preventing treatment fluid applied to the non-chuck-facing surface from contacting the edge region of the wafer. Retaining pins with enlarged heads engage the wafer edge and prevent it from being displaced upwardly when a high flow rate of gas is utilized. | 2011-06-23 |