25th week of 2022 patent applcation highlights part 75 |
Patent application number | Title | Published |
20220199483 | POWER DEVICE PACKAGING - A semiconductor device package includes a multilayer substrate including atop layer, a bottom layer and an intermediate layer between the top layer and the bottom layer. The package also includes one or more semiconductor dies embedded in the intermediate layer and conductive connector means to provide a conductive connection from the one or more dies. The conductive connector means extend through the top layer to provide connection means for one or more devices mounted on or adjacent the top layer. | 2022-06-23 |
20220199484 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR MODULE - In a semiconductor device, when a first surface of a first member is viewed in plan, a plurality of circuit blocks are disposed in an inner region of the first surface. The second member is joined to the first surface of the first member in surface contact with the first surface. The second member includes one or more circuit blocks. A conductive protrusion protrudes from the second member on an opposite side to the first member. One of the circuit blocks in the second member constitutes a first amplifier circuit including a plurality of first transistors that are connected in parallel to each other. At least one of the circuit blocks in the first member overlaps at least one circuit block in the second member in a plan view. | 2022-06-23 |
20220199485 | MODULE - A module includes a substrate including a first main surface, a first component mounted on the first main surface, a first sealing resin that covers the first main surface and a portion of connection of the first component to at least the first main surface, a first conductor pattern arranged on a surface of the first sealing resin on a side distant from the first main surface, and a columnar conductor as a metal member connected to the first conductor pattern to pass through the first sealing resin from an electrode drawn from the first component along the first main surface. | 2022-06-23 |
20220199486 | HEAT EXTRACTION PATH FROM A LASER DIE USING A HIGHLY CONDUCTIVE THERMAL INTERFACE MATERIAL IN AN OPTICAL TRANSCEIVER - A semiconductor package comprises a substrate and a ceramic carrier mounted to the substrate. An integrated circuit (IC) die is mounted to the ceramic carrier. A heat extraction path away from the IC die comprises: i) a thermal interface material over the IC die, the thermal interface material having a thickness of approximately 25 to 80 um; ii) an integrated heat spreader over the thermal interface material; iii) a ceramic carrier plate over the integrated heat spreader; and iv) an electrically conductive thermal pad between the ceramic carrier plate and a housing of the semiconductor package. | 2022-06-23 |
20220199487 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE FABRICATION METHOD - The semiconductor device includes a first semiconductor IC, a second semiconductor IC with a smaller heat generation quantity than the first semiconductor IC, a first heat conduction member covering at least a portion of the first semiconductor IC, a second heat conduction member covering the second semiconductor IC and the first heat conduction member, and a heat dissipation member. The heat dissipation member covers the second heat conduction member and dissipates heat produced from the first semiconductor IC and second semiconductor IC to the exterior. A thermal conductivity of the first heat conduction member is lower than a thermal conductivity of the second heat conduction member in a horizontal direction, which is a direction in which the first semiconductor IC and the second semiconductor IC are arrayed. | 2022-06-23 |
20220199488 | SEMICONDUCTOR STRUCTURE - A semiconductor structure includes a die including a circuitry disposed over a surface of the die or within the die and having specific functions for the die; a heat dissipation member attached to the die by an adhesive disposed between the surface of the die and the heat dissipation member; and a nanostructure disposed between the adhesive and the die, configured to conduct heat from the die to the heat dissipation member, protruding from the adhesive towards the surface of the die and contacting the surface of the die. | 2022-06-23 |
20220199489 | GALLIUM ALLOYS AS FILLERS FOR POLYMER THERMAL INTERFACE MATERIALS - Embodiments disclosed herein include polymer thermal interface materials. In an embodiment a thermal interface material (TIM) comprises a polymer matrix and a liquid metal filler in the polymer matrix. In an embodiment, the liquid metal filler comprises a liquid core and an oxide layer around the liquid core. In an embodiment, the liquid core comprises gallium or a gallium alloy, and the oxide layer comprises a metal oxide other than gallium oxide. | 2022-06-23 |
20220199490 | SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD FOR THE SAME - A semiconductor structure and a manufacturing method for the same. The semiconductor structure includes a plug element and a via element. The plug element includes a tungsten plug. The plug element has a plug size in a lateral direction. The via element is electrically connected on the plug element. The via element is non-symmetrical with respect a center line of the plug element extending along a longitudinal direction. The via element has a via size in the lateral direction. The plug size is bigger than the via size. | 2022-06-23 |
20220199491 | MOTOR DRIVE DEVICE - A motor drive device includes: a first inverter including a plurality of first switching elements and connected to a plurality of coils; a second inverter including a plurality of second switching elements and connected to the plurality of coils; a plurality of transfer switching elements connected to the second ends; a capacitor disposed at one side of a casing of a motor; first and second cooling channels disposed at both sides of the capacitor; a plurality of first power modules including some of the plurality of first switching elements and some of the transfer switching elements; and a plurality of second power modules including some of the plurality of second switching elements. | 2022-06-23 |
20220199492 | SEMICONDUCTOR COOLING ARRANGEMENT WITH IMPROVED BAFFLE - A semiconductor cooling arrangement. The semiconductor cooling arrangement comprises one or more semiconductor assemblies, a housing, and one or more baffles. Each assembly comprises a heatsink and one or more semiconductor power devices mounted on and thermally coupled to the heatsink. The housing is for housing the one or more assemblies in a chamber within the housing, and comprises inlet and outlet ports in fluid communication with the chamber. The baffles are arranged such that fluid flows through each baffle to a respective heatsink. Each baffle comprises through-holes arranged such that fluid flows through the through holes to a region of the semiconductor assembly to which a semiconductor power device is mounted, or to a region of the heatsink opposite a location to which a semiconductor power device is mounted. Each baffle is a printed circuit board, comprising control and/or monitoring circuitry for an adjacent semiconductor assembly, and being electrically connected to the one or more semiconductor power devices of that semiconductor assembly. | 2022-06-23 |
20220199493 | SEMICONDUCTOR DEVICE INCLUDING A THROUGH SILICON VIA STRUCTURE AND METHOD OF FABRICATING THE SAME - A semiconductor device may include a via hole, a first electrode, a second electrode and a first protecting insulation layer. The via hole may be formed to penetrate a substrate. The first electrode may include an electrode segment formed on a surface of the via hole. The second electrode may be formed on the first electrode along the surface of the via hole. The second electrode may include two ends that are positioned below a surface of the substrate. The first protecting insulation layer may be formed on the second electrode along the surface of the via hole. The first protecting insulation layer may include both ends that upwardly protrude from the both ends of the second electrode. | 2022-06-23 |
20220199494 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE WITH ETCH STOP LAYER HAVING GREATER THICKNESS - The present application discloses provides a method for fabricating a semiconductor device including providing a first semiconductor die including a first conductive layer, forming a first etch stop layer on the first conductive layer, bonding a second semiconductor die, which includes a second conductive layer above the first etch stop layer and a second etch stop layer on the second conductive layer, onto the first etch stop layer, performing a via etch process to concurrently form a first via opening to expose the first etch stop layer and a second via opening to expose the second etch stop layer, conformally forming isolation layers in the first via opening and the second via opening, performing a punch etch process to extend the first via opening and the second via opening, and concurrently forming a first through substrate via in the first via opening and a second through substrate via in the second via opening. | 2022-06-23 |
20220199495 | SEMICONDUCTOR-MODULE EXTERNAL TERMINAL - A semiconductor-module external terminal includes a bottom portion to be soldered and a terminal body vertically bent from the bottom portion, and the terminal body includes a first groove on a left end side and a second groove on a right end side of a bending portion which is bent immediately above the bottom portion, and the first groove and the second groove are asymmetrical with respect to a center line passing the terminal body in a vertical direction. | 2022-06-23 |
20220199496 | CHIP-ON-FILM PACKAGING STRUCTURE AND CHIP-ON-FILM PACKAGING METHOD - The present invention provides a chip-on-film (COF) packaging structure and a COF packaging method. The COF packaging structure includes a flexible substrate and a chip. The flexible substrate includes a first groove provided on a first surface of the flexible substrate, a protrusion provided in the first groove, and a substrate bonding pad disposed in the first groove. The chip includes a second groove provided on a second surface of the chip, and a chip bonding pad disposed on the second surface and corresponding to the substrate bonding pad. The first groove of the flexible substrate is matched with a peripheral shape of the chip, and the second groove is matched with the protrusion of the first groove to embed the chip in the flexible substrate. The chip bonding pad is electrically connected to the substrate bonding pad. | 2022-06-23 |
20220199497 | 3D PACKAGE CONFIGURATION - A novel 3D package configuration is provided by stacking a folded flexible circuit board structure on a package substrate and electrically connected therewith based on the foldable characteristics of the flexible circuit board, and the high temperature resistance of the flexible circuit board which is suitable for insulating layer process, metal layer process, photolithography process, etching and development process, to make conventional semiconductor dies of various functions be bonded on one die and/or two side of a flexible circuit board and electrically connected therewith in advance. | 2022-06-23 |
20220199498 | 3D PACKAGE CONFIGURATION - A novel 3D package configuration is provided by stacking a folded flexible circuit board structure on a package substrate and electrically connected therewith based on the foldable characteristics of the flexible circuit board, and the high temperature resistance of the flexible circuit board which is suitable for insulating layer process, metal layer process, photolithography process, etching and development process, to make conventional semiconductor dies of various functions be bonded on one die and/or two side of a flexible circuit board and electrically connected therewith in advance. | 2022-06-23 |
20220199499 | PACKAGE FOR HOUSING ELECTRONIC COMPONENT, ELECTRONIC DEVICE, AND ELECTRONIC MODULE - A package for housing an electronic component includes: a base portion including a first surface including a recessed portion in which an electronic component is mounted and also including a second surface located on an opposite side to the first surface; an external connection conductor located on the second surface; internal wiring located inside the base portion; first wiring located on the second surface and connected to the internal wiring; and second wiring located between the first wiring and the external connection conductor and connected to the external connection conductor, in which the first wiring and the second wiring are covered with an insulating layer. | 2022-06-23 |
20220199500 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICES, COMPONENT FOR USE THEREIN AND CORRESPONDING SEMICONDUCTOR DEVICE - A leadframe includes a pattern of electrically-conductive formations with one or more sacrificial connection formations extending bridge-like between a pair of electrically-conductive formations. The sacrificial connection formation or formations are formed at one of the first surface and the second surface of the leadframe and have a thickness less than the leadframe thickness between the first surface and the second surface. A filling of electrically-insulating material is molded between the electrically-conductive formations of the leadframe, with electrically-insulating material molded between the connection formation(s) and the other surface of the leadframe. The sacrificial connection formation(s) counter deformation and displacement of parts during formation and pre-molding of the leadframe. | 2022-06-23 |
20220199501 | ELECTRIC DRIVE MODULE - An electric drive module having a motor and an inverter that are disposed in a housing The motor includes a stator, which has a plurality of sets of windings. The inverter has a plurality of power semiconductors, which are mounted into a retaining member, an end plate, which is sealingly coupled to the retaining member, and an inlet port that extends through the end plate. Sets of the semiconductor devices are electrically coupled to corresponding sets of the windings. Power terminals on the semiconductor devices are coupled to a heat sink. Fins on the heat sinks extend into an annular region that is adjacent to axial ends of the windings. At least one of the retaining member and the end plate is sealingly coupled to the housing assembly. The inlet port, the annular region and cooling passages in the stator are coupled in fluid communication. | 2022-06-23 |
20220199502 | MULTIPLE SUBSTRATE PACKAGE SYSTEMS AND RELATED METHODS - Implementations of a semiconductor package may include a first substrate including a first group of leads physically coupled thereto and a second group of leads physically coupled thereto; a second substrate coupled over the first substrate and physically coupled to the first group of leads and the second group of leads; and one or more semiconductor die coupled between the first substrate and the second substrate. The second group of leads may be electrically isolated from the first substrate. | 2022-06-23 |
20220199503 | NOVEL LGA ARCHITECTURE FOR IMPROVING RELIABILITY PERFORMANCE OF METAL DEFINED PADS - Embodiments disclosed herein include electronic packages and methods of forming such electronic packages. In an embodiment, an electronic package comprises a package substrate with a die side and a land side. In an embodiment, a pad is on the land side. In an embodiment, a dielectric layer covers sidewalls of the pad, and a surface finish is over an exposed surface of the pad. | 2022-06-23 |
20220199504 | MODULE - A module comprises: a substrate having a first surface; a first component that is mounted on the first surface; a first sealing resin that covers the first surface and at least a portion of the first component that is connected to the first surface; a first conductor pattern that is disposed on a surface of the first sealing resin that is farther from the first surface; and a wire that serves as a plurality of connecting conductors each electrically interconnecting the first surface and the first conductor pattern, wherein when viewed in a direction perpendicular to the first surface, the plurality of connecting conductors are disposed so as to surround the first component, and the first conductor pattern includes a frame-shaped portion that electrically interconnects the plurality of connecting conductors outside the first component successively. | 2022-06-23 |
20220199505 | SEMICONDUCTOR DEVICE - A semiconductor device includes a substrate comprising a redistribution layer, a ball land provided on a bottom surface of the redistribution layer, a passivation layer surrounding the ball land on the bottom surface of the redistribution layer and spaced apart from the ball land by a space region formed between the passivation layer and the ball land, and a signal wiring line provided in the redistribution layer on the ball land, a semiconductor chip mounted on the substrate, and an external terminal adhered to the ball land. The signal wiring line includes a first wiring pattern extending in a first direction perpendicular to one side surface of the semiconductor chip, and a support pattern disposed under the one side surface of the semiconductor chip. A second width of the support pattern in a second direction is greater than a first width of the wiring pattern in the second direction. | 2022-06-23 |
20220199506 | PRINTED CIRCUIT BOARD - A printed circuit board includes a first insulating layer; a first wiring layer buried in the first insulating layer, exposed to one surface of the first insulating layer, and including a plurality of first wiring patterns; a second wiring layer including a plurality of second wiring patterns spaced apart from the plurality of first wiring patterns on the one surface of the first insulating layer; and a second insulating layer disposed on the one surface of the first insulating layer and covering the plurality of second wiring layers. At least a portion of the plurality of second wiring patterns on the one surface of the first insulating layer is disposed in regions between adjacent first wiring patterns among the plurality of first wiring patterns. | 2022-06-23 |
20220199507 | MULTI-LAYERED PACKAGING FOR SUPERCONDUCTING QUANTUM CIRCUITS - A quantum semiconductor device includes a qubit chip; an interposer chip, with a handler, including a through-silicon-via (TSV) coupled to a first side of the qubit chip. A multi-level wiring (MLW) layer contacts an underside of the interposer chip and coupling to the top side of the handler, the TSV facilitates an electrical signal connection between the MLW layer, a topside of the interposer chip and the qubit chip, wherein structure of the device mitigates signal cross-talk across respective lines of the MLW layer. | 2022-06-23 |
20220199508 | ELECTRONIC DEVICE AND MANUFACTURING METHOD THEREOF - An electronic device and a manufacturing method thereof are provided. The manufacturing method of the electronic device includes the following steps. A first carrier is provided. A first substrate is disposed on the first carrier. A first conductive structure is disposed on the first substrate, and the first carrier is removed. A second carrier is provided. A second substrate is disposed on the second carrier. A second conductive structure is disposed on the second substrate, and the second carrier is removed. The first substrate and the second substrate are combined. | 2022-06-23 |
20220199509 | WIRING STRUCTURE AND METHOD FOR MANUFACTURING THE SAME - A wiring structure and a method for manufacturing the same are provided. The wiring structure includes a lower conductive structure, an upper conductive structure and a conductive via. The lower conductive structure includes a first dielectric layer and a first circuit layer in contact with the first dielectric layer. The upper conductive structure is attached to the lower conductive structure. The upper conductive structure includes a plurality of second dielectric layers, a plurality of second circuit layers in contact with the second dielectric layers, and defines an accommodating hole. An insulation material is disposed in the accommodating hole. The conductive via extends through the insulation material, and electrically connects the lower conductive structure. | 2022-06-23 |
20220199510 | STRIP SUBSTRATE AND SEMICONDUCTOR PACKAGE - Disclosed is a strip substrate including a dielectric layer that has a plurality of unit regions spaced apart from each other in a first direction and a saw line region between the unit regions, a plurality of conductive dummy patterns on corresponding unit regions of the dielectric layer, a plurality of saw line patterns on the saw line region of the dielectric layer and extending in a second direction that intersects the first direction, and a protection pattern that covers the dielectric layer. Ends of the conductive dummy patterns are spaced apart from each other in a direction parallel to the first direction. Ends of the saw line patterns are spaced apart from each other in a direction parallel to the second direction. The protection pattern is between the ends of the conductive dummy patterns and between the ends of the saw line patterns. | 2022-06-23 |
20220199511 | PACKAGE SUBSTRATE AND SEMICONDUCTOR PACKAGE INCLUDING THE SAME - A package substrate includes an insulating layer having a mounting surface; a wiring pattern extending in the insulating layer; and a chip bonding pad provided on the mounting surface of the insulating layer and connected to the wiring pattern, the chip bonding pad having a tapered shape in which a horizontal cross-sectional area thereof gradually decreases away from the mounting surface of the insulating layer in a vertical direction. A portion of the chip bonding pad closest to the mounting surface of the insulating layer has a horizontal length of about 20 micrometers (μm) to about 30 μm. | 2022-06-23 |
20220199512 | Chip-On-Film Package and Semiconductor Chip - The present disclosure relates to a chip on film package, in which communication wires for communication with a control circuit are disposed to traverse a semiconductor chip thereunder so as to simplify the wiring inside the semiconductor chip. | 2022-06-23 |
20220199513 | WIRING BOARD AND METHOD OF MANUFACTURING THE SAME - A wiring board includes an insulating layer, a wiring layer and a plurality of conductive columns. The insulating layer has a first surface and a second surface opposite to the first surface. The wiring layer is disposed in the insulating layer and has a third surface and a fourth surface opposite to the third surface. The insulating layer covers the third surface, and the second surface of the insulating layer is flush with the fourth surface of the wiring layer. The conductive columns are disposed in the insulating layer and connected to the wiring layer. The conductive columns extend from the third surface of the wiring layer to the first surface of the insulating layer, and protrude from the first surface. | 2022-06-23 |
20220199514 | ELECTRONIC DEVICE HAVING INTEGRATED CIRCUIT CHIP CONNECTED TO PADS ON SUBSTRATE - The present disclosure provides an electronic device including a substrate, a conductive pad, a chip and an insulating layer. The conductive pad is disposed on the substrate. The chip is disposed on the conductive pad. The insulating layer is disposed between the conductive pad and the chip, wherein the insulating layer includes an opening, and the chip is electrically connected to the conductive pad through the opening. An outline of the opening includes a plurality of curved corners in a normal direction of the substrate. | 2022-06-23 |
20220199515 | ELECTROMIGRATION RESISTANT AND PROFILE CONSISTENT CONTACT ARRAYS - A package assembly includes a substrate and at least a first die having a first contact array and a second contact array. First and second via assemblies are respectively coupled with the first and second contact arrays. Each of the first and second via assemblies includes a base pad, a cap assembly, and a via therebetween. One or more of the cap assembly or the via includes an electromigration resistant material to isolate each of the base pad and the cap assembly. Each first cap assembly and via of the first via assemblies has a first assembly profile less than a second assembly profile of each second cap assembly and via of the second via assemblies. The first and second cap assemblies have a common applied thickness in an application configuration. The first and second cap assemblies have a thickness variation of ten microns or less in a reflowed configuration. | 2022-06-23 |
20220199516 | METAL LINES PATTERNED BY BOTTOM-UP FILL METALLIZATION FOR ADVANCED INTEGRATED CIRCUIT STRUCTURE FABRICATION - Embodiments of the disclosure are in the field of integrated circuit structure fabrication. In an example, an integrated circuit structure includes a plurality of conductive interconnect lines above a substrate, individual ones of the conductive interconnect lines having a top and sidewalls. An etch stop layer is on the top and along an entirety of the sidewalls of the individual ones of the conductive interconnect lines. | 2022-06-23 |
20220199517 | DIE STITCHING AND HARVESTING OF ARRAYED STRUCTURES - Multi-die structures with die-to-die routing are described. In an embodiment, each die is patterned into the same semiconductor substrate, and the dies may be interconnected with die-to-die routing during back-end wafer processing. Partial metallic seals may be formed to accommodate the die-to-die routing, programmable dicing, and various combinations of full metallic seals and partial metallic seals can be formed. This may also be extended to three dimensional structures formed using wafer-on-wafer or chip-on-wafer techniques. | 2022-06-23 |
20220199518 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR PACKAGE - A semiconductor device includes a semiconductor substrate having a semiconductor device on an active surface thereof. The semiconductor substrate has a quadrangular plane. An insulating layer is on the active surface of the semiconductor substrate. A passivation layer is on the insulating layer. The insulating layer includes an insulating layer central portion having a side surface extending in parallel with a side surface of the semiconductor substrate. The side surface of the insulating layer central portion is spaced apart from the side surface of the semiconductor substrate by a first size. An insulating layer corner portion is at each corner of the insulating layer central portion and protrudes from the side surface of the insulating layer central portion in a horizontal direction. The passivation layer covers the insulating layer central portion. | 2022-06-23 |
20220199519 | METAL INSULATOR METAL (MIM) CAPACITOR WITH PEROVSKITE DIELECTRIC - Metal insulator metal capacitors are described. In an example, a metal-insulator-metal (MIM) capacitor includes a first electrode plate, and a first capacitor dielectric on the first electrode plate. The first capacitor dielectric is or includes a perovskite high-k dielectric material. A second electrode plate is on the first capacitor dielectric and has a portion over and parallel with the first electrode plate, and a second capacitor dielectric is on the second electrode plate. A third electrode plate is on the second capacitor dielectric and has a portion over and parallel with the second electrode plate. | 2022-06-23 |
20220199520 | SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR PACKAGE - A semiconductor package includes a support substrate having connection wirings disposed therein. At least one capacitor is disposed on the support substrate. The capacitor has first and second electrodes that are exposed from an upper surface of the support substrate. A redistribution wiring layer covers the upper surface of the support substrate. The redistribution wiring layer has redistribution wirings electrically connected to the connection wirings and the first and second electrodes respectively. A semiconductor chip is disposed on the redistribution wiring layer. The semiconductor chip has chip pads that are electrically connected to the redistribution wirings and outer connectors disposed on a lower surface of the support substrate and electrically connected to the connection wirings. | 2022-06-23 |
20220199521 | HIGH ASPECT RATIO VIAS FOR INTEGRATED CIRCUITS - An interlayer interconnect for an integrated circuit includes a first line in a first wiring layer, a first via portion integral to and extending from the first line, and a second line in a second wiring layer that is adjacent to the first wiring layer. The interlayer interconnect also includes a third line in the second wiring layer that is a first distance from the second line, wherein the first distance is a pitch of the second wiring layer, and a second via portion integral to and extending from the second line and in electrical contact with the first via portion at an interface to form a via. The via extends a second distance that is at least one-and-a-quarter times the pitch. | 2022-06-23 |
20220199522 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor device including transistors on a substrate, a first interlayer insulating layer on the transistors, a first lower interconnection line and a second lower interconnection line in an upper portion of the first interlayer insulating layer, a dielectric layer being selectively on a top surface of the first interlayer insulating layer except top surfaces of the first and second lower interconnection lines, an etch stop layer on the first and second lower interconnection lines and the dielectric layer, a second interlayer insulating layer on the etch stop layer, and an upper interconnection line in the second interlayer insulating layer may be provided. | 2022-06-23 |
20220199523 | BARRIER-FREE INTERCONNECT STRUCTURE AND MANUFACTURING METHOD THEREOF - Semiconductor devices and method of forming the same are disclosed herein. A semiconductor device according to the present disclosure includes a first dielectric layer having a first top surface and a contact via extending through the first dielectric layer and rising above the first top surface of the first dielectric layer. | 2022-06-23 |
20220199524 | FUSES TO MEASURE ELECTROSTATIC DISCHARGE DURING DIE TO SUBSTRATE OR PACKAGE ASSEMBLY - A system and method for detecting and measuring electrostatic discharge during semiconductor assembly are described. A semiconductor device fabrication process forms a conductor between two metal routes in a series path on a semiconductor die. The series path is between a bump on the die and a substrate tie. The two metal routes have a width greater than a threshold based on a metal width capable of conducting a critical current density caused by an electrostatic discharge event without conductive failure or breakdown. The conductor has a width less than the threshold. When an electrostatic discharge event occurs, if the current exceeds a critical amount of current, the conductor experiences conductive breakdown and current ceases to flow. During later testing, this series path is tested for open connections, which indicate whether the conductor acting as an electrical on-die fuse experienced conductive failure during assembly of a semiconductor chip. | 2022-06-23 |
20220199525 | METAL-FREE FUSE STRUCTURES - The present disclosure relates to semiconductor structures and, more particularly, to a metal-free fuse structure and methods of manufacture. The structure includes: a first metal-free fuse structure comprising a top semiconductor material of semiconductor-on-insulator (SOI) technologies, the top semiconductor material including end portions with a first electrical resistance and a fuse portion of a second, higher electrical resistance electrically connected to the end portions; and a second metal-free fuse structure comprising the top semiconductor material of semiconductor-on-insulator (SOI) technologies, the top semiconductor material of the second metal-free fuse structure including at least a fuse portion of a lower electrical resistance than the second, higher electrical resistance. | 2022-06-23 |
20220199526 | INTEGRATED CIRCUIT DEVICES HAVING IMPROVED CONTACT PLUG STRUCTURES THEREIN - An integrated circuit device includes a substrate and a first electrically insulating layer on the substrate. An electrically conductive contact plug is provided, which extends at least partially through the first electrically insulating layer. The contact plug includes a protrusion having a top surface that is spaced farther from the substrate relative to a top surface of a portion of the first electrically insulating layer extending adjacent the contact plug. An electrically conductive line is provided with a terminal end, which extends on a first portion of the protrusion. A second electrically insulating layer is provided, which extends on a second portion of the protrusion and on the first electrically insulating layer. The second electrically insulating layer has a sidewall, which extends opposite a sidewall of the terminal end of the electrically conductive line. | 2022-06-23 |
20220199527 | Devices and Methods of Local Interconnect Stitches and Power Grids - According to one implementation of the present disclosure, a power grid comprising: one or more cells; a metal layer; first and second buried power rails; and one or more local interconnects, wherein one or more local interconnect stitches are configured to electrically couple the one or more cells to either of the first or second buried power rails through the metal layer and the one or more local interconnects. | 2022-06-23 |
20220199528 | Semiconductor Assembly - A semiconductor assembly is described that includes a substrate having top and bottom sides. An integrated circuit die coupled to the substrate includes first and second distinct sets of ground pads. In some embodiments, the first and second sets of ground pads are configured to have distinct ground return paths to a host system. In further embodiments, one of the ground return paths may include a metal plate coupled between ground contacts on the top side of the substrate and ground contacts on a printed circuit board of the host system. | 2022-06-23 |
20220199529 | SEMICONDUCTOR PACKAGE - Disclosed is a semiconductor package including a semiconductor chip that includes a chip pad on one surface of the semiconductor chip, a redistribution pattern on the one surface of the semiconductor chip and electrically connected to the chip pad, and a photosensitive dielectric layer between the semiconductor chip and the redistribution pattern. The photosensitive dielectric layer may be in physical contact with the redistribution pattern. The redistribution pattern includes a signal redistribution pattern, a ground redistribution pattern, and a power redistribution pattern. A vertical distance between the chip pad and the signal redistribution pattern may be greater than a width of the signal redistribution pattern. | 2022-06-23 |
20220199530 | SEMICONDUCTOR DEVICE WITH BACKSIDE SPACER AND METHODS OF FORMING THE SAME - Semiconductor device and the manufacturing method thereof are disclosed. An exemplary semiconductor device comprises a dielectric layer formed over a power rail; a bottom semiconductor layer formed over the dielectric layer; a backside spacer formed along a sidewall of the bottom semiconductor layer; a conductive feature contacting a sidewall of the dielectric layer and a sidewall of the backside spacer; channel semiconductor layers over the bottom semiconductor layer, wherein the channel semiconductor layers are stacked up and separated from each other; a metal gate structure wrapping each of the channel semiconductor layers; and an epitaxial source/drain (S/D) feature contacting a sidewall of each of the channel semiconductor layers, wherein the epitaxial S/D feature contacts the conductive feature, and the conductive feature contacts the power rail. | 2022-06-23 |
20220199531 | MEMORY DEVICE AND FABRICATION METHOD THEREOF - A memory device includes a memory array, disposed on a substrate of a peripheral-circuit structure; a conductive plug, extending through the memory array and connected to the peripheral-circuit structure; and a conductive pad layer, disposed over the memory array and including a plurality of conductive pads spaced apart from each other. The conductive plug protrudes into a corresponding conductive pad of the plurality of conductive pads. | 2022-06-23 |
20220199532 | BIT LINE AND SOURCE LINE CONNECTIONS FOR A 3-DIMENSIONAL ARRAY OF MEMORY CIRCUITS - A conductor-filled via formed between an interconnection conductor layer and a buried contact above a planar surface of a semiconductor substrate, includes: (a) a first portion that extends from the interconnection conductor layer through a first isolation layer to a step in a staircase structure formed above the buried contacts, wherein (i) the step of the staircase structure is aligned to the buried contact along a first direction substantially normal to the planar surface of the semiconductor substrate, (ii) at the top of the step, the step comprises a bit line layer, a source line layer and a second isolation layer between the bit line layer and the source line layer, and (iii) the first portion electrically contacting the layer at the top of the step; and (b) a second portion extending from a portion of the step below the layer at the top of the step to the buried contact, wherein a spacer insulator lines sidewalls of the conductor-filled via. | 2022-06-23 |
20220199533 | SEMICONDUCTOR STORAGE DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor storage device according to an embodiment includes: a first stacked body including a plurality of first electrode layers and a plurality of first insulating layers that are alternately stacked on a substrate in a first direction perpendicular to the substrate; a plurality of semiconductor films penetrating the first stacked body in the first direction; a second stacked body including a plurality of second electrode layers and a plurality of second insulating layers that are alternately stacked on the first stacked body in the first direction; and a plurality of contact plugs penetrating the second stacked body in the first direction and separately connected to the respective plurality of semiconductor films and the respective plurality of second electrode layers. | 2022-06-23 |
20220199534 | SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES - A semiconductor device includes a substrate having an active region, a gate structure disposed on the active region, a source/drain region disposed in the active region at a side of the gate structure, a first interlayer insulating layer and a second interlayer insulating layer sequentially disposed on the gate structure and the source/drain region, a first contact plug connected to the source/drain region through the first interlayer insulating layer, a second contact plug connected to the gate structure through the first interlayer insulating layer and the second interlayer insulating layer, a first metal line disposed on the second interlayer insulating layer, and having a metal via disposed in the second interlayer insulating layer and connected to the first contact plug, and a second metal line disposed on the second interlayer insulating layer, and directly connected to the second contact plug. | 2022-06-23 |
20220199535 | MICROELECTRONIC STRUCTURES INCLUDING BRIDGES - Disclosed herein are microelectronic structures including bridges, as well as related assemblies and methods. In some embodiments, a microelectronic structure may include a substrate and a bridge. | 2022-06-23 |
20220199536 | MICROELECTRONIC STRUCTURES INCLUDING BRIDGES - Disclosed herein are microelectronic structures including bridges, as well as related assemblies and methods. In some embodiments, a microelectronic structure may include a substrate and a bridge. | 2022-06-23 |
20220199537 | POWER-FORWARDING BRIDGE FOR INTER-CHIP DATA SIGNAL TRANSFER - An integrated circuit (IC) package, comprising a substrate that comprises a bridge die embedded within a dielectric. A first die comprising a first input/output (I/O) transmitter and a second die comprising a second I/O receiver and electrically coupled to the bridge die. A first signal trace and a first power conductor are within the bridge die. The first signal trace and the first power conductor are electrically coupled to the first I/O transmitter and the second I/O receiver. The first signal trace is to carry a digital signal and the first power conductor to provide a voltage for the second I/O receiver to read the digital signal. | 2022-06-23 |
20220199538 | SEMICONDUCTOR PACKAGE STRUCTURE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor package structure and a method for manufacturing a semiconductor package structure are provided. The semiconductor package structure includes a lower conductive structure, a first semiconductor device and a second semiconductor device. The upper conductive structure is disposed on the lower conductive structure. The second semiconductor device is electrically connected to the first semiconductor device by a first path in the upper conductive structure. The lower conductive structure is electrically connected to the first semiconductor device through a second path in the upper conductive structure under the first path. | 2022-06-23 |
20220199539 | MICROELECTRONIC STRUCTURES INCLUDING BRIDGES - Disclosed herein are microelectronic structures including bridges, as well as related assemblies and methods. In some embodiments, a microelectronic structure may include a substrate and a bridge. | 2022-06-23 |
20220199540 | GUIDED VIAS IN MICROELECTRONIC STRUCTURES - Disclosed herein are guided vias in microelectronic structures. For example, a microelectronic structure may include a metallization layer including a conductive via in contact with a conductive line, wherein a center of a top surface of the conductive via is laterally offset from a center of a bottom surface of the conductive via. | 2022-06-23 |
20220199541 | Dual-sided Routing in 3D SiP Structure - A semiconductor package is fabricated by attaching a first component to a second component. The first component is assembled by forming a first redistribution structure over a substrate. A through via is then formed over the first redistribution structure, and a die is attached to the first redistribution structure active-side down. The second component includes a second redistribution structure, which is then attached to the through via. A molding compound is deposited between the first redistribution structure and the second redistribution structure and further around the sides of the second component. | 2022-06-23 |
20220199542 | ANTENNA STRUCTURE AND IMAGE DISPLAY DEVICE INCLUDING THE SAME - An antenna structure according to an embodiment of the present disclosure includes a passivation layer, an antenna unit at least partially embedded in an upper portion of the passivation layer, and an insulating layer disposed on a top surface of the passivation layer to cover the antenna unit. A spatial efficiency of the antenna structure is improved and a thickness of the image display device is reduced to improve a bending property. | 2022-06-23 |
20220199543 | ELECTRONIC SUBASSEMBLY AND ELECTRONIC ASSEMBLAGE - An electronic subassembly encompassing at least one carrier substrate, an electronic circuit being embodied on at least one carrier substrate surface. The electronic subassembly encompasses at least one mechanical connecting boss that is connected, in a substrate connection region, to at least one of the carrier substrate surfaces. The connecting boss, conversely, has, on a side facing away from the substrate connection region, a terminating boundary layer which is made of a metal oxide and which is embodied to furnish an adhesive bonding surface for an adhesive layer in order to constitute an adhesively bonded composite assemblage with a join participant. | 2022-06-23 |
20220199544 | CAP STRUCTURE FOR INTERCONNECT DIELECTRICS AND METHODS OF FABRICATION - An integrated circuit structure includes a first interconnect level including a first dielectric between a pair of interconnect structures, a second interconnect level above the first interconnect level. The second interconnect level includes a cap structure including a second dielectric on the first dielectric, the cap structure includes a top surface and a sidewall surface and a liner comprising a third dielectric on the top surface and on the sidewall surface. | 2022-06-23 |
20220199545 | Selective EMI Shielding Using Preformed Mask with Fang Design - A semiconductor device has a semiconductor package including a substrate comprising a land grid array. A component is disposed over the substrate. An encapsulant is deposited over the component. The land grid array remains outside the encapsulant. A fanged metal mask is disposed over the land grid array. A shielding layer is formed over the semiconductor package. The fanged metal mask is removed after forming the shielding layer. | 2022-06-23 |
20220199546 | SHIELD STRUCTURES IN MICROELECTRONIC ASSEMBLIES HAVING DIRECT BONDING - Microelectronic assemblies, and related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first microelectronic component, having a first surface and an opposing second surface including a first direct bonding region at the second surface with first metal contacts and a first dielectric material between adjacent ones of the first metal contacts; a second microelectronic component, having a first surface and an opposing second surface, including a second direct bonding region at the first surface with second metal contacts and a second dielectric material between adjacent ones of the second metal contacts, wherein the second microelectronic component is coupled to the first microelectronic component by the first and second direct bonding regions; and a shield structure in the first direct bonding dielectric material at least partially surrounding the one or more of the first metal contacts. | 2022-06-23 |
20220199547 | FAN-OUT WAFER-LEVEL PACKAGING (FOWLP) INTEGRATED CIRCUITS (ICs) EMPLOYING AN ELECTRO-MAGNETIC INTERFERENCE (EMI) SHIELD STRUCTURE IN UNUSED FAN-OUT AREA FOR EMI SHIELDING, AND RELATED FABRICATION METHODS - Fan-out wafer-level packaging (FOWLP) integrated circuits (ICs) employing electro-magnetic (EM) interference (EMI) shield structure in fan out area for EMI shielding, and related fabricating methods are disclosed. The IC includes a semiconductor die (“IC die”) that is bonded to the reconstituted carrier wafer such that a fan-out area is provided between adjacent IC dies to provide area for fan-out interconnects to provide additional die interconnections to the IC die. In exemplary aspects, the IC includes an EMI shield that includes vias formed in an un-used area in fan-out area adjacent to the IC die electrically that are otherwise unused for input/output (I/O) signal interconnects for coupling I/O signals to the IC die. The EMI shield is electrically coupled to a ground node of the IC die to provide an effective EMI shield to block or attenuate unwanted EM noise propagated from the IC die outside the IC. | 2022-06-23 |
20220199548 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR MODULE - A semiconductor device includes first and second members. In the first member, a first electronic circuit including a semiconductor element is formed. The second member is joined to an area of part of a first surface of the first member, and includes a second electronic circuit including a semiconductor element formed of a semiconductor material different from that of the semiconductor element of the first electronic circuit. An interlayer insulating film covers the second member and an area of the first surface of the first member to which the second member is not joined. An inter-member connection wire on the interlayer insulating film couples the first and second electronic circuits through an opening in the interlayer insulating film. A shield structure including a first metal pattern disposed on the interlayer insulating film shields a shielded circuit, which is part of the first electronic circuit, in terms of radio frequencies. | 2022-06-23 |
20220199549 | SEMICONDUCTOR PACKAGE - A semiconductor package including a first semiconductor chip having an upper surface, a lower surface that is opposite to the upper surface, and a sidewall between the upper surface and the lower surface; a capping insulation layer covering the upper surface and the sidewall of the first semiconductor chip; and a shielding layer on the capping insulation layer, wherein a lower portion of the capping insulation layer includes a laterally protruding capping protrusion contacting a lower surface of the shielding layer. | 2022-06-23 |
20220199550 | SEMICONDUCTOR DEVICE PACKAGE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device package and a method for manufacturing a semiconductor device package are provided. The semiconductor device package includes a carrier, a sensor module, a connector, and a stress buffer structure. The sensor module is disposed on the carrier. The connector is connected to the carrier. The stress buffer structure connects the connector to the sensor module. | 2022-06-23 |
20220199551 | STIFFENER AND SOCKET EMBEDDED METAL INSERT ARCHITECTURES FOR POWER DELIVERY - Embodiments disclosed herein include electronic packages with stiffeners. In an embodiment, a stiffener for an electronic package comprises a first layer, that is conductive, and a second layer over the first layer, where the second layer is insulative. In an embodiment, the stiffener further comprises a third layer over the second layer, where the third layer is conductive. In an embodiment, the stiffener further comprises a leg attached to the third layer, where the leg extends towards the first layer and is substantially coplanar with a surface of the first layer opposite from the second layer. | 2022-06-23 |
20220199552 | SEMICONDUCTOR DEVICE PACKAGE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device package and a method for manufacturing a semiconductor device package are provided. The semiconductor device package includes a substrate, a clip, and a support structure. The clip is disposed on the substrate. The clip includes a first portion and a second portion separated from each other by a slit. The support structure is above the substrate and supports the clip. The support structure has a first surface and a second surface facing the first surface, and the first surface and the second surface define a gap. | 2022-06-23 |
20220199553 | ENVIRONMENTALLY PROTECTED PHOTONIC INTEGRATED CIRCUIT - An environmentally protected photonic integrated circuit, PIC, including an indium phosphide-based substrate that is at least partially covered with an epitaxial semiconductor layer. The InP-based substrate and/or the epitaxial layer are covered with a layer stack comprising different non-semiconductor layers. At least a first layer of the layer stack is provided with a through-hole that is arranged at a predetermined location. The InP-based substrate or epitaxial layer being accessible via the through-hole. The PIC including a dielectric protective layer covering the layer stack thereby provides a mechanical coupling structure. The protective layer is configured to protect the PIC from environmental contaminants. An opto-electronic system including the PIC. | 2022-06-23 |
20220199554 | MULTI-DIE MEMORY DEVICE WITH PEAK CURRENT REDUCTION - A memory device including a substrate including a substrate contact pad. The memory device includes a first memory die including a first power supply contact pad electrically coupled to the substrate contact pad and a first power supply circuit on the first memory die. The first memory die further includes a first electrostatic discharge (ESD) power clamp contact pad electrically coupled to the substrate contact pad and a first ESD power clamp circuit on the first memory die. The memory device further includes a second memory die including a second power supply contact pad electrically coupled to the substrate contact pad and a second power supply circuit on the second memory die and a second ESD power clamp contact pad electrically coupled to a second ESD power clamp circuit on the second memory die, wherein the second ESD power clamp contact pad is electrically disconnected from the substrate contact. | 2022-06-23 |
20220199555 | ELECTRONIC DEVICE - An electronic device includes a substrate, a transistor, and a ring resonator. The transistor is over the substrate. The ring resonator is over the substrate and includes a conductive loop and an impedance matching element. The conductive loop overlaps with the transistor. The impedance matching element is on the conductive loop and electrically isolated from the transistor. | 2022-06-23 |
20220199556 | PACKAGE SYSTEM AND PACKAGE - In various aspects, a package system includes at least a first package and a second package arranged on a same side of the package carrier. Each of the first package and the second package comprises an antenna to transmit and/or receive radio frequency signals. A cover may be arranged at a distance over the first package and the second package at the same side of the package carrier as the first package and the second package. The cover comprises at least one conductive element forming a predefined pattern on a side of the cover facing the first package and the second package. The predefined pattern is configured as a frequency selective surface. The package system further includes a radio frequency signal interface wirelessly connecting the antennas of the first package and the second package. The radio frequency signal interface comprises the at least one conductive element. | 2022-06-23 |
20220199557 | SEMICONDUCTOR DEVICE - In a semiconductor device, a first member having a first surface includes a plurality of circuit blocks disposed in an inner region of the first surface when the first surface is viewed in plan. The second member is joined to the first surface of the first member in surface contact with the first surface. The second member includes a plurality of first transistors that are connected in parallel to each other and form a first amplifier circuit. A conductive protrusion protrudes from the second member on an opposite side to the first member. The first transistors are disposed in a region not overlapping any of the circuit blocks in the first member in a plan view. | 2022-06-23 |
20220199558 | SEMICONDUCTOR DEVICE - In a semiconductor device, when a first surface of a first member is viewed in plan, at least one switch circuit including a switch is disposed within the first surface. A second member is joined to the first surface of the first member in surface contact with the first surface. The second member includes a plurality of transistors that are made of a compound semiconductor and form a radio-frequency amplifier circuit. A first conductive protrusion protrudes from the second member on an opposite side to the first member. The first member includes a circuit element disposed between the radio-frequency amplifier circuit and the at least one switch circuit in a plan view, the circuit element not forming the switch circuit. | 2022-06-23 |
20220199559 | SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING SEMICONDUCTOR STRUCTURE - A semiconductor package and a method for manufacturing a semiconductor package are provided. The semiconductor package includes a first semiconductor device, a second semiconductor device, and an alignment material. The first semiconductor device has a first bonding layer, and the first bonding layer includes a first bond pad contacting an organic dielectric material. The second semiconductor device has a second bonding layer, and the second bonding layer includes a second bond pad contacting the organic dielectric material. The alignment material is between the first bonding layer and the second bonding layer. | 2022-06-23 |
20220199560 | BONDED STRUCTURES WITHOUT INTERVENING ADHESIVE - A bonded structure can include a first reconstituted element comprising a first element and having a first side comprising a first bonding surface and a second side opposite the first side. The first reconstituted element can comprise a first protective material disposed about a first sidewall surface of the first element. The bonded structure can comprise a second reconstituted element comprising a second element and having a first side comprising a second bonding surface and a second side opposite the first side. The first reconstituted element can comprise a second protective material disposed about a second sidewall surface of the second element. The second bonding surface of the first side of the second reconstituted element can be directly bonded to the first bonding surface of the first side of the first reconstituted element without an intervening adhesive along a bonding interface. | 2022-06-23 |
20220199561 | SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME - A semiconductor package including a first die, through electrodes penetrating the first die, a first pad on a top surface of the first die and coupled to a through electrode, a second die on the first die, a second pad on a bottom surface of the second die, a first connection terminal connecting the first pad to the second pad, and an insulating layer that fills a region between the first die and the second die and encloses the first connection terminal. The first connection terminal includes an intermetallic compound made of solder material and metallic material of the first and second pads. A concentration of the metallic material in the first connection terminal is substantially constant regardless of a distance from the first pad or the second pad. | 2022-06-23 |
20220199562 | ASSEMBLY OF 2XD MODULE USING HIGH DENSITY INTERCONNECT BRIDGES - Embodiments disclosed herein include electronic package and methods of forming such packages. In an embodiment, an electronic package comprises a mold layer and a first die embedded in the mold layer. In an embodiment, the first die comprises first pads at a first pitch and second pads at a second pitch. In an embodiment, the electronic package further comprises a second die embedded in the mold layer, where the second die comprises third pads at the first pitch and fourth pads at the second pitch. In an embodiment, a bridge die is embedded in the mold layer, and the bridge die electrically couples the second pads to the fourth pads. | 2022-06-23 |
20220199563 | HIGH THERMAL DISSIPATION, PACKAGED ELECTRONIC DEVICE AND MANUFACTURING PROCESS THEREOF - The packaged power electronic device has a bearing structure including a base section and a transverse section extending transversely to the base section. A die is bonded to the base section of the bearing structure and has a first terminal on a first main face and a second and a third terminal on a second main face. A package of insulating material embeds the semiconductor die, the second terminal, the third terminal and at least partially the carrying base. A first, a second and a third outer connection region are electrically coupled to the first, the second and the third terminals of the die, respectively, are laterally surrounded by the package and face the second main surface of the package. The transverse section of the bearing structure extends from the base section towards the second main surface of the package and has a higher height with respect to the die. | 2022-06-23 |
20220199564 | CHIP-ON-LEAD SEMICONDUCTOR DEVICE, AND CORRESPONDING METHOD OF MANUFACTURING CHIP-ON-LEAD SEMICONDUCTOR DEVICES - A semiconductor device includes a support substrate with leads arranged therearound, a semiconductor die on the support substrate, and a layer of laser-activatable material molded onto the die and the leads. The leads include proximal portions facing towards the support substrate and distal portions facing away from the support substrate. The semiconductor die includes bonding pads at a front surface thereof which is opposed to the support substrate, and is arranged onto the proximal portions of the leads. The semiconductor device has electrically-conductive formations laser-structured at selected locations of the laser-activatable material. The electrically-conductive formations include first vias extending between the bonding pads and a front surface of the laser-activatable material, second vias extending between the distal portions of the leads and the front surface of the laser-activatable material, and lines extending at the front surface of the laser-activatable material and connecting selected first vias to selected second vias. | 2022-06-23 |
20220199565 | ANISOTROPIC ELECTRICALLY CONDUCTIVE FILM - An anisotropic electrically conductive film has a structure wherein the electrically conductive particles are disposed on or near the surface of an electrically insulating adhesive base layer, or a structure wherein an electrically insulating adhesive base layer and an electrically insulating adhesive cover layer are laminated together and the electrically conductive particles are disposed near the interface therebetween. Electrically conductive particle groups configured from two or more electrically conductive particles are disposed in a lattice point region of a planar lattice pattern. A preferred lattice point region is a circle centered on a lattice point. A radius of the circle is not less than two times and not more than seven times the average particle diameter of the electrically conductive particles. | 2022-06-23 |
20220199566 | SEMICONDUCTOR DEVICE AND BONDING METHOD - Semiconductor device A | 2022-06-23 |
20220199567 | SEMICONDUCTOR PACKAGE - A semiconductor package includes a substrate that includes a bonding pad, a first semiconductor chip disposed on the substrate, a second semiconductor chip disposed on a top surface of the first semiconductor chip that is opposite to the substrate, a chip pad disposed on the top surface of the first semiconductor chip, and a bonding wire that connects the chip pad to the bonding pad. The bonding wire includes a first upward protrusion and a second upward protrusion that are convexly curved in a direction away from the substrate. The second semiconductor chip has a first side surface between the first upward protrusion and the second upward protrusion. | 2022-06-23 |
20220199568 | MODULE - A module includes: a board having a first surface; a first component and a second component mounted on the first surface; and a wire disposed to extend across both the first component and the second component. The wire has one end and the other end that are both connected to the first surface, and the wire is grounded. As seen in a direction perpendicular to the first surface, the first component is located closer to the one end than the second component, a portion of the wire that is furthest from the first surface is located closer to the one end than to the other end, and the second component has an upper surface located lower than an upper surface of the first component. | 2022-06-23 |
20220199569 | CHEMICAL BONDING METHOD AND JOINED STRUCTURE - A bonded structure includes a first substrate; a second substrate placed opposite to the first substrate; an intermediate layer provided between the first substrate and the second substrate and including a first oxide thin film layered on the first substrate and a second oxide thin film layered on the second substrate; either or both of the first oxide thin film and the second oxide thin film of the intermediate layer being formed of oxide thin films having increased defects; and an interface between the first oxide thin film and the second oxide thin film=being bonded by chemical bonding, and the interface comprising a low-density portion whose density is lower than that of the two oxide thin films. | 2022-06-23 |
20220199570 | METHODS OF FORMING WIRE INTERCONNECT STRUCTURES AND RELATED WIRE BONDING TOOLS - A method of forming a wire interconnect structure includes the steps of: (a) forming a wire bond at a bonding location on a substrate using a wire bonding tool; (b) extending a length of wire, continuous with the wire bond, to a position above the wire bond; (c) moving the wire bonding tool to contact the length of wire, at a position along the length of wire, to partially sever the length of wire at the position along the length of wire; and (d) separating the length of wire from a wire supply at the position along the length of wire, thereby providing a wire interconnect structure bonded to the bonding location. | 2022-06-23 |
20220199571 | APPARATUS AND METHODS FOR TOOL MARK FREE STITCH BONDING - Apparatus and method for tool mark free stich bonding. In some embodiments, a method for wire bonding can include feeding a wire through a capillary tip and attaching a first end of the wire to a first location, thereby forming a ball bond. The method can further include moving the capillary tip towards a second location while the wire feeds out of the capillary tip. The method can further include attaching a second end of the wire to the second location while preventing contact between the capillary tip and the second location, thereby forming a stitch bond without a tool mark at the second location. | 2022-06-23 |
20220199572 | PROCESS FOR COLLECTIVELY BENDING MICROELECTRONIC COMPONENTS - The invention relates to a process for collectively bending microelectronic components comprising transferring microelectronic components ( | 2022-06-23 |
20220199573 | MODULAR LOW LATENCY ELECTRICAL SEQUENCE FOR DIE-TO-DIE INTERFACE - A system comprising a first die comprising a first receiver and a first transmitter to couple to a link between the first die and a second die comprising a second receiver and a second transmitter; and circuitry to place the first receiver and first transmitter into isolation modes; provide a first signal to the second die to request placement of the second transmitter into a deisolation mode; place the first receiver and first transmitter into deisolation modes responsive to a second signal from the second die; and provide a third signal to the second die to request placement of the second receiver into a deisolation mode. | 2022-06-23 |
20220199574 | MICROELECTRONIC STRUCTURES INCLUDING BRIDGES - Disclosed herein are microelectronic structures including bridges, as well as related assemblies and methods. In some embodiments, a microelectronic structure may include a substrate and a bridge. | 2022-06-23 |
20220199575 | MICROELECTRONIC STRUCTURES INCLUDING BRIDGES - Disclosed herein are microelectronic structures including bridges, as well as related assemblies and methods. In some embodiments, a microelectronic structure may include a substrate and a bridge. | 2022-06-23 |
20220199576 | TILED IMAGE SENSOR - The present invention relates to a tiled image sensor. The tiled image sensor includes: a substrate on which conductive wiring is formed; and a plurality of image sensor dies arranged on the substrate to be spaced apart from each other by a first distance and electrically connected to the conductive wiring. The image sensor die includes: a plurality of light receiving sub-regions formed to be spaced apart from each other by a second distance; a peripheral circuit that is formed between the plurality of light receiving sub-regions, converts pixel current generated for each pixel included in the plurality of light receiving sub-regions into image data, and outputs the image data in block units; and a contact pad, the contact pad formed on a surface of the image sensor die to electrically connect the image sensor die to the substrate. | 2022-06-23 |
20220199577 | SEMICONDUCTOR PACKAGE - A semiconductor package includes a base substrate and an interposer substrate. The interposer substrate includes a semiconductor substrate, a first passivation layer, a wiring region, a through via penetrating through the semiconductor substrate and the first passivation layer, and a second passivation layer covering at least a portion of the first passivation layer and having an opening exposing a lower surface of the through via. The semiconductor package further includes a conductive pillar extending from the opening of the second passivation layer; and a conductive bump disposed between the conductive pillar and the base substrate. The opening of the second passivation layer has inclined side surfaces such that a width of the opening decreases towards the first passivation layer, and side surfaces of the conductive pillar are positioned to overlap the inclined side surfaces of the second passivation layer in a vertical direction. | 2022-06-23 |
20220199578 | SEMICONDUCTOR DEVICE - A semiconductor device includes a first insulating substrate and a first semiconductor element joined to the first insulating substrate through the first conductive spacer. The first insulating substrate includes a first insulating layer and a first inner conductive layer disposed at a side of the first insulating layer. The first inner conductive layer includes a surface having a first region and a second region. The second region surrounds the first region and has larger surface roughness than the first region. The first conductive spacer is joined to the first region of the first inner conductive layer through a first junction layer. | 2022-06-23 |
20220199579 | 3D PACKAGE CONFIGURATION - A novel 3D package configuration is provided by stacking a plurality of semiconductor package units or a folded flexible circuit board structure on a lead frame and electrically connected therewith based on the foldable characteristics of the flexible circuit board, and the high temperature resistance of the flexible circuit board which is suitable for insulating layer process, metal layer process, photolithography process, etching and development process, to make conventional semiconductor dies of various functions be bonded on one die and/or two side of a flexible circuit board and electrically connected therewith in advance. | 2022-06-23 |
20220199580 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device according to the present embodiment includes a plurality of stacked first semiconductor chips. First columnar electrodes are connected to electrode pads of the first semiconductor chips and extend in a stacking direction of the first semiconductor chips. A plurality of second semiconductor chips are stacked above the first semiconductor chips. Second columnar electrodes are connected to electrode pads of the second semiconductor chips and extend in a stacking direction of the second semiconductor chips. Third columnar electrodes are respectively connected to tops of the first columnar electrodes and extend in the stacking direction of the second semiconductor chips. A resin layer covers the first semiconductor chips, the second semiconductor chips, the second columnar electrodes, and the third columnar electrodes and exposes tops of the second and third columnar electrodes. | 2022-06-23 |
20220199581 | MULTI-DIE PACKAGE STRUCTURE AND MULTI-DIE CO-PACKING METHOD - A multi-die package structure with an embedded die embedded in a substrate, a high flip chip die mounted above the substrate, and a low flip chip die placed below the substrate. The package is compact and low cost. | 2022-06-23 |
20220199582 | STACKED DIE PACKAGE INCLUDING A MULTI-CONTACT INTERCONNECT - The present disclosure is directed to a package that includes a plurality of die that are stacked on each other. The plurality of die are within a first resin and conductive layer is on the first resin. The conductive layer is coupled between ones of first conductive vias extending into the first resin to corresponding ones of the plurality of die. The conductive layer and the first conductive vias couple ones of the plurality of die to each other. A second conductive via extends into the first resin to a contact pad of the substrate, and the conductive layer is coupled to the second conductive via coupling ones of the plurality of die to the contact pad of the substrate. A second resin is on and covers the first resin and the conductive layer on the first resin. In some embodiments, the first resin includes a plurality of steps (e.g., a stepped structure). In some embodiments, the first resin includes inclined surfaces (e.g., sloped surfaces). | 2022-06-23 |