25th week of 2010 patent applcation highlights part 18 |
Patent application number | Title | Published |
20100155793 | SELF ALIGNED FIELD EFFECT TRANSISTOR STRUCTURE - Provided is a self aligned filed effect transistor structure. The self aligned field effect transistor structure includes: an active region on a substrate; a U-shaped gate insulation pattern on the active region; and a gate electrode self-aligned by the gate insulation pattern and disposed in an inner space of the gate insulation pattern. | 2010-06-24 |
20100155794 | REWORK METHOD OF METAL STRUCTURE OF SEMICONDUCTOR DEVICE - A rework method of a metal structure and devices thereof. A rework method may include forming a first metal layer over an insulating layer having a contact plug, a metal interconnection layer over a first metal layer and/or a second metal layer over a metal interconnection layer. A rework method may include performing a first wet etch process to remove first and/or second metal layers, except for a portion below a metal interconnection layer, removing a metal interconnection layer through a second wet etch process and/or planarizing a remaining portion of a first metal layer and/or a surface of an insulating layer through a first planarization process. An increase of a size of a contact hole, for example due to an over exposure of a contact hole, may be minimized. | 2010-06-24 |
20100155795 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device according to an embodiment includes: a substrate on which a source/drain region is formed; a gate oxide that includes a first oxide formed on the substrate and implanted with fluorine impurity, and a second oxide formed on the first oxide; a gate electrode that is formed on the gate oxide; and a spacer that is formed on a side of the gate electrode. | 2010-06-24 |
20100155796 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a semiconductor substrate, a back side drawn electrode formed by embedding a first conductive material in a contact hole penetrating the semiconductor substrate through an insulating film formed to include a uniform thickness, used also as an alignment mark, and configured to draw out an electrode to the back side of the semiconductor substrate. The device further includes a pad provided on the back side of the semiconductor substrate, and connected to the back side drawn electrode. | 2010-06-24 |
20100155797 | CMOS image sensors - CMOS image sensors and methods of manufacturing the same are provided, the CMOS image sensors include an epitaxial layer, a photodiode, a transfer transistor, CMOS transistors, first metal wirings and a second metal wiring formed on a substrate. The substrate may have a photodiode region, a floating diffusion region, an active pixel sensor (APS) array circuit region and a peripheral circuit region. The photodiode may be formed on the epitaxial layer in the photodiode region. The transfer transistor may be formed on the epitaxial layer in the floating diffusion region. The CMOS transistors may be formed on the epitaxial layer in the APS array circuit region and the peripheral circuit region. The first metal wirings may be formed over the photodiode region. The second metal wiring may be formed on one of the first metal wirings. The second metal wiring may be located higher than the first metal wirings. | 2010-06-24 |
20100155798 | SEMICONDUCTOR MEMORY DEVICE INCLUDING CELL ISOLATION STRUCTURE USING INACTIVE TRANSISTORS - Disclosed herein is a semiconductor memory device including floating body cells. The semiconductor memory device includes memory cell active regions formed on a Silicon-On Isolator (SOI) semiconductor substrate, a plurality of floating body cell transistors formed in the memory cell active regions, and inactive transistors for providing cell isolation that are formed between the plurality of floating body cell transistors. Here, the inactive transistors for providing cell isolation are controlled so that they always are in an OFF state while the semiconductor memory device is operating. | 2010-06-24 |
20100155799 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A first MOS transistor includes, as a first impurity region, a pair of first source/drain regions including first portions formed in a semiconductor substrate and second portions formed so as to project upward from the first portions. A second MOS transistor includes a pair of second source/drain regions including second impurity regions formed in the semiconductor substrate, third impurity regions located in contact with the second impurity regions so as to project upward from the semiconductor substrate, and fourth impurity regions located on the third impurity regions. The concentration of impurities in the third impurity regions is lower than that of impurities in the fourth impurity regions. The concentration of impurities in the first impurity regions is lower than that of impurities in the second impurity regions. The first, the second, the third and the fourth impurity regions are same conductivity type. | 2010-06-24 |
20100155800 | Creating Integrated Circuit Capacitance from Gate Array Structures - Techniques for using gate arrays to create capacitive structures within an integrated circuit are disclosed. Embodiments comprise placing a gate array of P-type field effect transistors (P-fets) and N-type field effect transistors (N-fets) in an integrated circuit design, coupling drains and sources for one or more P-fets and gates for one or more N-fets to a power supply ground, and coupling gates for the one or more P-fets and the drains and sources for one or more N-fets to a positive voltage of the power supply. In some embodiments, source-to-drain leakage current for capacitive apparatuses of P-fets and N-fets are minimized by biasing one or more P-fets and one or more N-fets to the positive voltage and the ground, respectively. In other embodiments, the capacitive structures may be implemented using fusible elements to isolate the capacitive structures in case of shorts. | 2010-06-24 |
20100155801 | Integrated circuit, 1T-1C embedded memory cell containing same, and method of manufacturing 1T-1C memory cell for embedded memory application - An integrated circuit includes a semiconducting substrate ( | 2010-06-24 |
20100155802 | Semiconductor device and method of forming semiconductor device - A method of forming a semiconductor device includes the following processes. First grooves are formed in a first insulating layer. A conductive material is formed which fills in each of the first grooves. A first mask is formed over the first insulating layer and the conductive material. The first mask has openings that define second grooves crossing the first grooves in plan view. The second grooves are formed in the first insulating layer and the conductive material by using the first mask. A plurality of conductive pillars are formed by removing a part of the conductive material in each of the first grooves. | 2010-06-24 |
20100155803 | METHOD AND STRUCTURE FOR INTEGRATING CAPACITOR-LESS MEMORY CELL WITH LOGIC - Methods for fabricating integrated circuits include fabricating a logic device on a substrate, forming an intermediate semiconductor substrate on a surface of the logic device, and fabricating a capacitor-less memory cell on the intermediate semiconductor substrate. Integrated circuits with capacitor-less memory cells formed on a surface of a logic device are also disclosed, as are multi-core microprocessors including such integrated circuits. | 2010-06-24 |
20100155804 | Shallow Trench Isolation For A Memory - In some embodiments, a gate structure with a spacer on its side may be used as a mask to form self-aligned trenches in a microelectronic memory, such as a flash memory. A first portion of the gate structure may be used to form the mask, together with sidewall spacers, in some embodiments. Then, after forming the shallow trench isolations, a second portion of the gate structure may be added to form a mushroom shaped gate structure. | 2010-06-24 |
20100155805 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND FABRICATING THE SAME - There is provided a nonvolatile semiconductor memory device, including, a tunnel insulator, a floating gate electrode including a first floating gate electrode and a second floating gate electrode being constituted with a nondegenerate state semiconductor, an intergate insulating film formed to cover at least continuously an upper and a portion of a side surface of the floating gate electrode, and a control gate electrode in order, and an isolation insulating film, a lower portion of the isolation insulating film being embedded in the semiconductor substrate in both sides of the floating gate electrode along a channel width direction, an upper portion of the isolation insulating film contacting with a side surface of the first floating gate electrode and protruding to a level between an upper surface of the semiconductor substrate and an upper surface of the first floating gate electrode. | 2010-06-24 |
20100155806 | SEMICONDUCTOR DEVICE - A semiconductor device includes an active zone doped according to a first type; a drain zone formed in the active zone and doped according to a second type; a source zone formed in the active zone and doped according to the second type; an insulated gate zone separated from the active zone by an insulating layer; a deep well, doped according to the second type such that the active zone is located between the gate zone and the well; a floating gate zone formed in the active zone under a space existing between the drain zone and the source zone, the floating gate zone including defects introducing deep levels in the bandgap of the semiconductor material, the deep levels being suited to trap carriers corresponding to the first type such that a charge state of the floating gate zone is modified and a drain source current varies due to the presence of a supplementary potential on the floating gate zone, a concentration of defects in the floating gate zone being strictly greater than 10 | 2010-06-24 |
20100155807 | Apparatus and methods for improved flash cell characteristics - Embodiments of an apparatus and methods for providing improved flash memory cell characteristics are generally described herein. Other embodiments may be described and claimed. | 2010-06-24 |
20100155808 | SEMICONDUCTOR MEMORY, SEMICONDUCTOR MEMORY SYSTEM USING THE MEMORY, AND METHOD FOR MANUFACTURING QUANTUM DOT USED IN SEMICONDUCTOR MEMORY - A semiconductor memory has a composite floating structure in which quantum dots composed of Si and coated with a Si oxide thin film are deposited on an insulating film formed on a semiconductor substrate, quantum dots coated with a high-dielectric insulating film are deposited on the quantum dots, and quantum dots composed of Si and coated with a high-dielectric insulating film are further deposited. Each of the quantum dots includes a core layer and a clad layer which covers the core layer. The electron occupied level in the core layer is lower than that in the clad layer. | 2010-06-24 |
20100155809 | SEMICONDUCTOR DEVICE OF COMMON SOURCE STRUCTURE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE OF COMMON SOURCE STRUCTURE - A semiconductor device having a common source structure and method of manufacturing the same are provided. In one embodiment, the method includes: forming a plurality of gate lines on a semiconductor substrate, each constituted by a floating gate, a dielectric layer, and a control gate having a line form; forming a first dielectric layer on the semiconductor substrate including the gate line; forming a trench having the line form in the first dielectric layer, wherein the trench exposes the semiconductor substrate between the gate lines; and forming a common source in the trench. According to an embodiment, the common source is implemented as a poly line in the trench. Therefore, etching the substrate to provide a trench for a common source can be excluded. Accordingly, it is possible to inhibit the common source from being opened due to a remaining material in a trench, and reduce damage to the semiconductor substrate. | 2010-06-24 |
20100155810 | MULTI-LAYER NONVOLATILE MEMORY DEVICES HAVING VERTICAL CHARGE STORAGE REGIONS - Some embodiments of the present invention provide nonvolatile memory devices including a plurality of intergate insulating patterns and a plurality of cell gate patterns that are alternately and vertically stacked on a substrate, an active pattern disposed on the substrate, the active pattern extending upwardly along sidewalls of the intergate insulating patterns and the cell gate patterns, a plurality of charge storage patterns disposed between the plurality of cell gate patterns and the active pattern, respectively, the plurality of the charge storage patterns being separated from each other, tunnel insulating patterns disposed between the plurality of cell gate patterns and the active pattern, respectively, and the tunnel insulating patterns extending to be directly connected to each other and a plurality of blocking insulating patterns disposed between the plurality of cell gate patterns and the plurality of charge storage patterns, respectively. A sidewall of the cell gate pattern may be recessed laterally so that an undercut region is defined and the charge storage pattern is disposed in the undercut region. | 2010-06-24 |
20100155811 | SEMICONDUCTOR DEVICE, METHOD OF FABRICATING THE SAME AND FLASH MEMORY DEVICE - A semiconductor device includes a semiconductor substrate, a gate formed over the semiconductor substrate, a source region formed in the semiconductor substrate at one side of the gate, a drain region formed in the semiconductor substrate at another side of the gate, and a channel region formed between the source region and the drain region, the channel region including a first channel region having a first threshold voltage and a second channel region having a second threshold voltage higher than the first threshold voltage. Accordingly, the semiconductor device has two channel regions having different threshold voltages. | 2010-06-24 |
20100155812 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A non-volatile memory of a semiconductor device has a tunnel insulation film provided on the active area; a floating gate electrode provided on the tunnel insulation film; a control gate electrode provided over the floating gate electrode; and an inter-electrode insulation film provided between the floating gate electrode and the control gate electrode, wherein, in a section of the non-volatile memory cell in a channel width direction, a dimension of a top face of the active area in the channel width direction is equal to or less than a dimension of a top face of the tunnel insulation film in the channel width direction, and the dimension of the top face of the tunnel insulation film in the channel width direction is less than a dimension of a bottom face of the floating gate electrode in the channel width direction. | 2010-06-24 |
20100155813 | SEMICONDUCTOR MEMORY DEVICE HAVING STACK GATE STRUCTURE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor memory device includes select transistors, cell transistors, and cell units. The select transistors formed on a substrate and include first electrodes. The cell transistors include second electrodes with a charge storage layer and a control. The cell units including a plurality of the cell transistors connected together in series between the two select transistors. A distance between the first electrodes and a distance between the first electrodes which is adjacent to the second electrodes and adjacent second electrodes are each at least double a distance between second electrodes. A surface of the substrate between second electrodes is flush with the surface of the substrate between the first electrode and the adjacent second electrodes. The surface of the substrate between the first electrodes is positioned lower than the surface of the substrate between the first electrodes and the second electrodes. | 2010-06-24 |
20100155814 | EEPROM ARRAY WITH WELL CONTACTS - A semiconductor integrated circuit device includes a cell well, a memory cell array formed on the cell well and having a memory cell area and cell well contact area, first wiring bodies arranged in the memory cell area, and second wiring bodies arranged in the cell well contact area. The layout pattern of the second wiring bodies is the same as the layout pattern of the first wiring bodies. The cell well contact area comprises cell well contacts that have the same dopant type as the cell well and that function as source/drain regions of dummy transistors formed in the cell well contact area. | 2010-06-24 |
20100155815 | AMMONIA PRE-TREATMENT IN THE FABRICATION OF A MEMORY CELL - A method of manufacturing a memory cell | 2010-06-24 |
20100155816 | HTO OFFSET AND BL TRENCH PROCESS FOR MEMORY DEVICE TO IMPROVE DEVICE PERFORMANCE - Memory devices having an increased effective channel length and/or improved TPD characteristics, and methods of making the memory devices are provided. The memory devices contain two or more memory cells on a semiconductor substrate and bit line dielectrics between the memory cells. The bit line dielectrics can extend into the semiconductor. The memory cell contains a charge trapping dielectric stack, a poly gate, a pair of pocket implant regions, and a pair of bit lines. The bit line can be formed by an implant process at a higher energy level and/or a higher concentration of dopants without suffering device short channel roll off issues because spacers at bit line sidewalls constrain the implant in narrower implant regions. | 2010-06-24 |
20100155817 | HTO OFFSET FOR LONG LEFFECTIVE, BETTER DEVICE PERFORMANCE - Memory devices having an increased effective channel length and/or improved TPD characteristics, and methods of making the memory devices are provided. The memory devices contain two or more memory cells on a semiconductor substrate and bit line dielectrics between the memory cells. The memory cell contains a charge trapping dielectric stack, a poly gate, a pair of pocket implant regions, and a pair of bit lines. The bit line can be formed by an implant process at a higher energy level and/or a higher concentration of dopants without suffering device short channel roll off issues because spacers at bit line sidewalls constrain the implant in narrower implant regions. | 2010-06-24 |
20100155818 | VERTICAL CHANNEL TYPE NONVOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - A method for fabricating, a vertical channel type nonvolatile memory device includes: alternately forming a plurality of sacrificial layers and a plurality of interlayer dielectric layers over a semiconductor substrate; etching the sacrificial layers and the interlayer dielectric layers to form a plurality of first openings for channel each of which exposes the substrate; filling the first openings to form a plurality of channels protruding from the semiconductor substrate; etching the sacrificial layers and the interlayer dielectric layers to form second openings for removal of the sacrificial layers between the channels; exposing sidewalls of the channels by removing the sacrificial layers exposed by the second openings; and forming a tunnel insulation layer, a charge trap layer, a charge blocking layer, and a conductive layer for gate electrode on the exposed sidewalls of the channels. | 2010-06-24 |
20100155819 | METHOD OF FABRICATING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - A method of fabricating a semiconductor device, includes forming an element isolation trench by processing a silicon substrate and a film to be processed, and filling the element isolation trench with an insulating film by a thermal CVD method. The thermal CVD method in filling the trench is executed under a film forming condition that the insulating film filling a part of the trench that is level with or is located lower than an upper surface of the silicon substrate has a porosity set so as to be not less than 5% and that the insulating film filling a part of the trench located higher than the upper surface of the silicon substrate has a lower deposition rate than the insulating film filling said part of the trench that is level with or is located lower than the upper surface of the silicon substrate. | 2010-06-24 |
20100155820 | Flash memory device and manufacturing method of the same - A flash memory device may include a device isolation layer and an active area formed over a semiconductor substrate, a memory gate formed over the active area, and a control gate formed over the semiconductor substrate including the memory gate, wherein the active area, where a source contact is to be formed, has the same interval spacing as a bit line, and a common source line area, where the source contact is to be formed, has an impurity area connecting neighboring active areas. | 2010-06-24 |
20100155821 | STACKED NON-VOLATILE MEMORY DEVICE AND METHODS FOR FABRICATING THE SAME - A stacked non-volatile memory device comprises a plurality of bit line and word line layers stacked on top of each other. The bit line layers comprise a plurality of bit lines that can be formed using advanced processing techniques making fabrication of the device efficient and cost effective. The device can be configured for NAND operation. | 2010-06-24 |
20100155822 | SEMICONDUCTOR MEMORY DEVICE WITH BIT LINE OF SMALL RESISTANCE AND MANUFACTURING METHOD THEREOF - A reduction of a resistance of a bit line of a memory cell array and a reduction of a forming area of the memory cell array are planed. | 2010-06-24 |
20100155823 | DEPLETION MODE BANDGAP ENGINEERED MEMORY - Memory cells comprising: a semiconductor substrate having a source region and a drain region disposed below a surface of the substrate and separated by a channel region; a tunnel dielectric structure disposed above the channel region, the tunnel dielectric structure comprising at least one layer having a hole-tunneling barrier height; a charge storage layer disposed above the tunnel dielectric structure; an insulating layer disposed above the charge storage layer; and a gate electrode disposed above the insulating layer are described along with arrays and methods of operation. | 2010-06-24 |
20100155824 | NANOCRYSTAL MEMORY WITH DIFFERENTIAL ENERGY BANDS AND METHOD OF FORMATION - A method of making a semiconductor device using a semiconductor substrate includes forming a first insulating layer having a first band energy over the semiconductor substrate. A first semiconductor layer having a second band energy is formed on the first insulating layer. The first semiconductor layer is annealed to form a plurality of first charge retainer globules from the first semiconductor layer. A first protective film is formed over each charge retainer globule of the plurality of first charge retainer globules. A second semiconductor layer is formed having a third band energy over the plurality of first charge retainer globules. The second semiconductor layer is annealed to form a plurality of storage globules from the second semiconductor layer over the plurality of first charge retainer globules. A magnitude of the second band energy is between a magnitude of the first band energy and a magnitude of the third band energy. | 2010-06-24 |
20100155825 | TRANSISTOR DEVICES WITH NANO-CRYSTAL GATE STRUCTURES - Embodiments of non-volatile semiconductor devices include a substrate having therein a source region and a drain region separated by a channel region extending to a first surface of the substrate, and a multilayered gate structure containing nano-crystals located above the channel region. The gate structure comprises a gate dielectric substantially in contact with the channel region, spaced-apart nano-crystals disposed in the gate dielectric, one or more impurity blocking layers overlying the gate dielectric, and a gate conductor layer overlying the one more impurity blocking layers. The blocking layer nearest the gate conductor can be used to adjust the threshold voltage of the device and/or retard dopant out-diffusion from the gate conductor layer. | 2010-06-24 |
20100155826 | Non-volatile memory device and method of fabricating the same - Provided are a non-volatile memory device and a method of fabricating the same. The non-volatile memory device may include a substrate and a plurality of semiconductor pillars on the substrate. A plurality of control gate electrodes may be stacked on the substrate and intersecting the plurality of semiconductor pillars. A plurality of dummy electrodes may be stacked adjacent to the plurality of control gate electrodes on the substrate, the plurality of dummy electrodes being spaced apart from the plurality of control gate electrodes. A plurality of via plugs may be connected to the plurality of control gate electrodes. A plurality of wordlines may be on the plurality of via plugs. Each of the plurality of via plugs may penetrate a corresponding one of the plurality of control gate electrodes and at least one of the plurality of dummy electrodes. | 2010-06-24 |
20100155827 | Semiconductor device having a multi-channel type MOS transistor - In a method of manufacturing a semiconductor device, an active channel pattern is formed on a substrate. The active channel pattern includes preliminary gate patterns and single crystalline silicon patterns that are alternately stacked with each other. A source/drain layer is formed on a sidewall of the active channel pattern. Mask pattern structures including a gate trench are formed on the active channel pattern and the source/drain layer. The patterns are selectively etched to form tunnels. The gate trench is then filled with a gate electrode. The gate electrode surrounds the active channel pattern. The gate electrode is protruded from the active channel pattern. The mask pattern structures are then removed. Impurities are implanted into the source/drain regions to form source/drain regions. A silicidation process is carried out on the source/drain regions to form a metal silicide layer, thereby completing a semiconductor device having a MOS transistor. | 2010-06-24 |
20100155828 | FIELD-EFFECT SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME - A semiconductor device comprises a semiconductor layer, a body region of a first conductivity type formed in the semiconductor layer and extending from a first surface of the semiconductor layer, a first region of a second conductivity type formed in the body region, and a second region of the first conductivity type formed in the body region. The first region extends from the first surface of the semiconductor layer and provides a current electrode region of the semiconductor device. The second region surrounds the first region. The doping concentration of the first conductivity type in the second region is greater than a doping concentration of the first conductivity type in the body region. | 2010-06-24 |
20100155829 | DEVICE FOR PROTECTING SEMICONDUCTOR DEVICE FROM ELECTROSTATIC DISCHARGE AND METHOD FOR FABRICATING THE SAME - A device for protecting a semiconductor device from electrostatic discharge may include a high voltage first conductivity type well formed in a semiconductor substrate. A first stack region may have a first conductivity type drift region, and a first conductivity type impurity region stacked in succession in the high voltage first conductivity type well. A second stack region may have a second conductivity type drift region, and a second conductivity type impurity region stacked in succession in the high voltage first conductivity type well. A device isolating film formed between the first stack region and the second stack region for isolating the first stack region from the second stack region. | 2010-06-24 |
20100155830 | ELECTRONIC SWITCHING DEVICE - An integrated switching device has a switching IGFET connected between a pair of main terminals, a protector IGFET connected between the drain and gate electrodes of the switching IGFET, and a gate resistor connected between a main control terminal and the gate electrode of the switching IGFET. The protector IGFET has its gate electrode connected to the source electrode of the switching IGFET. The protector IGFET turns on in response to an application of a verse voltage to the switching IGFET thereby protecting the same from a reverse current flow. | 2010-06-24 |
20100155831 | Deep trench insulated gate bipolar transistor - In one embodiment, a power transistor device comprises a substrate of a first conductivity type that forms a PN junction with an overlying buffer layer of a second conductivity type. The power transistor device further includes a first region of the second conductivity type, a drift region of the second conductivity type that adjoins a top surface of the buffer layer, and a body region of the first conductivity type. The body region separates the first region from the drift region. First and second dielectric regions respectively adjoin opposing lateral sidewall portions of the drift region. The dielectric regions extend in a vertical direction from at least just beneath the body region down at least into the buffer layer. A trench gate that controls forward conduction is disposed above the dielectric region adjacent to and insulated from the body region. | 2010-06-24 |
20100155832 | METHOD FOR FABRICATING SEMICONDUCTOR MEMORY DEVICE - A method for manufacturing a semiconductor device comprises forming a first spacer layer at sidewalls of one or more gate electrodes, forming a trench by etching an isolation insulating layer exposed between the gate electrodes, forming a second spacer layer on sidewalls of the gate electrodes and an inner surface of the trench and forming an interlayer insulating layer between the gate electrodes. | 2010-06-24 |
20100155833 | Semiconductor device having vertical type MOSFET and manufacturing method thereof - A method (and resultant structure) includes forming a semiconductor layer having plural stripe-like trenches, forming a gate electrode buried partially in each of the plural trenches, and introducing an impurity into the semiconductor layer by ion implantation after forming the gate electrode. The gate electrode has a buried portion formed in each of the trenches and a protruding portion situating above the buried portion and having a width larger than that of the buried portion. The introducing the impurity includes introducing an impurity into the semiconductor layer below the protruding portion by oblique ion implantation. | 2010-06-24 |
20100155834 | SEMICONDUCTOR DEVICE AND A METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes a semiconductor substrate provided with an active region including a gate forming area, a source forming area and a drain forming area. A recess is formed in the gate forming area. A gate is formed over the gate forming area that is formed with the recess and includes an insulation layer formed at an upper end portion of a side wall of the recess that is in contact with the source forming area. A source area and a drain area are formed in the active region on opposite sides of the gate. | 2010-06-24 |
20100155835 | Castellated gate MOSFET tetrode capable of fully-depleted operation - A castellated-gate MOSFET tetrode device capable of fully depleted operation is disclosed. The device includes a semiconductor substrate region having an upper portion with a top surface and a lower portion with a bottom surface. A source region and a drain region are formed in the semiconductor substrate region, with adjoined primary and secondary channel-forming regions also disposed therein between the source and drain regions, thereby forming an integrated cascade structure. Trench isolation insulator islands, having upper and lower surfaces, surround the source and drain regions as well as the channel-forming regions. Both the primary and secondary channel-forming regions include pluralities of thin, spaced, vertically-orientated semiconductor channel elements that span longitudinally along the device between the source and drain regions. First and second gate structures are provided in the form of pluralities of spaced, castellated first and second gate elements interposed between the primary and secondary channel elements, respectively, with first and second top gate members interconnecting the first and second gate elements at their upper vertical ends to cover the primary and secondary channel elements. The adjoined primary and secondary channel elements are super-self-aligned from the first and second gate elements to the source and drain regions. Finally, first and second dielectric layers separate the primary and secondary channel elements from their respective gate structures. | 2010-06-24 |
20100155836 | CO-PACKAGING APPROACH FOR POWER CONVERTERS BASED ON PLANAR DEVICES, STRUCTURE AND METHOD - A voltage converter includes an output circuit having a high-side device and a low-side device which can be formed on a single die (a “PowerDie”). The high-side device can include a lateral diffused metal oxide semiconductor (LDMOS) while the low-side device can include a planar vertical diffused metal oxide semiconductor (VDMOS). The voltage converter can further include a controller circuit on a different die which can be electrically coupled to, and co-packaged with, the power die. | 2010-06-24 |
20100155837 | SINGLE DIE OUTPUT POWER STAGE USING TRENCH-GATE LOW-SIDE AND LDMOS HIGH-SIDE MOSFETS, STRUCTURE AND METHOD - A voltage converter includes an output circuit having a high-side device and a low-side device which can be formed on a single die (a “PowerDie”). The high-side device can include a lateral diffused metal oxide semiconductor (LDMOS) while the low-side device can include a trench-gate vertical diffused metal oxide semiconductor (VDMOS). The voltage converter can further include a controller circuit on a different die which can be electrically coupled to, and co-packaged with the output circuit. | 2010-06-24 |
20100155838 | TRENCH TYPE MOSFET DEVICE AND METHOD OF MANUFACTURING THE SAME - A trench type Metal Oxide Silicon Field Effect Transistor (MOSFET) device and a method of manufacturing a trench type MOSFET device. A trench type MOSFET device may include a wide-trench source contact poly which may be formed on and/or over a space between deep-trench gate polys on and/or over a trench type power MOSFET device. An electric field may be formed around a source contact poly and/or a gate poly. A relatively strong electric field may be minimized at an edge between a trench gate and a source. Leakage may be minimized and/or reliability may be maximized. | 2010-06-24 |
20100155839 | LATERAL MOSFET WITH SUBSTRATE DRAIN CONNECTION - In one form a lateral MOSFET includes an active gate positioned laterally between a source region and a drain region, the drain region extending from an upper surface of a monocrystalline semiconductor body to a bottom surface of the monocrystalline semiconductor body, and a non-active gate positioned above the drain region. In another form the lateral MOSFET includes a gate positioned laterally between a source region and a drain region, the drain region extending from an upper surface of a monocrystalline semiconductor body to a bottom surface of the monocrystalline semiconductor body, the source region and the drain region being of a first conductivity type, a heavy body region of a second conductivity type in contact with and below the source region, and the drain region comprising a lightly doped drain (LDD) region proximate an edge of the gate and a sinker extending from the upper surface of the monocrystalline body to the bottom surface of the monocrystalline semiconductor body. | 2010-06-24 |
20100155840 | POWER MOSFET AND FABRICATING METHOD THEREOF - A power MOSFET is disclosed. In the power MOSFET, an epitaxial layer doped with dopants of a first conduction type is formed on a substrate. A first trench extends downward from a first region of the top surface of the epitaxial layer, and a second trench extends downward from the bottom of the first trench. The width of the second trench is smaller than that of the first trench. The first well is located adjacent to the bottom of the first trench and the bottom of the second trench, and is doped with dopants of a second conduction type. The second well extends downward from a second region of the top surface and is doped with dopants of the second conduction type. The first well and the second well are separated. A source region doped with dopants of the first conduction type is formed in the second well. | 2010-06-24 |
20100155841 | Semiconductor Device and Method for Fabricating the Same - A Semiconductor device and method for fabricating the same are disclosed. The method includes implanting first conduction type impurities into a semiconductor substrate to form a first well, implanting second conduction type impurities into the first well to form a second well, implanting second conduction type impurities into the second well to form an impurity region, forming a gate on the semiconductor substrate, and implanting second conduction type impurities to form a drain region in the impurity region on one side of the gate. | 2010-06-24 |
20100155842 | BODY CONTACTED HYBRID SURFACE SEMICONDUCTOR-ON-INSULATOR DEVICES - A portion of a top semiconductor layer of a semiconductor-on-insulator (SOI) substrate is patterned into a semiconductor fin having substantially vertical sidewalls. A portion of a body region of the semiconductor fin is exposed on a top surface of the semiconductor fin between two source regions having a doping of a conductivity type opposite to the body region of the semiconductor fin. A metal semiconductor alloy portion is formed directly on the two source regions and the top surface of the exposed body region between the two source regions. The doping concentration of the exposed top portion of the body region may be increased by ion implantation to provide a low-resistance contact to the body region, or a recombination region having a high-density of crystalline defects may be formed. A hybrid surface semiconductor-on-insulator (HSSOI) metal-oxide-semiconductor-field-effect-transistor (MOSFET) thus formed has a body region that is electrically tied to the source region. | 2010-06-24 |
20100155843 | FIELD EFFECT TRANSISTOR WITH ALTERNATE ELECTRICAL CONTACTS - A field effect transistor including: a support layer, a plurality of active zones based on a semiconductor, each active zone configured to form a channel and arranged between two gates adjacent to each other and consecutive, the active zones and the gates being arranged on the support layer, each gate including a first face on the side of the support layer and a second face opposite the first face. The second face of a first of the two gates is electrically connected to a first electrical contact made on the second face of the first of the two gates, and the first face of a second of the two gates is electrically connected to a second electrical contact passing through the support layer. The gates of the transistor are not electrically connected to each other. | 2010-06-24 |
20100155844 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - There is provided a semiconductor device having excellent device characteristics in which V | 2010-06-24 |
20100155845 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - A semiconductor integrated circuit device with a “PAD on I/O cell” structure in which a pad lead part is disposed almost in the center of an I/O part so as to reduce the chip layout area. In the I/O part, a transistor lies nearest to the periphery of the semiconductor chip. When seen in a plan view of the I/O part, a resistance lies above the transistor and a first and a second diode lie above the resistance; a second transistor lies above the diodes; and a logic block lies above the second transistor with a pad lead part, for example, formed in a metal wiring layer, therebetween. This permits the pad through the second transistor to be on the same node and therefore the pad lead part can be disposed almost in the center of the I/O part. | 2010-06-24 |
20100155846 | Metal-insulator-semiconductor tunneling contacts - A contact to a source or drain region. The contact has a conductive material, but that conductive material is separated from the source or drain region by an insulator. | 2010-06-24 |
20100155847 | SELF ALIGNED FIELD EFFECT TRANSISTOR STRUCTURE - Provided is a self aligned field effect transistor structure. The self aligned field effect transistor structure includes: an active region pattern on a substrate; a first gate electrode and a second gate electrode facing each other with the active region pattern therebetween; and a source electrode and a drain electrode connected to the active region pattern and disposed to be symmetric with respect to a line connecting the first and second gate electrodes, wherein the first and second gate electrodes and the source and drain electrodes are disposed on the same plane of the substrate. | 2010-06-24 |
20100155848 | Trigate static random-access memory with independent source and drain engineering, and devices made therefrom - A static random-access memory circuit includes at least one access device including source and drain sections for a pass region, at least one pull-up device and at least one pull-down device including source-and-drain sections for a pull-down region. The static random-access memory circuit is configured with external resistivity (R | 2010-06-24 |
20100155849 | TRANSISTORS WITH METAL GATE AND METHODS FOR FORMING THE SAME - A semiconductor device includes at least one first gate dielectric layer over a substrate. A first transition-metal oxycarbide (MC | 2010-06-24 |
20100155850 | TECHNIQUE FOR PROVIDING STRESS SOURCES IN TRANSISTORS IN CLOSE PROXIMITY TO A CHANNEL REGION BY RECESSING DRAIN AND SOURCE REGIONS - By recessing drain and source regions, a highly stressed layer, such as a contact etch stop layer, may be formed in the recess in order to enhance the strain generation in the adjacent channel region of a field effect transistor. Moreover, a strained semiconductor material may be positioned in close proximity to the channel region by reducing or avoiding undue relaxation effects of metal silicides, thereby also providing enhanced efficiency for the strain generation. In some aspects, both effects may be combined to obtain an even more efficient strain-inducing mechanism. | 2010-06-24 |
20100155851 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - There is disclosed a semiconductor device comprising a P-channel MIS transistor which includes an N-type semiconductor layer, a first gate insulating layer formed on the N-type semiconductor layer and containing a carbon compound of a metal, and an N-channel MIS transistor which includes a P-type semiconductor layer, a second gate insulating layer formed on the P-type semiconductor layer, and a second gate electrode formed on the second gate insulating layer. | 2010-06-24 |
20100155852 | Integrating Diverse Transistors On The Same Wafer - Different types of transistors, such as memory cells, higher voltage, and higher performance transistors, may be formed on the same substrate. A transistor may be formed with a first polysilicon layer covered by a dielectric. A second polysilicon layer over the dielectric may be etched to form a sidewall spacer on the gate of the transistor. The sidewall spacer may be used to form sources and drains and to define sub-lithographic lightly doped drains. After removing the spacer, the underlying dielectric may protect the lightly doped drains. | 2010-06-24 |
20100155853 | MULTIPLEXER AND METHOD OF MANUFACTURING THE SAME - A multiplexer can include a signal line arranged on a substrate and including a plurality of data wires extending in a first direction and electrically insulated from one another, where each of the data wires has at least one recess to provide at least two data wiring pieces. An address line is arranged on the signal line and includes a plurality of coding lines extending in a second direction different from the first direction and electrically insulated from the data wires. A plurality of switching elements are positioned in the recesses of the data wires and make electrical contact with the coding lines, where the switching element is configured to switch a data signal applied to the data wiring on and off in accordance with a coding signal applied to the coding lines, so that one of the data wires is selected according to a binary code of the address line corresponding to combinations of the coding lines to which coding signal is applied. | 2010-06-24 |
20100155854 | Methods of Fabricating Semiconductor Devices and Structures Thereof - Methods of fabricating semiconductor devices and structures thereof are disclosed. In one embodiment, a method of manufacturing a semiconductor device includes forming a gate material stack over a workpiece having a first region and a second region. A composition or a thickness of at least one of a plurality of material layers of the gate material stack is altered in at least the second region. The gate material stack is patterned, forming a first transistor in the first region and forming a second transistor in the second region. Altering the composition or the thickness of the at least one of the plurality of material layers of the gate material stack in at least the second region results in a first transistor having a first threshold voltage and a second transistor having a second threshold voltage, the second threshold voltage having a different magnitude than the first threshold voltage. | 2010-06-24 |
20100155855 | Band Edge Engineered Vt Offset Device - Band edge engineered Vt offset devices, design structures for band edge engineered Vt offset devices and methods of fabricating such structures is provided herein. The structure includes a first FET having a channel of a first compound semiconductor of first atomic proportions resulting in a first band structure and a first type. The structure further includes a second FET having a channel of a second compound semiconductor of second atomic proportions resulting in a second band structure and a first type. The first compound semiconductor is different from the second compound semiconductor such that the first FET has a first band structure different from second band structure, giving rise to a threshold voltage different from that of the second FET. | 2010-06-24 |
20100155856 | Transistor, a transistor arrangement and method thereof - A transistor, transistor arrangement and method thereof are provided. The example method may include determining whether a gate width of the transistor has been adjusted; and adjusting a distance between a higher-concentration impurity-doped region of the transistor and a device isolation layer of the transistor based on the adjusted gate width if the determining step determines the gate width of the transistor is adjusted. The example transistor may include a first device isolation layer defining a first active region, a first gate line having a first gate width and crossing over the first active region, a first lower-concentration impurity-doped region formed in the first active region at first and second sides of the first gate line and a first higher-concentration impurity-doped region formed in the lower-concentration impurity-doped region and not in contact with the gate line and the device-isolation layer. | 2010-06-24 |
20100155857 | A SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING THE SAME AND DESIGNING THE SAME - There is provided a technique for improving the flatness at the surface of members embedded in a plurality of recesses without resulting in an increase in the time required for the manufacturing processes. According to this technique, the dummy patterns can be placed up to the area near the boundary BL between the element forming region DA and dummy region FA by placing the first dummy pattern DP | 2010-06-24 |
20100155858 | ASYMMETRIC EXTENSION DEVICE - The present invention discloses a semiconductor device with an asymmetric channel extension structure capable of storing charges, improving gate oxide reliability, reducing parasitic capacitance and adjusting its channel extension current or turn-on resistance. A gate dielectric is formed on the semiconductor substrate. A gate is formed on the gate dielectric. A first isolation layer is formed over the sidewall of the gate. Dielectric spacers are formed on the sidewall of the first isolation layer. And at least one of the p-n junctions of source and drain regions is formed under the dielectric spacers. A fringing field induced extension region formed adjacent to asymmetric channel under gate dielectric and close to at least one of said doped regions. A threshold voltage adjustment implantation region formed under gate dielectric An anti-punch-through implantation region formed under threshold voltage adjustment implantation region. A pocket ion implantation region formed adjacent or near to at least one of said doped regions. Silicide layer is formed on the gate or the doped regions. | 2010-06-24 |
20100155859 | SELECTIVE SILICIDE PROCESS - A method of self-aligned silicidation on structures having high aspect ratios involves depositing a metal oxide film using atomic layer deposition (ALD) and converting the metal oxide film to metal film in order to obtain uniform step coverage. The substrate is then annealed such that the metal in regions directly overlying the patterned and exposed silicon reacts with the silicon to form uniform metal silicide at the desired locations. | 2010-06-24 |
20100155860 | TWO STEP METHOD TO CREATE A GATE ELECTRODE USING A PHYSICAL VAPOR DEPOSITED LAYER AND A CHEMICAL VAPOR DEPOSITED LAYER - One embodiment of the present invention relates a semiconductor device formed by utilizing a two step deposition method for forming a gate electrode without causing damages to an underlying gate dielectric material. In one embodiment, a first layer of gate electrode material (first gate electrode layer) is formed onto the surface of a gate dielectric material using a deposition that does not damage the gate dielectric material (e.g., physical vapor deposition) thereby resulting in a damage free interface between the gate dielectric material and the gate electrode material. A second layer of gate electrode material (second gate electrode layer) is then formed onto the first layer of gate electrode material using a chemical deposition method that provides increased deposition control (e.g., good layer uniformity, impurity control, etc.). The first and second gate electrode layers are then selectively patterned to cumulatively form a semiconductor device's gate electrode. | 2010-06-24 |
20100155861 | MICROELECTROMECHANICAL DEVICE WITH ISOLATED MICROSTRUCTURES AND METHOD OF PRODUCING SAME - A microelectromechanical systems (MEMS) device ( | 2010-06-24 |
20100155862 | PACKAGE FOR ELECTRONIC COMPONENT, MANUFACTURING METHOD THEREOF AND SENSING APPARATUS - A package for electronic component comprises a rectangular package body having a flat cut surface to be abutted on a flat mounting surface of a mounting substrate, a first side surface intersecting with the flat cut surface, and a first notch part formed at a boundary between the flat cut surface and the first side surface, an electronic component installed in the package body, and a first pad electrically connected to the electronic component and formed on an inner wall surface of the first notch part. | 2010-06-24 |
20100155863 | METHOD FOR MANUFACTURING A MICROELECTRONIC PACKAGE COMPRISING A SILICON MEMS MICROPHONE - A method for manufacturing a microelectronic package comprising a silicon MEMS microphone comprises the following steps: providing a basic panel ( | 2010-06-24 |
20100155864 | MEMS PROCESS AND DEVICE - A MEMS device, for example a capacitive microphone, comprises a flexible membrane | 2010-06-24 |
20100155865 | Semiconductor device and method of making the same - A semiconductor device includes a sensor portion, a cap portion, and an ion-implanted layer. The sensor portion has a sensor structure at a surface portion of a surface. The cap portion has first and second surfaces opposite to each other and includes a through electrode. The surface of the sensor portion is joined to the first surface of the cap portion such that the sensor structure is sealed between the sensor portion and the cap portion. The ion-implanted layer is located on the second surface of the cap portion. The through electrode extends from the first surface to the second surface and is exposed through the ion-implanted layer. | 2010-06-24 |
20100155866 | HIGH TEMPERATURE RESISTANT SOLID STATE PRESSURE SENSOR - A harsh environment transducer including a substrate having a first surface and a second surface, wherein the second surface is in communication with the environment. The transducer includes a device layer sensor means located on the substrate for measuring a parameter associated with the environment. The sensor means including a single crystal semiconductor material having a thickness of less than about 0.5 microns. The transducer further includes an output contact located on the substrate and in electrical communication with the sensor means. The transducer includes a package having an internal package space and a port for communication with the environment. The package receives the substrate in the internal package space such that the first surface of the substrate is substantially isolated from the environment and the second surface of the substrate is substantially exposed to the environment through the port. The transducer further includes a connecting component coupled to the package and a wire electrically connecting the connecting component and the output contact such that an output of the sensor means can be communicated. An external surface of the wire is substantially platinum, and an external surface of at least one of the output contact and the connecting component is substantially platinum. | 2010-06-24 |
20100155867 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device ( | 2010-06-24 |
20100155868 | IMAGE SENSOR AND MANUFACTURING METHOD THEREOF - Disclosed are an image sensor and a manufacturing method thereof. The image sensor includes a circuit layer on a first surface of a semiconductor substrate, a metal interconnection layer on the circuit layer, trenches formed in a second surface of the semiconductor substrate along a boundary of a pixel, and a light blocking layer in the trenches. The backside illumination type image sensor according to the embodiment has a light blocking structure at a rear surface of the semiconductor substrate, thereby improving sensing efficiency while inhibiting interference between adjacent pixels. | 2010-06-24 |
20100155869 | METHOD OF MANUFACTURING SOLID-STATE IMAGE PICKUP DEVICE AND SOLID-STATE IMAGE PICKUP DEVICE - A method includes preparing a cover member; preparing an image pickup element including a substrate including a pixel region including a plurality of photo detectors on a principal surface, a first concavo-convex portion including a plurality of first convex portions configured to concentrate light on the plurality of photo detectors, the first convex portions each having a lens shape, and a second concavo-convex portion surrounding the first concavo-convex portion, the second concavo-convex portion including a plurality of second convex portions; and fixing the cover member to a region of the image pickup element using a fixing member, the region being between the first concavo-convex portion and the second concavo-convex portion. | 2010-06-24 |
20100155870 | LIGHT GUIDE ARRAY FOR AN IMAGE SENSOR - An image sensor pixel that includes a photoelectric conversion unit supported by a substrate and an insulator adjacent to the substrate. The pixel includes a light guide that is located within an opening of the insulator and extends above the insulator such that a portion of the light guide has an air interface. The air interface improves the internal reflection of the light guide. Additionally, the light guide and an adjacent color filter are constructed with a process that optimizes the upper aperture of the light guide. These characteristics of the light guide eliminate the need for a microlens. | 2010-06-24 |
20100155871 | SILICONE RESIN COMPOSITION - A silicone resin composition containing (i) a silicone resin and (ii) fine metal oxide particles without having a reactive functional group or with a protected reactive functional group on the surface thereof (fine metal oxide particles B), wherein the silicone resin is obtained by carrying out a polymerization reaction between a silicone derivative having an alkoxysilyl group at an end of a molecule and a molecular weight of from 200 to 3000, and fine metal oxide particles having a reactive functional group on the surface thereof (fine metal oxide particles A), and wherein the fine metal oxide particles B are dispersed in the silicone resin (Embodiment 1); a silicone resin composition obtained by carrying out a polymerization reaction between a silicone derivative having a trifunctional alkoxysilyl group at an end of a molecule, and fine metal oxide particles having a reactive functional group on the surface thereof, wherein the silicone derivative contains two or more kinds of silicone derivatives each having a trifunctional alkoxysilyl group at an end of a molecule, and wherein the silicone derivative is added in two or more divided stages in the presence of the fine metal oxide particles in the polymerization reaction (Embodiment 2); and a silicone resin composition obtained by carrying out a polymerization reaction between a silicone derivative having an alkoxysilyl group at an end of a molecule or in a side chain thereof, and fine metal oxide particles having a reactive functional group on the surface thereof, wherein the alkoxysilyl group contains a silyl group having an alkoxy group and an aromatic group as functional groups directly bonded to a silicon atom (Embodiment 3). The silicone resin composition of the present invention can be suitably used as, for example, materials for encapsulating photosemiconductor elements for use in backlights for liquid crystal displays, traffic lights, outdoor big displays, advertisement sign boards, and the like. | 2010-06-24 |
20100155872 | IMAGE SENSOR AND MANUFACTURING METHOD OF IMAGE SENSOR - An image sensor includes a trench formed in a semiconductor substrate, a first reflection part formed in the trench and having an inclined, curved surface, a second reflection part formed on the first reflection part such that a remaining space of the trench is filled with the second reflection part, and a vertical type photodiode formed on a region of the substrate between trenches. A method for forming the image sensor includes forming a trench in a semiconductor substrate, forming a first reflection part having an inclined, curved surface in the trench, forming a second reflection part on the first reflection part such that a remaining space of the trench is filled with the second reflection part, and forming a vertical type photodiode on a region of the substrate between trenches. | 2010-06-24 |
20100155873 | Image Sensor and Method for Manufacturing the Same - A backside illumination (BSI) image sensor having a light receiving part at the wafer or die backside, and a manufacturing method thereof, are disclosed. The method includes polishing the light receiving part so that a super via protrudes, forming a first insulating layer to cover the protruding super via and the light receiving part, forming a photoresist pattern on the first insulating layer to expose a pad region, etching the first insulating layer to form spacers at sides of the protruding super via, repeatedly forming a second insulating layer covering the spacers, the super via and the light receiving part and etching the second insulating layer so that the spacers increase in width and cover an upper surface of the light receiving part, and forming a metal pad in the pad region to contact the super via. | 2010-06-24 |
20100155874 | Front Side Illuminated, Back-Side Contact Double-Sided PN-Junction Photodiode Arrays - The present invention is a photodiode detector array for use in computerized tomography (CT) and non-CT applications. Specifically, the present invention is a high-density photodiode arrays, with low dark current, low capacitance, high signal to noise ratio, high speed, and low crosstalk that can be fabricated on relatively large substrate wafers. More specifically the photodiode array of the present invention is fabricated such that the PN-junctions are located on both the front side and back side surfaces of the array, and wherein the front side PN-junction is in electrical communication with the back side PN-junction. Still more specifically, the present invention is a photodiode array awing PN-junctions that are electrically connected from the front to back surfaces and which can be operated in a fully depleted mode at low reverse bias. | 2010-06-24 |
20100155875 | Semiconductor device provided with photodiode, manufacturing method thereof, and optical disc device - A semiconductor device includes: a P-type semiconductor substrate; a first P-type semiconductor layer formed on the P-type semiconductor substrate; a second P-type semiconductor layer formed on the first P-type semiconductor layer and having a lower P-type impurity concentration than the first P-type semiconductor layer; an N-type semiconductor layer, which will form a cathode region, formed on the second P-type semiconductor layer; a first P-type diffusion layer formed by diffusing a P-type impurity in a partial region of the second P-type semiconductor layer; a second P-type diffusion layer formed by diffusing a P-type impurity in the second P-type semiconductor layer so as to be present adjacently beneath the first P-type diffusion layer at a lower P-type impurity concentration than the first P-type diffusion layer; and a photodiode formed in such a manner that the N-type semiconductor layer and the first P-type diffusion layer are isolated from each other. | 2010-06-24 |
20100155876 | Junction barrier Schottky (JBS) with floating islands - A Schottky diode includes a Schottky barrier and a plurality of dopant regions disposed near the Schottky barrier as floating islands to function as PN junctions for preventing a leakage current generated from a reverse voltage. At least a trench opened in a semiconductor substrate with a Schottky barrier material disposed therein constitutes the Schottky barrier. The Schottky barrier material may also be disposed on sidewalls of the trench for constituting the Schottky barrier. The trench may be filled with the Schottky barrier material composed of Ti/TiN or a tungsten metal disposed therein for constituting the Schottky barrier. The trench is opened in a N-type semiconductor substrate and the dopant regions includes P-doped regions disposed under the trench constitute the floating islands. The P-doped floating islands may be formed as vertical arrays under the bottom of the trench. | 2010-06-24 |
20100155877 | NOVEL SCHOTTKY DIODE FOR HIGH SPEED AND RADIO FREQUENCY APPLICATION - A semiconductor diode that is disclosed. An exemplary semiconductor diode includes a portion of a semiconductor substrate including a first dopant, a first well with a Schottky region, and a second well with a second dopant; and an isolation region replacement element positioned over the semiconductor substrate and adjacent to the first and second wells. | 2010-06-24 |
20100155878 | Configuration of high-voltage semiconductor power device to achieve three dimensional charge coupling - This invention discloses semiconductor device that includes a top region and a bottom region with an intermediate region disposed between said top region and said bottom region with a controllable current path traversing through the intermediate region. The semiconductor device further includes a trench with padded with insulation layer on sidewalls extended from the top region through the intermediate region toward the bottom region wherein the trench includes randomly and substantially uniformly distributed nano-nodules as charge-islands in contact with a drain region below the trench for electrically coupling with the intermediate region for continuously and uniformly distributing a voltage drop through the current path. | 2010-06-24 |
20100155879 | SEMICONDUCTOR DEVICE - A semiconductor device is provided that comprises a semiconductor substrate comprising an active area and a peripheral region adjacent the active area and structure positioned in the peripheral region for hindering the diffusion of mobile ions from the peripheral region into the active area. | 2010-06-24 |
20100155880 | Back gate doping for SOI substrates - A silicon-on-insulator (SOI) substrate comprises a base silicon substrate having a back gate region, wherein the back gate region has a first dopant concentration that is greater than 1×10 | 2010-06-24 |
20100155881 | Forming Isolation Regions For Integrated Circuits - A substrate may have active areas at different levels separated by a mask. Along the mask may be a shallow trench isolation. Along the shallow trench isolation may be a LOCOS isolation. The shape of a substrate transition region between the levels may be tunably controlled. The shallow trench isolation may reduce the bird's beak effect. | 2010-06-24 |
20100155882 | METHOD FOR BONDING TWO SUBSTRATES - The invention relates to a method for bonding two substrates by applying an activation treatment to at least one of the substrates, and performing the contacting step of the two substrates under partial vacuum. Due to the combination of the two steps, it is possible to carry out the bonding and obtain high bonding energy with a reduced number of bonding voids. The invention is in particular applicable to a substrate of processed or at least partially processed devices. | 2010-06-24 |
20100155883 | INTEGRATED MEMS AND IC SYSTEMS AND RELATED METHODS - An integrated MEMS and IC system (MEMSIC), as well as related methods, are described herein. According to some embodiments, a mechanical resonating structure is coupled to an electrical circuit (e.g., field-effect transistor). For example, the mechanical resonating structure may be coupled to a gate of a transistor. In some cases, the mechanical resonating structure and electrical circuit may be fabricated on the same substrate (e.g., Silicon (Si) and/or Silicon-on-Insulator (SOW and may be proximate to one another. | 2010-06-24 |
20100155884 | MELTING FUSE OF SEMICONDUCTOR AND METHOD FOR FORMING THE SAME - The present invention discloses a fuse of a semiconductor device and manufacturing method thereof. The fuse of a semiconductor device of the present invention includes a first conductive pattern; and a second conductive pattern which is separated from the first conductive pattern with a given gap, wherein the first conductive pattern and the second conductive pattern are melted in a laser irradiation to be connected. Accordingly, the present invention prevents the damage of the adjacent fuse in the repair process, enabling to improve the reliability of device and accomplish the high integration. | 2010-06-24 |
20100155885 | Fuse Corner Pad for an Integrated Circuit - A fuse corner pad is part of an integrated circuit that includes a built-in fuse contact and a plurality of auxiliary pads. The fuse contact is a conductive metallic or metalloid structure that is connected to a fuse element. The fuse contact and fuse element are used inside of the fuse corner pad for programmability (e.g., for security) and/or adjustment (e.g., trimming) of analog and/or digital signals. The fuse contact and fuse element are not required to be bonded to an external electrical connection (such as, a pin or ball). The auxiliary pads provide a variety of functional or non-functional applications, such as testing, probing, programming, and/or circuit adjustment. | 2010-06-24 |
20100155886 | SEMICONDUCTOR DEVICE - A semiconductor device is provided. The semiconductor device includes a chip having a plurality of first power voltage terminals connected in common to a first power voltage line, a plurality of second power voltage terminals connected in common with a second power voltage line, a first connection terminal, a second connection terminal connected to the first power voltage line or the second power voltage line, and an on-die capacitor. The semiconductor device also includes a package having a plurality of third power voltage terminals connected to the first power voltage terminals through a first wire by wire bonding during a packaging process and a plurality of fourth power voltage terminals connected to the second power voltage terminals through a second wire by wire bonding during the packaging process, and configured to package the chip, wherein one end of the on-die capacitor is connected to the first connection terminal, and the first connection terminal is connected to the second connection terminal through a third wire by wire bonding during the packaging process. | 2010-06-24 |
20100155887 | Common plate capacitor array connections, and processes of making same - A process of forming a semiconductive capacitor device for a memory circuit includes forming a first capacitor cell recess and a second capacitor cell recess that are spaced apart by a capacitor cell boundary of a first height. The process includes lowering the first height of the capacitor cell boundary to a second height. A common plate capacitor bridges between the first recess and the second recess over the boundary above the second height and below the first height. | 2010-06-24 |
20100155888 | SILICON INTERPOSER TESTING FOR THREE DIMENSIONAL CHIP STACK - A testing method for a silicon interposer employs a test probe and an electrically conductive glass handler. The silicon interposer includes multiple interconnects that extend between the opposed major surfaces of the interposer, namely from a test side of the interposer to a conductive glass handler side of the interposer. On the glass handler side, the interposer includes a layer of patterned insulative resist with open regions at some interconnects on the glass handler side and remaining resist regions at other interconnects on the glass handler side. The interposer may include a conductive adhesive layer that couples together interconnects at the open regions on the glass handler side. In this manner, a probe may send a test signal from a first interconnect at one location on the test side of the interposer, through the first interconnect, through the conductive adhesive, through a second interconnect to another probe on the test side of the interposer. The method thus provides same-sided probe testing of the interposer. The method also provides for loading or power application to the conductive glass handler and testing of circuits and interconnects on the test side of the silicon interposer. | 2010-06-24 |
20100155889 | CAPACITOR AND METHOD FOR FABRICATING THE SAME - A capacitor includes a lower electrode; a dielectric layer formed on a predetermined portion of the lower electrode; an upper electrode formed on the dielectric layer; a hard mask pattern formed on the upper electrode; and an isolation layer having a shape of a spacer, formed on one sidewall of the hard mask pattern, the upper electrode, and the dielectric layer. | 2010-06-24 |
20100155890 | MIM CAPACITOR OF SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A method of manufacturing a MIM capacitor of a semiconductor device and a MIM capacitor. A MIM structure and a metal layer may be formed using a single process. A method of manufacturing a MIM capacitor may include forming a hole on and/or over a lower metal wire region. A method of manufacturing a MIM capacitor may include forming a lower metal layer, an inter-metal dielectric and/or an upper metal layer on and/or over a hole to form a MIM structure. Patterns to form a MIM structure and a metal layer may be formed at substantially the same time. If etching is performed with a photoresist pattern as a mask, a MIM structure and a metal layer structure may be formed at substantially the same time using a single mask. | 2010-06-24 |
20100155891 | SEMICONDUCTOR DEVICE HAVING CYLINDRICAL LOWER ELECTRODE OF CAPACITOR AND MANUFACTURING METHOD THEREOF - To provide a semiconductor device including: plural capacitors each including a cylindrical lower electrode having an internal wall and an external wall, and an upper electrode that covers the external wall of the lower electrode via a capacitance dielectric film; and a supporting film having a buried portion buried in an internal region surrounded by the internal wall of the lower electrode, and a supporting portion a part of which is positioned within the internal region and remaining parts of which are positioned at outside of the internal region. The supporting portion sandwiches an upper end of the lower electrode at both ends of the upper end by covering the internal wall and the external wall of the upper end of the lower electrode. | 2010-06-24 |
20100155892 | Semiconductor Constructions - Some embodiments include methods of forming semiconductor constructions. Oxide is formed over a substrate, and first material is formed over the oxide. Second material is formed over the first material. The second material may be one or both of polycrystalline and amorphous silicon. A third material is formed over the second material. A pattern is transferred through the first material, second material, third material, and oxide to form openings. Capacitors may be formed within the openings. Some embodiments include semiconductor constructions in which an oxide is over a substrate, a first material is over the oxide, and a second material containing one or both of polycrystalline and amorphous silicon is over the first material. Third, fourth and fifth materials are over the second material. An opening may extend through the oxide; and through the first, second, third, fourth and fifth materials. | 2010-06-24 |