25th week of 2010 patent applcation highlights part 56 |
Patent application number | Title | Published |
20100159595 | METHOD OF GENERATING MYELINATING OLIGODENDROCYTES - A method of differentiating embryonic stem cells into oligodendroglial precursor cells and oligodendroglial cells by culturing a population of cells comprising a majority of cells that are characterized by a neural tube-like rosette morphology and are Pax6+/Sox1+ into a population of cells that are PDGFRα+. | 2010-06-24 |
20100159596 | SMALL MOLECULE COMPOUNDS FOR STEM CELL DIFFERENTIATION - Methods and small molecule compounds for stem cell differentiation are provided. One example of a class of compounds that may be used is represented by the compound having the structure IA or IB in the form of free base or a pharmaceutically acceptable salt, hydrate, solvate or N-oxide thereof: | 2010-06-24 |
20100159597 | CELL CULTURE MEMBRANE, CELL CULTURE KIT, POROUS MATERIAL, PRODUCTION METHOD FOR CELL CULTURE MEMBRANE AND PRODUCTION METHOD FOR POROUS MATERIAL - To produce a cell culture membrane having biocompatibility utilizing DNA of natural resources and a cell culture kit, the cell culture membrane having DNA ionically-cross-linked with calcium ions or magnesium ions is provided. To produce a porous material utilizing DNA, a production method for a cell culture membrane and a production method for a porous material, fine pores of 1 nm to 100 μm in diameter are prepared in the porous material. | 2010-06-24 |
20100159598 | In Vitro Methods for the Induction and Maintenance of Plant Cell Lines as Single Suspension Cells With Intact Cell Walls, and Transformation Thereof - The subject invention provides simple and consistent methods to break suspension cell aggregates to single cells with intact primary cell walls. The subject invention relates in part to cell separation of suspension cell aggregates cultured in medium containing pectin-degrading enzymes or tubulin de-polymerizing compounds including colchicine. The subject invention also relates to novel uses of compounds for such purposes. Another aspect of the subject invention relates to transformation of the subject, isolated cells. Such processes simplify and integrate single-cell-based transformation and selection processes into transgenic and transplastomic event-generation work processes. The subject invention also removes technical constraints and produces marker-free and uniformly expressing transgenic lines in a high throughput fashion to support various needs of animal health, biopharma, and trait and crop protection platforms. | 2010-06-24 |
20100159599 | LATERAL-FLOW POROUS MEMBRANE ASSAY WITH FLOW RATE CONTROL - Various modifications to a porous substrate, such as employed in lateral flow assay devices, to regulate or modify the flow rate and/or flow path pattern of a fluid through the porous substrate is described. The lateral flow assay device has a porous substrate matrix in fluid communication with a flow-rate control zone having a number of flow-rate control devices arranged as features in or on a substrate surface or laminates thereof in a body. The flow-rate control devices may include: a density gradient, porosity gradient, ion affinity gradient, micro-channels, and combinations thereof. | 2010-06-24 |
20100159600 | METHOD OF CONTROLLING FLUID FLOW IN MICROFLUIDIC DEVICE AND MICROFLUIDIC ANALYSIS APPARATUS - Provided are methods of controlling a fluid flow in a microfluidic device and a microfluidic analysis apparatus. According to the method, an inclination of the microfluidic device with respect to a horizontal direction can be adjusted to simply and accurately control a fluid flow in the microfluidic device. Thus, a fluid conveyance can be completely controlled, and an inspection can be performed using only a small amount of sample. In addition, the method of controlling the fluid flow in the microfluidic device can be manually performed by a user. Thus, since a power is not required, the method of controlling the fluid flow in the microfluidic device can be economical and simple. The microfluidic analysis apparatus includes an inclination operation unit for causing an inclination change of a receiving part of the microfluidic device with respect to a horizontal plane and an inclination control part for controlling an operation of the inclination operation unit to simply and accurately control the fluid flow, thereby to accurately analyze the fluid. | 2010-06-24 |
20100159601 | Automated analysis of discrete sample aliquots - An automated apparatus and method for analyzing liquid samples by forming discrete sample aliquots (boluses) in an elongated conduit which contains a hydrophobic carrier liquid. Aliquots may be analyzed by adding at least one reagent to the sample aliquot that reacts selectively with an analyte contained therein. The reaction product, which is selective for the analyte of interest and proportional to its concentration, is measured with an appropriate detector. Intrinsic sample properties of the sample may also be measured without the need for adding chemical reagents. The invention enables simple and accurate testing of samples using time honored wet-chemical analysis methods in microliter volume regimes while producing remarkably small volumes of waste. | 2010-06-24 |
20100159602 | CARBON MEASUREMENT IN AQUEOUS SAMPLES USING OXIDATION AT ELEVATED TEMPERATURES AND PRESSURES - Apparatus and methods for measuring the concentrations of organic and inorganic carbon, or of other materials, in aqueous samples are described, together with related, specially adapted components and sub-assemblies and related control, operational and monitoring systems. | 2010-06-24 |
20100159603 | SAMPLE TESTING SYSTEM, SAMPLE TESTING METHOD, AND COMPUTER PROGRAM PRODUCT - A sample testing system comprising: a transporting apparatus; a testing apparatus for obtain a sample and performing testing on the obtained sample; and a controller. The controller executes operation of: controlling the transporting apparatus so as to transport the sample rack in first direction, such that each sample container held in a sample rack is transported to a obtaining position on which the testing apparatus obtains a sample and then the sample rack is transported toward the second position; changing, when retesting of a sample contained in a sample container is necessary, the transporting direction from the first direction to second direction, and then controlling the transporting apparatus so as to transport the sample container accommodating the sample, for which retesting is necessary, to the obtaining position again. Sample testing method and a computer program product are also disclosed. | 2010-06-24 |
20100159604 | AUTOMATED SOLUTION-PHASE ITERATIVE SYNTHESIS - The first method for iterative solution-phase biomolecule synthesis is described. The method requires only 3 or fewer equivalents of building block at each coupling cycle, and incorporates a FSPE step at the end of each coupling/deprotection sequence to eliminate most byproducts. | 2010-06-24 |
20100159605 | Method of Correction of Particle Interference to Hemoglobin Measurement - A method of correction of particle interference to hemoglobin measurement of a blood sample on a hematology analyzer is provided. The method includes mixing an aliquot of a blood sample with a lytic reagent to lyse red blood cells and forming a sample mixture; measuring absorbance of the sample mixture at a predetermined wavelength of a hemoglobin chromogen formed in the sample mixture, and obtaining an apparent hemoglobin concentration of the blood sample using obtained absorbance; measuring concentration and size of cellular particles remaining in the sample mixture; removing contribution of the cellular particles to the apparent hemoglobin concentration using the concentration and the size of the cellular particles to obtain a corrected hemoglobin concentration of the blood sample; and reporting the corrected hemoglobin concentration of the blood sample. | 2010-06-24 |
20100159606 | METHOD, DEVICE AND APPARATUS FOR MEASURING THE CONCENTRATION OF CREATININE, AND METHOD, DEVICE AND APPARATUS FOR MEASURING THE AMOUNT OF SALT USING THE SAME - A method for measuring a concentration of creatinine includes the steps of: (A) mixing a sample containing creatinine with a creatinine quantitative reagent containing a metal complex of at least one of hexacyanoferrate and hexacyanoruthenate in the absence of picric acid and any enzyme responsive to creatinine, to cause the creatinine to reduce the metal complex; (B) electrochemically or optically measuring the amount of the metal complex reduced in the step (A); and (C) determining the concentration of the creatinine contained in the sample from the amount of the reduced metal complex measured in the step (B). | 2010-06-24 |
20100159607 | IL1RL-1 AS A CARDIOVASCULAR DISEASE MARKER AND THERAPEUTIC TARGET - This invention pertains to methods and compositions for the diagnosis and treatment of cardiovascular conditions. More specifically, the invention relates to isolated molecules that can be used to diagnose and/or treat cardiovascular conditions including cardiac hypertrophy, myocardial infarction, stroke, arteriosclerosis, and heart failure. | 2010-06-24 |
20100159608 | ASSESSING HEART FAILURE IN PATIENTS WITH ATRIAL FIBRILLATIN USING GDF-15 AND NATRIURETIC PEPTIDES - The present invention is concerned with methods and devices for medical diagnosis. Specifically, it relates to a method of diagnosing heart failure in a subject exhibiting atrial fibrillation, the method comprising determining the amount of GDF-15 in a sample of the subject and comparing the amount of GDF-15 with a suitable reference amount whereby heart failure is to be diagnosed. Moreover, the present invention relates to a diagnostic device and a kit for carrying out the aforementioned method. | 2010-06-24 |
20100159609 | System and Method for Alkylation Process Analysis - A method and apparatus is provided for determining concentration of components in a liquid hydrocarbon mixture including hydrocarbons and water flowing through an alkylation process. A fluid flow path conveys the liquid continuously from the alkylation process through a first instrument configured for measuring a property of the liquid mixture, and having responsivities to concentration of the components, which are independent of the concentration of the water. A temperature detector generates temperature data for the liquid, and a second instrument measures another property of the liquid mixture. The instruments have mutually distinct responsivities to concentrations of the components. A processor captures data from the temperature detector and instruments, using the data with a model of responsivities of various concentrations of the components at various temperatures, to determine a temperature compensated concentration of the components while the liquid mixture flows continuously through the fluid flow path. | 2010-06-24 |
20100159610 | METHOD AND ASSEMBLY FOR DETERMINING THE TEMPERATURE OF A TEST SENSOR - An assembly determines an analyte concentration in a sample of body fluid. The assembly includes a test sensor having a fluid-receiving area for receiving a sample of body fluid, where the fluid-receiving area contains a reagent that produces a measurable reaction with an analyte in the sample. The assembly also includes a meter having a port or opening configured to receive the test sensor; a measurement system configured to determine a measurement of the reaction between the reagent and the analyte; and a temperature-measuring system configured to determine a measurement of the test-sensor temperature when the test sensor is received into the opening. The meter determines a concentration of the analyte in the sample according to the measurement of the reaction and the measurement of the test-sensor temperature. | 2010-06-24 |
20100159611 | HYDRATION/DEHYDRATION SENSOR - A fluidic assay device or test format that can regulate or control the sample flow rate and modulate the manifestation of test results to reduce or eliminate errors is described. The assay device has a substrate with a flow-rate control zone that regulates the amount of time needed for development and appearance of a visual signal in the observation-feedback zone until the color transition in the detection zone reaches color stability. The present invention also describes absorbent articles incorporating such an assay device and methods of monitoring dehydration or testing ion strength of a urine sample using such a test format. | 2010-06-24 |
20100159612 | SENSOR CHIP AND METHOD FOR USE THEREOF - A sensor chip has: a light transmitting outer package, a plurality of reaction chambers disposed inside the outer package; a plurality of first induction paths that are connected to the reaction chambers and introduce a sample liquid into the reaction chambers; a first induction path where the induction paths merge; an introducing portion that is connected to the induction path and introduces the sample liquid; second induction paths that are connected to the reaction chambers respectively; a second induction path where the induction paths merge, and a cavity portion constituting a suction portion that is connected to the induction path and sucks the sample liquid. The total lengths of the first induction paths that are connected to different reaction chambers are different from each other, and different types of test reagents are held in the plurality of reaction chambers respectively. | 2010-06-24 |
20100159613 | Method for assaying the antioxidant capacity of a skin care product - A method for assaying the antioxidant capacity of a skin care product, the method including preparing an emulsion base, dissolving a sample of a skin care product into the emulsion base to form a homogeneous emulsion mixture, adding a detection probe to the homogeneous emulsion mixture, adding reactive oxygen species generator and/or reactive nitrogen species generator to the homogeneous emulsion mixture, measuring the fluorescence intensity change of the detection probe in the presence of the sample over time, in the presence of the standard over time, and in the presence of a blank over time, and calculating the initial rate of oxidation of the detection probe to determine the antioxidant capacity of the sample of the skin care product. | 2010-06-24 |
20100159614 | BIOCHIP AND APPARATUS FOR DETECTING BIOMATERIAL USING BIOCHIP - Provided is a biochip and an apparatus for detecting a biomaterial. The biochip includes a metal thin film on the surface of a substrate, restraining autofluorescence of the substrate, and a spacer on the metal thin film, having capture molecules immobilized on the surface of the spacer and specifically bound to target molecules. The spacer has a thickness controlled to enhance the strength of a fluorescence signal emitted from a fluorophore labeled with the target molecules and immobilized on the spacer by the specific binding between the capture molecule and the target molecule. | 2010-06-24 |
20100159615 | IMMUNOLOGICAL DETECTION METHOD USING AVIAN ANTIBODY - An object of the present invention is to provide an immunological detection method using an avian antibody, comprising suppressing a non-specific reaction caused by using an avian antibody. According to the present invention, there is provided an immunological detection method comprising detecting a target substance in a sample from a mammal using an avian antibody, characterized in that a non-specific reaction induced by the use of the avian antibody is suppressed. | 2010-06-24 |
20100159616 | Bio-Chip of Pattern-Arranged in Line, Method for Manufacturing the Same, and Method for Detecting an Analyte Bound in the Same - A bio-chip has a base plate, and a fluid resin layer positioned on the base plate and having a plurality of convexo-concave structures that are uniformly arranged in line. Side walls of the structures form reflecting films to form a Fabry-Perot interferometer structure. The bio-chip is used to detect an analyte provided to the bio-chip, so that it is possible to rapidly analyze the small amount of samples and to realize the detection sensitivity relatively higher than the conventional method. | 2010-06-24 |
20100159617 | SEMICONDUCTOR-DEVICE MANUFACTURING METHOD AND EXPOSURE METHOD - A semiconductor-device manufacturing method includes steps of performing a sidewall fabrication thereby forming a first pattern structure; measuring an amount of displacement of line portions of the first pattern structure; correcting an overlay specification for an overlay of the first pattern structure and a second pattern structure dynamically based on the amount of displacement; and determining whether an error in the overlay of the first pattern structure and the second pattern structure meets the corrected overlay specification. | 2010-06-24 |
20100159618 | Assembly of ordered carbon shells on semiconducting nanomaterials - In some embodiments of the invention, encapsulated semiconducting nanomaterials are described. In certain embodiments the nanostructures described are semiconducting nanomaterials encapsulated with ordered carbon shells. In some aspects a method for producing encapsulated semiconducting nanomaterials is disclosed. In some embodiments applications of encapsulated semiconducting nanomaterials are described. | 2010-06-24 |
20100159619 | METHOD FOR CRYSTALLIZING THIN FILM, METHOD FOR MANUFACTURING THIN FILM SEMICONDUCTOR DEVICE, METHOD FOR MANUFACTURING ELECTRONIC APPARATUS, AND METHOD FOR MANUFACTURING DISPLAY DEVICE - A gate insulating film ( | 2010-06-24 |
20100159620 | MANUFACTURING METHOD OF LIGHT EMITTING DIODE - Disclosed is a manufacturing method of a light emitting diode. The manufacturing method comprises the steps of preparing a substrate and mounting light emitting chips on the substrate. An intermediate plate is positioned on the substrate. The intermediate plate has through-holes for receiving the light emitting chips and grooves for connecting the through-holes to one another on its upper surface. A transfer molding process is performed with a transparent molding material by using the grooves as runners to form first molding portions filling the through-holes. Thereafter, the intermediate plate is removed, and the substrate is separated into individual light emitting diodes. Accordingly, it is possible to provide a light emitting diode in which the first molding portion formed through a transfer molding process is positioned within a region encompassed by cut surfaces of the substrate. Since the first molding portion is positioned within the region encompassed by the cut surfaces of the substrate, second molding portions can be symmetrically formed on the side surfaces of the first molding portions in various manners. | 2010-06-24 |
20100159621 | SURFACE-MOUNT TYPE OPTICAL SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A small and thin surface-mount type optical semiconductor device having high air tightness, which can be manufactured at a reduced cost includes: a base | 2010-06-24 |
20100159622 | LIGHT EMITTING DEVICE AND METHOD OF FORMING THE SAME - A light-emitting device includes a transparent substrate, a transparent adhesive layer on the transparent substrate, a first transparent conductive layer on the transparent adhesive layer, a multi-layer epitaxial structure and a first electrode on the transparent conductive layer, and a second electrode on the multi-layer epitaxial structure. The multi-layer epitaxial structure includes a light-emitting layer. The transparent substrate has a first surface facing the transparent adhesive layer and a second surface opposite to the first surface, wherein the area of the second surface is larger than that of the light-emitting layer, and the area ratio thereof is not less than 1.6. | 2010-06-24 |
20100159623 | Method for fabricating a liquid crystal display device and an LCD device thereby - A method for fabricating a LCD having enhanced aperture ratio and brightness includes: forming a gate line, a gate electrode, a common electrode and a common line in a first mask process; depositing a gate insulating layer covering the gate line, the gate electrode and the common electrode; forming an active layer on the gate insulating layer, and an ohmic contact layer on the active layer in a second mask process; forming a data line, a source electrode, and a drain electrode facing the source electrode in a third mask process; depositing a protective layer over the data line, the source electrode and the drain electrode; forming a pixel contact hole in a fourth mask process; and forming a pixel electrode, wherein the pixel electrode is connected to the drain electrode through the pixel contact hole in a fifth mask process using a reverse tapered photo-resist pattern. | 2010-06-24 |
20100159624 | ETCHANT FOR ETCHING DOUBLE-LAYERED COPPER STRUCTURE AND METHOD OF FORMING ARRAY SUBSTRATE HAVING DOUBLE-LAYERED COPPER STRUCTURES - An etchant for forming double-layered signal lines and electrodes of a liquid crystal display device includes hydrogen peroxide (H | 2010-06-24 |
20100159625 | Method for Manufacturing P Type Gallium Nitride Based Device - A method for manufacturing a p-type gallium nitride-based (GaN) device is disclosed. In accordance with the method, an Mg in an MgN | 2010-06-24 |
20100159626 | Nitride semiconductor light-emitting device and method for fabrication thereof - An adhesion layer of a hexagonal crystal is laid on a facet an optical resonator of a nitride semiconductor laser bar having a nitride-based III-V group compound semiconductor layer, and a facet coat is laid on the adhesion layer. In this way, a structure in which the facet coat is laid on the adhesion layer is obtained. | 2010-06-24 |
20100159627 | CRACK AND RESIDUE FREE CONFORMAL DEPOSITED SILICON OXIDE WITH PREDICTABLE AND UNIFORM ETCHING CHARACTERISTICS - A silicon oxide layer is formed by oxidation or decomposition of a silicon precursor gas in an oxygen-rich environment followed by annealing. The silicon oxide layer may be formed with slightly compressive stress to yield, following annealing, an oxide layer having very low stress. The silicon oxide layer thus formed is readily etched without resulting residue using HF-vapor. | 2010-06-24 |
20100159628 | MANUFACTURING METHOD OF IMAGE SENSOR OF VERTICAL TYPE - A manufacturing method of an image sensor of vertical type is provided that includes: forming an insulation layer with a metal wiring and a contact plug therein on a first substrate; bonding a second substrate having an image sensing unit over the insulation layer; forming a trench in the second substrate to divide the image sensing unit for each pixel; forming a PTI by gap-filling the trench with insulating material; forming a first material layer over the PTI, the image sensing unit, and the insulation layer; and forming a second material layer over the first material layer and performing a deuterium annealing process thereon. The crystal defects of the substrate generated when performing the trench etching on the donor substrate to define unit pixels are cured by performing the deuterium annealing process, making it possible to improve the sensitivity and illumination characteristics of the image sensor of vertical type. | 2010-06-24 |
20100159629 | METHOD TO TEXTURE A LAMINA SURFACE WITHIN A PHOTOVOLTAIC CELL - It is advantageous to create texture at the surface of a photovoltaic cell to reduce reflection and increase travel length of light within the cell. A method is disclosed to create texture at the surface of a silicon body by reacting a silicide-forming metal at the surface, where the silicide-silicon interface is non-planar, then stripping the silicide, leaving behind a textured surface. Depending on the metal and the conditions of silicide formation, the resulting surface may be faceted. The peak-to-valley height of this texturing will generally be between about 300 and about 5000 angstroms, which is well-suited for use in photovoltaic cells comprising a thin silicon lamina. | 2010-06-24 |
20100159630 | METHOD FOR MAKING A PHOTOVOLTAIC CELL COMPRISING CONTACT REGIONS DOPED THROUGH A LAMINA - In aspects of the present invention, a method is disclosed to form a lamina having opposing first and second surfaces. Heavily doped contact regions extend from the first surface to the second surface. Generally the lamina is formed by affixing a semiconductor donor body to a receiver element, then cleaving the lamina from the semiconductor donor body wherein the lamina remains affixed to the receiver element. In the present invention, the heavily doped contact regions are formed by doping the semiconductor donor body before cleaving of the lamina. A photovoltaic cell comprising the lamina is then fabricated. By forming the heavily doped contact regions before bonding to the receiver element and cleaving, post-bonding high-temperature steps can be avoided, which may be advantageous. | 2010-06-24 |
20100159631 | Reduced dark current photodetector - A photo-detector comprising: a photo absorbing layer comprising an n-doped semiconductor exhibiting a valence band energy level; a barrier layer, a first side of the barrier layer adjacent a first side of the photo absorbing layer, the barrier layer exhibiting a valence band energy level substantially equal to the valence band energy level of the doped semiconductor of the photo absorbing layer; and a contact area comprising a doped semiconductor, the contact area being adjacent a second side of the barrier layer opposing the first side, the barrier layer exhibiting a thickness and a conductance band gap sufficient to prevent tunneling of majority carriers from the photo absorbing layer to the contact area and block the flow of thermalized majority carriers from the photo absorbing layer to the contact area. Alternatively, a p-doped semiconductor is utilized, and conductance band energy levels of the barrier and photo absorbing layers are equalized. | 2010-06-24 |
20100159632 | TECHNIQUE FOR FABRICATION OF BACKSIDE ILLUMINATED IMAGE SENSOR - An array of backside illuminated image sensors is fabricated using a number of processes. These processes include fabricating front side components of the backside illuminated image sensors into or onto a first side of an epitaxial layer disposed over a substrate layer. Dopants are diffused from the substrate through a second side of the epitaxial layer to create a dopant gradient band in the epitaxial layer adjacent to the substrate layer. The backside of the array is then thinned to remove the substrate layer while retaining at least a portion of the dopant gradient band in the epitaxial layer. | 2010-06-24 |
20100159633 | METHOD OF MANUFACTURING PHOTOVOLTAIC DEVICE - Provided is a method of manufacturing a photovoltaic device using a Joule heating-induced crystallization method. The method includes: forming a first conductive pattern on a substrate; forming a photoelectric conversion layer on the substrate having the first conductive pattern; and crystallizing at least part of the photoelectric conversion layer by applying an electric field to the photoelectric conversion layer, wherein the photoelectric conversion layer includes a first amorphous semiconductor layer containing first impurities, a second intrinsic, amorphous semiconductor layer, and a third amorphous semiconductor layer containing second impurities. | 2010-06-24 |
20100159634 | EDGE FILM REMOVAL PROCESS FOR THIN FILM SOLAR CELL APPLICATIONS - The present invention provides a method and apparatus for edge film stack removal process for fabricating photovoltaic devices. In one embodiment, a method for manufacturing solar cell devices on a substrate includes providing a substrate into a chemical vapor deposition chamber, contacting a shadow frame disposed in the deposition chamber to a periphery region of the substrate, depositing a silicon-containing layer on the substrate through an aperture defined by the shadow frame, transferring the substrate to a physical vapor deposition chamber, depositing a transparent conductive layer on the silicon-containing layer, transferring the substrate to a laser edge removal tool, and laser scribing the layers formed on the periphery region of the substrate. | 2010-06-24 |
20100159635 | METHOD OF PATTERNING CONDUCTIVE LAYER AND DEVICES MADE THEREBY - Methods for patterning a conductor through oxidation are provided. Devices fabricated using the method include organic transistors having a gate electrode and dielectric layer patterned by the method, source and drain electrodes, and an organic semiconducting layer. | 2010-06-24 |
20100159636 | METHOD OF FORMING PHASE CHANGE LAYER AND METHOD OF MANUFCTURING PHASE CHANGE MEMORY DEVICE USING THE SAME - Disclosed herein are a method of forming a stable phase change layer without generating seams, and a method of manufacturing phase change memory device using the same. In the method of forming a phase change layer, the phase change layer is formed by performing a first deposition process of a phase change material, performing an etching process so as to etch the phase change material, and performing a second deposition process of a phase change material on the etched phase change material. The etching process and the second deposition process are performed a predetermined number of times. | 2010-06-24 |
20100159637 | Antimony precursor, phase-change memory device using the antimony precursor, and method of manufacturing the phase-change memory device - An antimony precursor including antimony, nitrogen and silicon, a phase-change memory device using the same, and a method of making the phase-change memory device. The phase-change memory device may have a phase-change film of a Ge | 2010-06-24 |
20100159638 | Method of fabricating nonvolatile memory device - A method of manufacturing a nonvolatile memory device including forming on a lower insulating layer a first sacrificial pattern having first openings extending in a first direction, forming a second sacrificial pattern having second openings extending in a second direction on the lower insulating layer and the first sacrificial pattern wherein the second openings intersect the first openings, etching the lower insulating layer using the first and second sacrificial patterns to form a lower insulating pattern having contact holes defined by a region where the first and second openings intersect each other, forming a bottom electrode in the contact holes, and forming a variable resistance pattern on the lower insulating pattern so that a portion of the variable resistance pattern connects to a top surface of the bottom electrode. | 2010-06-24 |
20100159639 | METHOD FOR MANUFACTURING TRANSISTOR - A hydrogen barrier layer is selectively provided over an oxide semiconductor layer including hydrogen and hydrogen is selectively desorbed from a given region in the oxide semiconductor layer by conducting oxidation treatment, so that regions with different conductivities are formed in the oxide semiconductor layer. After that, a channel formation region, a source region, and a drain region can be formed with the use of the regions with different conductivities formed in the oxide semiconductor layer. | 2010-06-24 |
20100159640 | METHOD AND APPARATUS FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method and apparatus for manufacturing a semiconductor device is disclosed, which is capable of realizing an extension of a cleaning cycle for a processing chamber, the method comprising preheating a substrate; placing the preheated substrate onto a substrate-supporting unit provided in a susceptor while the preheated substrate is maintained at a predetermined height from an upper surface of the susceptor provided in a processing chamber; and forming a thin film on the preheated substrate, wherein a temperature of the preheated substrate is higher than a processing temperature for forming the thin film in the processing chamber. | 2010-06-24 |
20100159641 | Memory cell formation using ion implant isolated conductive metal oxide - Memory cell formation using ion implant isolated conductive metal oxide is disclosed, including forming a bottom electrode below unetched conductive metal oxide layer(s), forming the unetched conductive metal oxide layer(s) including depositing at least one layer of a conductive metal oxide (CMO) material (e.g., PrCaMnO | 2010-06-24 |
20100159642 | Methods of manufacturing oxide semiconductor thin film transistor - Provided is a method of manufacturing an oxide semiconductor thin film transistor using a transparent oxide semiconductor as a material for a channel. The method of manufacturing the oxide semiconductor thin film transistor includes forming a passivation layer on a channel layer and performing an annealing process for one hour or more at a temperature of about 100° C. or above. | 2010-06-24 |
20100159643 | BONDING IC DIE TO TSV WAFERS - A method for bonding IC die to TSV wafers includes bonding at least one singulated IC die to respective ones of a plurality of IC die on a TSV wafer that includes a top semiconductor surface and TSV precursors including embedded TSV tips to form a die-wafer stack. The die-wafer stack is thinned beginning from the bottom surface of the TSV wafer to form a thinned die-wafer stack. The thinning includes exposing the embedded TSV tips to provide electrical access thereto from the bottom surface of the TSV wafer. The thinned die-wafer stack can be singulated to form a plurality of thinned die stacks. | 2010-06-24 |
20100159644 | LOW-COST FLIP-CHIP INTERCONNECT WITH AN INTEGRATED WAFER-APPLIED PHOTO-SENSITIVE ADHESIVE AND METAL-LOADED EPOXY PASTE SYSTEM - Various exemplary embodiments provide materials and methods for flip-chip packaging technology. The disclosed flip-chip packaging technology can use a single B-stage wafer-applied photo-sensitive adhesive along with printed interconnects, which does not include conventional underfill materials and processes. In one embodiment, a photo-sensitive adhesive can be applied on a semiconductor die or a base substrate with conductive bumps printed in through-openings of the photo-sensitive adhesive. One or more semiconductor dies can be laterally packaged or vertically stacked on the base substrate using the printed conductive bumps as interconnects there-between. | 2010-06-24 |
20100159645 | SEMICONDUCTOR APPARATUS AND PROCESS OF PRODUCTION THEREOF - A method of producing a semiconductor apparatus, the method including forming metal ball bumps in direct contact with a circuit pattern of a semiconductor device, forming a resin film to seal spaces between the metal ball bumps, cleaning the surfaces of the metal ball bumps projecting out from the resin film using plasma cleaning by removing components inviting a rise in a connection resistance and a decline in a joint strength, forming eutectic solder layers different in composition from the metal ball bumps on the surfaces of the metal ball bumps, cutting the semiconductor substrate into unit semiconductor chips, and mounting at least one of the chips on a mounting board from a bump forming surface side of the chip so as to connect the eutectic solder layers to the mounting board with the resin film directly contacting the chip and not directly contacting the mounting board. | 2010-06-24 |
20100159646 | Method of manufacturing wafer level package - The present invention relates to a method of manufacturing a wafer level package including the steps of: preparing a substrate wafer including a plurality of pads formed on a bottom surface, a plurality of chips positioned on a top surface, and dicing lines for dividing the chips; forming external connection units on the pads; coating resin on the dicing lines by positioning masks on the substrate wafer to expose only the dicing lines; removing the masks; encapsulating the chips positioned between the resin by coating the chips with encapsulant; removing the resin coated on the dicing lines; and cutting a wafer level package along the dicing lines exposed by removing the resin into units. | 2010-06-24 |
20100159647 | MULTILAYER PRINTED CIRCUIT BOARD AND THE MANUFACTURING METHOD THEREOF - A multilayer printed circuit board, wherein, on a resin-insulating layer that houses a semiconductor element, another resin-insulating layer and a conductor circuit are formed with conductor circuits electrically connected through a via hole, wherein a electromagnetic shielding layer is formed on a resin-insulating layer surrounding a concave portion for housing a semiconductor element or on the inner wall surface of the concave portion, and the semiconductor element is embedded in the concave portion. | 2010-06-24 |
20100159648 | ELECTROPHOTOGRAPH PRINTED ELECTRONIC CIRCUIT BOARDS - The present invention provides a device for producing printed electronic circuits using electrophotography | 2010-06-24 |
20100159649 | Method of fabricating a deep trench insulated gate bipolar transistor - In one embodiment, a method comprises forming an epitaxial layer over a substrate of an opposite conductivity type, the epitaxial layer being separated by a buffer layer having a doping concentration that is substantially constant in a vertical direction down to the buffer layer. A pair of spaced-apart trenches is formed in the epitaxial layer from a top surface of the epitaxial layer down at least into the buffer layer. A dielectric material is formed in the trenches over the first and second sidewall portions. Source/collector and body regions of are formed at the top of the epitaxial layer, the body region separating the source/collector region of the pillar from a drift region of the epitaxial layer that extends from the body region to the buffer layer. An insulated gate member is then formed in each of the trenches adjacent to and insulated from the body region. | 2010-06-24 |
20100159650 | Methods of fabricating semiconductor device having capacitorless one-transistor memory cell - A method of fabricating a semiconductor device having a capacitorless one-transistor memory cell includes forming a first floating body pattern on a lower insulating layer of a substrate and a first gate pattern crossing over the first floating body pattern and covering sidewalls of the first floating body pattern is formed. The first floating body pattern at both sides of the first gate pattern is partially etched to form a protrusion portion extending between and above the partially etched regions, and first impurity regions are formed in the partially etched regions of the first floating body pattern. | 2010-06-24 |
20100159651 | METHOD OF FORMING NANOCRYSTALS - Nanocrystals are formed over an insulating layer by depositing a semiconductor layer over the insulating layer. The semiconductor layer is annealed to form a plurality of globules from the semiconductor layer. The globules are annealed using oxygen. Semiconductor material is deposited on the plurality of globules to add semiconductor material to the globules. After depositing the semiconductor material, the globules are annealed to form the nanocrystals. The nanocrystals can then be used in a storage layer of a non-volatile memory cell, especially a split-gate non-volatile memory cell having a select gate over the nanocrystals and a control gate adjacent to the select gate. | 2010-06-24 |
20100159652 | METHOD OF MANUFACTURING A THIN FILM TRANSISTOR ARRAY SUBSTRATE - In manufacturing a thin film transistor array substrate, a passivation film is formed over the transistors. A first photoresist pattern is formed over the passivation film, with a first portion partially overlying at least one source/drain electrode of each transistor and overlying each pixel electrode region, and with a second portion thicker than the first portion. The passivation film is patterned using the first photoresist pattern as a mask. The first photoresist pattern's first portion is removed to form a second photoresist pattern which protrudes upward around the pixel electrode regions. A transparent conductive film is formed with recesses in the pixel electrode regions. A masking pattern is formed over the transparent film in each pixel electrode region, the masking pattern's top surface being below a top of the transparent film. The transparent film is patterned using the masking pattern as a mask to form the pixel electrodes. | 2010-06-24 |
20100159653 | METHOD FOR MANUFACTURING ION IMPLANTATION MASK, AND METHOD FOR MANUFACTURING SILICON CARBIDE SEMICONDUCTOR DEVICE - A method for manufacturing an ion implantation mask is disclosed which includes the steps of: forming an oxide film as a protective film over the entire surface of a semiconductor substrate; forming a thin metal film over the oxide film; and forming an ion-inhibiting layer composed of an ion-inhibiting metal over the thin metal film. The obtained ion implantation mask is used to form a deeper selectively electroconductive region. | 2010-06-24 |
20100159654 | SEMICONDUCTOR DEVICE HAVING BULB-SHAPED RECESS GATE AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes: a substrate; a first junction region and a second junction region formed separately from each other to a certain distance in the substrate; an etch barrier layer formed in the substrate underneath the first junction region; and a plurality of recess channels formed in the substrate between the first junction region and the second junction region. | 2010-06-24 |
20100159655 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR MEMORY DEVICES - A semiconductor memory device has a floating gate formed on a semiconductor substrate at certain intervals along a plane with a first insulator interposed therebetween, and a control gate formed on the layer of floating gates with a second insulator interposed therebetween. The device includes a semiconductor layer formed by selectively epitaxially growing the semiconductor substrate between the floating gates on the semiconductor substrate with a third insulator interposed therebetween. | 2010-06-24 |
20100159656 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A method for fabricating a semiconductor device includes: forming a GaN-based semiconductor layer on a substrate; forming a gate insulating film of aluminum oxide on the GaN-based semiconductor layer at a temperature equal to or lower than 450° C.; forming a protection film on an upper surface of the gate insulating film; performing a process with an alkaline solution in a state in which the upper surface of the gate insulating film is covered with the protection film; and forming a gate electrode on the gate insulating film. | 2010-06-24 |
20100159657 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor memory device includes: a semiconductor substrate, on which an impurity diffusion layer is formed in a cell array area; a gate wiring stack body formed on the cell array area, in which multiple gate wirings are stacked and separated from each other with insulating films; a gate insulating film formed on the side surface of the gate wiring stack body, in which an insulating charge storage layer is contained; pillar-shaped semiconductor layers arranged along the gate wiring stack body, one side surfaces of which are opposed to the gate wiring stack body via the gate insulating film, each pillar-shaped semiconductor layer having the same conductivity type as the impurity diffusion layer; and data lines formed to be in contact with the upper surfaces of the pillar-shaped semiconductor layers and intersect the gate wirings. | 2010-06-24 |
20100159658 | HIGH SPEED LATERAL HETEROJUNCTION MISFETS REALIZED BY 2-DIMENSIONAL BANDGAP ENGINEERING AND METHODS THEREOF - A method for forming and the structure of a strained lateral channel of a field effect transistor, a field effect transistor and CMOS circuitry is described incorporating a drain, body and source region on a single crystal semiconductor substrate wherein a hetero-junction is formed between the source and body of the transistor, wherein the source region and channel are independently lattice strained with respect the body region. The invention reduces the problem of leakage current from the source region via the hetero junction and lattice strain while independently permitting lattice strain in the channel region for increased mobility via choice of the semiconductor materials and alloy composition. | 2010-06-24 |
20100159659 | SEMICONDUCTOR DEVICE USED AS HIGH-SPEED SWITCHING DEVICE AND POWER DEVICE - A low resistance layer is formed on a semiconductor substrate, and a high resistance layer formed on the low resistance layer. A source region of a first conductivity type is formed on a surface region of the high resistance layer. A drain region of the first conductivity type is formed at a distance from the source region. A first resurf region of the first conductivity type is formed in a surface region of the high resistance layer between the source region and the drain region. A channel region of a second conductivity type is formed between the source region and the first resurf region. A gate insulating film is formed on the channel region, and a gate electrode formed on the gate insulating film. An impurity concentration in the channel region under the gate electrode gradually lowers from the source region toward the first resurf region. | 2010-06-24 |
20100159660 | METHOD OF MANUFACTURING FLASH MEMORY DEVICE - A method of manufacturing a flash memory device includes preparing a semiconductor substrate comprising a cell area and a peripheral area, forming a first well and an oxide-nitride-oxide (ONO) layer in the cell area, forming a second well in the peripheral area of the semiconductor substrate comprising the first well and forming a first oxide layer in the peripheral area, forming a first polysilicon layer over the ONO layer and the first oxide layer and performing a first etch process to form a memory gate comprising an ONO layer pattern and a first polysilicon pattern in the cell area, forming a second oxide layer pattern and a second polysilicon pattern over either sidewall of the memory gate and forming a gate in the peripheral area, performing a third etch process so that the second oxide layer pattern and the second polysilicon pattern remain over only the one sidewall of the memory gate to form a select gate, and forming a first impurity area in the semiconductor substrate between the memory gates adjacent to each other. | 2010-06-24 |
20100159661 | NONVOLATILE SEMICONDUCTOR STORAGE DEVICE AND MANUFACTURING METHOD THEREOF - An object of the present invention is to provide a nonvolatile semiconductor storage device with a superior charge holding characteristic in which highly-efficient writing is possible at low voltage, and to provide a manufacturing method thereof. | 2010-06-24 |
20100159662 | RAISED SOURCE/DRAIN WITH SUPER STEEP RETROGRADE CHANNEL - Systems and methods for raised source/drain with super steep retrograde channel. In accordance with a first embodiment of the present invention, in one embodiment, a semiconductor device comprises a substrate comprising a surface and a gate oxide disposed above the surface comprising a gate oxide thickness. The semiconductor device further comprises a super steep retrograde channel region formed at a depth below the surface. The depth is about ten to thirty times the gate oxide thickness. Embodiments in accordance with one embodiment may provide a more desirable body biasing voltage to threshold voltage characteristic than is available under the conventional art. | 2010-06-24 |
20100159663 | METHOD OF FABRICATING HIGH INTEGRATED SEMICONDUCTOR APPARATUS, AND SEMICONDUCTOR APPARATUS FABRICATED THEREBY - The present invention provides a method of fabricating a semiconductor apparatus including a vertical transistor and a semiconductor apparatus fabricated thereby which protect a pillar-shaped channel region to stabilize an operating characteristic of the semiconductor apparatus. The method of fabricating the semiconductor apparatus according to the present invention comprises: forming a pillar-shaped pattern on a semiconductor substrate; depositing a conductive layer surrounding the pattern; changing a feature of some portion of the conductive layer through an ion implanting process to form an oxide film; and removing the oxide film using an etching selectivity difference. | 2010-06-24 |
20100159664 | SILICON GERMANIUM HETEROJUNCTION BIPOLAR TRANSISTOR STRUCTURE AND METHOD - Disclosed is an improved semiconductor structure (e.g., a silicon germanium (SiGe) hetero-junction bipolar transistor) having a narrow essentially interstitial-free SIC pedestal with minimal overlap of the extrinsic base. Also, disclosed is a method of forming the transistor which uses laser annealing, as opposed to rapid thermal annealing, of the SIC pedestal to produce both a narrow SIC pedestal and an essentially interstitial-free collector. Thus, the resulting SiGe HBT transistor can be produced with narrower base and collector space-charge regions than can be achieved with conventional technology. | 2010-06-24 |
20100159665 | CAPACITOR FORMED ON A RECRYSTALLIZED POLYSILICON LAYER - The present invention provides a semiconductor device, a method of manufacture therefor, and an integrated circuit including the semiconductor device. The semiconductor device, among other elements, includes a recrystallized polysilicon layer | 2010-06-24 |
20100159666 | INTEGRATION OF CAPACITIVE ELEMENTS IN THE FORM OF PEROVSKITE CERAMIC - The use of a conductive bidimensional perovskite as an interface between a silicon, metal, or amorphous oxide substrate and an insulating perovskite deposited by epitaxy, as well as an integrated circuit and its manufacturing process comprising a layer of an insulating perovskite deposited by epitaxy to form the dielectric of capacitive elements having at least an electrode formed of a conductive bidimensional perovskite forming an interface between said dielectric and an underlying silicon, metal, or amorphous oxide substrate. | 2010-06-24 |
20100159667 | Methods of Forming Capacitors - A method of forming a capacitor includes providing material having an opening therein over a node location on a substrate. A shield is provided within and across the opening, with a void being received within the opening above the shield and a void being received within the opening below the shield. The shield is etched through within the opening. After the etching, a first capacitor electrode is formed within the opening in electrical connection with the node location. A capacitor dielectric and a second capacitor electrode are formed operatively adjacent the first capacitor electrode | 2010-06-24 |
20100159668 | METHOD FOR MANUFACTURING RESERVOIR CAPACITOR OF SEMICONDUCTOR DEVICE - A method for manufacturing a reservoir capacitor of a semiconductor device reduces the resistance of the reservoir capacitor to secure reliability of the semiconductor device. The method comprises: forming a dummy pattern having a lattice structure over a transistor; forming a first interlayer insulating film over the resulting structure including the dummy pattern; etching the first interlayer insulating film to form a line-structured storage node contact region between the lattice structures; and filling a conductive layer in the line-structured storage node contact region to form a line-structured storage node contact. | 2010-06-24 |
20100159669 | METHOD FOR FORMING DEEP TRENCH IN SEMICONDUCTOR DEVICE - A method for forming a deep trench in a semiconductor device includes: forming a hard mask over a substrate, forming a hard mask pattern over the substrate through etching the hard mask to thereby expose an upper portion of the substrate, forming a first trench through a first etching the exposed substrate using a gas containing bromide and a gas containing chloride and forming a second trench through a second etching the first trench using of a gas containing sulfur and fluorine, wherein a depth of the second trench is deeper than a depth of the first trench. | 2010-06-24 |
20100159670 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - The invention enhances the accuracy of an end point detection when an insulation film formed on a semiconductor substrate is dry-etched. Gate layers made of polysilicon are formed, and an end point detection dummy layer made of polysilicon is formed on a LOCOS. After the gate layers and the dummy layer are formed, a TEOS film is formed on a silicon substrate so as to cover the gate layers and the dummy layer. The TEOS film, a thin gate oxide film and a thick gate oxide film are then dry-etched to form sidewalls on the sidewalls of the gate layers and also expose the front surface of the P well of the silicon substrate in a region surrounded by the LOCOS. The end point detection dummy layer helps the end point detection by being exposed during this dry-etching to enhance the accuracy of the end point detection. | 2010-06-24 |
20100159671 | Neutron Detection Structure and Method of Fabricating - A method of fabricating a neutron detection structure includes temporarily bonding a carrier to a passivated SOI SRAM wafer, removing a first substrate, depositing a conversion layer where at least a portion of the first substrate was removed, permanently bonding a second substrate to the conversion layer, removing the carrier, and providing at least one electrical contact to the device layer. A method of fabricating a neutron detection structure, corresponding to an alternate embodiment, includes temporarily bonding a carrier to a passivated SOI SRAM wafer, removing a first substrate, depositing a conversion layer onto a second substrate, permanently bonding the coated substrate where at least a portion of the first substrate was removed, removing the carrier, and providing at least one electrical contact to the device layer. | 2010-06-24 |
20100159672 | METHOD AND DEVICE FOR CLEANING ELECTRONIC COMPONENTS PROCESSED WITH A LASER BEAM - The present invention relates to a method for processing with a laser beam and cleaning electronic components, wherein at least one new boundary surface is formed on an electronic component with the laser beam. The invention also relates to a device for processing and cleaning electronic components, comprising at least: a laser source for generating a laser beam, and at least one carrier for supporting an assembly of unseparated electronic components, wherein the carrier and the laser beam are displaceable relative to each other. | 2010-06-24 |
20100159673 | METHOD OF CUTTING AN ELECTRICAL FUSE - A semiconductor device includes a semiconductor substrate, and an electrical fuse including a first conductor including a first cutting target region, and a second conductor branched from the first conductor and connected to the first conductor and including a second cutting target region, which are formed on the semiconductor substrate, wherein a flowing-out region is formed of the first conductor flowing toward outside between the first cutting target region and the second cutting target region in a condition of cutting the electrical fuse. | 2010-06-24 |
20100159674 | METHOD OF FABRICATING SEMICONDUCTOR DEVICE - Provided is a method of fabricating a semiconductor device. The method includes forming a first layer, a second layer, an ion implantation layer between the first and second layers, and an anti-oxidation layer on the second layer, and performing a heat treating process to form an insulating layer between the first and second layers while preventing loss of the second layer using the anti-oxidation layer. | 2010-06-24 |
20100159675 | METHOD FABRICATING NONVOLATILE MEMORY DEVICE - A method of fabricating a nonvolatile memory device includes; forming a first sacrificial layer pattern including a first open area that extends in a first direction on a lower dielectric layer, forming a pre-lower dielectric layer pattern including a recess that extends in the first direction using the first sacrificial layer pattern, forming a second sacrificial layer pattern including a second open area that extends in a second direction on the pre-lower dielectric layer pattern and the first sacrificial layer pattern, wherein the second open area intersects the first open area, forming a lower dielectric layer pattern including contact holes spaced apart in the recess using the first sacrificial layer pattern and second sacrificial layer pattern, wherein the contact holes extend to a bottom of the lower dielectric layer pattern, and forming a bottom electrode in the contact hole. | 2010-06-24 |
20100159676 | Method For Manufacturing A Mono-Crystalline Semiconductor Layer on a Substrate - The described system relates to a method for forming a layer of a mono-crystalline semiconductor material on a substrate comprising providing a substrate, growing epitaxially a template comprising at least one monolayer of a semiconductor material on the substrate, thereafter depositing an amorphous layer of said semiconductor material on the template, and performing a thermal treatment or a laser anneal, thereby converting substantially all of the amorphous layer of the semiconductor material into a mono-crystalline layer of said semiconductor material. According to an embodiment, the semiconductor material is Ge, and the substrate is a Si substrate. The template is preferably a few monolayers thick. | 2010-06-24 |
20100159677 | SOLID-PHASE SHEET GROWING SUBSTRATE AND METHOD OF MANUFACTURING SOLID-PHASE SHEET - A solid-phase sheet growing substrate ( | 2010-06-24 |
20100159678 | GERMANIUM SUBSTRATE-TYPE MATERIALS AND APPROACH THEREFOR - Germanium circuit-type structures are facilitated. In one example embodiment, a multi-step growth and anneal process is implemented to grow Germanium (Ge) containing material, such as heteroepitaxial-Germanium, on a substrate including Silicon (Si) or Silicon-containing material. In certain applications, defects are generally confined near a Silicon/Germanium interface, with defect threading to an upper surface of the Germanium containing material generally being inhibited. These approaches are applicable to a variety of devices including Germanium MOS capacitors, pMOSFETs and optoelectronic devices. | 2010-06-24 |
20100159679 | MANUFACTURING METHOD FOR EPITAXIAL WAFER - To provide a manufacturing method for an epitaxial wafer that alleviates distortions on a back surface thereof due to sticking between a wafer and a susceptor, thereby preventing decrease in flatness thereof due to a lift pin. A manufacturing method for an epitaxial wafer according to the present invention includes: an oxide film forming step in which an oxide film is formed on a back surface thereof; an etching step in which a hydrophobic portion exposing a back surface of the semiconductor wafer is provided by partially removing the oxide film; a wafer placing step in which the semiconductor wafer is placed; and an epitaxial growth step in which an epitaxial layer is grown on a main surface of the semiconductor wafer; and the diameter of the lift pin installation circle provided on a circle on a bottom face of a susceptor is smaller than that of the hydrophobic portion. | 2010-06-24 |
20100159680 | Method for Manufacturing Semiconductor Device - A method for manufacturing a semiconductor device is disclosed. The method includes the steps of forming a nitride film on a semiconductor substrate, forming a photoresist pattern on the nitride film, the photoresist pattern exposing a portion of the semiconductor substrate, implanting in a portion of the semiconductor substrate using the photoresist pattern as a mask, removing the photoresist pattern by ashing and/or stripping, washing the resulting structure to remove photoresist pattern splinters, fragments or particles on the nitride film, and removing the nitride film by wet etching. | 2010-06-24 |
20100159681 | Ion implantation method and method for manufacturing semiconductor apparatus - An ion implantation method according to the present invention is provided, to selectively implant ions in a semiconductor area, which is a semiconductor substrate or a semiconductor layer formed on the semiconductor substrate, using an ion implantation mask, the method including the steps of: forming the ion implantation mask by exposing and developing of a photosensitive material film, in such a manner that the ion implantation mask includes a mask opening and a mask thin film section; and implanting ions using the ion implantation mask as a mask to form a plurality of diffusion layers with different diffusion depths in the semiconductor area corresponding to the mask opening section and the mask thin film section. | 2010-06-24 |
20100159682 | Method of removing photoresist - A method includes forming a photoresist pattern over a certain portion of a material layer to expose an ion implantation region, implanting impurities in the ion implantation region of the material layer using the photoresist pattern as an ion implantation barrier, and removing the photoresist pattern using plasma of a gas mixture including a hydrocarbon-based gas. | 2010-06-24 |
20100159683 | Method for Fabricating Semiconductor Device Having Recess Channel - A method for fabricating a semiconductor device having a recess channel includes forming an isolation layer that delimits an active region over a semiconductor substrate; exposing a region to be formed with a bulb recess trench over the semiconductor substrate; forming an upper trench by etching the exposed portion of the semiconductor substrate; forming, on a side wall of the upper trench, a silicon nitride barrier layer that exposes a bottom face of the upper trench but blocks a side wall of the upper trench; forming a lower trench of a bulb type by etching the exposed bottom face of the upper trench using the etch barrier layer as an etch mask, to form the bulb recess trench including the upper trench and the lower trench; forming a fin-structured bottom protrusion part including an upper face and a side face by etching the isolation layer so that the isolation layer has a surface lower than the bottom face of the lower trench; and forming a gate stack overlapped with the bulb recess trench and the bottom protrusion part. | 2010-06-24 |
20100159684 | Metal High-K (MHK) Dual Gate Stress Engineering Using Hybrid Orientation (HOT) CMOS - A hybrid orientation technology (HOT) CMOS structure is comprised of a tensile stressed NFET gate stack and a compressively stressed PFET gate stack, where each gate stack is comprised of a high dielectric constant oxide/metal, and where the source of the stress in the tensile stressed NFET gate stack and the compressively stressed PFET gate stack is the metal in the high-k metal gate stack. | 2010-06-24 |
20100159685 | Eliminating Poly Uni-Direction Line-End Shortening Using Second Cut - A method of forming an integrated circuit structure includes providing a substrate including a first active region and a second active region; forming a gate electrode layer over the substrate; and etching the gate electrode layer. The remaining portions of the gate electrode layer include a first gate strip and a second gate strip substantially parallel to each other; and a sacrificial strip unparallel to, and interconnecting, the first gate strip and the second gate strip. The sacrificial strip is between the first active region and the second active region. The method further includes forming a mask layer covering portions of the first gate strip and the second gate strip, wherein the sacrificial strip and portions of the first gate strip and the second gate strip are exposed through an opening in the mask layer; and etching the sacrificial strip and the portions of the first gate strip and the second gate strip through the opening. | 2010-06-24 |
20100159686 | Semiconductor device and method of manufacturing the same - A semiconductor device according to the present invention comprises a semiconductor substrate, a gate insulating film which is composed of a material whose main component is a tetravalent metal oxide, a mixture of a tetravalent metal oxide and SiO | 2010-06-24 |
20100159687 | SEMICONDUCTOR DEVICE HAVING ELECTRODE AND MANUFACTURING METHOD THEREOF - A manufacturing method of a semiconductor device includes a first electrode formation step of forming a control gate electrode above a surface of a semiconductor substrate with a control gate insulating film interposed between the control gate electrode and the semiconductor substrate, a step of forming a storage node insulating film on the surface of the semiconductor substrate, and a second electrode formation step of forming a memory gate electrode on a surface of the storage node insulating film. The second electrode formation step includes a step of forming a memory gate electrode layer on the surface of the storage node insulating film, a step of forming an auxiliary film, having an etching rate slower than that of the memory gate electrode layer, on a surface of the memory gate electrode layer, and a step of performing anisotropic etching on the memory gate electrode layer and the auxiliary film. | 2010-06-24 |
20100159688 | Device fabrication - Device fabrication is disclosed, including forming a first part of a device at a first fabrication facility as part of a front-end-of-the-line (FEOL) process, the first part of the device comprising a base wafer formed by FEOL processing, and subsequently performing one or more back-end-of-the-line (BEOL) processes at a second fabrication facility to form an IC, the one or more BEOL processes comprising finishing the forming of the device (e.g., an IC including memory) by depositing one or more memory layers on the base wafer. FEOL processing can be used to form active circuitry die (e.g., CMOS circuitry on a Si wafer) and BEOL processing can be used to form on top of each active circuitry die, one or more layers of cross-point memory arrays formed by thin film processing technologies that may or may not be compatible with or identical to some or all of the FEOL processes. | 2010-06-24 |
20100159689 | SEMICONDUCTOR DEVICES HAVING CONTACT PLUGS WITH STRESS BUFFER SPACERS AND METHODS OF FABRICATING THE SAME - A semiconductor device includes an inorganic insulating layer on a semiconductor substrate, a contact plug that extends through the inorganic insulating layer to contact the semiconductor substrate and a stress buffer spacer disposed between the node contact plug and the inorganic insulating layer. The device further includes a thin-film transistor (TFT) disposed on the inorganic insulating layer and having a source/drain region extending along the inorganic insulating layer to contact the contact plug. The device may further include an etch stop layer interposed between the inorganic insulating layer and the semiconductor substrate. | 2010-06-24 |
20100159690 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE THAT USES BOTH A NORMAL PHOTOMASK AND A PHASE SHIFT MASK FOR DEFINING INTERCONNECT PATTERNS - According to one embodiment of the present invention, a method of manufacturing a semiconductor device includes below steps. | 2010-06-24 |
20100159691 | PHOTOSENSITIVE RESIN COMPOSITION AND LAMINATE - Disclosed is a photosensitive resin composition showing excellent contrast performance after exposure to light. Also disclosed is a photosensitive resin laminate using the composition. The photosensitive resin composition comprises (a) 20 to 90% by mass of a binder having a carboxyl group, (b) 5 to 75% by mass of an addition-polymerizable monomer having at least one ethylenically unsaturated terminal group, (c) 0.01 to 30% by mass of a photopolymerization initiator, and (d) 0.01 to 10% by mass of a leuco dye, wherein a specific binder is contained as the binder (a) and a specific monomer is contained as the addition-polymerizable monomer (b). | 2010-06-24 |
20100159692 | ATTACHMENT USING MAGNETIC PARTICLE BASED SOLDER COMPOSITES - Electronic devices and methods for fabricating electronic devices are described. One method includes providing a first body with a plurality of composite bumps thereon, the composite bumps comprising a solder and magnetic particles. The method also includes applying a magnetic field to the magnetic particles to generate sufficient heat to melt the solder and form molten bump regions containing the magnetic particles therein. The method also includes coupling a second body to the first body through the molten bump regions, and cooling the molten bump regions to form solidified composite bumps coupling the second body to the first body. Other embodiments are described and claimed. | 2010-06-24 |
20100159693 | Method of Forming Via Recess in Underlying Conductive Line - A method of fabricating a semiconductor device includes forming a via in a dielectric layer that opens to a conductive line underlying the dielectric layer, and forming a via recess in the conductive line at the via. The via recess in the conductive line has a depth ranging from about 100 angstroms to about 600 angstroms. Via-fill material fills the via recess and at least partially fills the via, such that the via-fill material is electrically connected to the conductive line. The via recess may have a same size or smaller cross-section area than that of the via, for example. Such via structure may be part of a dual damascene structure in an intermetal dielectric structure, for example. | 2010-06-24 |
20100159694 | METHOD FOR DEPOSITING THIN TUNGSTEN FILM WITH LOW RESISTIVITY AND ROBUST MICRO-ADHESION CHARACTERISTICS - Methods of forming low resistivity tungsten films with good uniformity and good adhesion to the underlying layer are provided. The methods involve forming a tungsten nucleation layer using a pulsed nucleation layer process at low temperature and then treating the deposited nucleation layer prior to depositing the bulk tungsten fill. The treatment operation lowers resistivity of the deposited tungsten film. In certain embodiments, the depositing the nucleation layer involves a boron-based chemistry in the absence of hydrogen. Also in certain embodiments, the treatment operations involve exposing the nucleation layer to alternating cycles of a reducing agent and a tungsten-containing precursor. The methods are useful for depositing films in high aspect ratio and/or narrow features. The films exhibit low resistivity at narrow line widths and excellent step coverage. | 2010-06-24 |