26th week of 2015 patent applcation highlights part 62 |
Patent application number | Title | Published |
20150179399 | Apparatus and method for inspecting a surface of a sample - The invention relates to an apparatus for inspecting a surface of a sample, wherein the apparatus comprises: at least one charged particle source for generating an array of primary charged particle beams, a condenser lens for directing all charged particle beams to a common cross-over, a lens system for directing the primary charged particle beams from the common cross-over towards the sample surface and for focusing all primary charged particle beams into an array of individual spots on the sample surface, and a position sensitive secondary electron detector positioned at least substantially in or near a plane comprising said common cross-over. | 2015-06-25 |
20150179400 | Defect Discovery and Inspection Sensitivity Optimization Using Automated Classification of Corresponding Electron Beam Images - Various embodiments for classifying defects detected on a wafer are provided. One method includes acquiring an electron beam image generated by a defect review tool for a location of a defect detected on a wafer by a wafer inspection tool. The method also includes determining a classification of the defect based on at least the electron beam image and without input from a user. The method may also include feeding back the classification results to the wafer inspection tool and optimizing the parameters of the tool to maximize sensitivity to the defects of interest. | 2015-06-25 |
20150179401 | Method for Controlling an Interaction Between Droplet Targets and a Laser and Apparatus for Conducting said Method - A method for controlling an interaction between droplet targets and a high power and high-repetition-rate laser beam at a laser focus position of the laser beam including providing a droplet generator for generating a train of droplets as a droplet target with a predetermined droplet frequency and velocity in a predetermined direction; providing a high power, high-repetition-rate laser for emitting a pulsed laser beam, which is focused in the laser focus position; aligning the droplet generator such that the train of droplets runs through the laser focus position; generating a train of droplets as a droplet target; and emitting a pulsed laser beam in synchronization with the train of droplets, such that the droplet target interacts with the pulsed laser beam at the laser focus position | 2015-06-25 |
20150179402 | METHOD FOR PREPARING SAMPLES FOR IMAGING - A method and apparatus is provided for preparing samples for observation in a charged particle beam system in a manner that reduces or prevents artifacts. Material is deposited onto the sample using charged particle beam deposition just before or during the final milling, which results in an artifact-free surface. Embodiments are useful for preparing cross sections for SEM observation of samples having layers of materials of different hardnesses. Embodiments are useful for preparation of thin TEM samples. | 2015-06-25 |
20150179403 | Method and Apparatus for Electron Beam Lithography - A method of manufacturing a substrate is disclosed. The method includes receiving a plurality of pixel elements, wherein each of the pixel elements includes data members; and transferring the data members to a plurality of exposing devices that are configured to conditionally expose the substrate with an incident energy beam when coupled with the data members, wherein different data members of one pixel element are transferred at different system cycles. | 2015-06-25 |
20150179404 | PLASMA PROCESSING APPARATUS - In a vacuum arc discharge deposition apparatus, an orifice plate having an opening is arranged in a state of being insulated from a magnetic field duct including at least one curved portion for transporting a deposition particle in the middle of the at least one curved portion, in which a neutral particle and a charged particle are removed by applying a voltage to the orifice plate. | 2015-06-25 |
20150179405 | UPPER ELECTRODE AND PLASMA PROCESSING APPARATUS - In an exemplary embodiment, an upper electrode is disposed in a processing chamber to face a susceptor and provided with a plate-like member and an electrode part. In an exemplary embodiment, the plate-like member is formed with a gas distribution hole that distributes a processing gas used for a plasma processing. The electrode part is formed in a film shape by thermally spraying silicon onto a surface of the plate-like member where an outlet of the gas distribution hole is formed. | 2015-06-25 |
20150179406 | ELECTRICAL CIRCUIT TO IMPEDANCE MATCH A SOURCE AND A LOAD AT MULTIPLE FREQUENCIES, METHOD TO DESIGN SUCH A CIRCUIT - A matching circuit is provided to adapt electrical impedance simultaneously for at least one pair of a higher and a lower frequencies between a plasma reactor and a generator; said matching circuit comprises at least a “load and tune” L-type stage, and includes
| 2015-06-25 |
20150179407 | PLASMA PROCESSING APPARATUS AND PLASMA PROCESSING METHOD - Disclosed is a plasma processing method for generating plasma between an upper electrode connected with a VF power supply and a susceptor disposed to face the upper electrode to perform a plasma processing on a wafer by the plasma. The plasma processing method includes: providing an auxiliary circuit configured to reduce a difference between a reflection minimum frequency of a first route where a high frequency current generated from the VF power supply flows before ignition of the plasma and a reflection minimum frequency of a second route where the high frequency current generated from the VF power supply flows after the ignition of the plasma; igniting the plasma; and maintaining the plasma. | 2015-06-25 |
20150179408 | SUBSTRATE PROCESSING APPARATUS AND SUBSTRATE PROCESSING METHOD - A substrate processing apparatus and a substrate processing method can perform a plasma process using a microwave and a heat treatment through irradiation of the microwave on a substrate. A substrate processing apparatus | 2015-06-25 |
20150179409 | IN SITU CONTROL OF ION ANGULAR DISTRIBUTION IN A PROCESSING APPARATUS - A processing apparatus may include a plasma source coupled to a plasma chamber to generate a plasma in the plasma chamber, an extraction plate having an aperture disposed along a side of the plasma chamber; a deflection electrode disposed proximate the aperture and configured to define a pair of plasma menisci when the plasma is present in the plasma chamber; and a deflection electrode power supply to apply a bias voltage to the deflection electrode with respect to the plasma, wherein a first bias voltage applied to the deflection electrode is configured to generate a first angle of incidence for ions extracted through the aperture from the plasma, and a second bias voltage applied to the deflection electrode is configured to generate a second angle of incidence of ions extracted through the aperture from the plasma, the second angle of incidence being different from the first angle of incidence. | 2015-06-25 |
20150179410 | DRY ETCHING DEVICE AND ELECTRODE THEREOF - The invention discloses a dry etching device and an electrode thereof. The electrode comprises an electrode base, an insulation layer arranged on the electrode base, and an edge stage located on a peripheral surface of the insulation layer. The edge stage comprises at least a pad each for receiving a lifter pin of the dry etching device. The edge stage comprises various embosses arranged peripherally on the edge stage, so that small gaps are present around the embosses between the substrate and the edge stage. Therefore, the adhesive force between the substrate and the edge stage can be reduced, the adsorption phenomenon can be efficiently improved, the yield of the etched substrate can be enhanced and the life of the electrode of the dry etching device can be increased. | 2015-06-25 |
20150179411 | APPARATUS FOR GENERATING REACTIVE GAS WITH GLOW DISCHARGES AND METHODS OF USE - An apparatus for generating a flow of reactive gas for decontaminating a material, surface or area, which comprises a first electrode member comprising a first conductive sheet and a first plurality of conductive pins protruding from a surface of the first conductive sheet and a second electrode member comprising a second conductive sheet and a second plurality of conductive pins protruding from a surface of the second conductive sheet. The second electrode member is arranged in spaced relationship with the first electrode member to define a reactor channel between the first conductive sheet and the second conductive sheet The first plurality of conductive pins protrude within the reactor channel towards the second conductive sheet and the second plurality of conductive pins protrude within the reactor channel towards the first conductive sheet so as to form air gaps between the first plurality of conductive pins and the second plurality of conductive pins. An air blower generates a flow of air through the reactor channel. An electric pulse generator repetitively generates voltage pulses between the first and second electrode members so as to produce glow discharges in the air gaps between the conductive pins of the first plurality and the conductive pins of the second plurality, the voltage pulses being generated at a pulse repetition frequency greater than about 1 kHz and voltage pulse duration less than about 100 ns, the glow discharges being adapted to transform part of the flow of air into reactive gas. An output section delivers the reactive gas from the reactor channel to a sample or region to be decontaminated. | 2015-06-25 |
20150179412 | EDGE RING DIMENSIONED TO EXTEND LIFETIME OF ELASTOMER SEAL IN A PLASMA PROCESSING CHAMBER - An edge ring configured to surround an outer periphery of a substrate support in a plasma processing chamber wherein plasma is generated and used to process a substrate is disclosed, the substrate support comprising a base plate, a top plate, an elastomer seal assembly between the base plate and the top plate, and an elastomer seal configured to surround the elastomer seal assembly. The edge ring includes an upper inner surface having an edge step directed towards an interior portion of the edge ring and arranged to extend from an outer periphery of a top surface of the top plate to an outer periphery of an upper surface of the base plate, a lower inner surface, an outer surface, a lower surface extending from the lower inner surface to the outer surface, and a top surface extending from the outer surface to the upper inner surface. | 2015-06-25 |
20150179413 | Process Tools and Methods of Forming Devices Using Process Tools - In accordance with an embodiment of the present invention, a process tool includes a chuck configured to hold a substrate. The chuck is disposed in a chamber. The process tool further includes a shielding unit with a central opening. The shielding unit is disposed in the chamber over the chuck. | 2015-06-25 |
20150179414 | APPARATUS WITH SIDEWALL PROTECTION FOR FEATURES - Provided herein is an apparatus, including a patterned resist overlying a substrate; a number of features of the patterned resist, wherein the number of features respectively includes a number of sidewalls; and a sidewall-protecting material disposed about the number of sidewalls, wherein the sidewall-protecting material is characteristic of a conformal, thin-film deposition, and wherein the sidewall-protecting material facilitates a high-fidelity pattern transfer of the patterned resist to the substrate during etching. | 2015-06-25 |
20150179415 | SUBSTRATE PROCESSING APPARATUS - A substrate processing apparatus includes a chamber including a process chamber for performing a process on a substrate by a gas introduced thereto and an exhaust chamber for evacuating the gas in the process chamber, a shield member for separating the process chamber from the exhaust chamber provided in at least a part of a neighborhood of a side wall of the chamber, and a hollow relay member penetrating through the shield member for communicating the chamber with a pipe connected to a pressure gauge outside the chamber. The relay member is configured to receive a first gas flowing from the chamber into the relay member. The first gas has a first conductance. The first conductance is greater than a second conductance of a second gas flowing from the exhaust chamber into a gap between the relay member and the side wall of the chamber. | 2015-06-25 |
20150179416 | ADAPTER PLATE FOR POLISHING AND CLEANING ELECTRODES - An adapter plate configured to be attachable to a universal platen of a cleaning unit for cleaning upper electrodes from a plasma processing chamber is disclosed, the adapter plate includes a support surface and a mounting surface configured to be fastened to the universal platen of the cleaning unit. The support surface is configured to support an inner electrode or an outer electrode of a showerhead electrode assembly for cleaning upper or lower surfaces thereof. The support surface having a first set of holes configured to receive pins engaged in an upper surface of the inner electrode, a second set of holes configured to receive pins surrounding an outer periphery of the inner electrode, a third set of holes configured to receive pins engaged in an upper surface of the outer electrode, and a fourth set of holes configured to receive pins surrounding an outer periphery of the outer electrode. | 2015-06-25 |
20150179417 | PLASMA MONITORING METHOD AND PLASMA MONITORING SYSTEM - A plasma monitoring method using a sensor, the sensor having a substrate; a first electrode, the first electrode being a conductive electrode and formed on the substrate while being isolated from the substrate; an insulating film formed on the first electrode; a contact hole formed in the insulating film and having a depth from a surface of the insulating film to the first electrode; and a second electrode, the second electrode being a conductive electrode, formed on the surface of the insulating film, and faced to plasma during a plasma process, the plasma monitoring method including measuring and monitoring potentials of the first electrode and the second electrode or a potential difference between the first electrode and the second electrode during the plasma process is disclosed. A plasma monitoring system carrying out the plasma monitoring method is also disclosed. | 2015-06-25 |
20150179418 | MINIATURE PHYSICAL VAPOUR DEPOSITION STATION - The present invention is directed towards a physical vapor deposition station rendered novel in its miniature scale of operations and interchangeability of components to achieve amongst a plurality of vapor deposition methodologies and and surface treatment techniques available. Also disclosed is its distributed control and management using specific combination of instructional content integrated into a base station and removable flash drives at disposal of the operator. | 2015-06-25 |
20150179419 | Method for Mass Spectrometer with Enhanced Sensitivity to Product Ions - A mass spectrometry method comprises: introducing a first portion of a sample of ions including precursor ions comprising a first precursor-ion mass-to-charge (m/z) ratio into a first mass analyzer; transmitting the precursor ions from the first mass analyzer to a reaction or fragmentation cell such that a first population of product ions are continuously accumulated therein over a first accumulation time duration; initiating release of the accumulated first population of product ions from the reaction or fragmentation cell; continuously transmitting the released first population of product ions from the reaction cell to a second mass analyzer; transmitting a portion of the released first population of product ions comprising a first product-ion m/z ratio from the second mass analyzer to a detector; and detecting a varying quantity of the product ions having the first product-ion m/z ratio for a predetermined data-acquisition time period after the initiation of the release. | 2015-06-25 |
20150179420 | Ionization System for Charged Particle Analyzers - A sample ionization system includes at least an ionization source disposed at an ion source end of a charged particle analyzer, for selectably generating first ions in an analyzing mode of operation and second ions in a cleaning mode of operation. The first ions are one of positively and negatively charged and the second ions are the other one of positively and negatively charged. The second ions are directed through the charged particle analyzer toward a surface of an ion optic component, for at least partially neutralizing a buildup of charge caused by the first ions impinging on the surface of the at least one ion optic component. | 2015-06-25 |
20150179421 | ION OPTICAL ELEMENT - An ion optical element that may be used as an ion guide in a mass spectrometer, as a reflectron in a time-of-flight mass spectrometer, as an ion mobility drift tube in an ion mobility spectrometer, or as a collision cell or reaction cell in a mass spectrometer. The ion optical element has an inner tube made of a first ceramic material within an outer ceramic tube made of a second ceramic material. The electrical resistivity of the second ceramic material is two orders of magnitude or more higher than the electrical resistivity of the first ceramic material. In certain embodiments, the thermal conductivity of the second ceramic material is at least about an order of magnitude higher than the thermal conductivity of the first ceramic material. | 2015-06-25 |
20150179422 | Discharge Lamp and Vehicle Lamp - According to one embodiment, a discharge lamp includes a light-emitting part including a discharge space therein in which a metal halide and a gas are sealed, and a pair of electrodes which protrude toward an inside of the discharge space and are arranged to face each other while separated by a specified distance. Power consumption at a time of stable lighting is 20 W or more and 30 W or less. When a pressure of the gas sealed in the discharge space is X (atm), and a distance between a center axis of the electrodes and a surface of the metal halide is m (mm), a following expression is satisfied: 0.085≦m/X≦0.12. | 2015-06-25 |
20150179423 | PHOSPHOR MATERIALS, FLUORESCENT LAMPS PROVIDED THEREWITH, AND METHODS THEREFOR - Phosphor particles, methods for their use to produce fluorescent lamps, and fluorescent lamps that make use of such particles. Such a phosphor particle has a core surrounded by a shell, and the shell contains GdMgB | 2015-06-25 |
20150179424 | Efficient halogen tungsten bulb with high light efficiency - A high luminous efficiency energy-saving halogen tungsten lamp includes a bulb shell, a molybdenum bracket, a tungsten wire, molybdenum strips and molybdenum wires. The molybdenum strips, the tungsten wire and the molybdenum bracket are packaged in the bulb shell, the bulb shell is filled with circulating gas, an upper end of each molybdenum strip is respectively connected with one molybdenum wire, an upper end of each molybdenum wire extends out of the bulb shell, a lower end of a first molybdenum strips is connected with an upper end of the molybdenum bracket, a lower end of the molybdenum bracket is connected with the tungsten wire, and an upper end of the tungsten wire is connected with a second molybdenum strip. The high luminous efficiency energy-saving halogen tungsten lamp adopts a single-filament and single-end structure, the size of the bulb shell is smaller, and it has only one cold end, so that the heat loss of the glass bulb shell and a filament can be reduced, the luminous efficiency can be maximized, visible light output is much more, and the service life is also prolonged. | 2015-06-25 |
20150179425 | ADAPTER FOR REPLACEABLE LAMP - Embodiments of the present disclosure generally relate to an improved adapter for simplified lamps for use as a source of heat radiation in a rapid thermal processing (RTP) chamber. In one embodiment, a lamp assembly is provided. The lamp element includes a capsule having a filament disposed therein, a press seal extending from the capsule, and an adapter having a receptacle contoured to receive at least a portion of the press seal, wherein the press seal is removably engaged with the adapter. | 2015-06-25 |
20150179426 | A-SI SEASONING EFFECT TO IMPROVE SIN RUN-TO-RUN UNIFORMITY - Embodiments of the present invention provide methods for depositing a nitrogen-containing material on large-sized substrates disposed in a processing chamber. In one embodiment, a method includes processing a batch of substrates within a processing chamber to deposit a nitrogen-containing material on a substrate from the batch of substrates, and performing a seasoning process at predetermined intervals during processing the batch of substrates to deposit a conductive seasoning layer over a surface of a chamber component disposed in the processing chamber. The chamber component may include a gas distribution plate fabricated from a bare aluminum without anodizing. In one example, the conductive seasoning layer may include amorphous silicon, doped amorphous silicon, doped silicon, doped polysilicon, doped silicon carbide, or the like. | 2015-06-25 |
20150179427 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, AND RECORDING MEDIUM - A method of manufacturing a semiconductor device includes performing a cycle a predetermined number of times, the cycle including supplying a first precursor containing a specific element and a halogen group to form a first layer and supplying a second precursor containing the specific element and an amino group to modify the first layer into a second layer. A temperature of the substrate is set such that a ligand containing the amino group is separated from the specific element in the second precursor, the separated ligand reacts with the halogen group in the first layer to remove the halogen group from the first layer, the separated ligand is prevented from being bonded to the specific element in the first layer, and the specific element from which the ligand is separated in the second precursor is bonded to the specific element in the first layer. | 2015-06-25 |
20150179428 | CONTROLLED SPALLING OF GROUP III NITRIDES CONTAINING AN EMBEDDED SPALL RELEASING PLANE - A spall releasing plane is formed embedded within a Group III nitride material layer. The spall releasing plane includes a material that has a different strain, a different structure and a different composition compared with the Group III nitride material portions that provide the Group III nitride material layer and embed the spall releasing plane. The spall releasing plane provides a weakened material plane region within the Group III nitride material layer which during a subsequently performed spalling process can be used to release one of the portions of Group III nitride material from the original Group III nitride material layer. In particular, during the spalling process crack initiation and propagation occurs within the spall releasing plane embedded within the original Group III nitride material layer. | 2015-06-25 |
20150179429 | METHOD FOR TREATING SURFACE OF SEMICONDUCTOR LAYER, SEMICONDUCTOR SUBSTRATE, METHOD FOR MAKING EPITAXIAL SUBSTRATE - A surface treatment method for a semiconductor layer includes growing a first layer on a substrate in a growth reactor, the first layer consisting of one of gallium nitride, aluminum gallium nitride and indium aluminium nitride; growing a second layer of gallium nitride on a surface of the first layer, the gallium nitride of the second GaN layer having a composition ratio of gallium to nitrogen larger than 2; taking the substrate out of the growth reactor after growing the second layer; and removing the second layer after taking the substrate out of the growth reactor. | 2015-06-25 |
20150179430 | METHOD FOR DEPOSITING AN ALUMINIUM NITRIDE LAYER - A method for depositing an aluminium nitride layer on a substrate is provided that comprises: providing a silicon substrate; placing the substrate in a vacuum chamber; conditioning a surface of the substrate by etching and providing a conditioned surface; depositing an aluminium film onto the conditioned surface of the substrate by a sputtering method under an atmosphere of Argon and depositing an epitaxial aluminium nitride layer on the aluminium film by a sputtering method under an atmosphere of Nitrogen and Argon. | 2015-06-25 |
20150179431 | SUBSTRATE PROCESSING METHOD - A hydrophobizing agent vapor is supplied to a substrate and a surface of the substrate including a pattern is hydrophobized. Thereafter, the substrate is dried by vaporizing the hydrophobizing agent. The substrate to be processed is maintained in a state of not contacting water until it is dried after being hydrophobized. Collapse of a pattern formed on the substrate surface is thereby suppressed or prevented. | 2015-06-25 |
20150179432 | METHODS AND SYSTEMS FOR CHEMICAL MECHANICAL POLISH AND CLEAN - The present disclosure provides a method of fabricating a semiconductor device. The method includes providing a semiconductor structure including a metal gate (MG) layer formed to fill in a trench between two adjacent interlayer dielectric (ILD) regions; performing a chemical mechanical polishing (CMP) process using a CMP system to planarize the MG layer and the ILD regions; and cleaning the planarized MG layer using a O | 2015-06-25 |
20150179433 | Water-Repellent Protective Film, and Chemical Solution for Forming Protective Film - A surface treatment was conducted by using a liquid chemical containing a water-repellent protective film forming agent represented by the following general formula [1], subsequent to a step of cleaning a metal-based wafer and prior to a step of drying the wafer. | 2015-06-25 |
20150179434 | NANO-SCALE STRUCTURES - A nanoscale structure includes an array of pillars over an underlying layer, a separation wall layer including first separation walls formed over sidewalls of the pillars, and a block co-polymer (BCP) layer formed over the separation wall layer and filling gaps between the pillars. The BCP layer is phase-separated to include first domains that provide second separation walls formed over the first separation walls and second domains that are separated from each other by the first domains. | 2015-06-25 |
20150179435 | Method For Integrated Circuit Patterning - A method of forming a target pattern includes forming a plurality of lines over a substrate with a first mask and forming a first spacer layer over the substrate, over the plurality of lines, and onto sidewalls of the plurality of lines. The plurality of lines is removed, thereby providing a patterned first spacer layer over the substrate. The method further includes forming a second spacer layer over the substrate, over the patterned first spacer layer, and onto sidewalls of the patterned first spacer layer, and forming a patterned material layer over the second spacer layer with a second mask. Whereby, the patterned material layer and the second spacer layer collectively define a plurality of trenches. | 2015-06-25 |
20150179436 | Plasma densification of dielectrics for improved dielectric loss tangent - Defects in hydrogenated amorphous silicon are reduced by low-energy ion treatments and optional annealing. The treatments leave strongly-bonded hydrogen and other passivants in place, but increase the mobility of loosely-bonded and interstitially trapped hydrogen that would otherwise form unwanted two-level systems (TLS). The mobilized hydrogen atoms may be attracted to unused passivation sites or recombined into H | 2015-06-25 |
20150179437 | METHOD FOR MANUFACTURING A SILICON NITRIDE THIN FILM - A method for manufacturing a silicon nitride thin film comprises a step of charging silane, ammonia gas and nitrogen gas at an environment temperature below 350° C. to produce and deposit a silicon nitride thin film, wherein a rate of charging silane is 300-350 sccm, a rate of charging ammonia gas is 1000 sccm, a rate of charging nitrogen gas is 1000 sccm; a power of a high frequency source is 0.15˜0.30 KW, a power of a low frequency source is 0.15˜0.30 KW; a reaction pressure is 2.3˜2.6 Torr; a reaction duration is 4˜6 | 2015-06-25 |
20150179438 | GATE STACKS AND OHMIC CONTACTS FOR SIC DEVICES - SiC substrates are cleaned and provided to a process chamber. In-situ plasma surface treatments are applied to further clean the surface of the substrate. A dielectric interface layer is deposited in-situ to passivate the surface. Metal layers having a low work function are deposited above the dielectric interface layer. The stack is annealed at about 500C in forming gas to form low resistivity ohmic contacts to the SiC substrate. SiC substrates are cleaned and provided to a process chamber. In-situ plasma surface treatments are applied to further clean the surface of the substrate. A silicon oxide dielectric interface layer is deposited in-situ to passivate the surface. Optional plasma surface treatments are applied to further improve the performance of the silicon oxide dielectric interface layer. An aluminum oxide gate dielectric layer is deposited above the silicon oxide dielectric interface layer. | 2015-06-25 |
20150179439 | METHOD FOR PROCESSING GATE DIELECTRIC LAYER DEPOSITED ON GERMANIUM-BASED OR GROUP III-V COMPOUND-BASED SUBSTRATE - The present invention discloses a method for processing a gate dielectric layer deposited on a germanium-based or Group III-V compound-based substrate, belonging to a semiconductor device field. The method comprises the steps of depositing a high-K gate dielectric layer on the germanium-based or Group III-V compound-based substrate, and then performing a plasma process to the high-K gate dielectric layer by using fluorine plasma, wherein during the plasma process, a guiding electric field is applied so that fluorine ions, when being accelerated to a surface of the gate dielectric layer, has an energy of | 2015-06-25 |
20150179440 | SILANE AND BORANE TREATMENTS FOR TITANIUM CARBIDE FILMS - Methods of treating metal-containing thin films, such as films comprising titanium carbide, with a silane/borane agent are provided. In some embodiments a film comprising titanium carbide is deposited on a substrate by an atomic layer deposition (ALD) process. The process may include a plurality of deposition cycles involving alternating and sequential pulses of a first source chemical that comprises titanium and at least one halide ligand, a second source chemical comprising metal and carbon, wherein the metal and the carbon from the second source chemical are incorporated into the thin film, and a third source chemical, wherein the third source chemical is a silane or borane that at least partially reduces oxidized portions of the titanium carbide layer formed by the first and second source chemicals. In some embodiments treatment forms a capping layer on the metal carbide film. | 2015-06-25 |
20150179441 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device is disclosed in which proton implantation is performed a plurality of times to form a plurality of n-type buffer layers in an n-type drift layer at different depths from a rear surface of a substrate. The depth of the n-type buffer layer, which is provided at the deepest position from the rear surface of the substrate, from the rear surface of the substrate is more than 15 μm. The temperature of a heat treatment which is performed in order to change a proton into a donor and to recover a crystal defect after the proton implantation is equal to or higher than 400° C. In a carrier concentration distribution of the n-type buffer layer, a width from the peak position of carrier concentration to an anode is more than a width from the peak position to a cathode. | 2015-06-25 |
20150179442 | Methods for Forming Crystalline IGZO with a Seed Layer - Embodiments described herein provide method for forming crystalline indium-gallium-zinc oxide (IGZO). A substrate is provided. A seed layer is formed above the substrate. The seed layer has a crystalline structure that is substantially dominant along the c-axis. An IGZO layer is formed above the seed layer. The seed layer may include zinc oxide. A stack of alternating seed layers and IGZO layers may be formed. | 2015-06-25 |
20150179443 | CYCLICAL DEPOSITION OF GERMANIUM - In some aspects, methods for forming a germanium thin film using a cyclical deposition process are provided. In some embodiments, the germanium thin film is formed on a substrate in a reaction chamber, and the process includes one or more deposition cycles of alternately and sequentially contacting the substrate with a vapor phase germanium precursor and a nitrogen reactant. In some embodiments, the process is repeated until a germanium thin film of desired thickness has been formed. | 2015-06-25 |
20150179444 | Methods for Forming Crystalline IGZO Through Power Supply Mode Optimization - Embodiments described herein provide method for forming crystalline indium-gallium-zinc oxide (IGZO). A substrate is positioned relative to at least one target. The at least one target includes indium, gallium, zinc, or a combination thereof. A substantially constant voltage is provided across the substrate and the at least one target to cause a plasma species to impact the at least one target. The impacting of the plasma species on the at least one target causes material to be ejected from the at least one target to form an IGZO layer above the substrate. | 2015-06-25 |
20150179445 | Method of Forming Ga2O3-Based Crystal Film and Crystal Multilayer Structure - A method of forming a Ga | 2015-06-25 |
20150179446 | Methods for Forming Crystalline IGZO Through Processing Condition Optimization - Embodiments described herein provide method for forming crystalline indium-gallium-zinc oxide (IGZO). A substrate is provided. A layer is formed above the substrate using a PVD process. The layer includes indium, gallium, zinc, or a combination thereof. The PVD process is performed in a gaseous environment having a pressure of between about 1 mT and about 5 mT and including between about 20% and about 100% oxygen gas. The PVD process may be performed at a processing temperature between about 25° C. and about 400° C. The duty cycle of the PVD process may be between about 70% and about 100%. | 2015-06-25 |
20150179447 | Flexible Single-Crystalline Semiconductor Device and Fabrication Methods Thereof - Systems and methods herein relate to the fabrication of a single-crystal flexible semiconductor template that may be attached to a semiconductor device. The template fabricated comprises a plurality of single crystals grown by lateral epitaxial growth on a seed layer and bonded to a flexible substrate. The layer grown has portions removed to create windows that add to the flexibility of the template. | 2015-06-25 |
20150179448 | Methods for Forming Crystalline IGZO Through Annealing - Embodiments described herein provide method for forming crystalline indium-gallium-zinc oxide (IGZO). A substrate is provided. An IGZO layer is formed above the substrate. The IGZO layer is annealed in an environment consisting essentially of nitrogen gas. | 2015-06-25 |
20150179449 | Laser spike annealing using fiber lasers - The disclosure is directed to laser spike annealing using fiber lasers. The method includes performing laser spike annealing of a surface of a wafer by: generating with a plurality of fiber laser systems respective CW output radiation beams that partially overlap at the wafer surface to form an elongate annealing image having a long axis and a length L | 2015-06-25 |
20150179450 | MULTI-PATTERNING METHOD AND DEVICE FORMED BY THE METHOD - A multi-patterning method includes: patterning at least two first openings in a hard mask layer over a substrate using a first mask; forming spacers within two of the at least two first openings, each spacer having a spacer opening therein for patterning a respective first circuit pattern over the substrate, wherein each spacer defines a pattern-free region adjacent to a respective one of the at least two first circuit patterns, and patterning a second circuit pattern in the hard mask layer using a second mask. The second circuit pattern is located between and excluded from the pattern free regions adjacent the at least two first circuit patterns. | 2015-06-25 |
20150179451 | METHOD FOR PROCESSING GRAPHENE, METHOD FOR PRODUCING GRAPHENE NANORIBBONS, AND GRAPHENE NANORIBBONS - A gas comprising H | 2015-06-25 |
20150179452 | HIGH VOLTAGE DEPLETION MODE N-CHANNEL JFET - An integrated circuit and method having a JFET with a buried drift layer and a buried channel in which the buried channel is formed by implanting through segmented implant areas so that the doping density of the buried channel is between 25 percent and 50 percent of the doping density of the buried drift layer. | 2015-06-25 |
20150179453 | DEFECTIVE P-N JUNCTION FOR BACKGATED FULLY DEPLETED SILICON ON INSULATOR MOSFET - Methods for semiconductor fabrication include forming a well in a semiconductor substrate. A pocket is formed within the well, the pocket having an opposite doping polarity as the well to provide a p-n junction between the well and the pocket. Defects are created at the p-n junction such that a leakage resistance of the p-n junction is decreased. | 2015-06-25 |
20150179454 | FINFET DEVICE HAVING A STRAINED REGION - A method of fabricating a semiconductor device includes providing a substrate having a fin disposed thereon. A gate structure is formed on the fin. The gate structure interfaces at least two sides of the fin. A stress film is formed on the substrate including on the fin. The substrate including the stress film is annealed. The annealing provides a tensile strain in a channel region of the fin. For example, a compressive strain in the stress film may be transferred to form a tensile stress in the channel region of the fin. | 2015-06-25 |
20150179455 | Technique For Processing A Substrate - Techniques for processing a substrate are disclosed. In one exemplary embodiment, the technique may be realized as a method for processing a substrate, the method comprising: ionizing first material and second material in an ion source chamber of an ion source, the first material being boron (B) containing material, the second material being one of phosphorous (P) containing material and arsenic (As) containing material; generating first ions containing B and second ions containing one of P and As; and extracting the first and second ions from the ion source chamber and directing the first and second ions toward the substrate. | 2015-06-25 |
20150179456 | METHOD FOR SEALING PROCESSING MODULE - Embodiments of method for cooling a wafer are provided. A method for cooling a wafer includes placing the wafer in a processing module via a passage of a seat member. The method also includes moving a closure member toward the seat member in a diagonal manner. The method further includes engaging the seat member and the closure member and placing a portion of the closure member inside the passage. In addition, the method includes performing a process on the wafer in the processing module. | 2015-06-25 |
20150179457 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE WITH PATERNED HARD MASK - A method for fabricating a semiconductor device includes the following steps. First, a first interlayer dielectric is formed on a substrate. Then, a gate electrode is formed on the substrate so that the periphery of the gate electrode is surrounded by the first interlayer dielectric. Afterwards, a patterned mask layer is formed on the gate electrode, and a bottom surface of the patterned mask layer is level with a top surface of the first interlayer dielectric. A spacer is then formed on each sidewall of the gate electrode. Subsequently, a second interlayer dielectric is formed to cover a top surface and each side surface of the patterned mask layer. Finally, a self-aligned contact structure is formed in the first interlayer dielectric and the second interlayer dielectric. | 2015-06-25 |
20150179458 | WETTING PRETREATMENT FOR ENHANCED DAMASCENE METAL FILLING - Disclosed are pre-wetting apparatus designs and methods. These apparatus designs and methods are used to pre-wet a wafer prior to plating a metal on the surface of the wafer. Disclosed compositions of the pre-wetting fluid prevent corrosion of a seed layer on the wafer and also improve the filling rates of features on the wafer. | 2015-06-25 |
20150179459 | MULTI-PLASMA NITRIDATION PROCESS FOR A GATE DIELECTRIC - A gate dielectric can be formed by depositing a first silicon oxide material by a first atomic layer deposition process. The thickness of the first silicon oxide material is selected to correspond to at least 10 deposition cycles of the first atomic layer deposition process. The first silicon oxide material is converted into a first silicon oxynitride material by a first plasma nitridation process. A second silicon oxide material is subsequently deposited by a second atomic layer deposition process. The second silicon oxide material is converted into a second silicon oxynitride material by a second plasma nitridation process. Multiple repetitions of the atomic layer deposition process and the plasma nitridation process provides a silicon oxynitride material having a ratio of nitrogen atoms to oxygen atoms greater than ⅓, which can be advantageously employed to reduce the leakage current through a gate dielectric. | 2015-06-25 |
20150179460 | LOW TEMPERATURE POLY-SILICON THIN FILM TRANSISTOR AND MANUFACTURING METHOD THEREOF - The present disclosure relates to a low temperature poly-silicon thin film transistor which possesses electrical characteristics and reliability, and a method of manufacturing the thin film transistor. The low temperature poly-silicon thin film transistor at least includes a gate insulating layer which is a composite insulating layer comprising at least three dielectric layers, wherein the compactness of each dielectric layer successively increases in order of the formation sequence thereof in the manufacturing process. Because the relation between the compactness of each layer of the composite insulating layer and that of the others thereof is taken into account according to the present disclosure, each layer in the composite insulating layer of the low temperature poly-silicon thin film transistor manufactured by the method according to the present disclosure can have enhanced surface contact characteristic and thin film continuity. The thickness of each layer in the composite insulating layer is further considered, so that the parasitic capacitance can be effectively reduced, and thus the response rate of the transistor can be improved. Namely, by improving the GI film forming quality, the electrical characteristic and reliability of the low temperature poly-silicon thin film transistor can be improved | 2015-06-25 |
20150179461 | METHOD FOR DEPOSITING EXTREMELY LOW RESISTIVITY TUNGSTEN - Methods for depositing extremely low resistivity tungsten in semiconductor processing are disclosed herein. Methods involve annealing the substrate at various times during the tungsten deposition process to achieve uniform tungsten layers with substantially lower resistivity. | 2015-06-25 |
20150179462 | METHOD OF FORMING TI FILM - A method of forming a Ti film on a substrate disposed in a chamber by introducing a processing gas containing a TiCl | 2015-06-25 |
20150179463 | PREVENTION OF METAL LOSS IN WAFER PROCESSING - An embodiment includes a method comprising: etching a material to expose a metal component in a metal layer, which is located on a substrate, while the substrate is in an etch chamber that is under vacuum; and performing an ash process on the metal component while the substrate is still in the etch chamber that is still under vacuum; wherein the material includes at least one of a dielectric and a mask and the metal component includes at least one of an interconnect, a via, and a contact. Other embodiments are described herein. | 2015-06-25 |
20150179464 | DRY-ETCH FOR SELECTIVE TUNGSTEN REMOVAL - Methods of selectively etching tungsten relative to silicon-containing films (e.g. silicon oxide, silicon carbon nitride and (poly)silicon) as well as tungsten oxide are described. The methods include a remote plasma etch formed from a fluorine-containing precursor and/or hydrogen (H | 2015-06-25 |
20150179465 | ION BEAM ETCHING SYSTEM - The disclosed embodiments relate to methods and apparatus for removing material from a substrate. In various implementations, conductive material is removed from a sidewall of a previously etched feature such as a trench, hole or pillar on a semiconductor substrate. In practicing the techniques herein, a substrate is provided in a reaction chamber that is divided into an upper plasma generation chamber and a lower processing chamber by a corrugated ion extractor plate with apertures therethrough. The extractor plate is corrugated such that the plasma sheath follows the shape of the extractor plate, such that ions enter the lower processing chamber at an angle relative to the substrate. As such, during processing, ions are able to penetrate into previously etched features and strike the substrate on the sidewalls of such features. Through this mechanism, the material on the sidewalls of the features may be removed. | 2015-06-25 |
20150179466 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - Provided is a method of manufacturing a semiconductor device. The method includes providing an object to be processed including a multilayer film formed by alternately laminating a first film and a second film having different dielectric coefficients within a processing container of a plasma processing apparatus; and repeatedly performing a sequence including: supplying a first gas including O | 2015-06-25 |
20150179467 | Methods of Forming Patterns - Some embodiments include methods of forming patterns. A first mask is formed over a material. The first mask has features extending therein and defines a first pattern. The first pattern has a first level of uniformity across a distribution of the features. A brush layer is formed across the first mask and within the features to narrow the features and create a second mask from the first mask. The second mask has a second level of uniformity across the narrowed features which is greater than the first level of uniformity. A pattern is transferred from the second mask into the material. | 2015-06-25 |
20150179468 | METHOD OF ETCHING - A method of etching a feature in a substrate includes forming a mask structure over the substrate, the mask structure defining at least one re-entrant opening, etching the substrate through the opening to form the feature using a cyclic etch and deposition process, and removing the mask. | 2015-06-25 |
20150179469 | METHOD AND SYSTEM TO CONTROL POLISH RATE VARIATION INTRODUCED BY DEVICE DENSITY DIFFERENCES - An embodiment includes forming a first film over first and second portions of a SOC, the first portion including a first density of structures and the second portion including a second density of structures with the first density being denser than the second density; forming a second film over the first film; polishing the second film to remove some of the second film and form (a) a first section of the second film between sections of the first film located over the first portion, and (b) a second section of the second film between sections of the second film located over the second portion; etching the first film over the first and second portions and etching the first and second sections of the second film; and polishing the first film to expose top surfaces of the structures of the first and second portions. Other embodiments are described herein. | 2015-06-25 |
20150179470 | MULTI-SELECTIVE POLISHING SLURRY COMPOSITION AND A SEMICONDUCTOR ELEMENT PRODUCTION METHOD USING THE SAME - Provided are a multi-selective polishing slurry composition and a semiconductor element production method using the same. A silicon film provided with element patterns is formed on the uppermost part of a substrate having a first region and a second region. The element pattern density on the first region is higher than the element pattern density on the second region. Formed in sequence on top of the element patterns are a first silicon oxide film, a silicon nitride film and a second silicon oxide film. The substrate is subjected to chemical-mechanical polishing until the silicon film is exposed, by using a polishing slurry composition containing a polishing agent, a silicon nitride film passivation agent and a silicon film passivation agent. The polishing slurry composition may be a mixture of 100 parts by weight of a polishing agent suspension, containing a polishing agent, and from 40 to 120 parts by weight of an additive solution, and the additive solution can contain 100 parts by weight of a solvent, from 0.01 to 5 parts by weight of a silicon nitride film passivation agent and from 0.01 to 5 parts by weight of a silicon film passivation agent. | 2015-06-25 |
20150179471 | METHOD OF PRODUCING A SEMICONDUCTOR SUBSTRATE PRODUCT AND ETCHING LIQUID - A method of producing a semiconductor substrate product, having the steps of: providing an etching liquid containing water, a hydrofluoric acid compound, and a water-soluble polymer; and applying the etching liquid to a semiconductor substrate, the semiconductor substrate having a silicon layer and a silicon oxide layer, the silicon layer containing an impurity, and thereby selectively etching the silicon oxide layer. | 2015-06-25 |
20150179472 | METAL HARDMASK ALL IN ONE INTEGRATED ETCH - A method for forming conductive contacts in a dielectric layer is provided. Partial vias are etched into the dielectric layer through a via mask. Trenches are etched into the dielectric layer through a trench mask, wherein the etching the trenches completes and over etches the vias to widen bottoms of the vias. Tops of the trenches or vias are rounded. | 2015-06-25 |
20150179473 | DUAL WAVELENGTH ANNEALING METHOD AND APPARATUS - Methods and apparatus for thermal processing of semiconductor substrates are described. A solid state radiant emitter is used to provide a field of thermal processing energy. A second solid state radiant emitter is used to provide a field of activating energy. The thermal processing energy and the activating energy are directed to a treatment zone of the substrate, where the activating energy increases absorption of the thermal processing radiation in the substrate, resulting in thermal processing of the substrate in the areas illuminated by the activating energy. | 2015-06-25 |
20150179474 | METHOD FOR MODIFYING THE STRAIN STATE OF A BLOCK OF A SEMICONDUCTING MATERIAL - Method for modifying the strain state of a block of a semiconducting material comprising steps for:
| 2015-06-25 |
20150179475 | METHOD OF FABRICATING PACKAGING SUBSTRATE HAVING A THROUGH-HOLED INTERPOSER - A through-holed interposer is provided, including a board body, a conductive gel formed in the board body, and a circuit redistribution structure disposed on the board body. The conductive gel has one end protruding from a surface of the board body, and an area of the protruded end of the conductive gel that is in contact with other structures (e.g., packaging substrates or circuit structures) is increased, thereby strengthening the bonding of the conductive gel and reliability of the interposer. | 2015-06-25 |
20150179476 | METHOD OF FABRICATING A THROUGH-HOLED INTERPOSER - A through-holed interposer is provided, including a board body, a conductive gel formed in the board body, and a circuit redistribution structure disposed on the board body. The conductive gel has one end protruding from a surface of the board body, and an area of the protruded end of the conductive gel that is in contact with other structures (e.g., packaging substrates or circuit structures) is increased, thereby strengthening the bonding of the conductive gel and reliability of the interposer. | 2015-06-25 |
20150179477 | PACKAGED IC DEVICES AND ASSOCIATED IC DEVICE PACKAGING METHODS - A method of making packaged integrated circuit (IC) devices includes mixing a waste thermoset polymer material with a thermosetting polymer to form a mixed thermosetting polymer and packaging IC devices in a molding operation using the mixed thermosetting polymer to thereby recycle the waste thermoset polymer material. A packaged IC device includes an IC device and an encapsulating material surrounding the IC device. The encapsulating material includes a thermoset polymer matrix and thermoset polymer particles dispersed in thermoset polymer matrix. | 2015-06-25 |
20150179478 | NARROW-GAP FLIP CHIP UNDERFILL COMPOSITION - An underfill composition comprises a curable resin, a plurality of filler particles loaded within the resin, the filler particles comprising at least 50 weight % of the underfill composition. The filler particles comprise first filler particles having a particle size of from 0.1 micrometers to 15 micrometers and second filler particles having a particle size of less than 100 nanometers. A viscosity of the underfill composition is less than a viscosity of a corresponding composition not including the second filler particles. | 2015-06-25 |
20150179479 | METHODS TO PREVENT FILLER ENTRAPMENT IN MICROELECTRONIC DEVICE TO MICROELECTRONIC SUBSTRATE INTERCONNECTION STRUCTURES - Embodiments of the present description include methods for attaching a microelectronic device to a microelectronic substrate with interconnection structures after disposing of an underfill material on the microelectronic device, wherein filler particless within the underfill material may be repelled away from the interconnection structures prior to connecting the microelectronic device to the microelectronic structure. These methods may include inducing a charge on the interconnection structures and may include placing the interconnection structures between opposing plates and producing a bias between the opposing plates after depositing the underfill material on the interconnection structures. | 2015-06-25 |
20150179480 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device, includes providing a lead frame including a frame portion, including a through hole penetrating the lead frame, a device forming portion surrounded by the frame portion in plan view, including a die pad, and a semiconductor chip mounted on the die pad; after the providing step, sealing the semiconductor chip with sealing resin by supplying the sealing resin to the device forming portion via a first region of the frame portion in which the through hole is formed in plan view, thereby forming a sealing body sealing the device forming portion and the first region of the frame portion; and after the sealing step, removing a first part of the sealing body located at the first region of the frame portion from the lead frame by inserting a pin into the through hole. | 2015-06-25 |
20150179481 | Semiconductor Device and Method of Making Embedded Wafer Level Chip Scale Packages - A semiconductor device includes a carrier and a plurality of semiconductor die disposed over the carrier. An encapsulant is deposited over the semiconductor die. A composite layer is formed over the encapsulant to form a panel. The carrier is removed. A conductive layer is formed over the panel. An insulating layer is formed over the conductive layer. The carrier includes a glass layer, a second composite layer formed over the glass layer, and an interface layer formed over the glass layer. The composite layer and encapsulant are selected to tune a coefficient of thermal expansion of the panel. The panel includes panel blocks comprising an opening separating the panel blocks. The encapsulant or insulating material is deposited in the opening. A plurality of support members are disposed around the panel blocks. An interconnect structure is formed over the conductive layer. | 2015-06-25 |
20150179482 | PRODUCING METHOD OF ENCAPSULATING LAYER-COVERED SEMICONDUCTOR ELEMENT AND PRODUCING METHOD OF SEMICONDUCTOR DEVICE - A method for producing an encapsulating layer-covered semiconductor element includes a disposing step of disposing a semiconductor element on a support, an encapsulating step of embedding and encapsulating the semiconductor element by an encapsulating layer in an encapsulating sheet including a peeling layer and the encapsulating layer laminated below the peeling layer and made from a thermosetting resin before complete curing, and a heating step of heating and curing the encapsulating layer after the encapsulating step. The heating step includes a first heating step in which the encapsulating sheet is heated under a normal pressure at a first temperature, a peeling step in which the peeling layer is peeled from the encapsulating layer after the first heating step, and a second heating step in which the encapsulating layer is heated at a second temperature that is higher than the first temperature after the peeling step. | 2015-06-25 |
20150179483 | PHOTORESIST NOZZLE DEVICE AND PHOTORESIST SUPPLY SYSTEM - Embodiments of a photoresist supply system including a photoresist nozzle device are provided. The photoresist nozzle device includes a tube including a first segment, a curved segment connected to the first segment, and a second segment connected to the curved segment. The photoresist nozzle device also includes a nozzle connected to the second segment. | 2015-06-25 |
20150179484 | SUBSTRATE CLEANING APPARATUS AND SUBSTRATE PROCESSING APPARATUS - A substrate cleaning apparatus which can sufficiently clean a pen-sponge in its entirety, and can prevent particles, which have been once removed, from being reattached to the pen-sponge is disclosed. The substrate cleaning apparatus includes: a substrate holder configured to hold and rotate a substrate; a sponge cleaning tool to be brought into contact with a surface of the substrate; a cleaning element provided adjacent to the substrate held by the substrate holder; and a cleaning-tool moving mechanism configured to bring the sponge cleaning tool into contact with the cleaning element. The cleaning element has a cleaning surface that is to come in contact with the sponge cleaning tool, and a central portion of the cleaning surface is located at a higher position than a portion, of the cleaning surface, outside the central portion. | 2015-06-25 |
20150179485 | STAGE, STAGE MANUFACTURING METHOD, AND HEAT EXCHANGER - A stage includes a plate and a heat exchanger. The plate has a front surface, on which a substrate is mounted, and a rear surface. The heat exchanger is configured to individually supply a heat exchange medium to a plurality of two-dimensionally distributed and mutually non-inclusive regions of the rear surface of the plate and to recover the heat exchange medium thus supplied. | 2015-06-25 |
20150179486 | LOAD LOCK CHAMBER, SUBSTRATE PROCESSING SYSTEM AND METHOD FOR VENTING - A lock chamber for a substrate processing system is provided which includes at least a first conduit adapted to provide an inner portion of the lock chamber in fluid communication with atmospheric pressure or overpressure. Additionally, the lock chamber includes at least a first control valve for controlling a flow rate of the fluid communication of the inner portion of the chamber with the atmospheric pressure or the overpressure, wherein the control valve is adapted to continuously control the flow rate. Furthermore, an according method, a computer program and a computer readable medium adapted for performing the method is provided. | 2015-06-25 |
20150179487 | Multipurpose Combinatorial Vapor Phase Deposition Chamber - In some embodiments, apparatus are provided that provide for flexible processing in high productivity combinatorial (HPC) system. The apparatus allow for interchangeable functionality that includes deposition, plasma treatment, ion beam treatment, in-situ annealing, and in-situ metrology. The apparatus are designed so that the functionality may be integrated within a single processing chamber for enhanced flexibility. | 2015-06-25 |
20150179488 | ROBOT WITH INTEGRATED ALIGNER - A robot with an integrated aligner is provided that allows for the alignment of a semiconductor wafer while the semiconductor wafer transits between multiple stations. The robot with an integrated aligner may contain a rotational wafer support configured to rotate and/or translate, one or multiple robotic arms, and a sensor. The robot may pick and place the semiconductor wafer with the robotic arm from or into a station and from or onto the rotational wafer support. The robot may be configured to rotate the semiconductor wafer into a desired orientation when the semiconductor wafer is on the rotational wafer support. The rotation of the semiconductor wafer into a desired orientation may be aided the sensor. The robot may have a positioning mechanism which moves it between different positions in a semiconductor tool. | 2015-06-25 |
20150179489 | Substrate Processing Module, Substrate Processing Apparatus Including the same, and Substrate Transferring Method - There are provided a substrate processing module, and substrate processing apparatus including the same, and a substrate transferring method. The substrate processing module includes: a chamber having a passage formed on one side thereof and allowing a substrate to enter or exit therethrough; a first susceptor installed within the chamber, having at least one through hole formed in an upper surface thereof, and allowing the substrate to be placed thereon; a second susceptor installed within the chamber and allowing the substrate to be placed thereon; a rotary member provided within the chamber and rotating, based on a preset position; a holder connected to the rotary member and having a mounting surface allowing the substrate to be placed thereon; and a holder driving module driving the rotary member to move the holder to a standby position corresponding to the first susceptor or to a delivery position corresponding to the second susceptor. | 2015-06-25 |
20150179490 | SUBSTRATE PROCESSING APPARATUS, PROGRAM AND SUBSTRATE PROCESSING METHOD - A substrate processing apparatus includes a sealed container which interiorly has a space for housing substrates and is provided with an opening for introducing or discharging the substrates, an opening/closing mechanism for opening and closing the opening, a substrate processing part for performing cleaning process on the substrates, and a first transfer robot for discharging and introducing the substrates from and into the sealed container. Further, the substrate processing apparatus includes a schedule creating part adapted to create schedule data which defines timings at which the opening/closing mechanism opens and closes the opening, and timings at which the substrate transferring part introduces the substrates in the sealed container or discharges the substrates from the sealed container, according to time periods of processing of the substrates into the substrate processing part. | 2015-06-25 |
20150179491 | ROBOTIC SYSTEM AND DETECTION METHOD - A robotic system includes: an arm configured to carry a substrate to a mounting base; a hand disposed at a tip portion of the arm, the hand being configured to hold the substrate when the substrate is carried; a detector disposed on the hand, the detector being configured to detect the substrate; and an acquirer configured to recognize heights of the detector when the substrate is detected at a first position and a second position by the detector as heights of the substrate at respective positions and acquire a mounted-state of the substrate mounted on the mounting base based on the height of the substrate at the first position and the height of the substrate at the second position. | 2015-06-25 |
20150179492 | ELECTROSTATIC CHUCK APPARATUS - Disclosed is an electrostatic chuck apparatus which is configured of: an electrostatic chuck section; an annular focus ring section provided to surround the electrostatic chuck section; and a cooling base section which cools the electrostatic chuck section and the focus ring section. The focus ring section is provided with an annular focus ring, an annular heat conducting sheet, an annular ceramic ring, a nonmagnetic heater, and an electrode section that supplies power to the heater. | 2015-06-25 |
20150179493 | METHODS AND STRUCTURES FOR PROCESSING SEMICONDUCTOR DEVICES - Methods of forming semiconductor structures include providing a polymeric material over a carrier substrate, bonding another substrate to the polymeric material, and lowering a temperature of the polymeric material to below about 15° C. to separate the another substrate from the carrier substrate. Some methods include forming a polymeric material over a first substrate, securing a second substrate to the first substrate over the polymeric material, cooling the polymeric material to a temperature below a glass-transition temperature of the polymeric material, and separating the second substrate from the first substrate. Semiconductor structures may include a polymeric material over at least a portion of a first substrate, an adhesive material over the polymeric material, and a second substrate over the adhesive material. The polymeric material may have a glass transition temperature of about 10° C. or lower and a melting point of about 100° C. or greater. | 2015-06-25 |
20150179494 | METHOD FOR PRODUCING SEMICONDUCTOR DEVICE - A method for producing a semiconductor device having a semiconductor element obtained by dividing a semiconductor wafer comprises a temporary securing step of arranging a temporary securing film between a support member and the semiconductor wafer so as to temporarily secure the support member and the semiconductor wafer to each other; a grinding step of grinding a surface on the side opposite from the temporary securing film of the semiconductor wafer temporarily secured to the support member, and a semiconductor wafer peeling step of peeling the temporary securing film from the ground semiconductor wafer, wherein a semiconductor wafer edge-trimmed on an outer peripheral part of a surface opposing the support member is used as the semiconductor wafer, and the temporary securing step arranges the temporary securing film on the inside of the edge-trimmed part. | 2015-06-25 |
20150179495 | System and Method for Non-Contact Wafer Chucking - A non-contact wafer chucking apparatus includes a wafer chuck and a gripper assembly coupled to a portion of the wafer chuck. The wafer chuck includes pressurized gas elements configured to generate pressurized gas regions across a surface of the wafer chuck suitable for elevating the wafer above the surface of the wafer chuck. The wafer chuck further includes vacuum elements configured to generate reduced pressure regions across the surface of the wafer chuck having a pressure lower than the pressurized gas regions. The reduced pressure regions are suitable for securing the wafer above the wafer chuck without contact to the wafer chuck. The chucking apparatus includes a rotational drive unit configured to selectively rotate the wafer chuck. The gripper elements are reversibly couplable to an edge portion of the wafer so as to secure the wafer such that the wafer and gripper assembly rotate synchronously with the wafer chuck. | 2015-06-25 |
20150179496 | SEMICONDUCTOR WAFER TRANSFER JIG - The semiconductor wafer conveying tool which can realize the uniform heating to a surface of a semiconductor wafer when heating the semiconductor wafer is a semiconductor wafer conveying tool which holds the semiconductor wafer having a predetermined diameter to convey it wherein the tool is provided with a main body having an opening with a diameter which is larger than a diameter of the semiconductor wafer, and at least three supporting members each having a predetermined length, containing plural pins which are arranged corresponding to the diameter of the semiconductor wafer and being configured to be a holding mechanism for holding the semiconductor wafer concentrically at a projection position from an inner periphery portion of the main body around the opening, as shown in | 2015-06-25 |
20150179497 | ISOLATION STRUCTURE AND MANUFACTURING METHOD THEREOF FOR HIGH-VOLTAGE DEVICE IN A HIGH-VOLTAGE BCD PROCESS - The invention provides an isolation structure and a manufacturing method thereof for a high-voltage device in a high-voltage BCD process, the isolation structure comprising: a semiconductor substrate having a first type of doping; an epitaxial layer having a second type of doping over the semiconductor substrate, wherein the first type of doping is opposite to the second type of doping; an isolation region having the first type of doping, wherein the isolation region extends through the epitaxial layer into the semiconductor substrate, and wherein the isolation region has a doping concentration on the same order as a doping concentration of the epitaxial layer; a field oxide layer over the isolation region. This invention effectively isolates the epitaxial island where the BCD high-voltage device is located, thereby increasing the breakdown voltage of the high-voltage device in the BCD process. Further, with a minimum thickness of the field oxide layer, the parasitical threshold voltage between the aluminum wiring and the silicon surface of the high-voltage device can be higher than 1200V, thereby improving the planarization of oxide layer steps on the silicon surface in the whole high-voltage BCD process, and enhancing the reliability of the product. | 2015-06-25 |
20150179498 | NONVOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - A nonvolatile memory device includes gate structures formed over a substrate, each gate structure including a tunnel insulating layer, a floating gate, an inter-gate dielectric layer, and a control gate that are sequentially stacked, a protective layer formed on sidewalls of the floating gate, and a second insulating layer covering the gate structures and having an air gap formed between the gate structures, wherein an adhesive strength between the second insulating layer and the protective layer is smaller than an adhesive strength between the second insulating layer and the gate structure. | 2015-06-25 |