26th week of 2015 patent applcation highlights part 66 |
Patent application number | Title | Published |
20150179799 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor device includes an isolation layer defining an active region formed in a semiconductor substrate. A first recessing process is performed on the isolation layer to expose edge portions of the active region. A first rounding process is performed to round the edge portions of the active region. A second recessing process is performed on the isolation layer. A second rounding process is performed to round the edge portions of the active region. | 2015-06-25 |
20150179800 | METHOD DEVICE AND OPERATION METHOD OF SAID DEVICE - The present invention relates to a single field effect transistor capacitor-less memory device including a drain region, a source region, an intrinsic channel region between the drain region and the source region forming the single field effect transistor and a base. | 2015-06-25 |
20150179801 | THIN FILM TRANSISTOR AND METHOD FOR MANUFACTURING THE SAME - The present disclosure provides a thin film transistor and a method of manufacturing the same. The transistor includes:a substrate; a gate electrode, a source electrode, and a drain electrode; and an oxide semiconductor layer; wherein, the oxide semiconductor includes a source region and a drain region which electrically contact with the source electrode and the drain electrode respectively, and a channel region for providing a conductive channel between the source electrode and the drain electrode, wherein, a gate isolation layer is arranged between the oxide semiconductor layer and the gate region electrically contacting with the gate electrode, and an oxide semiconductor protective layer is arranged on the oxide semiconductor layer. The transistor in the present disclosure can prevent the oxide semiconductor layer from being damaged during the process of manufacturing, and thus improve the conductive of the device and its integrity. | 2015-06-25 |
20150179802 | THIN FILM TRANSISTOR, DISPLAY SUBSTRATE HAVING THE SAME AND METHOD OF MANUFACTURING A DISPLAY SUBSTRATE - A thin film transistor includes a gate electrode, an active pattern over the gate electrode and including an oxide semiconductor, an etch-stop layer covering the active pattern, a source electrode on the etch-stop layer, a drain electrode on the etch-stop layer and spaced from the source electrode, and an active protection pattern between the etch-stop layer and the active pattern and electrically coupled to the source electrode and the drain electrode. | 2015-06-25 |
20150179803 | SEMICONDUCTOR DEVICE - To provide a transistor having a high on-state current. A semiconductor device includes a first insulator containing excess oxygen, a first oxide semiconductor over the first insulator, a second oxide semiconductor over the first oxide semiconductor, a first conductor and a second conductor which are over the second oxide semiconductor and are separated from each other, a third oxide semiconductor in contact with side surfaces of the first oxide semiconductor, a top surface and side surfaces of the second oxide semiconductor, a top surface of the first conductor, and a top surface of the second conductor, a second insulator over the third oxide semiconductor, and a third conductor facing a top surface and side surfaces of the second oxide semiconductor with the second insulator and the third oxide semiconductor therebetween. The first oxide semiconductor has a higher oxygen-transmitting property than the third oxide semiconductor. | 2015-06-25 |
20150179804 | SEMICONDUCTOR DEVICE - The semiconductor device includes a transistor including an oxide semiconductor film having a channel formation region, a gate insulating film, and a gate electrode layer. In the transistor, the channel length is small (5 nm or more and less than 60 nm, preferably 10 nm or more and 40 nm or less), and the thickness of the gate insulating film is large (equivalent oxide thickness which is obtained by converting into a thickness of silicon oxide containing nitrogen is 5 nm or more and 50 nm or less, preferably 10 nm or more and 40 nm or less). Alternatively, the channel length is small (5 nm or more and less than 60 nm, preferably 10 nm or more and 40 nm or less), and the resistivity of the source region and the drain region is 1.9×10 | 2015-06-25 |
20150179805 | OXIDE SEMICONDUCTOR FILM AND SEMICONDUCTOR DEVICE - An oxide semiconductor film which has more stable electric conductivity is provided. The oxide semiconductor film comprises a crystalline region. The oxide semiconductor film has a first peak of electron diffraction intensity with a full width at half maximum of greater than or equal to 0.4 nm | 2015-06-25 |
20150179806 | SEMICONDUCTOR DEVICE - A semiconductor device includes a first transistor which includes a first gate electrode below its oxide semiconductor layer and a second gate electrode above its oxide semiconductor layer, and a second transistor which includes a first gate electrode above its oxide semiconductor layer and a second gate electrode below its oxide semiconductor layer and is provided so as to at least partly overlap with the first transistor. In the semiconductor device, a conductive film serving as the second gate electrode of the first transistor and the second gate electrode of the second transistor is shared between the first transistor and the second transistor. Note that the second gate electrode not only controls the threshold voltages (Vth) of the first transistor and the second transistor but also has an effect of reducing interference of an electric field applied from respective first gate electrodes of the first transistor and the second transistor. | 2015-06-25 |
20150179807 | NON-VOLATILE MEMORY DEVICE INCLUDING NANO FLOATING GATE AND METHOD FOR FABRICATING THE SAME - A non-volatile memory device includes a floating gate for charging and discharging of charges over a substrate. The floating gate comprises a linker layer formed over the substrate and including linkers to be bonded to metal ions and metallic nanoparticles formed out of the metal ions over the linker layer. | 2015-06-25 |
20150179808 | NON-VOLATILE MEMORY DEVICE INCLUDING FLEXIBLE NANO FLOATING GATE AND METHOD FOR FABRICATING THE SAME - A non-volatile memory device includes a floating gate for charging and discharging of charges over a flexible substrate. The floating gate includes a linker layer formed over the substrate and including a plurality of linkers to be bonded to a plurality of metal ions and a plurality of metallic nanoparticles formed out of the metal ions over the linker layer. | 2015-06-25 |
20150179809 | THIN FILM TRANSISTOR AND METHOD FOR MANUFACTURING THE SAME, ARRAY SUBSTRATE AND DISPLAY DEVICE - A thin film transistor and method for manufacturing the same, an array substrate and a display device are disclosed. The thin film transistor comprises a substrate; a gate electrode, a source electrode, a drain electrode and a semiconductor layer formed on the substrate; a gate insulating layer between the gate electrode and the semiconductor layer or between the gate electrode and the source and drain electrodes; an etching stop layer between the semiconductor layer and the source and drain electrodes having a source contact hole and a drain contact hole therein; and a source buffer layer between the source electrode and the semiconductor layer and a drain buffer layer between the drain electrode and the semiconductor layer. The source and drain electrodes are metal Cu electrodes, and the source and drain buffer layers are Cu alloy layer. The formation of the source and drain buffer layer improves the adhesion of the source and drain electrodes thereon to the semiconductor layer therebeneath, and thus improves the performance of the TFT and image quality. | 2015-06-25 |
20150179810 | SEMICONDUCTOR DEVICE - A change in electrical characteristics is suppressed and reliability in a semiconductor device using a transistor including an oxide semiconductor is improved. The semiconductor device includes an oxide semiconductor film over an insulating surface, an antioxidant film over the insulating surface and the oxide semiconductor film, a pair of electrodes in contact with the antioxidant film, a gate insulating film over the pair of electrodes, and a gate electrode which is over the gate insulating film and overlaps with the oxide semiconductor film. In the antioxidant film, a width of a region overlapping with the pair of electrodes is longer than a width of a region not overlapping with the pair of electrodes. | 2015-06-25 |
20150179811 | THIN FILM TRANSISTOR AND METHOD OF MANUFACTURING THE SAME, AND DISPLAY UNIT AND ELECTRONIC APPARATUS - There are provided a thin film transistor having a simple structure that allows reduction in leakage current at the time of gate negative bias, and a method of manufacturing the thin film transistor, and a display unit and an electronic apparatus. The thin film transistor includes: a gate electrode; a semiconductor film including a channel region that faces the gate electrode; and an insulating film provided at least at a position near an end portion on the gate electrode side of side walls of the semiconductor film. | 2015-06-25 |
20150179812 | THIN FILM TRANSISTOR AND DISPLAY DEVICE USING THE SAME - There is provided a bottom gate channel etched thin film transistor that can suppress initial Vth depletion and a Vth shift. A thin film transistor is formed, including a gate electrode interconnection disposed on a substrate, a gate insulating film, an oxide semiconductor layer to be a channel layer, a stacked film of a source electrode interconnection and a first hard mask layer, a stacked film of a drain electrode interconnection and a second hard mask layer, and a protective insulating film. | 2015-06-25 |
20150179813 | SEMICONDUCTOR DEVICE - It is an object to provide a method of manufacturing a crystalline silicon device and a semiconductor device in which formation of cracks in a substrate, a base protective film, and a crystalline silicon film can be suppressed. First, a layer including a semiconductor film is formed over a substrate, and is heated. A thermal expansion coefficient of the substrate is 6×10 | 2015-06-25 |
20150179814 | GRAPHENE DEVICES AND METHODS OF MANUFACTURING THE SAME - A graphene device may include a channel layer including graphene, a first electrode and second electrode on a first region and second region of the channel layer, respectively, and a capping layer covering the channel layer and the first and second electrodes. A region of the channel layer between the first and second electrodes is exposed by an opening in the capping layer. A gate insulating layer may be on the capping layer to cover the region of the channel layer, and a gate may be on the gate insulating layer. | 2015-06-25 |
20150179815 | Quantum Well IGZO Devices and Methods for Forming the Same - Embodiments described herein provide indium-gallium-zinc oxide (IGZO) devices, such as IGZO thin-film transistors (TFTs), and methods for forming such devices. A substrate is provided. A gate electrode is formed above the substrate. An IGZO channel layer is formed above the gate electrode. The IGZO channel layer has a first sub-layer including crystalline IGZO, a second sub-layer including amorphous IGZO, and a third sub-layer including magnesium and zinc. A source electrode and a drain electrode are formed above the IGZO channel layer. | 2015-06-25 |
20150179816 | NON-VOLATILE MEMORY (NVM) CELL AND A METHOD OF MAKING - A method of forming a flash memory cell includes forming a first hard mask and a second hard mask on a substrate. A select gate is formed as a spacer around the first hard mask. A charge storage layer is formed over the first and second hard masks and the select gate. A control gate is formed as a spacer around the second hard mask. A recess in the control gate is filled with a dielectric material. The recess is formed between a curved sidewall of the control gate and a sidewall of the charge storage layer directly adjacent the curved sidewall of the control gate. | 2015-06-25 |
20150179817 | Gate Formation Memory by Planarization - Semiconductor devices and methods of producing the devices are disclosed. The devices are formed by forming a gate structure on a substrate. The gate structure includes a charge trapping dielectric formed between the substrate and a first poly layer. A top dielectric is formed over the poly layer and a sidewall dielectric is formed on a side of the poly layer. A second poly layer is formed over the gate structure such that a portion of the second poly layer includes a vertical portion that is in contact with the sidewall dielectric and a top portion that is in contact with the top dielectric. The top portion of the second poly layer can then be removed through, for instance, planarization. | 2015-06-25 |
20150179818 | METHOD OF MANUFACTURING NONVOLATILE SEMICONDUCTOR STORAGE DEVICE AND NONVOLATILE SEMICONDUCTOR STORAGE DEVICE - A method of nonvolatile semiconductor storage device including forming a tunnel insulating film so as to contact a semiconductor substrate; forming a charge trap layer above the tunnel insulating film including a trap layer configured to trap charge and a block layer configured to block penetration of electrons; forming a control electrode so as to contact the charge trap layer; anisotropically etching the control electrode to expose a sidewall of the control electrode; depositing a deposit so as to be attached to a surface of the sidewall of the control electrode exposed by the etching; and anisotropically etching the charge trap layer using the deposit as a mask so that the charge trap layer projects in a gate-length direction from a lower end of the sidewall of the control electrode and a sidewall of the charge trap layer is exposed. | 2015-06-25 |
20150179819 | NON-VOLATILE MEMORY DEVICE INCLUDING CHARGE TRAPPING LAYER AND METHOD FOR FABRICATING THE SAME - A non-volatile memory device includes a charge trapping layer for trapping charges. The charge trapping layer includes a linker layer formed over a substrate and including linkers to be bonded to metal ions metallic nanoparticles formed out of the metal ions over the linker layer and a nitride filling gaps between the metallic nanoparticles. | 2015-06-25 |
20150179820 | NON-VOLATILE MEMORY DEVICE INCLUDING FLEXIBLE CHARGE TRAPPING LAYER AND METHOD FOR FABRICATING THE SAME - A non-volatile memory device includes a charge trapping layer for trapping charges over a flexible substrate. The charge trapping layer includes a linker layer formed over the flexible substrate and including linkers to be bonded to metal ions; metallic nanoparticles formed out of the metal ions over the linker layer; and a nitride filling gaps between the metallic nanoparticles. | 2015-06-25 |
20150179821 | SELECTIVE GATE OXIDE PROPERTIES ADJUSTMENT USING FLUORINE - Fluorine is located in selective portions of a gate oxide to adjust characteristics of the gate oxide. In some embodiments, the fluorine promotes oxidation which increases the thickness of the selective portion of the gate oxide. In some embodiments, the fluorine lowers the dielectric constant of the oxide at the selective portion. In some examples, having fluorine at selective portions of a select gate oxide of a non volatile memory may reduce program disturb of the memory. | 2015-06-25 |
20150179822 | SEMICONDUCTOR DEVICE CAPABLE OF REDUCING INFLUENCES OF ADJACENT WORD LINES OR ADJACENT TRANSISTORS AND FABRICATING METHOD THEREOF - A semiconductor device capable of reducing influences of adjacent word lines is provided in the present invention. The semiconductor device includes: a substrate, and a word line disposed in the substrate. The word line includes: a gate electrode, a gate dielectric layer disposed between the gate electrode and the substrate and at least one first charge trapping dielectric layer disposed adjacent to the gate electrode, wherein the first charge trapping dielectric layer comprises HfO | 2015-06-25 |
20150179823 | ELECTRODE STRUCTURE FOR NITRIDE SEMICONDUCTOR DEVICE, PRODUCTION METHOD THEREFOR, AND NITRIDE SEMICONDUCTOR FIELD-EFFECT TRANSISTOR - According to an electrode structure of an embodiment of the invention, an ohmic electrode is provided from recess to a surface of an insulating film without being in contact with the surface of the nitride semiconductor multilayer body, so that the insulating film covers the surface of the AlGaN barrier layer. Accordingly, during the formation process of the ohmic electrode by dry etching, the surface of the nitride semiconductor multilayer body can be protected by the insulating film. | 2015-06-25 |
20150179824 | PROCESS FOR FORMING A PLANAR DIODE USING ONE MASK - A planar diode and method of making the same employing only one mask. The diode is formed by coating a substrate with an oxide, removing a central portion of the oxide to define a window through which dopants are diffused. The substrate is given a Ni/Au plating to provide ohmic contact surfaces, and the oxide on the periphery of the window is coated with a polyimide passivating agent overlying the P/N junction. | 2015-06-25 |
20150179825 | DIODE DEVICE AND METHOD OF MANUFACTURING THE SAME - A diode device may include a first conductivity type first semiconductor region, a second conductivity type second semiconductor region partially formed inside an upper portion of the first semiconductor region, and second conductivity type third semiconductor regions partially formed inside the upper portion of the first semiconductor region, formed on sides of the second semiconductor region, and having an impurity concentration higher than that of the second semiconductor region. | 2015-06-25 |
20150179826 | DIODE DEVICE AND METHOD OF MANUFACTURING THE SAME - A diode device may include: a first semiconductor area having a first conductivity type; a second semiconductor area having a second conductivity type, provided on the first semiconductor area and having a uniform impurity density; a trench provided to pass through the second semiconductor area to contact the first semiconductor area; and a first metal layer provided on surfaces of the trench and the second semiconductor area. | 2015-06-25 |
20150179827 | Sensor Module and Method of Manufacturing the Same - The opto-electronic module ( | 2015-06-25 |
20150179828 | ARRANGEMENT WITH A COMPONENT ON A CARRIER SUBSTRATE, AN ARRANGEMENT AND A SEMI-FINISHED PRODUCT - An arrangement including a carrier substrate, and a component situated on a cover surface of the carrier substrate in a hollow space, and electrical contacts for the component, wherein the hollow space is comprised of a plurality of spacer elements arranged on the cover surface of the carrier substrate and a cover substrate mounted on the plurality of spacer elements is provided. A semi-finished product comprising a carrier substrate made of silicon, wherein one or more recesses are formed on one side of the carrier substrate, and wherein the semi-finished product further comprises an alkaline evaporated glass applied to the side of the carrier substrate having the one or more recesses is also provided. | 2015-06-25 |
20150179829 | COMPOSITION FOR FORMING PASSIVATION LAYER, SEMICONDUCTOR SUBSTRATE WITH PASSIVATION LAYER, METHOD OF PRODUCING SEMICONDUCTOR SUBSTRATE WITH PASSIVATION LAYER, PHOTOVOLTAIC CELL ELEMENT, METHOD OF PRODUCING PHOTOVOLTAIC CELL ELEMENT AND PHOTOVOLTAIC CELL - The composition for forming a passivation layer includes an organic aluminum compound represented by Formula (I) and an organic compound represented by Formula (II). In Formula (I), each R | 2015-06-25 |
20150179830 | OPTICAL SENSOR - An optical sensor includes a light receiving portion, a definition portion, and a selection portion. The definition portion defines an incident angle of an incident light that enters the light receiving portion. The selection portion selects a wavelength of the incident light that enters the light receiving portion. The definition portion has a light shielding film disposed above the light receiving portion, and an opening formed in the light shielding film. The selection portion has a slit formed in the light shielding film disposed within a region surrounded by the opening. | 2015-06-25 |
20150179831 | SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF - A semiconductor structure includes a silicon substrate, a protection layer, an electrical pad, an isolation layer, a redistribution layer, a conductive layer, a passivation layer, and a conductive structure. The silicon substrate has a concave region, a step structure, a tooth structure, a first surface, and a second surface opposite to the first surface. The step structure and the tooth structure surround the concave region. The step structure has a first oblique surface, a third surface, and a second oblique surface facing the concave region and connected in sequence. The protection layer is located on the first surface of the silicon substrate. The electrical pad is located in the protection layer and exposed through the concave region. The isolation layer is located on the first and second oblique surfaces, the second and third surfaces of the step structure, and the tooth structure. | 2015-06-25 |
20150179832 | PHOTODETECTORS BASED ON WURTZITE MgZnO - A photodetector (PD) includes a substrate, and a ZnO nucleation layer on the substrate. A wurtzite Mg | 2015-06-25 |
20150179833 | Photodetector and Method for Manufacturing the Same - A photodetector includes a substrate and an insulating arrangement formed in the substrate. The insulating arrangement electrically insulates a confined region of the substrate. The confined region is configured to generate free charge carriers in response to an irradiation. The photodetector further includes a read-out electrode arrangement configured to provide a photocurrent formed by at least a portion of the free charge carriers that are generated in response to the irradiation. The photodetector also includes a biasing electrode arrangement that is electrically insulated against the confined region by means of the insulating arrangement. The biasing electrode arrangement is configured to cause an influence on a spatial charge carrier distribution within the confined region so that fewer of the free charge carriers recombine at boundaries of the confined region compared to an unbiased state. | 2015-06-25 |
20150179834 | BARRIER-LESS METAL SEED STACK AND CONTACT - Approaches for forming barrier-less seed stacks and contacts are described. In an example, a solar cell includes a substrate and a conductive contact disposed on the substrate. The conductive contact includes a copper layer directly contacting the substrate. In another example, a solar cell includes a substrate and a seed layer disposed directly on the substrate. The seed layer consists essentially of one or more non-diffusion-barrier metal layers. A conductive contact includes a copper layer disposed directly on the seed layer. An exemplary method of fabricating a solar cell involves providing a substrate, and forming a seed layer over the substrate. The seed layer includes one or more non-diffusion-barrier metal layers. The method further involves forming a conductive contact for the solar cell from the seed layer. | 2015-06-25 |
20150179835 | Solar Cell - A solar cell includes an opto-electrical conversion structure, a first electrically-conductive structure, and a second electrically-conductive structure. The opto-electrical conversion structure has a light receiving surface and a back surface opposite to the light receiving surface. The first electrically-conductive structure is disposed on the light receiving surface and electrically connected to the opto-electrical conversion structure. The first electrically-conductive structure includes a first transparent electrically-conductive layer, an electrode structure, and a second transparent electrically-conductive layer. The first transparent electrically-conductive layer is disposed on the light receiving surface of the opto-electrical conversion structure. At least one portion of the first transparent electrically-conductive layer is disposed between the electrode structure and the light receiving surface of the opto-electrical conversion structure. The second transparent electrically-conductive layer covers the electrode structure and the first transparent electrically-conductive layer. The second electrically-conductive structure is disposed on the back surface of the opto-electrical conversion structure. | 2015-06-25 |
20150179836 | METALLIZATION OF SOLAR CELLS - Approaches for the metallization of solar cells and the resulting solar cells are described. In an example, a method of fabricating a solar cell involves forming a barrier layer on a semiconductor region disposed in or above a substrate. The semiconductor region includes monocrystalline or polycrystalline silicon. The method also involves forming a conductive paste layer on the barrier layer. The method also involves forming a conductive layer from the conductive paste layer. The method also involves forming a contact structure for the semiconductor region of the solar cell, the contact structure including at least the conductive layer. | 2015-06-25 |
20150179837 | SOLAR CELL AND METHOD FOR MANUFACTURING THE SAME - A solar cell is discussed. The solar cell includes a semiconductor substrate of a first conductive type, an emitter region of a second conductive type opposite the first conductive type, which is positioned at a front surface of the semiconductor substrate, a front passivation part positioned on a front surface of the emitter region, a front electrode part which passes through the front passivation part and is electrically connected to the emitter region, a back passivation part positioned on a back surface of the semiconductor substrate, and a back electrode part which passes through the back passivation part and is electrically connected to the semiconductor substrate. The front passivation part and the back passivation part each include a silicon oxide layer. One of the front passivation part and the back passivation part includes an aluminum oxide layer. | 2015-06-25 |
20150179838 | SOLAR CELL EMITTER REGION FABRICATION WITH DIFFERENTIATED P-TYPE AND N-TYPE REGION ARCHITECTURES - Methods of fabricating solar cell emitter regions with differentiated P-type and N-type regions architectures, and resulting solar cells, are described. In an example, a back contact solar cell includes a substrate having a light-receiving surface and a back surface. A first polycrystalline silicon emitter region of a first conductivity type is disposed on a first thin dielectric layer disposed on the back surface of the substrate. A second polycrystalline silicon emitter region of a second, different, conductivity type is disposed on a second thin dielectric layer disposed on the back surface of the substrate. A third thin dielectric layer is disposed laterally directly between the first and second polycrystalline silicon emitter regions. A first conductive contact structure is disposed on the first polycrystalline silicon emitter region. A second conductive contact structure is disposed on the second polycrystalline silicon emitter region. | 2015-06-25 |
20150179839 | CONTACT LAYERS FOR PHOTOVOLTAIC DEVICES - Solar cells and methods for forming a back contact layer for a solar cell are disclosed. The methods comprise depositing a first layer comprising a conductor on a substrate, depositing a second layer on the first layer, the second layer comprising between about 1 nm and about 25 nm of a metal chalcogenide, and forming a third layer operable as an absorber layer on the second layer. The absorber layer can comprise a photoactive semiconductor layer. In some embodiments, the absorber layer comprises a chalcogenide of copper-indium-gallium. In some embodiments, the absorber layer comprises a chalcogenide of copper-zinc-tin. In some embodiments, the absorber layer comprises CdTe. In some embodiments, the metal comprises Mo, W or Ta. In some embodiments, the metal comprises Mo. In some embodiments, the chalcogenide comprises S or Se or a combination thereof. | 2015-06-25 |
20150179840 | LIGHT RECEIVING/EMITTING ELEMENT, SOLAR CELL, OPTICAL SENSOR, LIGHT EMITTING DIODE, AND SURFACE EMITTING LASER ELEMENT TECHNICAL FIELD - A light receiving/emitting element | 2015-06-25 |
20150179841 | SOLAR CELL AND METHOD OF FABRICATING THE SAME - A solar cell according to the embodiment includes a light absorbing layer; a buffer layer on the light absorbing layer; a high resistance buffer layer on the buffer layer; and a window layer on the buffer layer, wherein the high resistance buffer layer has an energy bandgap higher than an energy bandgap of the window layer. | 2015-06-25 |
20150179842 | RECTIFIER AND TERAHERTZ DETECTOR USING THE SAME - Disclosed is a rectifier capable of performing a high speed rectifying operation, and includes: a first semiconductor layer; a second semiconductor layer; and a third semiconductor layer, in which the first semiconductor layer and the third semiconductor layer are formed of semiconductor layers having the same type, and the second semiconductor layer is formed between the first semiconductor layer and the third semiconductor layer, is formed of a semiconductor layer having a different type from that of the first semiconductor layer and the third semiconductor layer, and is formed in graded doped state. | 2015-06-25 |
20150179843 | PHOTOVOLTAIC DEVICE - A photovoltaic device includes a photovoltaic portion having light-receiving surface that receives light, the photovoltaic portion including a nano-structure. the nano-structure includes one or more first regions and one or more second regions. In each of the one or more first regions, semiconductor layer portions are arranged at a first density, and in each of the one or more second regions, at least one semiconductor layer portion is arranged at a second density lower than the first density. The nano-structure includes an insulator having a refractive index lower than that of the semiconductor layer portions arranged in the one or more first regions and the one or more second regions. | 2015-06-25 |
20150179844 | INAS/ALSB/GASB BASED TYPE- II SL PIN DETECTOR WITH P ON N AND N ON P CONFIGURATIONS - Novel N-structured In As/Al Sb(Al Ga Sb)/Ga Sb based type-II SL pin detector with p on n and n on p configurations are given to detect light in the Mid Wavelength Infrared Range-MWIR with a cut-off wavelength of 5 μm. Better carrier confinements are performed by placing AlSb layers switching from InAs layers to Ga Sb layers successively in the growth direction throughout the SL pin diode where zero bias detectivity is improved as 6×10 | 2015-06-25 |
20150179845 | SOLID-STATE IMAGING DEVICE, LIGHT DETECTING DEVICE, AND ELECTRONIC APPARATUS - A solid-state imaging device includes a Multi-Quantum Wells (MQW) structure which combines and uses a non-Group IV lattice matching-based compound semiconductor with an absolute value of a mismatch ratio of less than 1% on a silicon substrate so as to have sensitivity to at least infrared light. | 2015-06-25 |
20150179846 | STRUCTURES AND FABRICATION METHODS FOR SOLAR CELLS AND MODULES - Solar module structures and methods for assembling solar module structures. The solar module structures may be used in solar glass applications, building facade applications, rooftop installation applications as well as for centralized solar electricity generation. | 2015-06-25 |
20150179847 | BUILT-IN BYPASS DIODE - A bypass diode can include a first conductive region of a first conductivity type disposed above a substrate of a solar cell and a second conductive region of a second conductivity type disposed above the first conductive region. The bypass diode can include a thin dielectric region disposed directly between the first and second conductive regions. | 2015-06-25 |
20150179848 | DEPLOYABLE SOLAR PANEL SYSTEM - A deployable solar panel system including a basic unit of a plurality of photovoltaic (PV) panels electrically interconnected to each other and mechanically interconnected to each other by a hinge bonded to each PV panel, thereby allowing the basic unit to be folded for transportation and storage into a compact form and then unfolded for installation. | 2015-06-25 |
20150179849 | SOLAR CELL MODULE - Disclosed is a solar cell that includes a sealant, a solar cell within the sealant and having a front surface for exposure to light, a first protective member facing a front surface of the solar cell, a second protective member facing a rear surface of the solar cell, a wiring member on a rear surface of the solar cell and containing Cu. The sealant includes a first sealant layer over the rear surface of the solar cell and having relatively high viscosity, and a second sealant layer disposed between the first sealant layer and the solar cell and having relatively low viscosity. The first sealant layer disposed on a side of second protective member is in contact with a main surface of the wiring member, and the second sealant layer is in contact with a side surface of the wiring member. | 2015-06-25 |
20150179850 | RESIN FILM, BACKSHEET FOR SOLAR CELL MODULE, AND SOLAR CELL MODULE - To provide a resin film having excellent ultraviolet shielding properties, having an excellent outer appearance, further heaving excellent weather resistance, being hardly changeable in optical properties and mechanical properties over a long period of time, and being capable of being formed into a thin film of at most 20 μm, a backsheet provided with the resin film, and a solar cell module provided with the backsheet. | 2015-06-25 |
20150179851 | BIAXIALLY STRETCHED POLYESTER FILM FOR PROTECTING BACK SURFACE OF SOLAR CELL, AND METHOD FOR PRODUCING POLYESTER RESIN - A biaxially stretched polyester film for protecting a back surface of a solar cell, containing a polyester resin that is polymerized with addition of a Ti catalyst, a Mg compound, a P compound and a nitrogen-containing heterocyclic compound, and having a volume resistivity at 285° C. is 10×10 | 2015-06-25 |
20150179852 | SEALING FILM FOR SOLAR CELLS, SOLAR CELL MODULE, AND METHOD FOR SELECTING SEALING FILM FOR SOLAR CELLS - A sealing film for solar cells for a solar cell module constituting a solar power generation system with a system voltage of 600 V or more, and is capable of suppressing the generation of PID phenomenon; and a solar cell module are provided. Such sealing film for solar cells consists of a crosslinkable curable film of a composition containing an ethylene-polar monomer copolymer and a crosslinking agent. The film is characterized in that the product (92 v·t) of a volume resistivity (ρv [Ω·cm]) at 25° C. (JIS K6911-1995) of the sealing film after crosslinking curing and a thickness (t [cm]) of the sealing film for solar cells is 5.0×10 | 2015-06-25 |
20150179853 | POWER SOURCE FOR AN ACCOMMODATING INTRAOCULAR LENS - A power supply including a luminescent solar concentrator (LSC) adapted for placement in an eye includes a base material transparent to visible light; and fluorescent particles doped within the base material. The fluorescent particles are capable of absorbing and reemitting light in the ultraviolet spectrum. A concentration of the fluorescent particles as a function of radius from an optical axis of the LSC is reduced in at least a portion of the base material outside of a pupil diameter. At least one photovoltaic cell is configured to receive the light in the ultraviolet spectrum trapped within the base material and to convert the trapped light into electricity. | 2015-06-25 |
20150179854 | METHOD OF PACKAGING BALL LENS OF SOLAR COLLECTOR AND STRUCTURE THEREOF - A method of packaging ball lends of a solar collector contains step of coating optical clear adhesives on colloid layers twice, and the optical clear adhesives are solidified so that a solar cell, plural gold wires, and an electric circuit are packaged, thus eliminating use of a conventional support component, lowering weight of the solar collector, and simplifying the solar collector. Moreover, a dam is applied to absorb stray light so as to enhance light absorption of the solar cell and working efficiency of the solar collector. | 2015-06-25 |
20150179855 | Linear Condensation Assembly and Manufacturing Process Thereof - Provided are a linear condensation assembly and a manufacturing process therefor. The linear condensation assembly comprises a linear condensation glass panel, a sealing material layer, a solar cell and a back panel. The manufacturing process comprises: testing cell pieces in a grading manner; cutting the cell pieces; welding strip-shaped cells; and serially welding, stacking, inspecting and testing grid cell pieces ( | 2015-06-25 |
20150179856 | OPTICAL ELEMENT AND CONCENTRATING PHOTOVOLTAIC DEVICE - Provided are an optical element and a concentrating photovoltaic device which are each capable of preventing warpage and deformation of an optical functional pattern formed in a surface thereof due to stress even in an environment with extreme temperature changes. An optical element ( | 2015-06-25 |
20150179857 | SEMICONDUCTOR EPITAXIAL STRUCTURES AND SEMICONDUCTOR OPTOELECTRONIC DEVICES COMPRISING THE SAME - An optoelectronic device comprises a substrate; a converting structure for converting energy between light and electric current over the substrate; and a semiconductor buffer layer combination between the substrate and the converting structure, the semiconductor buffer layer combination comprising multiple first semiconductor layers and multiple second semiconductor layers alternately stacked, wherein each of the multiple first semiconductor layers comprises a first element, each of the multiple second semiconductor layers comprises a second element different from the first element, and the composition ratio of the first element gradually increases or decreases with an increase of the distance between the first semiconductor layers and the substrate. | 2015-06-25 |
20150179858 | SOLAR CELL AND MANUFACTURING METHOD THEREOF - A solar cell includes a crystalline silicon semiconductor substrate, an intrinsic amorphous silicon semiconductor layer, an amorphous silicon semiconductor layer and a transparent conductive layer. The crystalline silicon semiconductor substrate possesses a first doped type and a trench is formed thereon to form an enclosed area to define a first electrode region in the enclosed area and a second electrode region out of the enclosed area. The intrinsic amorphous silicon semiconductor layer, the amorphous silicon semiconductor layer and the transparent conductive layer are formed sequentially on the crystalline silicon semiconductor substrate and in the trench. Having discontinuity in the trench, the amorphous silicon semiconductor layer, the amorphous silicon semiconductor layer and the transparent conductive layer provide an isolation function between the previously defined first and second electrode regions. | 2015-06-25 |
20150179859 | SOLAR CELL WITH REDUCED ABSORBER THICKNESS AND REDUCED BACK SURFACE RECOMBINATION - Manufacture for an improved stacked-layered thin film solar cell. Solar cell has reduced absorber thickness and an improved back contact for Copper Indium Gallium Selenide solar cells. The back contact provides improved reflectance particularly for infrared wavelengths while still maintaining ohmic contact to the semiconductor absorber. This reflectance is achieved by producing a back contact having a highly reflecting metal separated from an absorbing layer with a dielectric layer. | 2015-06-25 |
20150179860 | CHALCOGENIDE-BASED MATERIALS AND IMPROVED METHODS OF MAKING SUCH MATERIALS - The present invention provides strategies for making high quality CIGS photoabsorbing materials from precursor films that incorporate a sub-stoichiometric amount of chalcogen(s). Chalcogen(s) are incorporated into the CIGS precursor film via co-sputtering with one or more other constituents of the precursor. Optional annealing also may be practiced to convert precursor into more desirable chalcopyrite crystalline form in event all or a portion of the precursor has another constitution. The resultant precursors generally are sub-stoichiometric with respect to chalcogen and have very poor electronic characteristics. The conversion of these precursors into CIGS photoabsorbing material via chalcogenizing treatment occurs with dramatically reduced interfacial void content. The resultant CIGS material displays excellent adhesion to other layers in the resultant photovoltaic devices. Ga migration also is dramatically reduced, and the resultant films have optimized Ga profiles in the top or bottom portion of the film that improve the quality of photovoltaic devices made using the films. | 2015-06-25 |
20150179861 | ETCHING OF INFRARED SENSOR MEMBRANE - The invention relates to an infrared thermal sensor comprising a substrate having a cavity, a cavity bottom wall formed by a continuous substrate surface. The sensor comprises a membrane adapted for receiving heat from incident infrared radiation, a beam suspending the membrane, and a thermocouple. This membrane comprises openings extending through the membrane for facilitating the passage of an anisotropic etchant for etching the cavity during manufacture. Each opening has a cross-section with a length to width ratio of at least 4. The width direction of respectively a first and a second set of openings is oriented according to respectively a first crystallographic orientation and a second crystallographic orientation, these orientations corresponding to different directions lying in loosely packed crystal lattice faces of the semiconductor substrate. | 2015-06-25 |
20150179862 | Avalanche Photodiode Detector - An avalanche photodiode detector is provided. The avalanche photodiode detector comprises an absorber region having an absorption layer for receiving incident photons and generating charged carriers; and a multiplier region having a multiplication layer; wherein the multiplier region is on a mesa structure separate from the absorber region and is coupled to the absorber region by a bridge for transferring charged carriers between the absorber region and multiplier region. | 2015-06-25 |
20150179863 | AVALANCHE PHOTODIODE UTILIZING INTERFACIAL MISFIT ARRAY - According to some embodiments of the present invention, an avalanche photodiode includes a first electrode, a second electrode spaced apart from the first electrode, a photon absorber layer formed to be in electrical connection with the first electrode, and a charge-carrier multiplication layer formed to be in electrical connection with the second electrode. The photon absorber layer is a semiconducting material that has a first lattice constant, and the charge-carrier multiplication layer is a semiconducting material that has a second lattice constant that is different from the first lattice constant. The photon absorber layer and the charge-carrier multiplication layer are connected together by an interfacial misfit (IMF) array at an interface thereof such that the IMF array provides at least part of an acceleration potential for an avalanche region of the avalanche photodiode. | 2015-06-25 |
20150179864 | CMOS INTEGRATED METHOD FOR THE FABRICATION OF THERMOPILE PIXEL WITH UMBRELLA ABSORBER ON SEMICONDUCTOR SUBSTRATE - A method of manufacturing a pixel structure having an umbrella absorber is disclosed. The method includes providing a substrate with a membrane on a first surface of the substrate. The membrane has one or more openings that expose one or more portions of the first surface, and includes a thermopile. A sacrificial layer is deposited on the membrane and in the one or more openings. The sacrificial layer is patterned to expose a portion of the membrane associated with one or more hot junctions of the thermopile. A rigid, thermally-conductive layer is formed on the sacrificial layer and on the exposed portion of the membrane associated with the one or more hot junctions of the thermopile. An absorber is deposited on the rigid, thermally-conductive layer. A cavity is formed in the substrate from a second surface of the substrate to the membrane and the sacrificial layer is removed. | 2015-06-25 |
20150179865 | SINGLE-STEP METAL BOND AND CONTACT FORMATION FOR SOLAR CELLS - A method for fabricating a solar cell is disclosed. The method can include forming a dielectric region on a surface of a solar cell structure and forming a first metal layer on the dielectric region. The method can also include forming a second metal layer on the first metal layer and locally heating a particular region of the second metal layer, where heating includes forming a metal bond between the first and second metal layer and forming a contact between the first metal layer and the solar cell structure. The method can include forming an adhesive layer on the first metal layer and forming a second metal layer on the adhesive layer, where the adhesive layer mechanically couples the second metal layer to the first metal layer and allows for an electrical connection between the second metal layer to the first metal layer. | 2015-06-25 |
20150179866 | METAL BOND AND CONTACT FORMATION FOR SOLAR CELLS - A method for fabricating a solar cell is disclosed. The method can include forming a dielectric region on a surface of a solar cell structure and forming a first metal layer on the dielectric region. The method can also include forming a second metal layer on the first metal layer and locally heating a particular region of the second metal layer, where heating includes forming a metal bond between the first and second metal layer and forming a contact between the first metal layer and the solar cell structure. The method can include forming an adhesive layer on the first metal layer and forming a second metal layer on the adhesive layer, where the adhesive layer mechanically couples the second metal layer to the first metal layer and allows for an electrical connection between the second metal layer to the first metal layer. | 2015-06-25 |
20150179867 | METHOD FOR MANUFACTURING PHOTOELECTRIC CONVERSION DEVICE - In a method for manufacturing a photoelectric conversion device which includes: a substrate including a photoelectric conversion element; and a light guide which includes an insulator having an opening corresponding to the photoelectric conversion element and containing silicon oxide and a member located in the opening and containing silicon nitride, the method includes: forming a first silicon nitride film which forms the member in the opening by a parallel plate type plasma CVD apparatus; and forming a second silicon nitride film which forms the member in the opening and on the first silicon nitride film by a high density plasma CVD apparatus. In the photoelectric conversion device, the first silicon nitride film has a thickness of 55 nm or more. | 2015-06-25 |
20150179868 | CHALCOGENIDE-BASED PHOTOVOLTAIC DEVICES AND METHODS OF MANUFACTURING THE SAME - In one example embodiment, a method includes sputtering one or more absorber layers over a substrate. In a particular embodiment, the substrate is pre-heated to a substrate temperature of at least approximately 300 degrees Celsius prior to the sputtering and during the sputtering of each of one or more of the absorber layers, and the sputtering of at least one of the absorber layers is performed in a sputtering atmosphere having a pressure of at least 0.5 Pascals. Additionally, in a particular embodiment, the sputtering of at least one of the absorber layers comprises sputtering from a sputter target that comprises a chalcogenide alloy that comprises copper (Cu) and one or more of sulfur (S), selenium (Se), or tellurium (Te). | 2015-06-25 |
20150179869 | AMORPHOUS SILICON PHOTOELECTRIC DEVICE AND FABRICATING METHOD THEREOF - An amorphous-silicon photoelectric device and a fabricating method thereof are disclosed. The amorphous-silicon photoelectric device includes: a substrate; a thin-film transistor and a photosensor with the photodiode structure, which are provided at different positions on the substrate; and a contact layer; in which the contact layer is located below the photosensor, and the contact layer is partially covered by the photosensor, moreover, the contact layer and the gate-electrode layer in the thin-film transistor are provided in a same layer and of a same material. According to the technical solutions of the present disclosure, the fabricating procedure of an a-Si photoelectric device can be simplified, thereby improving the fabrication efficiency and reducing costs. | 2015-06-25 |
20150179870 | CONTACTS FOR SOLAR CELLS - A method of fabricating a solar cell is disclosed. The method can include forming a dielectric region on a surface of a solar cell structure and forming a metal layer on the dielectric layer. The method can also include configuring a laser beam with a particular shape and directing the laser beam with the particular shape on the metal layer, where the particular shape allows a contact to be formed between the metal layer and the solar cell structure. | 2015-06-25 |
20150179871 | METHOD OF MANUFACTURING THIN-FILM PHOTOVOLTAIC MODULE - A method of manufacturing a thin-film photovoltaic module in which a photoelectric conversion element is deposited on a substrate, includes removing the photoelectric conversion element at a frame shape area from sides of the substrate toward inside with a predetermined width by a first removing step of scanning a first photoelectric conversion element removing device at the area along the sides of the substrate to remove the photoelectric conversion element for the predetermined width, and a second removing step of scanning a second photoelectric conversion element removing device within the area along the sides of the substrate to remove the photoelectric conversion element that is not removed in the first removing step at a width narrower than the predetermined width and without superimposing a center line of a scanning path on a center line of a scanning path of the first photoelectric conversion element removing device. | 2015-06-25 |
20150179872 | LIGHT-EMITTING DEVICE - A light emitting device comprising a plurality of current spreading layers including a first P doped layer, a first N doped layer and a second P doped layer, wherein the N doped layer having a doping level and thickness configured for substantial depletion or full depletion. | 2015-06-25 |
20150179873 | SMALL-SIZED LIGHT-EMITTING DIODE CHIPLETS AND METHOD OF FABRICATION THEREOF - Diode includes light emitting region, first metal layer, dielectric layer, and second metal layer. Light emitting diode includes n-type group III-nitride portion, p-type group III-nitride layer, and light emitting region sandwiched between n- and p-type layers. First metal layer may be coupled to p-type III-N portion and plurality of first terminals. First metal layer and p-type III-N portion may have substantially similar lateral size that is smaller than 200 micrometers. A portion of light emitting region and first metal layer may include a single via. Electrically-insulating layer may be coupled to first metal layer and sides of the single via. First terminals may be exposed from electrically-insulating layer. Second metal layer may include second terminal and may be coupled to electrically-insulating layer and to n-type III-N portion through the single via. The thickness of the diode excluding second terminal may be between 2 and 20 micrometers. Other embodiments are described. | 2015-06-25 |
20150179874 | LIGHT EMITTING DIODE STRUCTURE - A light emitting diode (LED) structure includes a substrate, a N-type semiconductor layer, a light emitting layer and a P-type semiconductor layer. The N-type semiconductor layer is disposed on the substrate. The light emitting layer is adapted to emit a light with dominant wavelength between 365 nm and 490 nm and disposed on the N-type semiconductor layer. The P-type semiconductor layer is disposed on the blue light emitting layer and includes a P—AlGaN layer. A thickness of the P—AlGaN layer is more than 85% a thickness of the P-type semiconductor layer. | 2015-06-25 |
20150179875 | TEMPLATE FOR GROWING SEMICONDUCTOR, METHOD OF SEPARATING GROWTH SUBSTRATE AND METHOD OF FABRICATING LIGHT EMITTING DEVICE USING THE SAME - A template for growing a semiconductor, a method of separating a growth substrate and a method of fabricating a light emitting device using the same are disclosed. The template for growing a semiconductor includes a growth substrate including a nitride substrate; a seed layer disposed on the growth substrate and including at least one trench; and a growth stop layer disposed on a bottom surface of the trench, wherein the trench includes an upper trench and a lower trench, and the upper trench has a smaller width than the lower trench. | 2015-06-25 |
20150179876 | LED WITH CURRENT INJECTION CONFINEMENT TRENCH - A method and structure for forming an array of LED devices is disclosed. The LED devices in accordance with embodiments of the invention may include a confined current injection area, embedded mirror, or sidewall passivation layer, and any combination thereof. | 2015-06-25 |
20150179877 | NANOWIRE DEVICE - A nanowire device and a method of forming a nanowire device that is poised for pick up and transfer to a receiving substrate are described. In an embodiment, the nanowire device includes a base layer and a nanowire on and protruding away from a first surface of the base layer. The nanowire may include a core, a shell, and an active layer between the core and the shell. A top electrode layer may be on a second surface of the base layer opposite the first surface and in electrical contact with the core, and a bottom electrode layer may be on and electrical contact with the shell. In an embodiment, the base layer is characterized by a maximum width of the micro scale, and the nanowire is characterized by a maximum width or length of the nano scale. | 2015-06-25 |
20150179878 | LIGHT EMITTING DEVICE - The disclosed light emitting device includes an intermediate layer interposed between the light emitting semiconductor structure and the substrate. The light emitting semiconductor structure includes a first conductivity-type semiconductor layer, a second conductivity-type semiconductor layer, and an active layer interposed between the first conductivity-type semiconductor layer and the second conductivity-type semiconductor layer, wherein the active layer has a multi quantum well structure including at least one period of a pair structure of a quantum barrier layer including Al | 2015-06-25 |
20150179879 | LIGHT EMITTING DIODE WITH IMPROVED LIGHT EXTRACTION EFFICIENCY - Disclosed is a light emitting diode (LED) having improved light extraction efficiency. The LED includes a light emitting structure positioned on a substrate and having a first semiconductor layer, an active layer and a second semiconductor layer. A first electrode pad is electrically connected to the first semiconductor layer. A second electrode pad is positioned on the substrate. An insulating reflective layer covers a portion of the light emitting structure, and is positioned under the second electrode pad, so that the second electrode pad is spaced apart from the light emitting structure. At least one upper extension is connected to the second electrode pad to be electrically connected to the second semiconductor layer. Further, a pattern of light extraction elements is positioned on the second semiconductor layer. | 2015-06-25 |
20150179880 | NITRIDE SEMICONDUCTOR STRUCTURE - A nitride light emitting diode structure including a first type doped semiconductor layer, a second type doped semiconductor layer, a light emitting layer, a first metal pad, a second metal pad and a magnetic film is disclosed. The magnetic film disposed between the first metal pad and the first type doped semiconductor layer includes a zinc oxide (ZnO) layer doped with cobalt (Co). The content of Co in the ZnO layer ranges from 5% to 25% by molar ratio. | 2015-06-25 |
20150179881 | NITRIDE LED STRUCTURE WITH DOUBLE GRADED ELECTRON BLOCKING LAYER - A group III nitride-based light emitting device includes an n-type semiconductor layer; a first p-type semiconductor layer; an active region; and an electron blocking region comprising AlGaInN located between the active region and the first p-type semiconductor layer, and including at least an upgraded layer and a downgraded layer. An aluminium composition of the upgraded layer of the electron blocking region increases from an active region side to a first p-type semiconductor layer side of the electron blocking region, and an aluminium composition of the downgraded layer of the electron blocking region decreases from the active region side to the first p-type semiconductor layer side of the electron blocking region. The nitride-based light emitting device may be a light emitting diode or a laser diode. | 2015-06-25 |
20150179882 | LIGHT EMITTING DEVICE AND LIGHT EMITTING DEVICE PACKAGE HAVING THE SAME - Disclosed is a light emitting device. The light emitting device includes a light emitting structure including a first conductivity-type semiconductor layer, an active layer, and a second conductivity-type semiconductor layer and a light extraction structure formed on the first conductivity-type semiconductor layer, and the light extraction structure includes a plurality of cylinders and a void is formed in each cylinder. | 2015-06-25 |
20150179883 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND A SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device and the device resulted thereof is disclosed. In one aspect, the device has a heterogeneous layer stack of one or more III-V type materials, at least one transmission layer of the layer stack having a roughened or textured surface for enhancement of light transmission. The method includes (a) growing the transmission layer of a III-V type material, (b) providing a mask layer on the transmission layer, the mask layer leaving first portions of the transmission layer exposed, and (c) partially decomposing the first exposed portions of the transmission layer. Suitably redeposition occurs in a single step with decomposition, so as to obtain a textured surface based on crystal facets of a plurality of grown crystals. The resulting device has a light-emitting element. The transmission layer hereof is suitably present at the top side. | 2015-06-25 |
20150179884 | LIGHT EMITTING DEVICE AND LIGHT EMITTING APPARATUS HAVING THE SAME - A light emitting device is provided a transmissive substrate; a first pattern portion including a protrusions; a second pattern portion including a concaves having a width smaller than a width of each protrusion; a light emitting structure including a first conductive semiconductor layer, a second conductive semiconductor layer and an active layer, under the transmissive substrate; a first electrode under the first conductive semiconductor layer; a reflective electrode layer under the second conductive semiconductor layer; a second electrode under the reflective electrode layer; a first connection electrode under the first electrode; a second connection electrode under the second electrode; and an insulating support member around the first electrode and the first connection electrode and around the second electrode and the second connection electrode. A transmissive resin layer is on the transmissive substrate and an insulating layer is between the insulating support member and the reflective electrode layer. | 2015-06-25 |
20150179885 | LIGHT EMITTING CHIP - A light emitting chip of the present invention includes a device chip having a sapphire substrate and a light emitting layer formed over the front surface of the sapphire substrate and a transparent member bonded to the back surface of the sapphire substrate by a resin transmissive to emitted light from the light emitting layer. The transparent member is transmissive to the emitted light from the light emitting layer. A groove is formed in an abutting surface of the transparent member against the device chip in such a manner as to be exposed to the side surface and the abutting surface of the transparent member. The groove width of the groove is smaller than the length of one side of the device chip. | 2015-06-25 |
20150179886 | DIODE HAVING VERTICAL STRUCTURE - A light emitting diode includes a conductive layer, an n-GaN layer on the conductive layer, an active layer on the n-CaN layer, a p-GaN layer on the active layer, and a p-electrode on the p-GaN layer. The conductive layer is an n-electrode. | 2015-06-25 |
20150179887 | Light Emitting Diode - A light emitting diode includes an epitaxial substrate, an active layer, a tunneling layer, a current spreading layer, and an electrode unit. The active layer includes a first conductive type film, a quantum well structure, and a second conductive type film that is made from Al | 2015-06-25 |
20150179888 | SEMICONDUCTOR LIGHT EMITTING STRUCTURE AND SEMICONDUCTOR PACKAGE STRUCTURE - A semiconductor light emitting structure includes an epitaxial structure, an N-type electrode pad, a P-type electrode pad and an insulation layer. The N-type electrode pad and the P-type electrode pad are disposed on the epitaxial structure apart, wherein the P-type electrode pad has a first upper surface. The insulation layer is disposed on the epitaxial structure and located between the N-type electrode pad and the P-type electrode pad, wherein the insulation layer has a second upper surface. The first upper surface of the P-type electrode pad and the second upper surface of the insulation layer are coplanar. | 2015-06-25 |
20150179889 | Light-Emitting Device with Reflecting Electrode - An electrode structure for effectively improving the stability of a semiconductor LED includes a reflecting layer capable of current spreading. In such an electrode structure, the current injects from the side surface of the reflecting layer to form a certain potential gradient over the contact surface between the electrode and the LED contact surface, thereby inhibiting the metal ion of the reflecting layer from migration due to electric field during usage, thereby improving device stability. In addition, the electrode portion for current injection can include a high-reflectivity material yet not vulnerable to ion migration, thereby increasing the entire reflecting area and improving luminous efficiency. | 2015-06-25 |
20150179890 | SEMICONDUCTOR LIGHT EMITTING ELEMENT - A semiconductor light emitting element includes a first conductive type semiconductor layer, a light emitting layer, and a second conductive type semiconductor layer disposed in this order. The semiconductor light emitting element includes first and second electrodes, a first insulating film and a translucent electrode. The first electrode is provided on the first conductive type semiconductor layer and includes a first pad portion and a first extending portion. The first insulating film covers the first extending portion. The translucent electrode is connected to an upper surface of the second conductive type semiconductor layer and extends over the first insulating film. The second electrode is connected to the translucent electrode at a position on the first insulating film. The second electrode includes a second pad portion and a second extending portion extending along the first extending portion so as to be superimposed over the first extending portion. | 2015-06-25 |
20150179891 | LIGHT EMITTING DEVICE - A method of manufacturing a light emitting device includes a first step of mounting a light emitting element on a substrate having a conductor wiring and electrically connecting the light emitting element with the conductor wiring, a second step of disposing a light reflecting resin which reflects light from the light emitting element to surround the light emitting element, and a third step of disposing a sealing member after hardening the light reflecting resin to cover the light emitting element. | 2015-06-25 |
20150179892 | Warm White LED and Fabrication Method Thereof - A warm-white-light LED structure combines a red light wafer and a blue light wafer via a bonding layer. A reflecting layer is arranged over upper and lower surfaces of the bonding layer respectively; the lower surface of the red light wafer takes up one-third or less of the upper surface of the blue light wafer, which effectively reduces packaging structure volume and time of bondings so as to optimize process flow and save fabrication cost. | 2015-06-25 |
20150179893 | Semiconductor Light-Emitting Device Preventing Metal Migration - A semiconductor light-emitting device is configured to prevent or reduce metal migration. The device includes: an n-type semiconductor layer, a light-emitting layer, and a p-type semiconductor layer; a reflecting layer disposed over the p-type semiconductor layer and containing a metal that tends to migrate; a well ring structure at the p-type semiconductor layer and substantially surrounding the reflecting layer to prevent the metal from migrating towards a side wall of the device; and a metal coating layer over the reflecting layer and extending towards the well ring structure to form an ohmic contact with the p-type semiconductor of the entire well ring structure. The device reliability is improved as the p-type semiconductor layer forms a well ring structure have “pining” effect surrounding the reflecting layer, thereby preventing the metal from migrating towards the device edge along the contact surface between the reflecting layer and the p-type semiconductor. | 2015-06-25 |
20150179894 | METHODS OF LOCATING DIFFERENTLY SHAPED OR DIFFERENTLY SIZED LED DIE IN A SUBMOUNT - Methods of locating a plurality of light emitting diode (LED) dies in a submount include providing the plurality of LED dies across a surface of the submount, the submount including a plurality of tubs corresponding in shape and/or size with the shape and/or size of the LED dies to fill each tub with correspondingly shaped and/or sized LED die. | 2015-06-25 |
20150179895 | LED SUBMOUNT WITH INTEGRATED INTERCONNECTS - A submount for light emitting diode (LED) die includes a substrate containing a plurality of tubs configured to receive an LED die, and a plurality of integrated interconnects integrated into the substrate. At least a portion of the interconnects for each tub have an exposed portion on a side of the submount and at least some of the plurality of the interconnects are not connected to other interconnects in the submount. | 2015-06-25 |
20150179896 | PACKAGE STRUCTURE OF LIGHT EMITTING DIODE - A package structure of light emitting diode includes a substrate and a light emitting diode die. The substrate has an upper surface and a lower surface opposite to each other. Two upper metal pads without mutual conduction are arranged on the upper surface. Two lower metal pads without mutual conduction are arranged on the lower surface. The light emitting diode die is disposed across the two upper metal pads. The light emitting diode die has a first electrode and a second electrode electrically connected to the two upper metal pads respectively. Wherein an orthographic projection area of one of the lower metal pads is greater than or equal to an orthographic projection area of the light emitting diode die, and the orthographic projection area of the light emitting diode die is totally located within the orthographic projection area of one of the lower metal pads. | 2015-06-25 |
20150179897 | LIGHT EMITTER COMPONENTS AND METHODS HAVING IMPROVED PERFORMANCE - Light emitter components and methods having improved performance and related methods are disclosed. In one embodiment, a light emitter component can include a submount and at least one light emitting diode (LED) chip disposed over the submount. The submount can contact at least two different sides of the at least one LED chip. In one aspect, a submount can include surface portions adapted to receive portions one or more LED chips. In one aspect, one or more LED chips can be embedded within the submount. | 2015-06-25 |
20150179898 | LED MODULE - A LED module includes a substrate, a LED chip supported on the substrate, a metal wiring installed on the substrate, the metal wiring including a mounting portion on which the LED chip is mounted, an encapsulating resin configured to cover the LED chip and the metal wiring, and a clad member configured to cover the metal wiring to expose the mounting portion, the encapsulating resin arranged to cover the clad member. | 2015-06-25 |