26th week of 2014 patent applcation highlights part 53 |
Patent application number | Title | Published |
20140179003 | ALTERNATIVE EXPORT PATHWAYS FOR VECTOR EXPRESSED RNA INTERFERENCE - The present invention is directed to nucleic acid molecules containing a loop sequence designed to circumvent exportin-5 mediated export, and methods using these novel molecules. | 2014-06-26 |
20140179004 | CELL FOR USE IN IMMUNOTHERAPY WHICH CONTAINS MODIFIED NUCLEIC ACID CONSTRUCT ENCODING WILMS TUMOR GENE PRODUCT OR FRAGMENT THEREOF, METHOD FOR PRODUCING SAID CELL, AND SAID NUCLEIC ACID CONSTRUCT - A cell of the present invention contains a nucleic acid construct encoding a WT1 gene product or a fragment of the WT1 gene product. The nucleic acid construct contains (i) a region encoding a desired fragment of the WT1 gene product and (ii) only AUG as a functional start codon. The present invention can provide a cell into which the nucleic acid construct is introduced so that an expression level of a WT1 gene product or a fragment of the WT1 gene product is remarkably enhanced. | 2014-06-26 |
20140179005 | Methods and Products for Producing Engineered Mammalian Cell Lines With Amplified Transgenes - Methods of inserting genes into defined locations in the chromosomal DNA of cultured mammalian cell lines which are subject to gene amplification are disclosed. In particular, sequences of interest (e.g., genes encoding biotherapeutic proteins) are inserted proximal to selectable genes in amplifiable loci, and the transformed cells are subjected to selection to induce co-amplification of the selectable gene and the sequence of interest. The invention also relates to meganucleases, vectors and engineered cell lines necessary for performing the methods, to cell lines resulting from the application of the methods, and use of the cell lines to produce protein products of interest. | 2014-06-26 |
20140179006 | CRISPR-CAS COMPONENT SYSTEMS, METHODS AND COMPOSITIONS FOR SEQUENCE MANIPULATION - The invention provides for systems, methods, and compositions for manipulation of sequences and/or activities of target sequences. Provided are vectors and vector systems, some of which encode one or more components of a CRISPR complex, as well as methods for the design and use of such vectors. Also provided are methods of directing CRISPR complex formation in eukaryotic cells and methods for selecting specific cells by introducing precise mutations utilizing the CRISPR/Cas system. | 2014-06-26 |
20140179007 | EXPRESSION OF GRANULAR STARCH HYDROLYZING ENZYME IN TRICHODERMA - The present invention relates to filamentous fungal host cells and particularly | 2014-06-26 |
20140179008 | BUFFER KIT AND METHOD OF GENERATING A LINEAR pH GRADIENT - A buffer kit includes a first eluent and second eluent. The first eluent solution includes at least four buffer salts where at least three of the four buffer salts are a monovalent buffer salt, have a net negative charge or a net neutral zwitterionic charge, and include a sulfonate group and an amine. The second eluent solution includes at least four buffer salts where at least three of the four buffer salts are a monovalent buffer salt, have a net negative charge or a net neutral zwitterionic charge, and include a sulfonate group and an amine. The first eluent solution has a first pH and the second eluent solution has a second pH where the first pH and second pH are different values. The buffer kit provides a linear pH gradient that forms an approximately straight line from at least the first pH to the second pH. | 2014-06-26 |
20140179009 | MINERAL WOOL PRODUCT - The invention relates to a mineral wool product comprising mineral fibers that is marked with an UV or IR active substance and can therefore be identified under exposure to suitable radiation. | 2014-06-26 |
20140179010 | METHODS OF DETECTING REVERSE TRIIODOTHYRONINE BY MASS SPECTROMETRY - Provided are methods for determining the amount of reverse T3 in a sample using mass spectrometry. The methods generally involve ionizing reverse T3 in a sample and detecting and quantifying the amount of the ion to determine the amount of reverse T3 in the sample. | 2014-06-26 |
20140179011 | RAPID FLUORESCENCE TAGGING OF GLYCANS AND OTHER BIOMOLECULES WITH ENHANCED MS SIGNALS - Reagents comprising MS active, fluorescent molecules with an activated functionality for reaction with amines useful in tagging biomolecules such as N-glycans and uses thereof are taught and described. | 2014-06-26 |
20140179012 | METHOD OF ANALYZING A BLOOD SAMPLE - A method of analyzing a blood sample is provided. The method comprises providing a system configured to perform an analysis of a glucose level of the blood sample disposed on a test medium, wherein the test medium is one of a quantity of test media in a user's supply, monitoring, by the system, the number of test media of the supply used in performing the analysis, determining, by the system, that a threshold value of test media has been reached, the threshold value being less than the quantity, and performing, by the system, once the threshold value has been reached, an ordering procedure. | 2014-06-26 |
20140179013 | METHODS AND SYSTEMS FOR ANALYZING A BLOOD SAMPLE - A method of analyzing a blood sample is provided. The method comprises providing a glucometer configured to analyze a blood sample and a remote computing device separate from the glucometer, analyzing, by the glucometer, the blood sample, and presenting, by the glucometer, encoded results. The encoded results may be presented as a machine-readable visually-encoded representation of one or more results of the analysis, in which case the method further comprises imaging, by the remote computing device, the representation. The encoded results may be presented as a capacitive profile, in which case the method further comprises reading, by a capacitive sensing input mechanism of the remote computing device, the capacitive profile. According to either option, the method further comprises decoding, by the remote computing device, the representation, thereby retrieving at least one of the results. | 2014-06-26 |
20140179014 | FLUORESCENT NITRIC OXIDE PROBES AND ASSOCIATED METHODS - Nitric oxide probes including a compound represented by Formula, I, II, III, IV, V, VI or a combination thereof are provided. Methods of using these nitric oxide probes to detect nitric oxide are also provided. | 2014-06-26 |
20140179015 | RESPONSIVE LUMINESCENT LATHANIDE COMPLEXES - The invention provides a compound of formula (I): | 2014-06-26 |
20140179016 | Reagent for Measuring Degree of Oxidative Stress and Method of Measuring Degree of Oxidative Stress - The present invention provides a reagent for measuring a degree of oxidative stress that includes a compound represented by the following general formula (I) or a salt thereof, and a method of measuring a degree of oxidative stress using the reagent for measuring a degree of oxidative stress. In the general formula (I), R | 2014-06-26 |
20140179017 | TETRACATIONIC CYCLOPHANES AND THEIR USE IN THE SEQUESTRATION OF POLYAROMATIC HYDROCARBONS BY WAY OF COMPLEXATION - Novel tetracationic cyclophanes incorporating π-electron poor organic compounds into their ring structures, as well as methods of making the cyclophanes, are provided. The cyclophanes are able to form electron donor-acceptor complexes with a variety of polyaromatic hydrocarbons (PAHs) ranging in size, shape, and electron density. Also provided are methods of using the cyclophanes in the sequestration of PAHs in liquid or gaseous samples, the separation of PAHs from liquid or gaseous samples, the detection of PAHs in liquid samples, and the exfoliation of graphene via pseudopolyrotaxane formation. | 2014-06-26 |
20140179018 | METHOD FOR ANALYZING HALOGEN OXOACIDS - To quantitatively analyze halogen oxoacids such as bromic acid and perchloric acid, an HPLC/MS in which a mass spectrometer is connected to the outlet of a column of a high performance liquid chromatograph (HPLC) is used, and by using a reverse-phase column having an ion exchange function as the column, as well as a mixed liquid of an ammonium formate buffer solution and acetonitrile as the mobile phase, gradient analysis in which the concentration of ammonium formate in ammonium formate/acetonitrile is increased is performed. Thereby, a common HPLC/MS apparatus configuration using no suppressor makes it possible to appropriately separate various halogen oxoacids and other components contained in a sample and to detect them at high sensitivity. | 2014-06-26 |
20140179019 | Simultaneous Global Thermometry, Barometry, and Velocimetry Systems and Methods - Microbeads include small preformed microbead substrates, which may comprise, for example, silica particles having a characteristic dimension less than 2 millimeters. A plurality of luminophores are applied to an exposed surface of the microbead substrates, wherein the luminophores are selected for detecting pressure and/or temperature. A plurality of luminophores absorb light at a predetermined wavelength to transition to an excited state, and they luminesce at different wavelengths when returning to the ground state. The luminescence may be phosphorescence or fluorescence. In some embodiments the microbeads include at least one pressure-sensitive luminophore, at least one temperature-sensitive luminophore, and at least one reference luminophore that is neither pressure-sensitive nor temperature-sensitive. In some embodiments the microbeads are configured for use in digital particle image velocimetry. | 2014-06-26 |
20140179020 | Methods and Apparatus for Identifying Ion Species Formed during Gas-Phase Reactions - A method for matching each of a plurality of progenitor ion types to respective product or fragment ion types, comprising: generating the plurality of progenitor ion types over a time range by ionizing compounds eluting during the time range using an atmospheric pressure ion source; generating the product or fragment ion types within a pressure range of 750 mTorr to atmospheric pressure in an ionization chamber or first vacuum chamber; detecting abundances of the plurality of progenitor ion types and the product or fragment ion types using a mass analyzer; calculating a plurality of extracted ion chromatograms (XICs) relating to the detected abundances; automatically detecting and characterizing chromatogram peaks within each XIC; automatically generating synthetic analytical fit peaks; performing cross-correlation score calculations between each pair of synthetic analytical fit peaks; and recognizing matches based on the cross correlation scores. | 2014-06-26 |
20140179021 | HIGH THROUGHPUT MICROFLUIDIC DEVICE - A microfluidic element comprising at least one pair of plates, at least one of said plates having an open channel distributed on a surface that is adjacent the other plate in the pair. In use, said plates are releasably clamped together so as to form an enclosed, continuous microfluidic channel between the plates that is suitable for the passage of a fluid. | 2014-06-26 |
20140179022 | ROTATING SHIELDED MAGNETIC ACTUATOR - Magnetic actuators comprising at least one shielded rotatable magnet are presented. Systems comprising such magnetic actuators and methods for using such magnetic actuators to isolate magnetic particles in a fluid are also presented. | 2014-06-26 |
20140179023 | METHOD FOR DETECTING A TARGET PARTICLE IN BIOSAMPLE CONTAINING PANCREATIC JUICE - Provided is a method for detecting a target particle in a biosample containing pancreatic juice, the method enabling the detection in a solution that has a lower concentration or number density of the target particles than the level possible for conventional photoanalysis techniques. This method comprises: a probe-binding step for preparing a sample solution, which contains a biosample containing pancreatic juice and a fluorescent probe capable of binding to a target particle, and binding the fluorescent probe to the target particle in the biosample; and a calculation step for calculating the number of molecules of the target particles bound to the fluorescent probes by the scanning molecule counting method. A light emission property of emitted light is different between a state where the fluorescent probe is bound to the target particle and a state where the fluorescent probe is present alone. In a state where the fluorescent probe is bound to the target particle, the fluorescent probe emits fluorescence having a wavelength of 600 nm or longer. | 2014-06-26 |
20140179024 | DEVICE AND METHODS FOR DETECTING ANALYTES IN SALIVA - The invention provides a device for detecting drugs of abuse or other compounds in saliva. The invention thus provides a device for detecting the presence of one or more analytes in a saliva sample, comprising: (a) One or more pre-treatment regions for specifically or non-specifically removing at least a part of the fraction of the saliva sample interfering with detection of the one or more analytes; and (b) A detection region comprising a biosensor surface, the surface comprising: molecules capable of specifically binding the one or more analytes; or the one or more analytes and/or analyte analogues. | 2014-06-26 |
20140179025 | PARTICLES - A coated magnetic particle comprising an optionally porous magnetic polymer particle of a matrix polymer, said polymer particle having on a surface and/or in the pores thereof superparamagnetic crystals, said coated particle having a coat formed of a coating polymer, wherein said coated magnetic particle is essentially non-autofluorescent. | 2014-06-26 |
20140179026 | METHOD FOR GENERATING QUANTIZED ANOMALOUS HALL EFFECT - A method for generating quantum anomalous Hall effect is provided. A topological insulator quantum well film in 3QL to 5QL is formed on an insulating substrate. The topological insulator quantum well film is doped with a first element and a second element to form the magnetically doped topological insulator quantum well film. The doping of the first element and the second element respectively introduce hole type charge carriers and electron type charge carriers in the magnetically doped topological insulator quantum well film, to decrease the carrier density of the magnetically doped topological insulator quantum well film to be smaller than or equal to 1×10 | 2014-06-26 |
20140179027 | ADJUSTING INTENSITY OF LASER BEAM DURING LASER OPERATION ON A SEMICONDUCTOR DEVICE - Among other things, a system and method for adjusting the intensity of a laser beam applied to a semiconductor device are provided for herein. A sensor is configured to measure the intensity of a laser beam reflected from the semiconductor device. Based upon the reflection intensity, an intensity of the laser beam that is applied to the semiconductor device is adjusted, such as to alter an annealing operation performed on the semiconductor device, for example. | 2014-06-26 |
20140179028 | PLASMA DOPING APPARATUS AND PLASMA DOPING METHOD - Disclosed is a plasma doping apparatus provided with a plasma generating mechanism. The plasma generating mechanism includes a microwave generator that generates microwave for plasma excitation, a dielectric window that transmits the microwave generated by the microwave generator into a processing container, and a radial line slot antenna formed with a plurality of slots. The radial line slot antenna radiates the microwave to the dielectric window. A control unit controls the plasma doping apparatus such that a doping gas and a gas for plasma excitation are supplied into the processing container by a gas supply unit in a state where the substrate is placed on a holding unit, and then plasma is generated by the plasma generating mechanism to perform doping on the substrate such that the concentration of the dopant implanted into the substrate is less than 1×10 | 2014-06-26 |
20140179029 | METHOD OF PROCESSING A SEMICONDUCTOR STRUCTURE - A method according to embodiments of the invention includes providing a wafer including a semiconductor structure grown on a growth substrate, the semiconductor structure comprising a III-nitride light emitting layer sandwiched between an n-type region and a p-type region. The wafer is bonded to a second substrate. The growth substrate is removed. After bonding the wafer to the second substrate, the wafer is processed into multiple light emitting devices. | 2014-06-26 |
20140179030 | Dissolution Rate Monitor - A multiple channel site-isolated reactor system and method are described. The system contains a reactor block with a plurality of reactors. Input lines are coupled to each reactor to provide a fluid to the respective reactors. A sealing element associated with each reactor contacts a surface of a substrate disposed below the reactor block, which defines isolated regions on the surface of the substrate. A dissolution rate monitor extends into each reactor to monitor a rate of real-time dissolution of one or more layers on the surface of the substrate when it is disposed proximate to the surface of the substrate. | 2014-06-26 |
20140179031 | DESIGNED ASPERITY CONTACTORS, INCLUDING NANOSPIKES, FOR SEMICONDUCTOR TEST USING A PACKAGE, AND ASSOCIATED SYSTEMS AND METHODS - Nanospike contactors suitable for semiconductor device test, and associated systems and methods are disclosed. A representative apparatus includes a package having a wafer side positioned to face toward a device under test and an inquiry side facing away from the wafer side. A plurality of wafer side sites are carried at the wafer side of the package. The nanospikes can be attached to nanospike sites on a wafer side of the package. Because of their small size, multiple nanospikes make contact with a single pad/solderball on the semiconductor device. In some embodiments, after detecting that the device under test passes the test, the device under the test can be packaged to create a known good die in a package. | 2014-06-26 |
20140179032 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - Provided is a method of manufacturing a semiconductor device including a step of testing every one of through-electrodes. A second probe test is conducted to check an electrical coupling state between a plurality of copper post bumps formed on the side of the surface of a wafer and electrically coupled to a metal layer and a plurality of bumps formed on the side of the back surface of the wafer and electrically coupled to the metal layer (also another metal layer) via a plurality of through-electrodes by probing to each of the bumps on the side of the back surface while short-circuiting between the copper post bumps (electrodes). By this test, conduction between the bumps (electrodes) on the back surface side is checked. | 2014-06-26 |
20140179033 | Methods for Forming Templated Materials - Methods of forming layers can comprise defining a plurality of discrete site-isolated regions (SIRs) on a substrate, forming a first layer on one of the discrete SIRs, forming a second layer on the first layer, measuring a lattice parameter or an electrical property of the second layer, The process parameters for the formation of the first layer are varied in a combinatorial manner between different discrete SIRs to explore the possible layers that can result in suitable lattice matching for second layer of a desired crystalline structure. | 2014-06-26 |
20140179034 | SEMICONDUCTOR PHOTONIC PACKAGE - A method for assembling a semiconductor photonic package device includes bonding a portion of a first surface of a semiconductor die portion to a portion of a carrier portion, bonding a single mode optical ferrule portion to a portion of the first surface of the semiconductor die portion, and disposing a cover plate assembly in contact with the optical ferrule portion and the carrier portion. | 2014-06-26 |
20140179035 | METHOD FOR DISPENSING GLUE ON LED CHIP - A method for dispensing glue on an LED chip includes following steps: providing a glue dispensing device which includes a syringe, a needle head communicating with the syringe, and a valve mounted on the needle head for controlling flowing of content in the syringe out of the syringe, wherein the valve has an aperture, and a diameter of the aperture is adjustable; providing glue and injecting the glue into the syringe; providing an LED chip which is mounted a circuit board and orientating the needle head of the glue dispensing device towards the LED chip, wherein the needle head is spaced from the LED chip, and the diameter of the aperture of the valve is adjusted to a predetermined size; squeezing the glue out of the syringe under a predetermined pressure and a predetermined time, wherein the glue dispensed on the LED chip forms an encapsulation structure. | 2014-06-26 |
20140179036 | METHOD AND SYSTEM FOR HETEROGENEOUS SUBSTRATE BONDING FOR PHOTONIC INTEGRATION - A method of fabricating a composite integrated optical device includes providing a substrate comprising a silicon layer, forming a waveguide in the silicon layer, and forming a layer comprising a metal material coupled to the silicon layer. The method also includes providing an optical detector, forming a metal-assisted bond between the metal material and a first portion of the optical detector, forming a direct semiconductor-semiconductor bond between the waveguide, and a second portion of the optical detector. | 2014-06-26 |
20140179037 | METHOD FOR MANUFCTURING BACKLIGHT MODULE - A method for manufacturing a backlight module comprises following steps: providing a substrate; providing a flip chip LED and mounting the flip chip LED on a top surface of the substrate to electrically connect with two electrodes via flip chip bonding; providing a frame and mounting the frame on the top surface of the substrate, wherein the frame defines a through hole which receives the flip chip LED therein; and providing a phosphor layer and mounting the phosphor layer on a top end of the frame away from the substrate to make the phosphor layer cover a top end of the through hole and the flip chip LED. | 2014-06-26 |
20140179038 | METHOD FOR MANUFCTURING LIGHT EMITTING DIODE PACKAGE - A method for manufacturing an LED package comprising following steps: providing a substrate and an LED chip mounted on the substrate; providing glue and arranging the glue on a periphery of the substrate and drying the glue to form a blocking loop to enclose the LED chip therein; and injecting the glue in the blocking loop, and drying the glue to form a packaging layer to encapsulate the LED chip therein. Light emitted from the LED chip travels through a top surface of the packaging layer, a periphery of the packaging layer, and the blocking loop to illuminate. | 2014-06-26 |
20140179039 | METHOD FOR MANUFACTURING LIGHT EMITTING DIODE MODULE - A method for manufacturing an LED module includes following steps: providing a SMT (Surface Mount Technology) apparatus having a CCD (Charge-Coupled Device) image sensor and a nozzle, and providing a PCB and fixing the PCB in the SMT apparatus; providing a plurality of LEDs and mounting the LEDs on the PCB by the SMT apparatus; providing a plurality of lenses each having a plurality of patterned portions formed on an outer face of the lens, and the CCD image sensor imaging the lens and identifying the patterned portions, and then the SMT apparatus obtaining a location of the lens relative to the LED; positioning the lens on the PCB to cover the LED by the SMT apparatus; and fixing the lens on the PCB. | 2014-06-26 |
20140179040 | MULTILAYER FILM FOR ENCAPSULATING OXYGEN AND/OR MOISTURE SENSITIVE ELECTRONIC DEVICES - The present invention relates to a multilayer barrier film capable of encapsulating a moisture and/or oxygen sensitive electronic or optoelectronic device, the barrier film including at least one nanostructured layer including reactive nanoparticles capable of interacting with moisture and/or oxygen, the reactive nanoparticles being distributed within a polymeric binder, and at least one ultraviolet light neutralizing layer comprising a material capable of absorbing ultraviolet light, thereby limiting the transmission of ultraviolet light through the barrier film. | 2014-06-26 |
20140179041 | APPARATUS AND METHOD FOR MANUFACTURING THIN FILM ENCAPSULATION - An apparatus and method for manufacturing a thin film encapsulation includes: a first cluster configured to form a first inorganic layer on a display substrate using a sputtering process; a second cluster configured to form a first organic layer on the first inorganic layer on the display substrate using a monomer deposition process; and a third cluster configured to form a second inorganic layer on the first organic layer on the display substrate using a chemical vapor deposition (CVD) process or a plasma enhanced chemical vapor deposition (PECVD) process. | 2014-06-26 |
20140179042 | LIGHT-EMITTING DIODE MANUFACTURING METHOD - A light-emitting diode manufacturing method comprises steps of: providing a flexible material layer having a flexible reflective layer and phosphor glue in the flexible reflective layer; providing a hard material layer having a substrate and an LED chip on the substrate; combining the flexible material layer and the hard material layer together wherein the LED chip inserts into the phosphor glue and is surrounded by the flexible reflective layer; and solidifying the flexible reflective layer and the phosphor glue to form a reflective cup and a phosphor layer, respectively. | 2014-06-26 |
20140179043 | METHOD OF SEPARATING SUBSTRATE AND METHOD OF FABRICATING SEMICONDUCTOR DEVICE USING THE SAME - A method of fabricating a semiconductor device, the method including: forming a first mask pattern including a masking region and an open region on a substrate; forming a sacrificial layer to cover the substrate and the first mask pattern; patterning the sacrificial layer to form a seed layer and to expose the first mask pattern; forming a second mask pattern on the exposed first mask pattern; forming an epitaxial layer on the seed layer and the second mask pattern, and forming a void between the second mask pattern and the epitaxial layer; and separating the substrate from the epitaxial layer. | 2014-06-26 |
20140179044 | METHOD OF MANUFACTURING ORGANIC LIGHT EMITTING DIODE DISPLAY - An OLED display includes a first polysilicon layer pattern on a substrate having a first gate electrode, a second gate electrode, and a first capacitor electrode, a gate insulating layer pattern, a second polysilicon layer pattern including a first active layer, a second active layer, and a capacitor polycrystalline dummy layer, a third amorphous silicon layer pattern including first source and drain resistant contact layers on a predetermined region of the first active layer, second source and drain resistant contact layers on a predetermined region of the second active layer, and a capacitor amorphous dummy layer on the capacitor polycrystalline dummy layer, and a data metal layer pattern including first source/drain electrodes, second source/drain electrodes, and a second capacitor electrode. | 2014-06-26 |
20140179045 | TRANSPARENT CONDUCTIVE ELECTRODE STACK CONTAINING CARBON-CONTAINING MATERIAL - A transparent conductive electrode stack containing a work function adjusted carbon-containing material is provided. Specifically, the transparent conductive electrode stack includes a layer of a carbon-containing material and a layer of a work function modifying material. The presence of the work function modifying material in the transparent conductive electrode stack shifts the work function of the layer of carbon-containing material to a higher value for better hole injection into the OLED device as compared to a transparent conductive electrode that includes only a layer of carbon-containing material and no work function modifying material. | 2014-06-26 |
20140179046 | SEMICONDUCTOR NANOCRYSTAL PROBES FOR BIOLOGICAL APPLICATIONS AND PROCESS FOR MAKING AND USING SUCH PROBES - A semiconductor nanocrystal compound and probe are described. The compound is capable of linking to one or more affinity molecules. The compound comprises (1) one or more semiconductor nanocrystals capable of, in response to exposure to a first energy, providing a second energy, and (2) one or more linking agents, having a first portion linked to the one or more semiconductor nanocrystals and a second portion capable of linking to one or more affinity molecules. One or more semiconductor nanocrystal compounds are linked to one or more affinity molecules to form a semiconductor nanocrystal probe capable of bonding with one or more detectable substances in a material being analyzed, and capable of, in response to exposure to a first energy, providing a second energy. Also described are processes for respectively: making the semiconductor nanocrystal compound; making the semiconductor nanocrystal probe; and treating materials with the probe. | 2014-06-26 |
20140179047 | Field Effect Transistor-Based Bio-Sensor - An apparatus comprises: a sensing element formed on a buried oxide layer of a substrate and providing communication between a source region and a drain region; a gate dielectric layer on the sensing element, the gate dielectric layer defining a sensing surface on the sensing element; a passive surface surrounding the sensing surface; and a compound bound to the sensing surface and not bound to the passive surface, the compound having a ligand specifically configured to preferentially bind a target molecule to be sensed. An electrolyte solution in contact with the sensing surface and the passive surface forms a top gate of the apparatus. | 2014-06-26 |
20140179048 | METHOD FOR PREPARING ABSORBING LAYER OF SOLAR CELL AND THERMAL TREATMENT DEVICE THEREOF - A method for preparing an absorbing layer of a solar cell includes the following steps. An absorbing layer precursor containing at least one group XIV element is loaded on a substrate. A solid vapor source containing a group XIV element, the same as the group XIV element in the absorbing layer precursor is provided. The solid vapor source corresponds to the absorbing layer precursor. The solid vapor source and the absorbing layer precursor are kept apart by a distance. A heating process is performed so that the absorbing layer precursor forms an absorbing layer, the solid vapor source is vaporized and generates a gas containing the group XIV element, and the gas containing the group XIV element inhibits the effusion of the group XIV element of the absorbing layer precursor so that the proportion of the group XIV element in the formed absorbing layer is consistent. | 2014-06-26 |
20140179049 | SILICON/GERMANIUM-BASED NANOPARTICLE PASTES WITH ULTRA LOW METAL CONTAMINATION - Silicon based nanoparticle inks are described with very low metal contamination levels. In particular, metal contamination levels can be established in the parts-per-billion range. The inks of particular interest generally comprise a polymer to influence the ink rheology. Techniques are described that are suitable for purifying polymers soluble in polar solvents, such as alcohols, with respect metal contamination. Very low levels of metal contamination for cellulose polymers are described. | 2014-06-26 |
20140179050 | MODULE ASSEMBLY FOR THIN SOLAR CELLS - Solar cells are packaged by placing the solar cells between sheets of encapsulants. The encapsulants are exposed to ultraviolet (UV) light to cure the encapsulants and bond the encapsulants together to encapsulate the solar cells. The UV curing steps may be performed to bond one of the encapsulants to a transparent top cover and the solar cells, and to bond the other encapsulant to the solar cells and a backsheet. A protective package that includes the transparent top cover, encapsulated solar cells, and the backsheet is then optionally mounted on a frame. | 2014-06-26 |
20140179051 | METHOD OF MANUFACTURING AN ORGANIC LIGHT-EMITTING DISPLAY DEVICE - A method of forming an organic light-emitting display in which a pixel electrode is formed by extending from source and drain electrodes, a capacitor including a thin upper capacitor electrode formed below the pixel electrode and constituting a metal-insulator-metal (MIM) CAP structure, thereby simplifying manufacturing processes, increasing an aperture ratio, and improving a voltage design margin. | 2014-06-26 |
20140179052 | METHOD OF FORMING A THIN FILM AND AN ELECTRONIC DEVICE - A method of forming a thin film includes coating one side of a transferring stamp including a hydrophilic polymer layer with a hydrophilic solution to form a transfer layer, and transferring the transfer layer to the substrate. | 2014-06-26 |
20140179053 | METHOD FOR FABRICATING ABSORBING LAYER OF SOLAR CELL AND THERMAL TREATMENT DEVICE THEREOF - A method for fabricating an absorbing layer of a solar cell and a thermal treatment device thereof adapted for forming an absorbing layer on a substrate are disclosed. The method includes the following steps. First, a solid-phase vapor source in a chamber and an absorbing layer precursor on a substrate are maintained by a predetermined distance. The solid-phase vapor source contains tin. The absorbing layer precursor contains copper, zinc, tin and sulfur. The temperature inside the chamber is raised to a forming temperature, so that the absorbing layer precursor forms an absorbing layer on the substrate. | 2014-06-26 |
20140179054 | METHOD FOR FORMING PATTERNS OF DIFFERENTLY DOPED REGIONS - The disclosed technology generally relates to forming patterns of doped semiconductor regions, and more particularly to methods of forming such patterns in fabricating photovoltaic devices. In one aspect, a method of forming a pattern of different doped regions at the same side of a semiconductor substrate comprises providing a patterned doped layer on a surface of the semiconductor substrate at predetermined locations where at least one first doped region is to be formed. The method additionally includes selectively growing at least one second doped region epitaxially at the same side of the semiconductor substrate using the patterned doped layer as an epitaxial growth mask. Furthermore, selectively growing comprises driving dopants from the patterned doped layer into the semiconductor substrate to form the first doped region at the predetermined locations. | 2014-06-26 |
20140179055 | METHOD FOR PRODUCING PHOTOELECTRIC CONVERSION ELEMENT AND METHOD FOR PRODUCING IMAGING DEVICE - The method produces a photoelectric conversion element comprising a lower electrode, an electron blocking layer, a photoelectric conversion layer, an upper electrode, and a sealing layer which are laminated on one another in this order. The method includes a step of forming a transparent conductive oxide into a film at a deposition rate of 0.5 Å/s or higher by a sputtering method to form the upper electrode having a stress of −50 MPa to −500 MPa on the photoelectric conversion layer. | 2014-06-26 |
20140179056 | LASER-ABSORBING SEED LAYER FOR SOLAR CELL CONDUCTIVE CONTACT - Laser-absorbing seed layers for solar cell conductive contacts and methods of forming solar cell conductive contacts are described. For example, a method of fabricating a solar cell includes forming a metal seed paste above a substrate. The metal seed paste includes a laser-absorbing species. The metal seed paste is irradiated with a laser to form a metal seed layer. The irradiating includes exciting the laser-absorbing species. A conductive contact for the solar cell is then formed from the metal seed layer. | 2014-06-26 |
20140179057 | METHOD FOR MANUFACTURING OXIDE SEMICONDUCTOR LAYER AND THIN FILM TRANSISTOR HAVING OXIDE SEMICONDUCTOR LAYER - A method for manufacturing an oxide semiconductor layer includes following steps: providing a substrate; forming an oxide semiconductor layer on the substrate by sputtering a first kind of metallic ions from a first metallic oxide sputtering target, and sputtering at least two second kinds of metallic ions from a second metallic oxide sputtering target. The at least two second kind of metallic ions are different from the first kind of metallic ions. A proportion of the first kind of metallic ions and the at least two second kind of metallic ions is adjustable by controlling a depositing speed of the oxide semiconductor layer and a period of using a baffle plate in sputtering. A method for manufacturing a thin film transistor is also provided. | 2014-06-26 |
20140179058 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - An object is to manufacture a semiconductor device including an oxide semiconductor at low cost with high productivity in such a manner that a photolithography process is simplified by reducing the number of light-exposure masks In a method for manufacturing a semiconductor device including a channel-etched inverted-staggered thin film transistor, an oxide semiconductor film and a conductive film are etched using a mask layer formed with the use of a multi-tone mask which is a light-exposure mask through which light is transmitted so as to have a plurality of intensities. In etching steps, a first etching step is performed by wet etching in which an etchant is used, and a second etching step is performed by dry etching in which an etching gas is used. | 2014-06-26 |
20140179059 | PACKAGE-LEVEL INTEGRATED CIRCUIT CONNECTION WITHOUT TOP METAL PADS OR BONDING WIRE - An integrated circuit method is provided with package-level connectivity, between internal electronic circuitry thereof and contact points on a package substrate thereof, without requiring top metal pads or bonding wires. | 2014-06-26 |
20140179060 | IN SITU-BUILT PIN-GRID ARRAYS FOR CORELESS SUBSTRATES, AND METHODS OF MAKING SAME - A coreless pin-grid array (PGA) substrate includes PGA pins that are integral to the PGA substrate without the use of solder. A process of making the coreless PGA substrate integrates the PGA pins by forming a build-up layer upon the PGA pins such that vias make direct contact to pin heads of the PGA pins. | 2014-06-26 |
20140179061 | THIN WAFER HANDLING - A first area of a first surface of an encapsulated component can be thinned, the component including: a semiconductor chip having an active surface opposite the first surface, and an encapsulant extending outwardly from edges of the semiconductor chip. An entire area of the active surface may be aligned with the first area. After the abrading, a second area of the encapsulated component beyond the first area may have a thickness greater than a thickness of the first area. The second area can be configured to fully support the abraded encapsulated component in a state of the encapsulated component being manipulated by handling equipment. | 2014-06-26 |
20140179062 | Isolation Rings for Packages and the Method of Forming the Same - A device includes a first package component, and a second package component underlying, and bonded to, the first package component. A molding material is disposed under the first package component and molded to the first and the second package components, wherein the molding material and the first package component form an interface. An isolation region includes a first edge, wherein the first edge of the isolation region contacts a first edge of the first package component and a first edge of the molding material. The isolation has a bottom lower than the interface. | 2014-06-26 |
20140179063 | RESIN SEALING TYPE SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME, AND LEAD FRAME - The invention is directed to firm bonding between semiconductor dies etc bonded to a lead frame and wire-bonding portions of the lead frame by ultrasonic Al wire bonding, and the prevention of shortcircuit between the semiconductor dies etc due to a remaining portion of the outer frame of the lead frame after the outer frame is cut. By extending the wire-bonding portion etc on the lead frame in a wire-bonding direction and connecting the wire-bonding portion etc to the outer frame of the lead frame through a connection lead etc, the ultrasonic vibration force in the ultrasonic Al wire bonding is prevented from dispersing and the Al wire and the wire-bonding portion etc are firmly bonded. The outer frame is cut after a resin sealing process is completed. Even when a portion of the outer frame remains on the side surface of the resin package, connection between the connection lead etc and other hanging lead etc are prevented by providing a notch etc in the outer frame between the connection lead etc and the hanging lead etc. | 2014-06-26 |
20140179064 | METHOD FOR FABRICATING A PACKAGE-IN-PACKAGE FOR HIGH HEAT DISSIPATION - A method for fabricating a semiconductor system starts with providing a first component including a first semiconductor chip attached to a pad of a first metal leadframe made of a first metal sheet of high thermal conductivity. A second component including a second semiconductor chip attached to a pad of a second metal leadframe made of a second metal sheet wire-bondable on both surfaces is provided. The second component is encapsulated in a polymeric housing leaving un-encapsulated the lead surfaces facing away from the second chip. The polymeric housing of the second component is attached to the first chip using a layer of low thermal conductivity, whereby the un-encapsulated lead surfaces face away from the first chip. Bonding wires are connected to the un-encapsulated surfaces of the second component leads to the leads of the first component. | 2014-06-26 |
20140179065 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device includes attaching a curable film to a first connection member including a first circuit terminal, attaching a conductive film to a second connection member including a second circuit terminal, and thermally compressing the first connection member to the second connection member, with the first connection member and the second connection member placed such that the curable film and the conductive film face each other. | 2014-06-26 |
20140179066 | PACKAGING STRUCTURE - A method of assembling a packaging structure is provided and includes directly electrically interconnecting respective active surfaces of first and second chips in a face-to-face arrangement, electrically interconnecting at least one of the respective sidewalls of the first and second chips to a common chip and orienting the respective active surfaces of the first and second chips transversely with respect to the common chip. | 2014-06-26 |
20140179067 | FABRICATION METHOD OF SEMICONDUCTOR PACKAGE - A semiconductor package and a fabrication method thereof are disclosed. The fabrication method includes the steps of providing a semiconductor chip having an active surface and a non-active surface opposing to the active surface, roughening a peripheral portion of the non-active surface so as to divide the non-active surface into the peripheral portion formed with a roughened structure and a non-roughened central portion, mounting the semiconductor chip on a chip carrier via a plurality of solder bumps formed on the active surface, forming an encapsulant on the chip carrier to encapsulate the semiconductor chip. The roughened structure formed on the peripheral portion of the non-active surface of the semiconductor chip can reinforce the bonding between the semiconductor chip and the encapsulant, and the non-roughened central portion of the non-active surface of the semiconductor chip can maintain the structural strength of the semiconductor chip. | 2014-06-26 |
20140179068 | NON-VOLATILE MEMORY HAVING 3D ARRAY OF READ/WRITE ELEMENTS WITH LOW CURRENT STRUCTURES AND METHODS THEREOF - A three-dimensional array read/write (R/W) memory elements is formed across multiple layers of planes positioned at different distances above a semiconductor substrate. It is preferable to operate the R/W elements with low current and high resistive states. The resistance of these resistive states depends also on the dimension of the R/W elements and is predetermined by the process technology. A sheet electrode in series with the R/W element and a method of forming it provide another degree of freedom to adjust the resistance of the R/W memory element. The thickness of the sheet electrode is adjusted to obtain a reduced cross-sectional contact in the circuit path from the word line to the bit line. This allows the R/W memory element to have a much increased resistance and therefore to operate with much reduced currents. The sheet electrode is formed with little increase in cell size. | 2014-06-26 |
20140179069 | FABRICATION METHOD OF SEMICONDUCTOR APPARATUS - A method of fabricating a semiconductor apparatus includes forming an insulating layer on a semiconductor substrate, forming a source post in the insulating layer, and forming a semiconductor layer over the source post and the insulating layer. | 2014-06-26 |
20140179070 | Anti-Fuses on Semiconductor Fins - A device includes a substrate, isolation regions at a surface of the substrate, and a semiconductor region over a top surface of the isolation regions. A conductive feature is disposed over the top surface of the isolation regions, wherein the conductive feature is adjacent to the semiconductor region. A dielectric material is disposed between the conductive feature and the semiconductor region. The dielectric material, the conductive feature, and the semiconductor region form an anti-fuse. | 2014-06-26 |
20140179071 | TWO-STEP SHALLOW TRENCH ISOLATION (STI) PROCESS - Methods of making an integrated circuit are disclosed. An embodiment method includes etching a trench in a silicon substrate, depositing a first layer of isolation material in the trench, the first layer of isolation material projecting above surface of the silicon substrate, capping the first layer of isolation material by depositing a second layer of isolation material, the second layer of isolation material extending along at least a portion of sidewalls of the first layer of isolation material, epitaxially-growing a silicon layer upon the silicon substrate, the silicon layer horizontally adjacent to the second layer of isolation material, and forming a gate structure on the silicon layer, the gate structure defining a channel. | 2014-06-26 |
20140179072 | SEMICONDUCTOR DEVICE HAVING EPITAXIAL SEMICONDUCTOR LAYER ABOVE IMPURITY LAYER - The semiconductor device includes a first transistor including a first impurity layer of a first conductivity type formed in a first region of a semiconductor substrate, a first epitaxial semiconductor layer formed above the first impurity layer, a first gate insulating film formed above the first epitaxial semiconductor layer, and a first gate electrode formed above the first gate insulating film, and a second transistor including a second impurity layer of the second conductivity type formed in a second region of the semiconductor substrate, a second epitaxial semiconductor layer formed above the second impurity layer and having a thickness different from that of the first epitaxial semiconductor layer, a second gate insulating film formed above the second epitaxial semiconductor layer and having a film thickness equal to that of the first gate insulating film and a second gate electrode formed above the second gate insulating film. | 2014-06-26 |
20140179073 | SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME - A method of manufacturing a semiconductor device may include: forming active patterns of pillar-shapes upward protruding from a substrate, the active patterns fully doped with dopants of one conductivity type; forming a gate electrode extending in one direction, the gate electrode overlapped with sidewalls of the active patterns; and forming a gate insulating layer between the gate electrode and the active patterns. | 2014-06-26 |
20140179074 | METHOD OF MAKING MOSFET INTEGRATED WITH SCHOTTKY DIODE WITH SIMPLIFIED ONE-TIME TOP-CONTACT TRENCH ETCHING - Method for fabricating MOSFET integrated with Schottky diode (MOSFET/SKY) is disclosed. Gate trench is formed in an epitaxial layer overlaying semiconductor substrate, gate material is deposited therein. Body, source, dielectric regions are successively formed upon epitaxial layer and the gate trench. Top contact trench (TCT) is etched with vertical side walls defining Schottky diode cross-sectional width SDCW through dielectric and source region defining source-contact depth (SCD); and partially into body region by total body-contact depth (TBCD). A heavily-doped embedded body implant region (EBIR) of body-contact depth (BCD)2014-06-26 | |
20140179075 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - According to one embodiment, a method for manufacturing a semiconductor device includes: forming a plurality of trenches; forming a gate insulating film; burying a gate electrode; burying an insulating member; projecting the insulating member; forming a base layer; forming a mask film; forming a first semiconductor layer; forming a carrier ejection layer; forming a first electrode; and forming a second electrode. The projecting includes projecting the insulating member from the upper surface of the semiconductor substrate by removing an upper layer portion of the semiconductor substrate. The mask film is formed so as to cover the projected insulating member. The forming the first semiconductor layer includes forming a first semiconductor layer of the first conductivity type in an upper layer portion of the base layer by doping the base layer with impurity, the upper layer portion having a lower surface below an upper end of the gate electrode. | 2014-06-26 |
20140179076 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - Even when a semiconductor device having field effect transistors driven by relatively different power supply voltages provided over a semiconductor substrate is manufactured by the gate-last process, the breakdown voltage of the transistor on the higher voltage side can be ensured. | 2014-06-26 |
20140179077 | METHOD OF FORMING SEMICONDUCTOR DEVICE INCLUDING SILICIDE LAYERS - A method includes forming a gate structure on a semiconductor material region, wherein the gate structure includes spacer elements abutting a gate electrode layer. The gate electrode layer is etched to provide a recess. A hard mask layer is formed over the gate electrode layer in the recess. Silicide layers are then formed on a source region and a drain region disposed in the semiconductor material region, while the hard mask is disposed over the gate electrode layer. A source contact and a drain contact is then provided, each source and drain contact being conductively coupled to a respective one of the silicide layers. | 2014-06-26 |
20140179078 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A method for fabricating a semiconductor device includes: forming a silicon nitride film having a refractive index equal to or larger than 2.2 on a nitride semiconductor layer; and introducing at least one of elements that are oxygen, nitrogen, fluorine, phosphorus, sulfur and selenium into the silicon nitride film, the silicon nitride film including the at least one of elements remaining on the nitride semiconductor layer. The at least one of elements is introduced by a process of exposing the silicon nitride film to plasma including the at least one of elements, a process of ion-implanting the at least one of elements into the silicon nitride film, or a process of thermally diffusing the at least one of elements into the silicon nitride film. The silicon nitride film is formed in contact with a surface of the nitride semiconductor layer. | 2014-06-26 |
20140179079 | MANUFACTURING METHOD OF LATERAL DOUBLE DIFFUSED METAL OXIDE SEMICONDUCTOR DEVICE - The present invention discloses a manufacturing method of a lateral double diffused metal oxide semiconductor (LDMOS) device. The LDMOS device includes: a substrate, an epitaxial layer, a first conductivity type channel stop region, a first conductivity type top region, an isolation oxide region, a field oxide region, a first conductivity type well, a gate, a second conductivity type lightly doped region, a second conductivity type source, and a second conductivity type drain. The present invention defines the channel stop region, the top region, the isolation oxide region, and the field oxide region by a same oxide region mask, wherein the isolation oxide region and the field oxide region are located on the channel stop region and the top region respectively. | 2014-06-26 |
20140179080 | High Voltage Device with Reduced Leakage - A semiconductor device is provided which includes a semiconductor substrate, a gate structure formed on the substrate, sidewall spacers formed on each side of the gate structure, a source and a drain formed in the substrate on either side of the gate structure, the source and drain having a first type of conductivity, a lightly doped region formed in the substrate and aligned with a side of the gate structure, the lightly doped region having the first type of conductivity, and a barrier region formed in the substrate and adjacent the drain. The barrier region is formed by doping a dopant of a second type of conductivity different from the first type of conductivity. | 2014-06-26 |
20140179081 | SEMICONDUCTOR DEVICE MANUFACTURING METHOD - A semiconductor manufacturing method includes exposing on a photoresist film a first partial pattern of a contact hole, overlapping a part of a gate interconnection in alignment with an alignment mark formed simultaneously with forming the gate interconnection, exposing on the photoresist film a second partial pattern, overlapping a part of an active region in alignment with an alignment mark formed simultaneously with forming the active region, developing the photoresist film to form an opening at the portion where the first partial pattern and the second partial pattern have been exposed, and etching an insulation film to form a contact hole down to the gate interconnection and the source/drain diffused layer. | 2014-06-26 |
20140179082 | Selective Etching of Hafnium Oxide Using Non-Aqueous Solutions - Provided are methods for processing semiconductor substrates having hafnium oxide structures as well as one or more of silicon nitride, silicon oxide, polysilicon, and titanium nitride structures. Selected etching solution compositions and processing conditions provide high etching selectivity of hafnium oxide relative to these other materials. As such, hafnium oxide structures may be partially or completely removed without significant damage to other exposed structures made from these other materials. In some embodiments, the etching rate hafnium oxide is two or more times greater than the etching rate of silicon oxide and/or twenty or more times greater that the etching rate of polysilicon. The etching rate of hafnium oxide may be one and half times greater than the etching rate of silicon nitride and/or five or more times greater than the etching rate of titanium nitride. | 2014-06-26 |
20140179083 | HIGH DIE STRENGTH SEMICONDUCTOR WAFER PROCESSING METHOD AND SYSTEM - Embodiments of methods and systems for processing a semiconductor wafer are described. In one embodiment, a method for processing a semiconductor wafer involves performing laser stealth dicing on the semiconductor wafer to form a stealth dicing layer within the semiconductor wafer and after performing laser stealth dicing, cleaning the semiconductor wafer from a back-side surface of the semiconductor wafer with a blade to remove at least a portion of the stealth dicing layer. Other embodiments are also described. | 2014-06-26 |
20140179084 | WAFER DICING FROM WAFER BACKSIDE - Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. For example, a method includes applying a protection tape to a wafer front side, the wafer having a dicing tape attached to the wafer backside. The dicing tape is removed from the wafer backside to expose a die attach film disposed between the wafer backside and the dicing tape. Alternatively, if no die attach film is initially disposed between the wafer backside and the dicing tape, a die attach film is applied to the wafer backside at this operation. A water soluble mask is applied to the wafer backside. Laser scribing is performed on the wafer backside to cut through the mask, the die attach film and the wafer, including all layers included within the front side and backside of the wafer. A plasma etch is performed to treat or clean surfaces of the wafer exposed by the laser scribing. A wafer backside cleaning is performed and a second dicing tape is applied to the wafer backside. The protection tape is the removed from the wafer front side. | 2014-06-26 |
20140179085 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, SUBSTRATE PROCESSING APPARATUS, AND NON-TRANSITORY COMPUTER-READABLE RECORDING MEDIUM - A method of manufacturing a semiconductor device can enhance controllability of the diameters of grains of a film containing a predetermined element such as a silicon film when the film is formed. The method includes (a) forming a seed layer containing a predetermined element and carbon on a substrate by performing a cycle a predetermined number of times, the cycle including alternately performing supplying a first source gas containing the predetermined element, an alkyl group and a halogen group to the substrate and supplying a second source gas containing the predetermined element and an amino group to the substrate, or by performing supplying the first source gas to the substrate a predetermined number of times; and (b) forming a film containing the predetermined element on the seed layer by supplying a third source gas containing the predetermined element and free of the alkyl group to the substrate. | 2014-06-26 |
20140179086 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, METHOD OF PROCESSING SUBSTRATE, SUBSTRATE PROCESSING APPARATUS AND COMPUTER-READABLE RECORDING MEDIUM - A method of manufacturing a semiconductor device, includes: alternately performing (i) a first step of alternately supplying a first raw material containing a first metal element and a halogen element and a second raw material containing a second metal element and carbon to a substrate by a first predetermined number of times, and (ii) a second step of supplying a nitridation raw material to the substrate, by a second predetermined number of times, wherein alternating the first and second steps forms a metal carbonitride film containing the first metal element having a predetermined thickness on the substrate. | 2014-06-26 |
20140179087 | NANOELECTRONIC STRUCTURE AND METHOD OF PRODUCING SUCH - The present invention relates to semiconductor devices comprising semiconductor nanoelements. In particular the invention relates to devices having a volume element having a larger diameter than the nanoelement arranged in epitaxial connection to the nanoelement. The volume element is being doped in order to provide a high charge carrier injection into the nanoelement and a low access resistance in an electrical connection. The nanoelement may be upstanding from a semiconductor substrate. A concentric layer of low resistivity material forms on the volume element forms a contact. | 2014-06-26 |
20140179088 | METHOD FOR MANUFACTURING SEMICONDUCTOR SUBSTRATE - The inventive concept provides methods for manufacturing a semiconductor substrate. The method may include forming a stop pattern surrounding an edge of a substrate, forming a transition layer an entire top surface of the substrate except the stop pattern, and forming an epitaxial semiconductor layer on the transition layer and the stop pattern. The epitaxial semiconductor layer may not be grown from the stop pattern. That is, the epitaxial semiconductor layer may be isotropically grown from a top surface and a sidewall of the transition layer by a selective isotropic growth method, so that the epitaxial semiconductor layer may gradually cover the stop pattern. | 2014-06-26 |
20140179089 | Process for Producing at Least One Silicon-Based Nanoelement in a Silicon Oxide Section and Process for the Manufacture of a Device Employing the Production Process - The process for the production of at least one silicon-based nanoelement ( | 2014-06-26 |
20140179090 | STORAGE AND SUB-ATMOSPHERIC DELIVERY OF DOPANT COMPOSITIONS FOR CARBON ION IMPLANTATION - A supply source for delivery of a CO-containing dopant gas composition is provided. The composition includes a controlled amount of a diluent gas mixture such as xenon and hydrogen, which are each provided at controlled volumetric ratios to ensure optimal carbon ion implantation performance. The composition can be packaged as a dopant gas kit consisting of a CO-containing supply source and a diluent mixture supply source. Alternatively, the composition can be pre-mixed and introduced from a single source that can be actuated in response to a sub-atmospheric condition achieved along the discharge flow path to allow a controlled flow of the dopant mixture from the interior volume of the device into an ion source apparatus. | 2014-06-26 |
20140179091 | METHOD FOR FORMING ULTRA-SHALLOW DOPING REGIONS BY SOLID PHASE DIFFUSION - A method for forming ultra-shallow dopant regions in a substrate is provided. One embodiment includes depositing a first dopant layer containing a first dopant in direct contact with the substrate, patterning the first dopant layer, depositing a second dopant layer containing a second dopant in direct contact with the substrate adjacent the patterned first dopant layer, the first and second dopant layers containing an oxide, a nitride, or an oxynitride, where the first and second dopant layers contain an n-type dopant or a p-type dopant with the proviso that the first or second dopant layer do not contain the same dopant, and diffusing the first dopant from the first dopant layer into the substrate to form a first ultra-shallow dopant region in the substrate, and diffusing the second dopant from the second dopant layer into the substrate to form a second ultra-shallow dopant region in the substrate. | 2014-06-26 |
20140179092 | METHOD FOR FORMING VOID-FREE POLYSILICON AND METHOD FOR FABRICATING SEMICONDUCTOR DEVICE USING THE SAME - A method for fabricating a semiconductor device includes forming a buried gate electrode in a semiconductor substrate. An insulating layer is formed over the buried gate electrode and is etched to form a contact hole exposing the semiconductor substrate. A sacrificial spacer is formed on sidewalls of the insulating layer defining the contact hole. A polysilicon layer pattern is formed in the contact hole. The sacrificial spacer is removed to form an air gap around the polysilicon layer pattern. A thermal process is performed to remove a seam existing in the polysilicon layer pattern. | 2014-06-26 |
20140179093 | GATE STRUCTURE FORMATION PROCESSES - Gate structures and methods of fabricating gate structures of semiconductor devices are provided. One method includes, for instance: providing a sacrificial layer over a substrate; patterning the sacrificial layer to form a gate opening within the sacrificial layer; providing a gate structure within the gate opening in the sacrificial layer; and removing the sacrificial layer, leaving the gate structure over the substrate. In enhanced aspects, the method includes: forming a reverse sidewall-spacer within the gate opening within the sacrificial layer, and after providing the gate structure, recessing the gate structure within the gate opening, and providing a gate cap within the gate recess in the gate structure. | 2014-06-26 |
20140179094 | SEMICONDUCTOR DEVICE HAVING FIELD PLATE ELECTRODE AND METHOD FOR MANUFACTURING THE SAME - According to one embodiment, in a semiconductor device, a first semiconductor layer of a first conductivity type has a first impurity concentration. A second semiconductor layer of the first conductivity type is formed on the first semiconductor layer and has a second impurity concentration lower than the first impurity concentration. A field plate electrode is formed in a lower portion of a trench formed in the second semiconductor layer through a first insulating film so as to bury the lower portion of the trench. A second insulating film is formed in the upper portion of the trench so as to be in contact with the top surface of the field plate electrode. A gate electrode is formed in the upper portion of the trench through a gate insulating film so as to bury the upper portion of the trench to sandwich the second insulating film. | 2014-06-26 |
20140179095 | Methods and Systems for Controlling Gate Dielectric Interfaces of MOSFETs - Embodiments provided herein describe methods and systems for forming gate dielectrics for field effect transistors. A substrate including a germanium channel and a germanium oxide layer on a surface of the germanium channel is provided. A metallic layer is deposited on the germanium oxide layer. The metallic layer may be nanocrystalline or amorphous. The deposition of the metallic layer causes the germanium oxide layer to be reduced such that a metal oxide layer is formed adjacent to the germanium channel. | 2014-06-26 |
20140179096 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device includes a substrate including a first region and a second region, a gate group disposed in the first region of the substrate, the gate group including a plurality of cell gate patterns and at least one selection gate pattern, a first gate pattern disposed in the second region of the substrate, a group spacer covering a top surface and a side surface of the gate group, the group spacer having a first inflection point, and a first pattern spacer covering a top surface and a side surface of the first gate pattern, the first pattern spacer having a second inflection point. | 2014-06-26 |
20140179097 | DEPOSITION APPARATUS AND METHOD - A method for filling features in a layer over a substrate is provided. A dispersion of nanoparticles less than 5 nm is placed on the layer. The liquid is frozen by lowering a temperature of the liquid. The frozen liquid is sublimated by decreasing pressure and subsequently heating the frozen liquid, wherein the nanoparticles are not sublimated. | 2014-06-26 |
20140179098 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - The semiconductor device includes a capacitor including a plurality of interconnection layers stacked over each other, the plurality of interconnection layers each including a plurality of electrode patterns extended in a first direction, a plurality of via parts provided between the plurality of interconnection layers and electrically interconnecting the plurality of the electrode patterns between the interconnection layers adjacent to each other, and an insulating films formed between the plurality of interconnection layers and the plurality of via parts. Each of the plurality of via parts is laid out, offset from a center of the electrode pattern in a second direction intersecting the first direction, and the plurality of electrode patterns has a larger line width at parts where the via parts are connected to, and a distance between the electrode patterns and the adjacent electrode patterns is reduced at the parts. | 2014-06-26 |
20140179099 | METHODS AND STRUCTURE FOR CARRIER-LESS THIN WAFER HANDLING - Methods of forming a microelectronic assembly and the resulting structures and devices are disclosed herein. In one embodiment, a method of forming a microelectronic assembly includes removing material exposed at portions of a surface of a substrate to form a processed substrate having a plurality of thinned portions separated by integral supporting portions of the processed substrate having a thickness greater than a thickness of the thinned portions, at least some of the thinned portions including a plurality of electrically conductive interconnects extending in a direction of the thicknesses of the thinned portions and exposed at the surface; and removing the supporting portions of the substrate to sever the substrate into a plurality of individual thinned portions, at least some individual thinned portions including the interconnects. | 2014-06-26 |
20140179100 | Method to Control Depth Profiles of Dopants Using a Remote Plasma Source - Methods and apparatus for processing using a remote plasma source are disclosed. The apparatus includes an outer chamber enclosing a substrate support, a remote plasma source, and a showerhead. A substrate heater can be mounted in the substrate support. A transport system moves the substrate support and is capable of positioning the substrate. The remote plasma source may be used to provide a plasma surface treatment or as a source to incorporate dopants into a pre-deposited layer. | 2014-06-26 |
20140179101 | SEMICONDUCTOR DEVICE WITH AIR GAP AND METHOD FOR FABRICATING THE SAME - A method for fabricating a semiconductor device includes forming a semiconductor structure having an open portion over a substrate, forming a sacrificial spacer on sidewalls of the open portion, forming a recessed first plug in the open portion, forming an air gap by removing the sacrificial spacer, forming a capping layer to expose the top surface of the recessed first plug and to cap the air gap, forming a protective layer over the capping layer and the recessed first plug, forming an ohmic contact layer over the protective layer, and forming a second plug over the ohmic contact layer. | 2014-06-26 |
20140179102 | SEMICONDUCTOR DEVICE WITH AIR GAPS AND METHOD FOR FABRICATING THE SAME - A method for fabricating a semiconductor device includes forming a plurality of bit line structures over a substrate, forming contact holes between the bit line structures, forming sacrificial spacers on sidewalls of the contact holes, forming first plugs recessed inside the contact holes, forming air gaps by removing the sacrificial spacers, forming conductive capping layers capping the first plugs and the air gaps, and forming second plugs over the conductive capping layers. | 2014-06-26 |