26th week of 2014 patent applcation highlights part 78 |
Patent application number | Title | Published |
20140181511 | SECURE SYSTEM FOR ALLOWING THE EXECUTION OF AUTHORIZED COMPUTER PROGRAM CODE - Systems and methods for selective authorization of code modules are provided. According to one embodiment, file system or operating system activity relating to a code module is intercepted by a kernel mode driver of a computer system. The code module is selectively authorized by authenticating a cryptographic hash value of the code module with reference to a multi-level whitelist. The multi-level whitelist includes (i) a global whitelist database remote from the computer system that is maintained by a trusted service provider and that contains cryptographic hash values of approved code modules, which are known not to contain viruses or malicious code and (ii) a local whitelist database containing cryptographic hash values of at least a subset of the approved code modules. The activity relating to the code module is allowed when the cryptographic hash value matches one of the cryptographic hash values of approved code modules within the multi-level whitelist. | 2014-06-26 |
20140181512 | COMPUTER IMPLEMENTED METHOD FOR PERFORMING CLOUD COMPUTING ON DATA BEING STORED PSEUDONYMOUSLY IN A DATABASE - The invention relates to a computer implemented method for performing cloud computing on data of a first user employing cloud components, the cloud components comprising a first database and a data processing component, wherein an asymmetric cryptographic key pair is associated with the first user, said asymmetric cryptographic key pair comprising a public key and a private key, the data being stored pseudonymously non-encrypted in the first database with the data being assigned to an identifier, wherein the identifier comprises the public key, the method comprising retrieving the data from the first database by the data processing component, wherein retrieving the data from the first database comprises receiving the identifier and retrieving the data assigned to the identifier from the first database, wherein the method further comprises processing the retrieved data by the data processing component and providing a result of the analysis. | 2014-06-26 |
20140181513 | CENTRALIZED SECURE DEVICE PAIRING - Various embodiments are generally directed to pairing computing devices for collaborative interaction via a network through a centralized secure device pairing service. An apparatus comprises a controller processor circuit, and a controller storage communicatively coupled to the controller processor circuit to store an initial private key and to store instructions that when executed by the controller processor circuit cause the controller processor circuit to create a first signature using the initial private key, transmit the first signature to an issuing server via a network, receive a group public key and an associated member private key from the issuing server, create a second signature using the member private key, transmit the second signature to a member device via the network; receive a third signature from the member device; and authenticate the third signature using the group public key. Other embodiments are described and claimed herein. | 2014-06-26 |
20140181514 | ENCRYPTION KEY MANAGEMENT PROGRAM, DATA MANAGEMENT SYSTEM - An objective of the present invention is to ensure security of the file sharing function provided by cloud storages without significantly decreasing the convenience of cloud storages. The encryption key management program according to the present invention encrypts, using authentication information of a user, a group shared key shared in a user group and stores it as an encrypted group shared key. The encryption key management program, upon receiving a request from a user, sends the encrypted group shared key corresponding to the requesting user. | 2014-06-26 |
20140181515 | MOBILE COMMUNICATION DEVICES, WIRELESS ACCESS POINTS, AND WIRELESS LOCAL AREA NETWORK (WLAN) AUTHENTICATION METHODS THEREOF - A Wireless Access Point (WAP) including a Local Area Network (LAN) interface and a first wireless module is provided. The LAN interface is configured to provide access to the Internet. The first wireless module is configured to generate a plurality of security parameters associated with a Wireless Local Area Network (WLAN) technology, use the WLAN technology to perform an authentication procedure with a mobile communication device according to the security parameters, and after completing the authentication procedure, provide a Hotspot service of the WLAN technology to the mobile communication device via the LAN interface, wherein the security parameters are transmitted, prior to the authentication procedure, to the mobile communication device via an encrypted connection which is established using a cellular network technology. | 2014-06-26 |
20140181516 | DETECTION METHOD FOR FRAUDULENT MAIL, DETECTION PROGRAM THEREFOR, AND DETECTION DEVICE THEREFOR - Preliminarily sharing internal-transmission-secret-key-information used in e-mail addressed to an internal-network, between transmitting and receiving-terminals, and generating external-transmission-secret-key information used in an e-mail addressed to an external-network and external-transmission-public-key-information corresponding to the external-transmission-secret-key-information, in transmitting a mail, generating verification-information by encrypting first characteristic-amount-target-information including a characteristic-amount-target-item included in an outgoing-mail and adding, to the outgoing-mail header, the verification-information and characteristic-amount-target-item-information corresponding to the characteristic-amount-target-item, and, in receiving a mail, generating second characteristic-amount-target-information including a characteristic-amount-target-item indicated by the characteristic-amount-target-item-information added to the incoming-mail, decrypting the verification-information, generating third characteristic-amount-target-information, and verifying whether the second and the third coincide. | 2014-06-26 |
20140181517 | Cloud Centric Application Trust Validation - In accordance with the exemplary embodiments of the invention there is at least a method and an apparatus to perform the method of sending towards a key management device associated with an application service provider for an application, a key request for the application being booted in the cloud network; and in response to the key request, receiving an application specific key for the application, where the key is based on multiple factors associated with the application server. Further, there is at least a method and an apparatus to perform the method of receiving a key request from an application server of a cloud network for the application being booted in the cloud network; in response to the key request, authenticating the request using multiple attributes associated with the application server; and sending an application specific key for the application towards the application server. | 2014-06-26 |
20140181518 | SECURE MOBILE APP CONNECTION BUS - A secure mobile application connection bus is disclosed. First encryption information and an identifier associated with a data storage location on a mobile device are provided from a first application to a second application. Second encryption information associated with the second mobile application is retrieved from the data storage location. The second mobile application is configured to provide data to the data storage location. Data is transferred securely between the first mobile application and the second mobile application via the data storage location. | 2014-06-26 |
20140181519 | SYSTEMS AND METHODS FOR SECURELY PLACE SHIFTING MEDIA CONTENT - Systems and methods are provided for securely providing a place-shifted media stream from a place shifting device to a remote player via a communications network. A request for a connection is received from the remote player at the place shifting device via the communications network. In response to the request for the connection, an authorization credential is requested from a central server via the communications network. Further, in response to the authorization credential received from the central server, the place-shifted media stream between the place shifting device and the remote player can be established over the communications network. At least a portion of the place-shifted media stream may be encrypted based upon the authorization credential. | 2014-06-26 |
20140181520 | METHOD USING A SINGLE AUTHENTICATION DEVICE TO AUTHENTICATE A USER TO A SERVICE PROVIDER AMONG A PLURALITY OF SERVICE PROVIDERS AND DEVICE FOR PERFORMING SUCH A METHOD - A method for authenticating a user to a provider, among a plurality of providers. The method uses an authentication device comprising, for each of provider, a record comprising a pairing key and first data, both as shared data. Provider authentication data comprises a first cryptogram obtained by encrypting said first data with said pairing key. Authenticating provider authentication data is performed at the authentication device by the steps of decrypting said first cryptogram by means of the pairing key stored in one of said records, then comparing the result of this decryption with first data resulting from pairing data stored in said record, if the comparison does not indicate a match, then processing again the previous decryption and comparison steps by using the pairing key of another record until each of said records stored in the authentication device has been processed. | 2014-06-26 |
20140181521 | PROVISIONING OF ELECTRONIC DEVICES - Systems and methods for provisioning electronic devices. In some embodiments, a method may include receiving a first message at a provisioning server, the first message originated by a computing device, the first message including a device identifier associated with an automation device. The method may also include receiving a second message at the provisioning server, the second message originated by the automation device and including at least a device identifier portion. In response to the device identifier portion of the second message matching the device identifier of the first message and/or in response to the automation device not being associated with a provisioning account, the method may then include providing configuration information to the automation device. | 2014-06-26 |
20140181522 | COMMUNICATION NODE, KEY SYNCHRONIZATION METHOD, AND KEY SYNCHRONIZATION SYSTEM - In general, according to one embodiment, a communication node includes a key synchronization controller and an application communicator. The key synchronization controller controls synchronization of an application key on the basis of a node-based signaling process and a session-based signaling process, where the former process is for starting or ending exchanging of an application key between a correspondent node and the communication node and the latter process is for synchronizing a rule for assignment of the application key to a session with the correspondent node, the session shared with the correspondent node. The application communicator provides the application key in accordance with the rule, the key for use by an application having the session. | 2014-06-26 |
20140181523 | GESTURE-BASED ENCRYPTION METHODS AND SYSTEMS - Methods and systems for transmitting and receiving are disclosed. For example, a method for establishing secure communications can include measuring one or more human gestures using a sensor on a first device so as to create a first metric of the one or more human gestures, creating a strong encryption key based on the first metric, including time-based information incorporated into the first metric, and communicating to a second device using the strong encryption key to encrypt data sent to the second device. | 2014-06-26 |
20140181524 | AUTHENTICATION METHOD, AUTHENTICATION SYSTEM, AND AUTHENTICATION CHIP USING COMMON KEY CRYPTOGRAPHY - A method is disclosed for authenticating, by a processor that controls a parent device, a child device includes: authenticating the child device by making a comparison between a value obtained by operating, for a first response value, a third transform function, which is decided based on a number of a difference between the value set in an authentication chip of the parent device and the value set in an authentication chip of the child device, and the second response value, wherein a first and a second response values are obtained by operating a first and a second transform functions for output values generated by operating an encryption function for performing encryption for secret keys in authentication chips of the parent device and the child device, respectively. | 2014-06-26 |
20140181525 | DIGITAL RIGHTS MANAGEMENT OF STREAMING CONTENTS AND SERVICES - Managing digital rights of contents and services streamed to a client device, including: receiving and validating a certificate from the client device; enabling the client device to log into and communicate with a server using a secure protocol to establish a private relationship between the client device and the server; and transmitting a resource identifier to the client device using the secure protocol when the private relationship is established. | 2014-06-26 |
20140181526 | METHODS AND SYSTEMS FOR BYPASSING AUTHENTICITY CHECKS FOR SECURE CONTROL MODULES - Methods and systems are provided for bypassing an authenticity check for a secure control module. In one embodiment, a method includes: receiving authenticity data from a secure source, wherein the authenticity data includes a signature and an identifier that is unique to the control module; programming the control module with the authenticity data; and bypassing the authenticity check of a control program of the control module based on the authenticity data. | 2014-06-26 |
20140181527 | UNSECURE NETWORK SOCKET COMMUNICATION - Disclosed herein are techniques for secure communications through unsecure sockets. It is determined whether an executable file contains a signature from a trustworthy source. If the executable file contains the trustworthy signature, communication from a process is permitted. | 2014-06-26 |
20140181528 | FILE TAMPER DETECTION - This disclosure relates generally to methods and systems for determining when a file has changed. According to one aspect of the present disclosure, a method of determining if contents of a file have changed can include determining if a digital signature created as a function of contents of the file has changed, and when the digital signature has changed, overlaying the contents of the file with a first mark that indicates the contents have changed and blocks a view of the contents of the file. | 2014-06-26 |
20140181529 | VERIFICATION OF PASSWORD USING A KEYBOARD WITH A SECURE PASSWORD ENTRY MODE - The present invention includes a device and method to authenticate a user to a computer prior to the user having access to the computer or network. As user name and password protocols are nearly ubiquitous in authentication applications used today, there have been developed many nefarious techniques to defeat the security of such systems. It is relatively easy to write a computer program to guess passwords and then use those passwords to defeat security and cause harm and mischief to a computer, its users and others. To thwart such activity, the present invention provides a novel device that can be provided within a keyboard, in a computer, or in a third device having connectivity thereto. The device in conjunction with the method provides a secure password mode and a challenge/response protocol to verify that the password is entered in response to a particular request for a password. | 2014-06-26 |
20140181530 | System and Method for Protecting Cloud Services from Unauthorized Access and Malware Attacks - Disclosed are systems, methods and computer program products for protecting cloud security services from unauthorized access and malware attacks. In one example, a cloud server receives one or more queries from security software of the user device. The server analyzes a system state and configuration of the user device to determine the level of trust associated with the user device. The server also analyzes the one or more queries received from the security software to determine whether to update the level of trust associated with the user device. The server determines, based on the level of trust, how to process the one or more queries. Finally, the server provides responses to the one or more queries from the security software based on the determination of how to process the one or more queries. | 2014-06-26 |
20140181531 | SYSTEMS AND METHODS FOR QUEUE LEVEL SSL CARD MAPPING TO MULTI-CORE PACKET ENGINE - The present invention is directed towards systems and methods for distributed operation of a plurality of cryptographic cards in a multi-core system. In various embodiments, a plurality of cryptographic cards providing encryption/decryption resources are assigned to a plurality of packet processing engines in operation on a multi-core processing system. One or more cryptographic cards can be configured with a plurality of hardware or software queues. The plurality of queues can be assigned to plural packet processing engines so that the plural packet processing engines share cryptographic services of a cryptographic card having multiple queues. In some embodiments, all cryptographic cards are configured with multiple queues which are assigned to the plurality of packet processing engines configured for encryption operation. | 2014-06-26 |
20140181532 | ENCRYPTED FLASH-BASED DATA STORAGE SYSTEM WITH CONFIDENTIALITY MODE - Raw or unencrypted data is encrypted using a standard encryption algorithm and stored in a Flash memory array. The raw or unencrypted data may be pre-processed before it is encrypted. Pre-processing may include data scrambling, pre-encryption data mixing, or both. Data scrambling may involve an invertible transformation. The scrambled data may then be used to seed a sequence generator. Each output from the sequence generator may be processed using a bit-by-bit Exclusive Or (XOR) operation to impart random or pseudorandom statistical properties. Pre-encryption data mixing may combine the scrambled (or unscrambled) data with information that is unique to each chunk of data, as well as with a user-supplied secret key. This helps ensure that identical raw data chunks are not stored as identical encrypted data chunks in the Flash memory array. | 2014-06-26 |
20140181533 | SECURE OBJECT HAVING PROTECTED REGION, INTEGRITY TREE, AND UNPROTECTED REGION - A method and structure for a secure object, as tangibly embodied in a computer-readable storage medium. The secure object includes a cryptographically protected region containing at least one of code and data, an initial integrity tree that protects an integrity of contents of the cryptographically protected region; and an unprotected region that includes a loader, an esm (enter secure mode) instruction, and one or more communication buffers. | 2014-06-26 |
20140181534 | CRYPTOGRAPHIC CIRCUIT PROTECTION FROM DIFFERENTIAL POWER ANALYSIS - According to an example embodiment, a device provides cryptographic processing functions using secret data. The device can include protection from differential power analysis (DPA). The encryption processing circuit and its memory can be decoupled from external power source(s) during encryption-related computations. A local power storage element, such as a capacitive element, can provide power while the encryption processing circuit is decoupled from the external power source(s). The local power storage element can then be reconnected and charged once the encryption-related computations are completed or paused. | 2014-06-26 |
20140181535 | TAP-TO-WAKE AND TAP-TO-LOGIN NEAR FIELD COMMUNICATION (NFC) DEVICE - Described herein are techniques related to a tap-to-wake and tap-to-login system. This Abstract is submitted with the understanding that it will not be used to interpret or limit the scope and meaning of the claims. A tap-to-wake and tap-to-login system allows a user of a near field device to wake up a computing platform from a deep sleep state using a bump/tap without having to move a mouse or enter a keyboard stroke. | 2014-06-26 |
20140181536 | USING TEMPERATURE MARGIN TO BALANCE PERFORMANCE WITH POWER ALLOCATION - A method and apparatus using temperature margin to balance performance with power allocation. Nominal, middle and high power levels are determined for compute elements. A set of temperature thresholds are determined that drive the power allocation of the compute elements towards a balanced temperature profile. For a given workload, temperature differentials are determined for each of the compute elements relative the other compute elements, where the temperature differentials correspond to workload utilization of the compute element. If temperature overhead is available, and a compute element is below a temperature threshold, then particular compute elements are allocated power to match or drive toward the balanced temperature profile. | 2014-06-26 |
20140181537 | GUARDBAND REDUCTION FOR MULTI-CORE DATA PROCESSOR - A multi-core data processor includes multiple data processor cores and a power controller. Each data processor core has a first input for receiving a clock signal, a second input for receiving a power supply voltage, and an output for providing an idle signal. The power controller is coupled to each of the data processor cores for providing the clock signal and the power supply voltage to each of the data processor cores. The power controller provides at least one of the clock signal and the power supply voltage to an active one of the data processor cores in dependence on a number of idle signals received from the data processor cores. | 2014-06-26 |
20140181538 | Controlling Configurable Peak Performance Limits Of A Processor - In one embodiment, the present invention includes a processor having a plurality of cores each to execute instructions, a non-volatile storage to store maximum peak operating frequency values each a function of a given number of active cores, a configuration storage to store frequency limits each corresponding to one of the maximum peak operating frequency values or a configurable clip frequency value less than the maximum peak operating frequency value. In turn, a power controller is configured to limit operating frequency of the cores to a corresponding frequency limit obtained from the configuration storage. Other embodiments are described and claimed. | 2014-06-26 |
20140181539 | SYSTEM FOR ADAPTIVE -POWER CONSUMPTION DESIGN IN ULTRATHIN COMPUTING DEVICES - A system and method for adaptive power consumption in a computing device having a chassis forming an enclosure for a chamber. The computing device further includes, in the chamber, a heterogeneous processing unit that includes a CPU operatively coupled with a GPU and that generates thermal and performance information for the CPU and GPU, a memory, and a memory controller that connects the memory to the heterogeneous processing unit. A passive cooling subsystem and an active cooling subsystem cools off the chamber. A plurality of thermal sensors are positioned to monitor temperatures within the chamber. A thermal detection and control unit receives thermal and performance information from the heterogeneous processing unit and the plurality of thermal sensors and responsively adjusts overall power consumption of the heterogeneous processing unit, the memory controller, the memory and the active cooling subsystem to maintain performance of the heterogeneous processing unit while minimizing thermal heating. | 2014-06-26 |
20140181540 | HYBRID BATTERY PACK - A power source for supplying power to a mobile computing system comprising a Li polymer battery coupled in parallel with a supercapacitor cell battery. The Li polymer battery supplies substantially all the continuous currents demanded by the system load. The supercapacitor cell battery supplies substantially all the transient current demanded by the system load. The Li polymer battery may charge the supercapacitor cell battery when the voltage difference is larger than the difference caused by internal impedance difference. | 2014-06-26 |
20140181541 | INFORMATION EQUIPMENT AND BATTERY CHARGE CIRCUIT - To protect a battery when an anomaly of a charge circuit occurs. Information equipment includes: a charge circuit for controlling an output voltage of a DC power supply and applying the controlled voltage to a battery; a battery protection circuit for interrupting a first power supply path connecting the battery and the charge circuit when an anomaly of the battery occurs; an input voltage detection circuit for detecting an input voltage which is input from the DC power supply to the charge circuit; and an interruption circuit for determining that an anomaly of the charge circuit has occurred, and interrupting a second power supply path connecting the first power supply path or the DC power supply and the charge circuit when the input voltage detected by the input voltage detection circuit fluctuates and indicates an abnormal value. | 2014-06-26 |
20140181542 | System and Method For Dynamically Controlling A Plurality Of Cores In A Multicore Central Processing Unit Based On Tempature - A method of controlling power within a multicore central processing unit (CPU) is disclosed. The method may include monitoring a die temperature, determining a degree of parallelism within a workload of the CPU, and powering one or more cores of the CPU up or down based on the degree of parallelism, the die temperature, or a combination thereof. | 2014-06-26 |
20140181543 | PORTABLE TERMINAL, RECORDING MEDIUM - A portable terminal supplies power to a chip card therein with host power off. A power controller supplies power from a battery to a host, the chip card, and a CLF; a first switch opens/closes a power supply channel to the chip card, branching from a power supply channel from the power controller to the host; a second switch opens/closes a power supply channel to the chip card, branching from a power supply channel from the power controller to the CLF; a switch controller opens the first switch and closes the second switch if the CLF detects a contactless RF signal, if the host is off or if the portable terminal is in a low battery mode, and if the contactless RF signal conforms to the communication method of the chip card, and the switch controller closes the first switch and opens the second switch if the host is on. | 2014-06-26 |
20140181544 | Reducing Power Consumption of a Redundant Power System Utilizing Sleep Power Consumption Considerations for Power Supply Units Within the Redundant Power System - A method, system, and information handling system provides better system power consumption of a redundant power system having a plurality of power supply units (PSUs) by taking into consideration each PSU's sleep power consumption during selection of one or more PSUs to place into a “hot spare” sleep mode. For each PSU, power efficiency data at different load ratings are measured and stored. During the PSU selection, a calculation of system power consumption is conducted on each of several configurations where a different PSU is hypothetically disabled. Each calculation takes into consideration both the sleep power consumption of a disabled PSU and power efficiency data of an enabled PSU. Selection of one or more PSUs to disable is determined according to the configuration yielding the lower or lowest system input power consumption based on the results of the calculations. | 2014-06-26 |
20140181545 | Dynamic Balancing Of Power Across A Plurality Of Processor Domains According To Power Policy Control Bias - In an embodiment, a processor includes multiple domains including a core domain having at least one core to execute instructions and a graphics domain including at least one graphics engine to perform graphics operations and a power controller to control power consumption of the processor. The power controller may include a logic to receive an indication of a priority domain of the domains and to dynamically allocate power to the domains based on a power limit, one or more maximum domain frequency requests, and the priority domain indication. Other embodiments are described and claimed. | 2014-06-26 |
20140181546 | METHOD AND APPARATUS FOR POWER RESOURCE PROTECTION - An apparatus may comprise a platform power protection circuit to monitor an electric current over a platform input line, the electric current received on the platform input line from a current source, and output an alert signal from a comparator when current output is determined to exceed a current threshold. The apparatus may further include logic to assert a control signal to reduce power consumption in one or more platform components coupled to the platform input line when the alert signal is received. Other embodiments are disclosed and claimed. | 2014-06-26 |
20140181547 | SMART CHARGING SYSTEM FOR HYBRID BATTERY PACK - A hybrid battery pack and a power supply procedure for supplying power to a mobile computing system comprising a Li polymer battery coupled in parallel with a supercapacitor cell battery. The Li polymer battery supplies substantially all the continuous currents demanded by the system load. The supercapacitor cell battery supplies substantially all the transient current demanded by the system load. A charging control logic circuit is coupled to the power source and the system load, and operable to control the Li polymer battery to charge the supercapacitor cell battery at a constant rate while the supercapacitor cell battery supplies current to the system load. The control logic can also send instructions to have system load reduced if the supercapacitor cell battery is depleted before it can be charged with an external charger. | 2014-06-26 |
20140181548 | System and Method for Using Energy Efficient Ethernet to Control Energy Efficiencies in Lower Layers - A system and method for using energy-efficient Ethernet to control energy efficiency in lower layers. In one example, an energy-efficiency control policy in a first Ethernet device can be configured to determine a need for transitioning of at least a part of the first Ethernet device into an energy saving sate. Based on such a determination, an energy-efficiency control signal can be transmitted from the first Ethernet device to a first non-Ethernet device. The receipt of the energy-efficiency control signal by the first non-Ethernet device is used to initiate a transition by the first non-Ethernet device into an energy saving state, which in turn may initiate a transition by downstream non-Ethernet devices into an energy saving state. This process creates a single unified energy-efficiency policy domain. | 2014-06-26 |
20140181549 | System and Method for Managing Power Consumption of an Information Handling System - An AC-to-DC power adapter provides DC power to an information handling system at a first higher DC voltage or a second lower DC voltage based upon a power state of the information handling system. For example, approximately 19 Volts DC power is provided if the information handling system is in an on state or if the information handling system is charging a battery. Approximately 13 Volts DC power is provided if the information handling system is in a reduced power state, such as an ACPI S3 state, with a battery having a substantially full charge. | 2014-06-26 |
20140181550 | SYSTEM HAVING TUNABLE PERFORMANCE, AND ASSOCIATED METHOD - A system having tunable performance includes: a plurality of units, wherein at least one unit includes a hardware circuit; at least one global/local busy level detector including a global busy level detector, wherein the global busy level detector is arranged to detect an entire global busy level of the plurality of units; at least one local busy level detector, wherein each local busy level detector is arranged to detect a local busy level of at least one portion of the units; and a global/local system performance manager arranged to tune the performance of the system according to the entire global busy level and the at least one local busy level, wherein a weight of the at least one local busy level is higher than that of the entire global busy level. An associated method is also provided. | 2014-06-26 |
20140181551 | MIXED CELL TYPE BATTERY MODULE AND USES THEREOF - Various embodiments are generally directed to operation of a computing device powered with first and second sets of energy storage cells, the cells of the first set structurally optimized for higher density storage of electric power, and the cells of the second set structurally optimized for providing electric power at a high electric current level. A battery module includes a casing, a first cell disposed within the casing to store electric energy with a high density, and a second cell disposed within the casing to provide electric energy stored therein with a high current level. Other embodiments are described and claimed herein. | 2014-06-26 |
20140181552 | MULTI-MODE DEVICE POWER-SAVING OPTIMIZATION - Methods and systems input an energy consumption profile for each of a plurality of different sleep modes available for a device, and input a probability distribution of interjob times for the device. The methods and systems then compute the optimal time-out period for each sleep mode based on the energy consumption profile of each sleep mode and the probability distribution of interjob times. Further, such methods and systems monitor the usage of the device to determine the current interjob time, and switch between sleep modes to relatively lower power sleep modes as the current interjob time becomes larger. | 2014-06-26 |
20140181553 | Idle Phase Prediction For Integrated Circuits - A method and apparatus for idle phase prediction in integrated circuits is disclosed. In one embodiment, an integrated circuit (IC) includes a functional unit configured to cycle between intervals of an active state and an idle state. The IC further includes a prediction unit configured to record a history of idle state durations for a plurality of intervals of the idle state. Based on the history of idle state durations, the prediction unit is configured to generate a prediction of the duration of the next interval of the idle state. The prediction may be used by a power management unit to, among other uses, determine whether to place the functional unit in a low power (e.g., sleep) state. | 2014-06-26 |
20140181554 | POWER CONTROL FOR MULTI-CORE DATA PROCESSOR - A multi-core data processor includes multiple data processor cores and a circuit. The multiple data processor cores each include a power state controller having a first input for receiving an idle signal, a second input for receiving a release signal, a third input for receiving a control signal, and an output for providing a current power state. In response to the idle signal, the power state controller causes a corresponding data processor core to enter an idle state. In response to the release signal, the power state controller changes the current power state from the idle state to an active state in dependence on the control signal. The circuit is coupled to each of the multiple data processor cores for providing the control signal in response to current power states in the multiple data processor cores. | 2014-06-26 |
20140181555 | MANAGING A POWER STATE OF A PROCESSOR - A method and system for managing a power state of a processor are described herein. The method includes receiving, at the processor, a signal indicating that an interrupt is to be sent to the processor. The method also includes transitioning the processor from the deep idle state to the shallow idle state in response to receiving the signal and transitioning the processor from the shallow idle state to an active state in response to receiving the interrupt. | 2014-06-26 |
20140181556 | Idle Phase Exit Prediction - A method and apparatus for exiting a low power state based on a prior prediction is disclosed. An integrated circuit (IC) includes a functional unit configured to, during operation, cycle between intervals of an active state and intervals of an idle state. The IC also include a power management unit configured to place the functional unit in a low power state responsive to the functional unit entering the idle state. The power management unit is further configured to preemptively cause the functional unit to exit the low power state at a predetermined time after entering the low power. The predetermined time is based on a prediction of idle state duration made prior to entering the low power state. The prediction may be generated by a prediction unit, based on a history of durations of intervals in which the functional unit was in the idle state. | 2014-06-26 |
20140181557 | METHODS AND APPARATUS RELATED TO PROCESSOR SLEEP STATES - A system includes a processor including at least a first core and a local interrupt controller associated with the first core. The first core is operable to store its architectural state prior to entering a first core sleep state, and the processor is operable to receive and implement a request for entering a system sleep state in which the first core is in the first core sleep state and the local interrupt controller is powered down and exit the system sleep state by restoring the local interrupt controller and restoring the saved architectural state of the first core. | 2014-06-26 |
20140181558 | REDUCING POWER CONSUMPTION OF VOLATILE MEMORY VIA USE OF NON-VOLATILE MEMORY - A method includes initiating a transition from an operating mode to a sleep mode at an electronic device that includes a volatile memory and a non-volatile memory. In response to the initiating, data is copied from the volatile memory to the non-volatile memory and a portion of the volatile memory is disabled. Another method includes determining that a low performance mode condition is satisfied at an electronic device that includes a volatile memory that stores a first copy of read-only data and a non-volatile memory that stores a second copy of the read-only data. A memory mapping of the read-only data is updated from the volatile memory to the non-volatile memory. A portion of the volatile memory that stores the first copy is disabled and access of the read-only data is directed to the non-volatile memory instead of the volatile memory. | 2014-06-26 |
20140181559 | SUPPORTING RUNTIME D3 AND BUFFER FLUSH AND FILL FOR A PERIPHERAL COMPONENT INTERCONNECT DEVICE - Particular embodiments described herein provide for an apparatus that includes a means for determining a power state for a device connected to a system, a means for determining that the device should change power states, and means for sending a signal to the device to put the device in a D3-cold state while the system is a GO/SO state. In an embodiment, the device is a peripheral component interconnect (PCI) device. Also, the particular example implementation can include means for sending a WAKE# signal from a controller to the device to cause the device to exit the D3-cold state, wherein the WAKE# signal was sent from a designated WAKE# signal pin on the controller. In some embodiments, the WAKE# signal is not sent to other devices in the system. | 2014-06-26 |
20140181560 | PLATFORM POWER CONSUMPTION REDUCTION VIA POWER STATE SWITCHING - Methods and apparatus relating to platform power consumption reduction via power state switching are described. In one embodiment, control logic causes a processor to enter a first low power consumption state (e.g., S0ix) instead of a second low power consumption state (e.g., S3) based on whether a threshold time period exists between a first wake event (e.g., corresponding to a first one of one or more awake requests) and a second wake event (e.g., corresponding to a second one of the one or more awake requests). Other embodiments are also claimed and disclosed. | 2014-06-26 |
20140181561 | POWER THROTTLING QUEUE - A power throttling queue includes a queue and a throttling circuit. The queue has multiple entries. Each entry has a data field and a valid field. The multiple entries include a first portion and a selectively disabled second portion. The throttling circuit is coupled to the queue, and selectively disables the second portion in response to a number of valid entries of the first portion. | 2014-06-26 |
20140181562 | METHOD FOR PREVENTING OVER-HEATING OF A DEVICE WITHIN A DATA PROCESSING SYSTEM - A method for providing over-heating protection of a target device within an information processing system is disclosed. A determination is made whether or not a power status of the information processing system is set to turn on a main power of a power supply device. If the power status of the information processing system is set to turn on a main power of a power supply device, a power switch of the target device is turned on; otherwise, another determining is made whether or not the target device is set to operate based on a user's setting. If the target device is set to operate based on the user's setting, the power switch of the target device is turned on; otherwise, the power switch of the target device is turned off. | 2014-06-26 |
20140181563 | SYSTEM AND METHOD FOR DETERMINATION OF LATENCY TOLERANCE - Particular embodiments described herein can offer a method that includes determining that a first reported latency tolerance associated with at least one first device has not been received, and causing determination of a platform latency tolerance based, at least in part, on a first predefined latency tolerance, which is to serve as a substitute for the first reported latency tolerance. | 2014-06-26 |
20140181564 | DETERMINING REDUNDANCY IN A POWER DISTRIBUTION SYSTEM - A computer-implemented method identifies the path of a first power circuit to a first power supply that is connected to supply power to an electronic device, and identifies the path of a second power circuit to a second power supply that is connected to supply power to the electronic device. The method then compares the path of the first power distribution circuit with the path of the second power distribution circuit to determine a measure of redundancy in the first and second distribution paths. A measure of redundancy may then be output to a user. | 2014-06-26 |
20140181565 | STORAGE APPARATUS - A storage apparatus writes data to a storage drive or reads data from a storage drive in response to an I/O request sent from a server. The storage apparatus includes a plurality of AC-DC power supplies supplying the storage drive with drive power is provided with a plurality of power supply paths provided for the respective AC-DC power supplies. A plurality of gate units are provided to the respective power supply paths and configured to stop supplying drive power to the storage drive through the corresponding power supply path when detecting voltage abnormality in the drive power supplied from the AC-DC power supply to the storage drive. The power supply paths allow each of the storage drives belonging to a same RAID group to receive the supply of the drive power from the AC-DC power supplies through different power supply paths, respectively. | 2014-06-26 |
20140181566 | INFORMATION PROCESSING APPARATUS AND POWER SUPPLY CONTROL CIRCUIT - Provided is an information processing apparatus including: a power supply control portion that performs control of a power supply; a detection signal emitting portion that, when a connection of an external power source is detected in an operation stand-by state in which power consumption is suppressed and an operation is on stand-by, emits a detection signal only for a certain time period, in accordance with the detection; and a power supply portion that supplies power to the power supply control portion based on the detection signal emitted by the detection signal emitting portion and also stops the power supply to the power supply control portion after a certain time period elapses from the connection in the operation stand-by state. | 2014-06-26 |
20140181567 | COMMAND CONTROL CIRCUIT FOR MEMORY DEVICE AND MEMORY DEVICE INCLUDING THE SAME - Exemplary embodiments disclose a command control circuit including a command decoder configured to generate an internal command signal using a chip select (CS) signal and a command signal, and a CS gating logic configured to provide the CS signal to the command decoder, wherein the CS gating logic is further configured to provide the CS signal to the command decoder in response to a clock enable (CKE) signal being at a first level, and block the CS signal from the command decoder in response to the CKE signal being at a second level. | 2014-06-26 |
20140181568 | INTERFACE FOR CONTROLLING THE PHASE ALIGNMENT OF CLOCK SIGNALS FOR A RECIPIENT DEVICE - Interface circuitry transmitting transactions between an initiator and a recipient includes: a clock input receiving a clock signal; a transaction input receiving transactions; clock outputs for outputting the clock signal; transaction outputs outputting the transactions to the recipient; and synchronising circuits clocked by the clock signal and transmitting the transactions to the transaction output in response to the clock signal. A controllable delay circuit is provided between the clock input and the synchronising circuits. A further synchronising circuit configured to provide a similar delay. Phase detection circuitry is arranged to detect alignment of the received clock signals. Calibration control circuitry adjusts a delay of the controllable delay circuit during calibration until the phase detection circuitry detects alignment. The calibration control circuitry controls the controllable delay circuit to generate a delay to the clock signal in dependence upon the delay that generated the alignment detected during calibration. | 2014-06-26 |
20140181569 | SYSTEMS AND METHODS FOR SYNCHRONIZING OPERATIONS AMONG A PLURALITY OF INDEPENDENTLY CLOCKED DIGITAL DATA PROCESSING DEVICES WITHOUT A VOLTAGE CONTROLLED CRYSTAL OSCILLATOR - Example systems, apparatus, and methods receive audio information including a plurality of frames from a source device, wherein each frame of the plurality of frames includes one or more audio samples and a time stamp indicating when to play the one or more audio samples of the respective frame. In an example, the time stamp is updated for each of the plurality of frames using a time differential value determined between clock information received from the source device and clock information associated with the device. The updated time stamp is stored for each of the plurality of frames, and the audio information is output based on the plurality of frames and associated updated time stamps. A number of samples per frame to be output is adjusted based on a comparison between the updated time stamp for the frame and a predicted time value for play back of the frame. | 2014-06-26 |
20140181570 | SIGNAL PROCESSING CIRCUITRY WITH FRONTEND AND BACKEND CIRCUITRY CONTROLLED BY SEPARATE CLOCKS - An apparatus comprises read channel circuitry and associated signal processing circuitry comprising frontend processing circuitry and backend processing circuitry. The frontend processing circuitry comprises a loop detector and equalizer configured to determine an equalized read channel signal from a read channel signal and a decoding module configured to apply verification and scrambling processing on a decoded read channel signal. The backend processing circuitry comprises a backend detector, an interleaver, a backend decoder, and a de-interleaver configured to perform an iterative decoding process on the equalized read channel signal to determine the decoded read channel signal. The frontend processing circuitry is controlled by a first clock having an associated first clock rate and the backend processing circuitry is controlled by a selected one of the first clock and a second clock having an associated second clock rate determined at least in part by the first clock rate and a maximum clock rate. | 2014-06-26 |
20140181571 | MANAGING FAST TO SLOW LINKS IN A BUS FABRIC - Systems and methods for managing fast to slow links in a bus fabric. A pair of link interface units connect agents with a clock mismatch. Each link interface unit includes an asynchronous FIFO for storing transactions that are sent over the clock domain crossing. When the command for a new transaction is ready to be sent while data for the previous transaction is still being sent, the link interface unit prevents the last data beat of the previous transaction from being sent. Instead, after a delay of one or more clock cycles, the last data beat overlaps with the command of the new transaction. | 2014-06-26 |
20140181572 | Provide an Appliance Like Test Vehicle for IT Disaster Recovery - A high availability/disaster recovery appliance test vehicle that contains a preconfigured high availability/disaster recovery solution for quick implementation at a test environment. The hardware and software components may be preconfigured with test applications and data and all the necessary networking, SAN and operating system requirements. This single shippable rack can be used to certify a multi site high availability/disaster recovery architecture that supports both local and site failover and site to site data replication. The unit is plug and play which reduces the effort required to begin the evaluation and reduces the number of IT teams that need to be involved. An apparatus and method for implementing the above high availability/disaster recovery vehicle are provided. | 2014-06-26 |
20140181573 | FABRIC DISCOVERY FOR A CLUSTER OF NODES - Implementations of discovery functionalities in accordance with the present invention are characterized by being exceptionally minimalistic. A primary reason and benefit for such minimalistic implementations relate to these discovery functionalities being implemented via a management processor and associated resources of a system on a chip (SoC) unit as opposed to them being implemented on data processing components of a cluster of nodes (i.e., central processing core components). By focusing on such a minimalist implementation, embodiments of the present invention allow discovery functionalities to be implemented on a relatively low-cost low-power management processor coupled to processing cores that provide for data serving functionality in the cluster of nodes. | 2014-06-26 |
20140181574 | ERROR CORRECTION AND RECOVERY IN CHAINED MEMORY ARCHITECTURES - Electronic apparatus, systems, and methods to construct and operate the electronic apparatus and/or systems include a memory unit configured to receive data flow from two directions. The memory unit can be configured serially in a chain with other memory units. The chain can include an error check and correcting unit (ECC). Additional apparatus, systems, and methods are disclosed. | 2014-06-26 |
20140181575 | DATA ERROR DETECTION AND CORRECTION USING HASH VALUES - The subject disclosure is directed towards a data storage service that uses hash values, such as substantially collision-free hash values, to maintain data integrity. These hash values are persisted in the form of mappings corresponding to data blocks in one or more data stores. If a data error is detected, these mappings allow the data storage service to search the one or more data stores for data blocks having matching hash values. If a data block is found that corresponds to a hash value for a corrupted or lost data block, the data storage service uses that data block to repair the corrupted or lost data block. | 2014-06-26 |
20140181576 | MEMORY ALLOCATION FOR VIRTUAL MACHINES USING MEMORY MAP - Apparatuses and methods associated with memory allocations for virtual machines are disclosed. In embodiments, an apparatus may include a processor; a plurality of memory modules; and a memory controller configured to provide a layout of the memory modules. The apparatus may further include a VMM configured to be operated by the processor to manage execution of a VM by the processor including selective allocation of the memory modules to the VM using the layout of the memory modules provided to the VMM by the memory controller. Other embodiments may be described and claimed. | 2014-06-26 |
20140181577 | SYSTEMATIC MITIGATION OF MEMORY ERRORS - A system and method for mitigating memory errors in a computer system. Faulty memory is identified and tested by a memory manager of an operating system. The memory manager may perform diagnostic tests while the operating system is executing on the computer system. Regions of memory that are being used by software components of the computer system may also be tested. The memory manager maintains a stored information about faulty memory regions. Regions are added to the stored information when they are determined to be faulty by a diagnostic test tool. Memory regions are allocated to software components by the memory manager after checking the stored information about faulty memory regions. This ensures a faulty memory region is never allocated to a software component of the computer system. | 2014-06-26 |
20140181578 | METHOD AND APPARATUS FOR SLICE PARTIAL REBUILDING IN A DISPERSED STORAGE NETWORK - A dispersed storage system includes a plurality of storage units that each include a partial rebuild grid module. The partial rebuild grid module includes partial rebuilding functionality to reconstruct one of a plurality of encoded data slices wherein the plurality of encoded data slices are generated from a data segment based on an error encoding dispersal function. In the partial rebuilding process, a data slice is rebuilt by combining in any order slice partials generated from at least a threshold number T of the plurality of data slices. | 2014-06-26 |
20140181579 | SYSTEMS AND METHODS FOR ON-LINE BACKUP AND DISASTER RECOVERY - A data recovery system includes a plurality of customer computers to be backed-up, each customer computer running a client software to communicate back-up data files; a system management platform coupled to the client software over the Internet, the system management platform receiving inputs from a web user portal to control operations of the client software and the system management platform to back up the customer computer; and two or more data storage silos, each including: a plurality of storage directors communicating with the client software; and a clustered data storage array. | 2014-06-26 |
20140181580 | SPECULATIVE NON-FAULTING LOADS AND GATHERS - According to one embodiment, a processor includes an instruction decoder to decode an instruction to read a plurality of data elements from memory, the instruction having a first operand specifying a storage location, a second operand specifying a bitmask having one or more bits, each bit corresponding to one of the data elements, and a third operand specifying a memory address storing a plurality of data elements. The processor further includes an execution unit coupled to the instruction decoder, in response to the instruction, to read one or more data elements speculatively, based on the bitmask specified by the second operand, from a memory location based on the memory address indicated by the third operand, and to store the one or more data elements in the storage location indicated by the first operand. | 2014-06-26 |
20140181581 | ERROR RECOVERY WITHIN INTEGRATED CIRCUIT - An integrated circuit includes one or more portions having error detection and error correction circuits and which is operated with operating parameters giving finite non-zero error rate as well as one or more portions formed and operated to provide a zero error rate. | 2014-06-26 |
20140181582 | AUTOMATIC RETRY FOR POSITION IDENTIFIERS - Applications performance for applications that access connections may be improved by providing a method of automatically retrying failed connections. A method for executing a communication interface may include receiving a retry timer length, receiving an indication that an application group is executing, opening position identifiers for the application group, failing to open at least one position identifier, and automatically retrying opening the position identifier after the retry timer length. | 2014-06-26 |
20140181583 | SERVER AND METHOD FOR PROTECTING AGAINST FAN FAILURE THEREIN - A method for protecting against fan failure in a server uses a storage unit and a plurality of fans in the server. The method includes the following steps. A rotation speed of each of the plurality of fans is detected. A continuous working time period of each fan is timed. The rotation speed reading and the continuous working time period reading of each fan is compared with predefined rotation speed values and predefined continuous working time periods stored in the storage unit. The results of comparisons are made. A countdown is started when any of the results of comparison falls into one of predefined failure conditions for the fans. Unless a renew or other countdown-amending signal is received, the server is counted down to zero and then shut down. A server equipped to be able to carry out the protecting method is also provided. | 2014-06-26 |
20140181584 | DEBUGGING SYSTEM OF INTEGRATED CIRCUIT AND DEBUGGING METHOD THEREOF - A debugging method of an integrated circuit is disclosed. The debugging method is applied to an integrated circuit and a debugging system. The debugging method includes the following steps: selecting an error event of the integrated circuit; selecting a plurality of observing signals of the integrated circuit; storing values of the observing signals at a time point and embedding values of the observing signals in an observing packet to output the observing packet when the error event happens at the time point; outputting the observing packet and a plurality of data packets of the integrated circuit sequentially according to a priority value table; encoding the observing packet to output a plurality of output signals; and outputting the output signals via a transmission interface of the debugging system. | 2014-06-26 |
20140181585 | REAL USAGE MODEL FOR SOLID-STATE DRIVE - An embodiment is a technique to generate failure mode information for solid-state drive (SSD) in real environment. An environmental acquisition module acquires environmental information from an environmental sensor. A learning and update module generates an environmental profile based on the acquired environmental information. A failure acquisition module associates failure information from an SSD controller that controls an SSD with the environmental profile. An operation analyzer analyzes the associated failure information using pre-determined information provided by a database to generate failure mode information. A decision module decides if the failure mode information is valid. | 2014-06-26 |
20140181586 | METHOD AND APPARATUS FOR PERFORMING HOST BASED DIAGNOSTICS USING A SERVICE PROCESSOR - A method for performing a set of diagnostics on a host system using a service processor. The method includes recognizing a power-on event, and in response checking a diagnostic flag, where the diagnostic flag indicates the set of diagnostics to be performed. Retrieving, from internal storage of the service processor, a disk image including the set of diagnostics to be performed. Mounting, using a disk image reader, the disk image to obtain a mounted disk image. Making the mounted disk image accessible as a device using a virtual device driver. Mounting, using a connection between the service processor and the host system, the device within the host system, and performing the set of diagnostics on the host system. | 2014-06-26 |
20140181587 | Hardware Based Redundant Multi-Threading Inside a GPU for Improved Reliability - A system and method for verifying computation output using computer hardware are provided. Instances of computation are generated and processed on hardware-based processors. As instances of computation are processed, each instance of computation receives a load accessible to other instances of computation. Instances of output are generated by processing the instances of computation. The instances of output are verified against each other in a hardware based processor to ensure accuracy of the output. | 2014-06-26 |
20140181588 | SEMICONDUCTOR MEMORY APPARATUS AND OPERATING METHOD THEREOF - A semiconductor memory apparatus includes: a user setting unit configured to generate test data and a delay control signal in response to an external command and an external address; a delay locked loop (DLL) clock generation unit including a replica configured to have a delay time controlled in response to the delay control signal; and a data output unit configured to output the test data in response to a DLL clock signal outputted from the DLL clock generation unit. | 2014-06-26 |
20140181589 | MEMORY CONTROLLER AND OPERATING METHOD OF MEMORY CONTROLLER - A method of operating a memory controller to control a memory device includes reading a read vector from the memory device and correcting one or more errors in the read vector, where a power consumed at the correcting is varied according to the number of errors in the read vector. | 2014-06-26 |
20140181590 | AUTOMATED END-TO-END TESTING VIA MULTIPLE TEST TOOLS - The development of automated tests that span end-to-end business processes, such as may be executed in part by each of multiple Enterprise Resource Planning systems, is a very complex activity. Beside expert know-how of various tools, such end-to-end business process testing requires various test automation tools to cover complex business processes to provide automated tests. Various embodiments herein are built on an approach for building and connecting automated end-to-end tests that combines test scripts from multiple test tools. These embodiments include functionality to assemble test scripts from multiple test tools into a single, composite test script that allows passing of information between the test scripts during performance of an end-to-end automated process test. These and other embodiments are illustrated and described herein. | 2014-06-26 |
20140181591 | TEST STRATEGY FOR PROFILE-GUIDED CODE EXECUTION OPTIMIZERS - Systems, methods and computer program products are described herein for testing a system that is designed to optimize the execution of code within an application or other computer program based on profile data collected during the execution of such code. The embodiments described herein utilize what is referred to as a “profile data mutator” to mutate or modify the profile data between the point when it is collected and the point when it is used to apply an optimization. By mutating the profile data at this point, testing of a system for optimized code execution can be significantly more thorough. Furthermore, such profile data mutation leads to a more scalable and efficient testing technique for profile-guided systems for optimized code execution. | 2014-06-26 |
20140181592 | DIAGNOSTICS OF DECLARATIVE SOURCE ELEMENTS - A method for diagnosing declarative source elements in an application, such as in debugging markup source elements or visual elements in an application, is disclosed. Diagnosis information is associated with an object source of a visual element. The diagnosis information is provided for the visual element during the runtime of the application. | 2014-06-26 |
20140181593 | CORRELATION OF SOURCE CODE WITH SYSTEM DUMP INFORMATION - The present arrangements relate to analyzing a software error. At least one dump file created in response to a crash of software executing on a processing system can be accessed. Based on the dump file, a base version of at least one software module that was loaded when the crash occurred can be identified. Based on the dump file, maintenance that has been applied to the at least one software module also can be identified. A report recommending new corrective maintenance to be applied to the at least one software module can be generated. | 2014-06-26 |
20140181594 | Signature-Based Store Checking Buffer - A system and method for optimizing redundant output verification, are provided. A hardware-based store fingerprint buffer receives multiple instances of output from multiple instances of computation. The store fingerprint buffer generates a signature from the content included in the multiple instances of output. When a barrier is reached, the store fingerprint buffer uses the signature to verify the content is error-free. | 2014-06-26 |
20140181595 | ESTIMATING LIFESPAN OF SOLID-STATE DRIVE USING REAL USAGE MODEL - An embodiment is a technique to estimate lifespan of a solid-state drive (SSD). Real environmental information from an environmental processor is received. The real environmental information corresponds to an environment of a solid-state drive (SSD). The lifespan of the SSD is estimated using the real environmental information and an internal data usage model. The estimated lifespan is made available for retrieval. | 2014-06-26 |
20140181596 | WEAR-OUT EQUALIZATION TECHNIQUES FOR MULTIPLE FUNCTIONAL UNITS - Wear-out equalization techniques for multiple functional hardware units are disclosed. An integrated circuit includes a power control unit (PCU) configured to monitor indicators of wear-out incurred by multiple functional hardware units of the integrated circuit. The PCU calculates cumulative wear-out metrics of the functional hardware units based on the monitored indicators and performs an equalization action to equalize the cumulative wear-out metrics of the functional hardware units. | 2014-06-26 |
20140181597 | SYSTEMS AND METHODS FOR DEBUGGING MODEL BASED MESSAGE SEQUENCES - A system for simplifying message sequences is disclosed. The system includes a shrink component and a message simplification component. The shrink component is configured to receive a failure inducing message sequence and to provide a shrunk sequence based on the failure inducing message sequence. The shrunk sequence has less or equal number of messages than the failure inducing message sequence. The message simplification component is configured to receive the shrunk sequence and to simplify messages within the shrunk sequence to generate a simplified message sequence including debugging hints. | 2014-06-26 |
20140181598 | INFORMATION PROCESSING METHOD, INFORMATION PROCESSING DEVICE AND RECORDING MEDIUM - An information processing method includes: obtaining, when an operation control in an automatic operation process used for automatically executing an operation control for a plurality of computers is executed, when an error is detected in a first computer among the plurality of computers is executed, first information that indicates the role of the first computer and second information that indicates the configuration of a system to which the first computer belongs; and obtaining case data including a condition that matches or is similar to a condition that includes at least the contents of the operation control, the contents of the error, the role of the first computer indicated by the first information and the configuration of the system to which the first computer belongs which is indicated in the second information. | 2014-06-26 |
20140181599 | TASK SERVER AND METHOD FOR ALLOCATING TASKS - At least two task servers connect to a database server. The database server includes a task list. A task server accesses the task list to search a task which is an earliest presenting task. When the searched task has not been executed, the task server marks the searched task with a serial number of the task. The task server records an execution start time of the searched task. When a time of executing the searched task is more than a predefined time, the task server prompts a user to deal with an error of the task server. | 2014-06-26 |
20140181600 | INTELLIGENTLY MONITORING AND DISPATCHING INFORMATION TECHNOLOGY SERVICE ALERTS - In a method for intelligently monitoring and dispatching an Information Technology (IT) service alert, a computer receives a service error alert and classifies the service error alert. The computer assigns the service error alert, based on the service error alert class. The computer monitors the progress of the resolution of the service error alert. | 2014-06-26 |
20140181601 | METHOD OF TESTING MULTIPLE DATA PACKET SIGNAL TRANSCEIVERS CONCURRENTLY - A method of testing, such as for a bit error rate (BER), of multiple data packet signal transceivers during which a tester and the data packet signal transceivers exchange sequences of test data packets and summary data packets. The tester provides the test data packets which contain respective pluralities of data bits with respective predetermined bit patterns. Responsive thereto, the data packet signal transceivers provide the summary data packets which contain respective summary data indicative of the number of data bits with the respective predetermined bit patterns that are correctly received by corresponding ones of the data packet signal transceivers. | 2014-06-26 |
20140181602 | MODELING MEMORY ARRAYS FOR TEST PATTERN ANALYSIS - A method includes receiving in a computing apparatus a model of an integrated circuit device including a memory array. The memory array is modeled as a plurality of device primitives. A test pattern analysis of the memory array is performed using the model in the computing apparatus. A system includes a memory array modeling unit and a test pattern analysis unit. The memory array modeling unit is operable to generate a model of an integrated circuit device including an memory array. The memory array is modeled as a plurality of device primitives. The test pattern analysis unit is operable to performing a test pattern analysis of the memory array using the model in the computing apparatus. | 2014-06-26 |
20140181603 | METHOD AND APPARATUS FOR TUNING SCAN CAPTURE PHASE ACTIVITY FACTOR - A method and apparatus for tuning the activity factor of a scan capture phase is described. In one example an activity factor is determined for a die to be tested. The die may be isolated or part of a wafer. A structural scan test is modified to run with an activity factor based on the determined activity factor. The modified structural scan test is run and the die is characterized based on the test. | 2014-06-26 |
20140181604 | CHANNEL CONTROL CIRCUIT AND SEMICONDUCTOR DEVICE HAVING THE SAME - A channel control circuit having a plurality of channels according to an embodiment of the present invention includes: a channel control signal generating block configured to generate a channel control signal capable of selectively controlling an activated state of a channel in response to a combination of a first test mode signal and a second test mode signal; a scan buffer control signal generating block configured to generate a scan buffer control signal in response to the first test mode signal and a scan signal; a clock buffer control signal generating block configured to generate a clock buffer control signal in response to the channel control signal and the scan buffer control signal; and a clock input buffer configured to generate a clock output signal, which is used as an internal clock of a semiconductor device, in response to the clock buffer control signal. | 2014-06-26 |
20140181605 | ASYNCHRONOUS PROGRAMMABLE JTAG-BASED INTERFACE TO DEBUG ANY SYSTEM-ON-CHIP STATES, POWER MODES, RESETS, CLOCKS, AND COMPLEX DIGITAL LOGIC - An asynchronous debug interface is disclosed that allows TAG agents, JTAG-based debuggers, firmware, and software to debug, access, and override any functional registers, interrupt registers, power/clock gating enables, etc., of core logic being tested. The asynchronous debug interface works at a wide range of clock frequencies and allows read and write transactions to take place on a side channel, as well as within the on chip processor fabric without switching into a debug or test mode. The asynchronous debug interface works with two-wire and four-wire JTAG controller configurations, and is compliant with IEEE standards, such as 1149.1, 1149.7, etc., and provides an efficient and seamless way to debug complex system-on-chip states and system-on-chip products. | 2014-06-26 |
20140181606 | DIRECT SCAN ACCESS JTAG - The present disclosure describes novel methods and apparatuses for directly accessing JTAG Tap domains that exist in a scan path of many serially connected JTAG Tap domains. Direct scan access to a selected Tap domain by a JTAG controller is achieved using auxiliary digital or analog terminals associated with the Tap domain and connected to the JTAG controller. During direct scan access, the auxiliary digital or analog terminals serve as serial data input and serial data output paths between the selected Tap domain and the JTAG controller. | 2014-06-26 |
20140181607 | LOCK STATE MACHINE OPERATIONS UPON STP DATA CAPTURES AND SHIFTS - Operating a state machine includes enabling operation of the state machine upon receiving a signal indicating a change from operation of a test access port to a scan test port. The process maintains the state machine in an IDLE 1 state while receiving a scan test port capture signal and transitions the state machine to an IDLE 2 state when receiving a scan test port shift signal. The process then transitions the state machine to a SEQUENCE 1 state, then to a SEQUENCE 2 state, and then to a SEQUENCE 3 state when receiving sequential scan test port capture signals. The state machine then transitions to an UNLOCK TAP state and then back to the IDLE 1 state when receiving sequential scan test port shift signals on the test mode select/capture select lead. | 2014-06-26 |
20140181608 | TAP AND LINKING MODULE FOR SCAN ACCESS OF MULTIPLE CORES WITH IEEE 1149.1 TEST ACCESS PORTS - An architecture for testing a plurality of circuits on an integrated circuit is described. The architecture includes a TAP Linking Module located between test pins on the integrated circuit and 1149.1 Test Access Ports (TAP) of the plurality of circuits to be tested. The TAP Linking Module operates in response to 1149.1 scan operations from a tester connected to the test pins to selectively switch between 1149.1 TAPs to enable test access between the tester and plurality of circuits. The TAP Linking Module's 1149.1 TAP switching operation is based upon augmenting 1149.1 instruction patterns to affix an additional bit or bits of information which is used by the TAP Linking Module for performing the TAP switching operation. | 2014-06-26 |
20140181609 | SEMICONDUCTOR TEST SYSTEM AND METHOD - A test controller applies test stimulus signals to the input pads of plural die on a wafer in parallel. The test controller also applies encoded test response signals to the output pads of the plural die in parallel. The encoded test response signals are decoded on the die and compared to core test response signals produced from applying the test stimulus signals to core circuits on the die. The comparison produces pass/fail signals that are loaded in to scan cells of an IEEE 1149.1 scan path. The pass/fail signals then may be scanned out of the die to determine the results of the test. | 2014-06-26 |
20140181610 | BULK DATA TRANSFER - This disclosure relates to network data communication. Some embodiments include initiating a network connection between an original source and an ultimate destination, transmitting a block of data from the original source to the ultimate destination on the network, requesting retransmission of lost blocks from the ultimate destination to the source and retransmitting the lost blocks from source to the ultimate destination. These embodiments further include measuring round-trip time of a retransmit request, the round-trip time measured from a time of transmission of a retransmit request from the ultimate destination to a time of reception at the ultimate destination after retransmission from the original source and setting the round-trip time as a minimum retransmission request time for the network connection, wherein the round-trip time includes latencies of the network connection and in data processes at the original source and at the ultimate destination. | 2014-06-26 |