26th week of 2019 patent applcation highlights part 68 |
Patent application number | Title | Published |
20190198330 | Passivation of Nonlinear Optical Crystals | 2019-06-27 |
20190198331 | SUBSTRATE PROCESSING APPARATUS, METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND NON-TRANSISTORY COMPUTER-READABLE RECORDING MEDIUM | 2019-06-27 |
20190198332 | METHOD OF PROCESSING WORKPIECE | 2019-06-27 |
20190198333 | METHODS OF PROCESSING SEMICONDUCTOR DEVICE STRUCTURES AND RELATED SYSTEMS | 2019-06-27 |
20190198334 | METHOD OF FABRICATING A METAL LAYER | 2019-06-27 |
20190198335 | SUBSTRATE PROCESSING METHOD | 2019-06-27 |
20190198336 | ETCHING METHOD | 2019-06-27 |
20190198337 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD | 2019-06-27 |
20190198338 | UNIFORM EUV PHOTORESIST PATTERNING UTILIZING PULSED PLASMA PROCESS | 2019-06-27 |
20190198339 | METHODS OF FABRICATING INTEGRATED CIRCUIT DEVICES | 2019-06-27 |
20190198340 | SEMICONDUCTOR MANUFACTURING METHODS FOR PATTERNING LINE PATTERNS TO HAVE REDUCED LENGTH VARIATION | 2019-06-27 |
20190198341 | COMPOSITION FOR FORMING ORGANIC FILM, SUBSTRATE FOR MANUFACTURING SEMICONDUCTOR DEVICE, METHOD FOR FORMING ORGANIC FILM, AND PATTERNING PROCESS | 2019-06-27 |
20190198342 | Methods of Forming Micropatterns and Substrate Processing Apparatus | 2019-06-27 |
20190198343 | SELF-ALIGNED PLANARIZATION OF LOW-K DIELECTRICS AND METHOD FOR PRODUCING THE SAME | 2019-06-27 |
20190198344 | ETCHING SOLUTION, ETCHING METHOD, AND METHOD FOR MANUFACTURING AN ELECTRONIC COMPONENT | 2019-06-27 |
20190198345 | ATOMIC LAYER ETCHING USING A COMBINATION OF PLASMA AND VAPOR TREATMENTS | 2019-06-27 |
20190198346 | METHOD FOR CONTROLLING THE AMOUNT OF RADIATION HAVING A PREDETERMINED WAVELENGTH TO BE ABSORBED BY A STRUCTURE DISPOSED ON A SEMICONDUCTOR | 2019-06-27 |
20190198347 | STRUCTURES, METHODS AND APPLICATIONS FOR ELECTRICAL PULSE ANNEAL PROCESSES | 2019-06-27 |
20190198348 | MANUFACTURING METHOD OF ELECTRODE PATTERN, THIN FILM TRANSISTOR AND MANUFACTURING METHOD THEREOF, AND DISPLAY PANEL | 2019-06-27 |
20190198349 | ETCHING METHOD AND ETCHING APPARATUS | 2019-06-27 |
20190198350 | METHOD OF PROCESSING SUBSTRATE | 2019-06-27 |
20190198351 | PACKAGE STRUCTURE AND METHOD THEREOF | 2019-06-27 |
20190198352 | SEMICONDUCTOR PACKAGE WITH FILLER PARTICLES IN A MOLD COMPOUND | 2019-06-27 |
20190198353 | SWITCH-MODE CONVERTER MODULE | 2019-06-27 |
20190198354 | METHODS OF FABRICATING SEMICONDUCTOR PACKAGES | 2019-06-27 |
20190198355 | Method of Manufacturing a Package Having a Power Semiconductor Chip | 2019-06-27 |
20190198356 | SUBSTRATE PROCESSING DEVICE | 2019-06-27 |
20190198357 | WORKPIECE PROCESSING APPARATUS | 2019-06-27 |
20190198358 | ENVIRONMENT MAINTAINING SYSTEM AND METHOD FOR PRECISION PRODUCTION | 2019-06-27 |
20190198359 | SUBSTRATE PROCESSING APPARATUS AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE | 2019-06-27 |
20190198360 | DEVICE AND METHOD FOR TURNING CELL OVER | 2019-06-27 |
20190198361 | INTEGRATED CIRCUIT CONTROLLED EJECTION SYSTEM (ICCES) FOR MASSIVELY PARALLEL INTEGRATED CIRCUIT ASSEMBLY (MPICA) | 2019-06-27 |
20190198362 | METHOD FOR PREFIXING OF SUBSTRATES | 2019-06-27 |
20190198363 | SUBSTRATE PROCESSING DEVICE | 2019-06-27 |
20190198364 | EXCIMER LASER ANNEALING APPARATUS | 2019-06-27 |
20190198365 | METHOD AND SYSTEM FOR DUAL STRETCHING OF WAFERS FOR ISOLATED SEGMENTED CHIP SCALE PACKAGES | 2019-06-27 |
20190198366 | SEMICONDUCTOR PACKAGING APPARATUS AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE USING THE SAME | 2019-06-27 |
20190198367 | HIGH PRESSURE WAFER PROCESSING SYSTEMS AND RELATED METHODS | 2019-06-27 |
20190198368 | WAFER PROCESSING SYSTEMS INCLUDING MULTI-POSITION BATCH LOAD LOCK APPARATUS WITH TEMPERATURE CONTROL CAPABILITY | 2019-06-27 |
20190198369 | SUBSTRATE PROCESSING APPARATUS AND METHOD OF OPERATING SUBSTRATE PROCESSING APPARATUS | 2019-06-27 |
20190198370 | Article Storage Facility | 2019-06-27 |
20190198371 | METHOD AND DEVICE FOR ALIGNMENT OF SUBSTRATES | 2019-06-27 |
20190198372 | SYSTEM FOR DYNAMICALLY COMPENSATING POSITION ERRORS OF A SAMPLE | 2019-06-27 |
20190198373 | METHOD FOR CONTROLLING SEMICONDUCTOR PROCESS | 2019-06-27 |
20190198374 | WAFER LEVEL FLAT NO-LEAD SEMICONDUCTOR PACKAGES AND METHODS OF MANUFACTURE | 2019-06-27 |
20190198375 | WAFER LEVEL FLAT NO-LEAD SEMICONDUCTOR PACKAGES AND METHODS OF MANUFACTURE | 2019-06-27 |
20190198376 | WAFER LEVEL FLAT NO-LEAD SEMICONDUCTOR PACKAGES AND METHODS OF MANUFACTURE | 2019-06-27 |
20190198377 | TEMPORARY CARRIER DEBOND INITIATION, AND ASSOCIATED SYSTEMS AND METHODS | 2019-06-27 |
20190198378 | MASK-INTEGRATED SURFACE PROTECTIVE TAPE | 2019-06-27 |
20190198379 | CHUCK TABLE CORRECTION METHOD AND CUTTING APPARATUS | 2019-06-27 |
20190198380 | Integrated Circuit and Method of Forming an Integrated Circuit | 2019-06-27 |
20190198381 | AIR-GAP SPACERS FOR FIELD-EFFECT TRANSISTORS | 2019-06-27 |
20190198382 | SELECTIVE ETCHES FOR REDUCING CONE FORMATION IN SHALLOW TRENCH ISOLATIONS | 2019-06-27 |
20190198383 | DAM LAMINATE ISOLATION SUBSTRATE | 2019-06-27 |
20190198384 | SEMICONDUCTOR DEVICE WITH TWO-PART INSULATION STRUCTURE WITHIN NON-ACTIVE REGION | 2019-06-27 |
20190198385 | Method for transfer of a useful layer | 2019-06-27 |
20190198386 | METHOD FOR MANUFACTURING BONDED SOI WAFER | 2019-06-27 |
20190198387 | SEMICONDUCTOR DEVICE, MANUFACTURING METHOD THEREOF, SOLID-STATE IMAGING DEVICE, AND ELECTRONIC APPARATUS | 2019-06-27 |
20190198388 | METHODS FOR PROCESSING SEMICONDUCTOR DICE AND FABRICATING ASSEMBLIES INCORPORATING SAME | 2019-06-27 |
20190198389 | Methods For Controllable Metal And Barrier-Liner Recess | 2019-06-27 |
20190198390 | REMOVAL METHOD AND PROCESSING METHOD | 2019-06-27 |
20190198391 | Selective Deposition of Metal-Organic Frameworks | 2019-06-27 |
20190198392 | METHODS OF ETCHING A TUNGSTEN LAYER | 2019-06-27 |
20190198393 | FABRICATION OF SELF-ALIGNED GATE CONTACTS AND SOURCE/DRAIN CONTACTS DIRECTLY ABOVE GATE ELECTRODES AND SOURCE/DRAINS | 2019-06-27 |
20190198394 | FABRICATION OF SELF-ALIGNED GATE CONTACTS AND SOURCE/DRAIN CONTACTS DIRECTLY ABOVE GATE ELECTRODES AND SOURCE/DRAINS | 2019-06-27 |
20190198395 | ELECTRICALLY CONDUCTIVE VIA(S) IN A SEMICONDUCTOR SUBSTRATE AND ASSOCIATED PRODUCTION METHOD | 2019-06-27 |
20190198396 | MANUFACTURING PROCESS OF ELEMENT CHIP | 2019-06-27 |
20190198397 | ASSEMBLY FOR 3D CIRCUIT WITH SUPERPOSED TRANSISTOR LEVELS | 2019-06-27 |
20190198398 | SIMPLIFIED BLOCK PATTERNING WITH WET STRIPPABLE HARDMASK FOR HIGH-ENERGY IMPLANTATION | 2019-06-27 |
20190198399 | Vertical FET with Various Gate Lengths by an Oxidation Process | 2019-06-27 |
20190198400 | JUNCTION FORMATION IN THICK-OXIDE AND THIN-OXIDE VERTICAL FETS ON THE SAME CHIP | 2019-06-27 |
20190198401 | METHOD OF MANUFACTURING A CMOS TRANSISTOR | 2019-06-27 |
20190198402 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAME | 2019-06-27 |
20190198403 | OVERLAY ERROR AND PROCESS WINDOW METROLOGY | 2019-06-27 |
20190198404 | METHOD OF INSPECTING SEMICONDUCTOR DEVICE | 2019-06-27 |
20190198405 | STATISTICAL FRAMEWORK FOR TOOL CHAMBER MATCHING IN SEMICONDUCTOR MANUFACTURING PROCESSES | 2019-06-27 |
20190198406 | SUBSTRATE AND PACKAGE MODULE INCLUDING THE SAME | 2019-06-27 |
20190198407 | CAVITY PACKAGES | 2019-06-27 |
20190198408 | DISPLAY PANEL AND DISPLAY APPARATUS | 2019-06-27 |
20190198409 | BONDED STRUCTURES | 2019-06-27 |
20190198410 | SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME | 2019-06-27 |
20190198411 | SEMICONDUCTOR DEVICE | 2019-06-27 |
20190198412 | CHIP ON FILM PACKAGE AND DISPLAY DEVICE INCLUDING THE SAME | 2019-06-27 |
20190198413 | SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF | 2019-06-27 |
20190198414 | S-Contact Thermal Structure with Active Circuitry | 2019-06-27 |
20190198415 | SEMICONDUCTOR PACKAGE AND A METHOD OF MANUFACTURING THE SAME | 2019-06-27 |
20190198416 | MICROELECTRONICS PACKAGE WITH AN INTEGRATED HEAT SPREADER | 2019-06-27 |
20190198417 | CHIP ON FILM PACKAGE | 2019-06-27 |
20190198418 | BORON NITRIDE NANOTUBE ENHANCED ELECTRICAL COMPONENTS | 2019-06-27 |
20190198419 | THERMALLY INSULATING COMPOSITION AND ELECTRONIC DEVICES ASSEMBLED THEREWITH | 2019-06-27 |
20190198420 | ELECTRONIC ASSEMBLY WITH A DIRECT BONDED COPPER SUBSTRATE | 2019-06-27 |
20190198421 | HEAT RADIATING PLATE-LINED CERAMICS SUBSTRATE | 2019-06-27 |
20190198422 | SEMICONDUCTOR APPARATUS AND MANUFACTURING METHOD THEREOF | 2019-06-27 |
20190198423 | DEVICE MODULE EMBEDDED WITH SWITCH CHIP AND MANUFACTURING METHOD THEREOF | 2019-06-27 |
20190198424 | POWER MODULE WITH BUILT-IN POWER DEVICE AND DOUBLE-SIDED HEAT DISSIPATION AND MANUFACTURING METHOD THEREOF | 2019-06-27 |
20190198425 | THERMAL INTERFACE MATERIAL STRUCTURES INCLUDING PROTRUDING SURFACE FEATURES TO REDUCE THERMAL INTERFACE MATERIAL MIGRATION | 2019-06-27 |
20190198426 | SEMICONDUCTOR DEVICE HAVING A STRUCTURE FOR INSULATING LAYER UNDER METAL LINE | 2019-06-27 |
20190198427 | THROUGH ELECTRODE SUBSTRATE AND SEMICONDUCTOR DEVICE | 2019-06-27 |
20190198428 | POWER SEMICONDUCTOR MODULE DEVICE AND POWER SEMICONDUCTOR MODULE MANUFACTURING METHOD | 2019-06-27 |
20190198429 | FAN-OUT SEMICONDUCTOR PACKAGE | 2019-06-27 |