26th week of 2011 patent applcation highlights part 72 |
Patent application number | Title | Published |
20110161661 | ENHANCED AUTHORIZATION PROCESS USING DIGITAL SIGNATURES - A method is provided for enhancing security of a communication session between first and second endpoints which employs a key management protocol. The method includes sending a first message to a first end point over a communications network requesting a secure communication session therewith. The message includes an identity of a second end point requesting the authenticated communication session. A digital certificate is received from the first endpoint over the communications network. The digital certificate is issued by a certifying source verifying information contained in the digital certificate. The digital certificate includes a plurality of fields, one or more of which are transformed in accordance with a transformation algorithm. A reverse transform is applied to the one or more transformed fields to obtain the one or more fields. The digital certificate is validated and a second message is sent to the first endpoint indicating that validation is complete. | 2011-06-30 |
20110161662 | SYSTEM AND METHOD FOR UPDATING DIGITAL CERTIFICATE AUTOMATICALLY - A system and method for automatically updating a digital certificate prompts a user of a client computer to update a current digital certificate if a period of validity of the current digital certificate elapses or is about to elapse, and creates a new digital certificate if the current digital certificate needs to be updated. The system and method further deletes the current digital certificate, and loads the new digital certificate into a storage system of the client computer. | 2011-06-30 |
20110161663 | INTELLIGENT CACHING FOR OCSP SERVICE OPTIMIZATION - An online certificate status checking protocol (OCSP) system is provided for use with a first device, an end device and a certificate authority. The first device can provide a certificate. The end device can provide an OCSP request based on the certificate and process an OCSP response. The certificate authority can provide a CRL update. The certificate has a validity period. The OCSP system includes an OCSP responder, and OCSP proxy and a cache. The OCSP responder can provide the OCSP response. The OCSP proxy can receive the OCSP request from the end device, can send the OCSP request to the OCSP responder, can receive the OCSP response from the OCSP responder and can send the OCSP response to the end device. The cache can store information based on the OCSP response. The OCSP proxy can further store, in the cache, information based on the OCSP response and can send a proactive OCSP request to the OCSP responder based on a predetermined policy. The OCSP responder can further send a proactive OCSP response to the OCSP proxy in response to the proactive OCSP request. The OCSP proxy can further update the information in the cache based on the proactive OCSP response. The OCSP proxy can additionally provide, using the updated information in the cache, a second OCSP response to the end device in response to a subsequent request from the end device related to information of the certificate. | 2011-06-30 |
20110161664 | MEANS OF MITIGATING DENIAL OF SERVICE ATTACKS ON IP FRAGMENTATION IN HIGH PERFORMANCE IPSEC GATEWAYS - Embodiments of the invention reduce the probability of success of a DOS attack on a node receiving packets by decreasing the probability of random collisions of packets sent by a malicious user with those sent by honest users. The probability of random collisions may be reduced in one class of embodiments of the invention by supplementing the identification field of the IP header of each transmitted packet with at least one bit from another field of the header. The probability of random collisions may be reduced in another class of embodiments of the invention by ensuring that packets sent from a transmitting IPsec node to a receiving IPsec node are not fragmented. | 2011-06-30 |
20110161665 | METHOD AND SYSTEM FOR RESOLVING CONFLICTS BETWEEN IPSEC AND IPV6 NEIGHBOR SOLICITATION - A method of enabling host devices having an IPsec policy to communicate with one another via an IPv6 communication network, which includes the following steps: extracting a Media Access Control identifier (MAC ID) for a target host from a security policy for an IPv6 address for the target host; searching for the MAC ID of the target host in an Address Resolution Protocol (ARP) table on a source host; upon locating the MAC ID of the target host, creating a temporal neighbor cache entry in a neighbor cache table for the target host; and enabling a security association between the source host and the target host based on the temporal neighbor entry in the neighbor cache table, which allows IPv6 communications to be exchanged between the target host and the source host. | 2011-06-30 |
20110161666 | DIGITAL CONTENT RETRIEVAL UTILIZING DISPERSED STORAGE - A method begins by a processing module obtaining a unique retrieval matrix based on an identity of the playback device and sending a request for retrieval of a set of encoded broadcast data slices to a dispersed storage network (DSN) memory, wherein the request includes the unique retrieval matrix and identity of the set of encoded broadcast data slices. The method continues with the processing module receiving a subset of the set of encoded broadcast data slices from the DSN memory, wherein the subset of the set of encoded broadcast data slices is based on the unique retrieval matrix. The method continues with the processing module storing the subset of the sets of encoded broadcast data slices. | 2011-06-30 |
20110161667 | TRUSTED GRAPHICS RENDERING FOR SAFER BROWSING ON MOBILE DEVICES - The present disclosure describes a method and apparatus for determining a safety level of a requested uniform resource locator (URL) on a mobile device. Secure memory may be configured to host at least one database comprising a plurality of uniform resource locators (URLs) and to also host information representing at least one logo indicative of a safety level of the URLs in the database. Secure circuitry may be configured to compare a requested URL with the database to determine if the requested URL corresponds to one of the URLs of the database and to select an appropriate logo stored in the secure memory. The secure circuitry may be further configured to direct overlay circuitry to blend the appropriate logo onto rendered data from a frame buffer video memory for display to a user. | 2011-06-30 |
20110161668 | METHOD AND DEVICES FOR DISTRIBUTING MEDIA CONTENTS AND RELATED COMPUTER PROGRAM PRODUCT - A method of distributing media content over networks where content is shared includes coupling downloading metadata, which is accessed to start downloading media contents from the network, with semantic metadata representative of the semantic information associated with at least one of the content, and with source metadata indicative of the source of the media content. At least one of the semantic and the source metadata may be made accessible without downloading, even partially, the media content. A digital signature may also be applied to the metadata to enable the verification that, at reception, the metadata is intact and has not been subjected to malicious tampering. | 2011-06-30 |
20110161669 | System and Method for Enabling Device Dependent Rights Protection - A system and method for enhancing the protection of digital properties while also increasing the flexibility of distribution of the digital properties. In one embodiment, the digital property is protected through the binding of at least one unique client device identifier with the digital property prior to distribution. Decryption at a client device would therefore be dependent on a comparison of the unique client device identifier that is extracted from the encrypted digital property with a unique client device identifier of the device that is seeking to access the digital property. | 2011-06-30 |
20110161670 | Reducing Leakage of Information from Cryptographic Systems - A system is described for reducing leakage of meaningful information from cryptographic operations. The system uses a pairwise independent hash function to generate a modified secret key SK′ having individual components. The system forms a modified secret key collection that includes SK′ and its individual components. The system then uses the modified secret key collection to decrypt a message. The decryption involves providing multiple partial operation results in separate respective steps. Leakage of meaningful information is reduced due to difficulty in piecing together meaningful information from information leaked by the separate partial operations. In one example, the hash function has the form H | 2011-06-30 |
20110161671 | SYSTEM AND METHOD FOR SECURING DATA - A system and method are provided for securing data. The method includes generating a first public encryption key by a cryptographic processor associated with a first computer subsystem; sending the first public encryption key to a second computer subsystem; and receiving first encrypted data at the first computer subsystem, the first encrypted data having been encrypted by the second computer subsystem using the first public encryption key. The method further includes generating a first private encryption key by the cryptographic processor; decrypting the first encrypted data using the first private encryption key generated by the cryptographic processor to obtain a first decrypted data; and storing the first decrypted data in a memory associated with the cryptographic processor. | 2011-06-30 |
20110161672 | Provisioning, upgrading, and/or changing of hardware - In some embodiments a secure permit request to change a hardware configuration is created. The secure permit request is sent to a remote location, and a permit sent from the remote location in response to the permit request is received. The hardware configuration is changed in response to the received permit. Other embodiments are described and claimed. | 2011-06-30 |
20110161673 | METHOD AND APPARATUS FOR ENHANCING SECURITY OF WIRELESS COMMUNICATIONS - The present invention is related to a method and apparatus for enhancing security of communications. The apparatus comprises a security processing unit, a data processing unit, a cross-layer watermarking unit, and optionally a smart antenna processor. The security processing unit generates a token/key to be used in watermarking and sends a node security policy to other components. The data processing unit generates user data. The cross-layer watermarking unit includes at least one of Layer-2/3, Layer-1 and Layer-0. Each layer performs a different scheme or degree of watermarking. The cross-layer watermarking unit embeds the token/key into the user data transmission on at least one of the layers selectively in accordance with a security policy. | 2011-06-30 |
20110161674 | DOCUMENT AUTHENTICATION USING DOCUMENT DIGEST VERIFICATION BY REMOTE SERVER - A method of generating a self-authenticating document while utilizing document digest stored on a server for verification purposes. Authentication information for the document is encoded in barcode which is printed on the document. A document digest is calculated from the authentication information and transmitted to a server to be stored. When authenticating a scanned copy of the document, the barcode is read to extract the authentication information. A target document digest is calculated from the extracted authentication information and transmitted to the server for verification. The server compares the target document digest with the previously stored document digest. If they are not the same, the barcode has been altered. If they are the same, the extracted authentication information is used to authenticate the scanned copy. A document ID may be generated and transmitted to the server, and used by the server to index or search for the stored document digest. | 2011-06-30 |
20110161675 | SYSTEM AND METHOD FOR GPU BASED ENCRYPTED STORAGE ACCESS - A system and method for graphics processing unit (GPU) based encryption of data storage. The method includes receiving a write request, which includes write data, at a graphics processing unit (GPU) encryption driver and storing the write data in a clear data buffer. The method further includes encrypting the write data with a GPU to produce encrypted data and storing the encrypted data in an encrypted data buffer. The encrypted data in the encrypted data buffer is sent to an IO stack layer operable to send the request to a data storage device. GPU implemented encryption and decryption relieves the CPU from these tasks and yield better overall performance. | 2011-06-30 |
20110161676 | ENTERING A SECURED COMPUTING ENVIRONMENT USING MULTIPLE AUTHENTICATED CODE MODULES - Systems, apparatuses, and methods, and for entering a secured system environment using multiple authenticated code modules are disclosed. In one embodiment, a processor includes a decoder and control logic. The decoder is to decode a secured enter instruction. The control logic is to find an entry corresponding to the processor in a match table in a master authenticated code module and to read a master header and an individual authenticated code module from the master authenticated code module in response to decoding the secured enter instruction. | 2011-06-30 |
20110161677 | SEAMLESSLY ENCRYPTING MEMORY REGIONS TO PROTECT AGAINST HARDWARE-BASED ATTACKS - Systems, apparatuses, and methods, and for seamlessly protecting memory regions to protect against hardware-based attacks are disclosed. In one embodiment, an apparatus includes a decoder, control logic, and cryptographic logic. The decoder is to decode a transaction between a processor and memory-mapped input/output space. The control logic is to redirect the transaction from the memory-mapped input/output space to a system memory. The cryptographic logic is to operate on data for the transaction. | 2011-06-30 |
20110161678 | CONTROLLER FOR CONTROLLING NAND FLASH MEMORY AND DATA STORAGE SYSTEM - According to one embodiment, a controller controlling a storage device connected to a host device and storing data includes a pseudorandom number generator, and a scramble circuit. The pseudorandom number generator generates a pseudorandom number based on identification information of the controller. The scramble circuit scrambles data received from the host device using the pseudorandom number. | 2011-06-30 |
20110161679 | TIME BASED DISPERSED STORAGE ACCESS - A method begins with a processing module receiving a data retrieval request and obtaining a real-time indicator corresponding to when the data retrieval request was received. The method continues with the processing module determining a time-based data access policy based on the data retrieval request and the real-time indicator and accessing a plurality of dispersed storage (DS) units in accordance with the time-based data access policy to retrieve encoded data slices. The method continues with the processing module decoding the threshold number of encoded data slices in accordance with an error coding dispersal storage function when a threshold number of the encoded data slices have been retrieved. | 2011-06-30 |
20110161680 | DISPERSED STORAGE OF SOFTWARE - A data de-duplication method begins by a processing module receiving a plurality of data storage requests from a plurality of requesting devices wherein a data storage request includes the data and a requester identifier (ID). The method continues with the processing module obtaining a data identifier (ID) for the data. For each of the plurality of data storage requests, the method continues with the processing module producing a requester storage record, dispersed storage error encoding the requester storage record to produce a set of encoded requester storage record slices, and sending the set of encoded requester storage record slices to a dispersed storage network (DSN) memory for storage therein. The method continues with the processing module dispersed storage error encoding at least a portion of the data to produce a set of encoded data slices and sending the set of encoded data slices to the DSN memory for storage therein. | 2011-06-30 |
20110161681 | DIRECTORY SYNCHRONIZATION OF A DISPERSED STORAGE NETWORK - A method begins by a processing module dispersed storage error encoding data to produce a set of encoded data slices and generating a transaction identifier regarding storage of the set of encoded data slices. The method continues with the processing module outputting a plurality of write request messages to a plurality of dispersed storage (DS) units, wherein each of the plurality of write request messages includes the transaction identifier and a corresponding one of the set of encoded data slices. The method continues with the processing module receiving write response messages from at least some of the DS units, wherein each of the write response messages includes a reference to the transaction identifier. The method continues with the processing module updating directory information regarding storage of the data to produce updated directory information when at least a write threshold number of the write response messages have been received. | 2011-06-30 |
20110161682 | PROCESSOR VOLTAGE REGULATION - A voltage regulator module (VRM) includes a first interface configured to couple to a first substrate interface at a first voltage. The VRM also includes a second interface configured to couple to a first processor interface at a second voltage. A first regulator module couples to the first interface and to the second interface. The first regulator module is configured to receive power at the first interface, to convert power to the second voltage, and to deliver power to the first processor interface at the second voltage. A method for providing power to a processor includes receiving power from a first substrate interface at a first voltage. The received power is regulated to generate power at a second voltage. The regulated power is provided to a processor at a first processor interface coupled to the processor. The processor interface delivers power to a logic group of a plurality of logic groups of the processor. | 2011-06-30 |
20110161683 | APPARATUS FOR HIGH EFFICIENT REAL-TIME PLATFORM POWER MANAGEMENT ARCHITECTURE - In some embodiments, the invention provides a higher efficiency, real-time platform power management architecture for computing platforms. A more direct power management architecture may be provided using integrated voltage regulators and in some embodiments, a direct power management interface (DPMI) as well. Integrated voltage regulators, such as in-silicon voltage regulators (ISVR) can be used to implement quicker, more highly responsive power state transitions. | 2011-06-30 |
20110161684 | MINI POWER SUPPLY MODULE - The present invention discloses a mini power supply module comprising a circuit board and a power connector. Said power connector is abutted and electrically connected with said power connector through coupling parts. Said power connector is provided with an orientating mechanism to change the angle between said power connector and said circuit board. Said power connector is further included with an input port for receiving the input of an external power source, a contact terminal for matching with the connector on motherboard, and at least one output port for outputting power to peripheral devices. | 2011-06-30 |
20110161685 | Temperature Control Method and Electronic Device Thereof - A temperature control method and an electronic device thereof are disclosed. A temperature control method applicable to an electronic device comprises the following steps. A power-consumption vs. temperature lookup table is provided, which records a plurality of thermal zones and a plurality of power consumption budgets corresponding thereto. An initial power consumption budget is obtained from the power-consumption vs. temperature lookup table based on an initial thermal zone value. The power consumption modes of the plural processing units are dynamically regulated according to each detected duty basis of the processing units, and the initial power consumption budget. The power consumption budget is dynamically changed according to a detected temperature of the electronic device and the power-consumption vs. temperature lookup table. | 2011-06-30 |
20110161686 | POWER SUPPLY CONTROL MODULE, ELECTRONIC DEVICE, AND RESET CONTROL METHOD - According , one embodiment, a power supply control module includes: a memory module; power supply controller; a voltage determination module; and reset execution module. The power supply controller performs supply/cutoff control of a voltage from a main power supply to a load via a power supply circuit by performing ON/OFF control of a switch module. The voltage determination module determines whether, during a standby state operating on a voltage supplied from a charge accumulating module, a value of the voltage supplied from the charge accumulating module is equal to or smaller than a reset threshold value set in advance. The reset execution module performs a reset execution operation for clearing a status retained in a memory module, the voltage determination module determines that the value of the voltage is equal to or smaller than the reset threshold value. | 2011-06-30 |
20110161687 | POWER SUPPLY APPARATUS, POWER RECEPTION APPARATUS AND INFORMATION NOTIFICATION METHOD - There is provided a power supply apparatus including a power supply unit configured to supply power, via a bus line, to another device with which an agreement about a power specification for power supply is achieved, a communication unit configured to communicate between power supplied from the power supply unit and the another device using frequency dividing, and an state input unit configured to accept an input of one or more predetermined states from outside. When the predetermined state is input to the state input unit, the communication unit applies a parameter indicating the state and communicates with the another device. | 2011-06-30 |
20110161688 | INFORMATION PROCESSING APPARATUS - According to one embodiment, an information processing apparatus includes a body housing comprising a top surface, a display housing connected to the body housing to pivotably move between a close position where the top surface is covered by the display housing and an open position where the top surface is opened, an acceleration sensor configured to detect an acceleration of the information processing apparatus, an opening/closing sensor configured to detect whether the display housing is located in the close position, an interface port provided in the body housing and configured to be connectable with an external device, and a controller configured to determine whether to power the interface port based on outputs of the acceleration sensor and the opening/closing sensor. | 2011-06-30 |
20110161689 | CARD PERIPHERAL DEVICE AND CARD SYSTEM - Disclosed herein is a card peripheral device including, an electronic part unit, a connector part, and a power supply unit, wherein the electronic part unit includes a controller, and at least a second interface, out of a first interface and the second interface, and the controller has a function to vary data transfer speed depending on whether power feed of the first power by the power supply terminal is received or the second power by the power supply unit is received. | 2011-06-30 |
20110161690 | VOLTAGE SCALING SYSTEMS - A voltage scaling system is provided and includes a processor, a latency predictor, a controller, and a voltage supplier. The processor performs functions and includes a function unit with variable-latency. The function unit is divided into several power domains. When the processor performs the functions, the function unit generates a latency signal according to a current circuit execution speed. The latency predictor predicts performance of the processor according to the received latency signal to generate a predication signal. The controller compares a value of the predication signal with at least one reference value. The controller generates control signals according to the comparison result. The voltage supplier couples to a first voltage source providing a high voltage and a second voltage source providing a low voltage. The voltage supplier is switched to provide the high or low voltage to the power domains according to the control signals, respectively. | 2011-06-30 |
20110161691 | SEMICONDUCTOR INTEGRATED CIRCUIT AND CONTROL METHOD OF SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit includes: a plurality of domains each supplied power supply voltage from corresponding one of a plurality of power supply units; and a plurality of operation control units each connected to corresponding one of the plurality of domains and controlling an operational state of the corresponding domain, wherein each of the domain transmits a operation change request to the corresponding operation control unit, the operation change request representing a request for a change of the operational state with a change in current value of the domain, and the operation control unit calculates a current change rate of the domain resulted from the change of operational state upon receiving the operation change request, and transmits a response signal approving the change of operational state to the corresponding domain in case of the current change rate is within a specified value. | 2011-06-30 |
20110161692 | SYSTEM AND METHOD FOR MULTIPLE POE POWER SUPPLY MANAGEMENT - A system and method for multiple power over Ethernet (PoE) power supply management. Power supply status signals indicative of an operating condition of a plurality of PoE power supplies are provided to a plurality of power sourcing equipment (PSE) controller chips. Pre-configured combination logic within each of the PSE controller chips converts an indicated operational state of the plurality of PoE power supplies into a powering decision for each of the Ethernet ports served by the PSE controller chip within one microsecond. | 2011-06-30 |
20110161693 | INLINE POWER CONTROLLER - An inline power controller includes at least one analog interface circuit module (AICM) having a first analog input node for receiving an inline power port voltage, a second analog input node for receiving an inline power port current, a first analog output for effecting an inline power port voltage, a second analog output for effecting an inline power port current, and a digital interface converting the received inline power port voltage to a digital value, the inline power port current to a digital value, a first digital value to the first analog output and a second digital value to the second analog output. A digital serial bus (DSB) couples the AICM to a digital controller via digital serial bus interfaces (DSBIs). | 2011-06-30 |
20110161694 | INFORMATION PROCESSING APPARATUS - According to one embodiment, an information processing apparatus includes a device controller, an operation mode switching circuit, a line switch, and a controller. The device controller includes a wakeup function and performs transmission with the external device through a data line. The operation mode switching circuit changes an operation mode of a sleep-and-charge function and performs transmission with the external device through the data line. The line switch selectively connects the data line with either of the device controller or the operation mode switching circuit. The controller controls a power supply to the device controller and a drive of the operation mode switching circuit and the line switch in accordance with the condition of the main body. | 2011-06-30 |
20110161695 | POWER-SAVING NETWORK MANAGEMENT SERVER, NETWORK SYSTEM, AND METHOD OF DETERMINING SUPPLY OF POWER - A power-saving network management server, which is coupled to a network system including a network device and manages a state of power to the network device, wherein the power-saving network management server is configured to: store network configuration information and task allocation information; determine starting or stopping of the power supply to the port of the network device based on the updated network configuration information and task allocation information; store a determination result of the starting or stopping of the power supply to the port as a port determination result; and control the power supply to the port of the network device based on the port determination result. | 2011-06-30 |
20110161696 | REDUCING ENERGY CONSUMPTION IN A CLOUD COMPUTING ENVIRONMENT - Functionality can be implemented within a cloud manager to leverage energy consumption data of cloud processing and their associated facility resources when selecting computing nodes to complete the job. The cloud manager can determine possible computing nodes to complete the job based on the job attributes. The cloud manager can determine aggregate energy data of the cloud resources from an energy usage database. The cloud manager can analyze the energy usage data to determine a configuration of the computing nodes to perform the job that reduces total energy consumption. For example, a configuration of servers can be based on a number of servers and processor utilization at the servers to perform the job. The cloud manager can assign the job to the servers and set the processor utilization at the servers in accordance with the resource configuration determined to minimize energy consumption. | 2011-06-30 |
20110161697 | METHOD AND SYSTEM FOR DISCOVERABILITY OF POWER SAVING P2P DEVICES - In a method and system, a first wireless device may be periodically cycled between an available state and a power saving state. While in the available state, the first wireless device may receive a probe request sent from a second wireless device operating in a discovery state. The first wireless device may transmit a probe response to the second wireless device. Other embodiments are described and claimed. | 2011-06-30 |
20110161698 | System management controller entry into reduced power state - A system includes an operating system, first hardware, second hardware, and a system management controller, the latter which also may be considered an integrated management module or a baseboard management module. The first hardware executes the operating system and is under control of the operating system. The operating system causes the first hardware to enter a first reduced power state. The second hardware is different than the first hardware and is not under control of the operating system. The system management controller is implemented by the second hardware. In response to the operating system causing the first hardware to enter the first reduced power state, the system management controller causes the second hardware to enter a second reduced power state corresponding to the first reduced power state. The first reduced power state may be a more-power-conserving reduced power state than the second reduced power state. | 2011-06-30 |
20110161699 | Methods and System for Reducing Battery Leakage in an Information Handling System - A method for reducing current leakage in a battery in communication with an information handling system (IHS) is disclosed herein. The method includes providing a battery management unit (BMU) in the battery, the BMU in communication with an embedded controller, wherein the BMU comprises a detector pin. The method further includes placing the BMU in a standby mode to disable power from the battery to the IHS while the battery is coupled to the IHS, and configuring the BMU to exit the standby mode, if an external power supply is coupled to the IHS, to enable battery power from the battery to the IHS. Also disclosed is an information handling system (IHS) which includes an embedded controller operable to initiate a power-on sequence in the IHS, and a battery having a battery management unit (BMU), wherein the BMU is initially placed in a standby mode to disable battery power to the IHS, the BMU in communication with the embedded controller. The system may further include a power switch in communication with the embedded controller and the BMU, and a control switch configured to be switched on if an external power supply is coupled to the IHS or if the power switch is activated without the external power supply, wherein the BMU unit exits the standby mode if the control switch is switched on, thereby enabling battery power to the IHS. | 2011-06-30 |
20110161700 | APPARATUS AND METHOD FOR REDUCING POWER CONSUMPTION OF ACCESS POINT FUNCTION IN PORTABLE TERMINAL - An apparatus and a method for operating as a virtual terminal to participate in competition for medium access while a mobile terminal operates as an access point are provided. In a case where the mobile terminal accesses a medium while competing with a terminal that transmits data of low priority, an apparatus and a method for entering a low power mode to resolve a power consumption problem of the mobile terminal are provided. The apparatus includes a medium competing unit, which allows the mobile terminal to operate as a virtual terminal and participate in competition for a medium access when data to be transmitted does not exist in the mobile terminal operating as an Access Point (AP). | 2011-06-30 |
20110161701 | REGULAR OR DESIGN APPLICATION - An electronic timer system includes a counter-based time generator for continuously generating raw base time, and a translator for translating between raw base time and local precise time. The counter-based time generator is driven by an oscillator. The timer system further includes a temperature sensor placed in the proximity of the oscillator or a crystal used by the oscillator, and a look-up control table holding temperature values associated with corresponding control values representative of the configurable parameter value A. The look-up control table is generated when the timer system is synchronized with a synchronization source so that the temperature and control values are characteristic of the operation of the timer system in synchronization. The timer system is also configured for reading, when no synchronization source is available, a temperature value from the temperature sensor, and for extracting, based on the temperature value, a control value from the look-up control table corresponding to a suitable (quantized) representation of the temperature value. The timer system is then able to configure the parameter variable A in accordance with the extracted control value. | 2011-06-30 |
20110161702 | TECHNIQUES FOR ENTERING A LOW-POWER LINK STATE - Techniques to cause a point-to-point link between system components to engage in a negotiation process that may lead to the link transitioning from an active state in which data may be transmitted between system components to a low power state where data may not be transmitted. The negotiation process may occur between each pair of nodes within an electronic system that are interconnected via point-to-point link. The negotiation may ensure that there are no pending transactions or transactions that may occur within an upcoming period of time. Through this negotiation each component acknowledges and agrees to transition the link to the low power state. | 2011-06-30 |
20110161703 | PCI EXPRESS ENHANCEMENTS AND EXTENSIONS - A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses. | 2011-06-30 |
20110161704 | DATA PROCESSING APPARATUS, CONTROL METHOD, AND STORAGE MEDIUM - A data processing apparatus includes a storage unit and operates in a first power mode in which power that the storage unit can operate is supplied to the storage unit or in a second power mode in which power that the storage unit can operate is not supplied to the storage unit. The data processing apparatus includes an input unit configured to input data, a storing unit configured to store the data in the storage unit, a setting unit configured to set waiting time for making the data processing apparatus wait to shift from the first power mode to the second power mode according to a storage destination if the data is stored in the storage unit, and a control unit configured to shift the data processing apparatus from the first power mode to the second power mode when the waiting time elapses after the data is stored in the storage unit. | 2011-06-30 |
20110161705 | MULTIPLE-QUEUE MULTIPLE-RESOURCE ENTRY SLEEP AND WAKEUP FOR POWER SAVINGS AND BANDWIDTH CONSERVATION IN A RETRY BASED PIPELINE - Methods and apparatus relating to multiple-queue multiple-resource entry sleep and wakeup for power savings and bandwidth conservation in a retry based pipeline are described. In one embodiment, a bit indicates whether a corresponding queue entry is asleep or awake with respect to arbitration for resources in a retry based pipeline. Furthermore, multiple entries from different queues may be grouped together and multiple resources may be grouped together. Other embodiments are also disclosed. | 2011-06-30 |
20110161706 | COMPUTER SYSTEM WITH OVERCLOCKING FUNCTION AND METHOD - An overclocking method applied to a computer system includes the following steps: setting a first operating voltage and a first clock rate; generating a first control signal to a power supply and generating a second control signal to a clock generator according to the first operating voltage and the first clock rate, respectively; controlling the computer system into a sleep mode; resuming the computer system from the sleep mode after a predetermined time; restarting the power supply and the clock generator, and generating the first operating voltage by the power supply according to the first control signal and, generating the first clock rate by the clock generator according to the second control signal; and setting a parameter of a memory controller in a north bridge chip of the computer system via the first clock rate and the first operating voltage. | 2011-06-30 |
20110161707 | POWER MANAGEMENT OF COMPUTERS - A method of controlling power consumption in a computer by detecting whether or not there is any user activity, and also the identity of each process running on the computer. The identity of each process running on the computer is compared with a set of identities of previously identified processes, these having been deemed to be processes for which it is desirable that the computer maintains a high power state. The computer adopts a low power state if all the detected identities of processes are not in the set of high power state processes or no user activity is detected. The low power state is a state in which the computer is able to service requests. The computer freely adopts any available higher power state if user activity is detected or a detected process is in the set of high power state processes. The power state selected may depend on workload. | 2011-06-30 |
20110161708 | PRIMARY SIDE CONTROL CIRCUIT AND METHOD FOR ULTRA-LOW IDLE POWER OPERATION - A method and circuit for reducing power consumption during idle mode to ultra-low levels, such as about 1/10 | 2011-06-30 |
20110161709 | METHOD AND SYSTEM FOR POWER SAVING MANAGEMENT - The present invention discloses a method and a system for power saving management. The method includes: a new power consuming state attribute added for existing device object of the communication network management system is configured, wherein the power consuming state attribute is used for indicating the power consuming state of the electrical energy; performing the power saving management on the device by setting the power consuming state of the object corresponding to the device. With the above technical solution, the division of the state information could be clearer and more efficient, meanwhile, the redundancy can be eliminated, in addition, has the feather of wide adaptability. | 2011-06-30 |
20110161710 | LAPTOP COMPUTER AND HINGE MODULE WITH ANGLE DETECTOR THEREOF - A laptop computer includes a main body, a display device, a hinge module and an angle detector. The hinge module is pivotally interconnected between the display device and the main body such that the display device is swiveled relative to the main body to be folded against or unfolded away from the main body. The hinge module includes a first hinge component and a second hinge component. The first hinge component is secured to the main body. The second hinge component is pivotally connected with the first hinge component and includes an end secured to the display device. The angle detector is coupled with an opposite end of the second hinge component for measuring a rotation angle of the second hinge component. | 2011-06-30 |
20110161711 | Control Device, Control Method, and Recording Medium - Power consumption by an external device can be reduced while controlling the external device by a generic device driver even when the generic device driver does not have a power management function for the external device. When a command generated by operation of a POS application | 2011-06-30 |
20110161712 | COOLING APPLIANCE RATING AWARE DATA PLACEMENT - Physical storage systems dissipate large amounts of heat as a result of operations performed on data stored on the physical storage systems. Existing cooling mechanisms use cooling appliances with different cooling characteristics to dissipate the heat. However, the existing cooling mechanisms do not consider the cooling characteristics of the cooling appliances when moving/storing data, resulting in an inefficient use of the cooling appliances and a waste of power. Functionality can be implemented to identify datasets that cause generation of large amounts of heat in the associated physical storage system(s). These heat-intensive datasets can be moved to cooler physical storage system(s) that are identified based, at least in part, on cooling characteristics of the cooling appliances and a proximity of the physical storage system(s) to the cooling appliances. This can ensure that the cooling appliances with the best cooling characteristics are used to cool the most heat intensive datasets. | 2011-06-30 |
20110161713 | COMMAND LATENCY REDUCTION AND COMMAND BANDWIDTH MAINTENANCE IN A MEMORY CIRCUIT - A method includes operating an arbitration logic of a memory controller at a core clock frequency lower than that of a memory clock frequency. The memory controller is configured to generate a command sequence including a number of commands in accordance with a number of external requests to access the memory. The method also includes parallelizing the number of commands in the command sequence based on a timing requirement for a non-first command in the command sequence defined by a memory-access protocol being satisfied at a rising edge or a falling edge of the core clock relative to a previous command in the command sequence. Further, the method includes ensuring, through the parallelizing, availability of the number of commands in the command sequence to a memory interface operating at the memory clock frequency at a command rate equal to the memory clock frequency. | 2011-06-30 |
20110161714 | CORRELATION TECHNIQUE FOR DETERMINING RELATIVE TIMES OF ARRIVAL/DEPARTURE OF CORE INPUT/OUTPUT PACKETS WITHIN A MULTIPLE LINK-BASED COMPUTING SYSTEM - A method is described that comprises receiving a timing exposure packet having timestamp information. The timestamp information identifies a cycle of a clock signal at which the packet was made available for transfer from a core to a physical layer within a component of a link-based computing system. The packet having been transmitted from the physical layer and also having phase information. The phase information identifies a cycle of the clock signal at which the packet was transferred from the core to the physical layer. | 2011-06-30 |
20110161715 | INFORMATION PROCESSING APPARATUS OR INFORMATION PROCESSING METHOD - According to the present invention, a phase shift of data received by an external device controller is delayed and corrected, and a control signal used for the data load control on the external device controller side is delayed period-by-period. Further, the phase shift is adjusted and then the control signal is adjusted. The adjustment can beneficially be performed very quickly. Moreover, the present invention is also beneficial for preventing a failure to load data. | 2011-06-30 |
20110161716 | SYSTEMS, METHODS, AND APPARATUSES FOR PROVIDING ACCESS TO REAL TIME INFORMATION - Methods, apparatuses, and systems are provided for providing access to real time information. A method may include running an application on top of a virtual platform. The method may further include determining a real time. The real time may define a non-simulation time that is maintained independently of the virtual platform such that the real time is not affected by performance of the virtual platform or of the application running on top of the virtual platform. The method may additionally include providing the determined real time for access by the application. Corresponding apparatuses and systems are also provided. | 2011-06-30 |
20110161717 | IMAGE FORMING APPARATUS - Even in a case where a master-CPU of an image forming section and a slave-CPU of a sheet transportation section are driven by respective oscillation circuits with different oscillation accuracies, a large difference in accuracy is not caused in transfer sheet transportation speed driven by clock signals formed by the respective oscillation circuits. In the master-CPU and the slave-CPU that are cascadingly connected to each other, in order to calculate a clock frequency of an oscillation circuit of the target-CPU, a predetermined time transmitted from the other CPU connected to the target-CPU is counted by the clock signal of the target-CPU. With reference to the predetermined time, an operating process, such as division of an acquired counter value by the predetermined time, acquires an error of the clock frequency of the oscillation circuit driving the slave-CPU, and corrects the error, thereby improving the accuracy thereof. | 2011-06-30 |
20110161718 | Command Decoding Method and Circuit of the Same - A decoding circuit for decoding a command is provided. The received command is transmitted during at least two clock periods of a clock signal, and the received command is divided to a former encoded data and a latter encoded data. The decoding circuit includes a pre-trigger signal generating unit, a comparing unit, and a starting signal generating unit. The pre-trigger signal generating unit receives the former encoded data and generates a pre-trigger signal when the former encoded data of the received command matches the corresponding former encoded data of a predetermined command. The comparing unit generates a match signal when the latter encoded data of the received command is the same with the latter encoded data of the predetermined command. The starting signal generating unit outputs a starting signal according to the pre-trigger signal and the match signal. The starting signal starts a corresponding operation of the predetermined command. | 2011-06-30 |
20110161719 | PROCESSING DEVICES - An embodiment of a processing device includes a function unit and a control unit. The function unit receives input data and performs a specific operation to the input data to generate result data. The control unit receives the result data and generates an output signal. The control unit latches the result data according to a first clock signal to generate first data and latches the result data according to a second clock signal to generate second data. The control unit compares the first data with the second data to generate a control signal and selects the first data or the second data to serve as data of the output signal according to the control signal. The second clock signal is delayed from the first clock signal by a predefined time period. | 2011-06-30 |
20110161720 | IMAGE PROCESSING APPARATUS AND METHOD OF TRANSMITTING REFERENCE CLOCK - An engine unit and a control unit are connected via an interface. A power source supplies electric power to the interface. The engine unit is controlled based on a reference clock generated in the control unit and transmitted to the engine unit via the interface. Only when a voltage output from the power source to the interface is in the operating-voltage range, the clock generator sends the reference clock to the engine unit via the interface. | 2011-06-30 |
20110161721 | Method and system for achieving a remote control help session on a computing device - A method and system for achieving a remote control help session on a computing device. The method includes receiving, at an online service datacenter, a request from a remote service provider computer to obtain a pass code for an end user of a malfunctioning computing device. Sending the pass code to the remote service provider computer, wherein a service provider technician provides the pass code to the end user. Securely connecting the malfunctioning computing device to the online service datacenter. Securely connecting the remote service provider computer to the online service datacenter. Linking the remote service provider computer to a PC session indicated by the pass code and enabling the service provider computer to connect through the online service datacenter to the malfunctioning computing device. The remote service provider computer, via firmware residing on the malfunctioning computing device, enables the service provider technician to diagnose, repair, and/or optimize the malfunctioning computing device. | 2011-06-30 |
20110161722 | Systems and Methods for a Communication Protocol Between a Local Controller and a Master Controller - Systems and methods for local management units in a photovoltaic energy system. In one embodiment, a method implemented in a computer system includes: attempting to communicate on a first active channel with a master management unit from a local management unit that controls a solar module; if communication with the master management unit on the first active channel has not been established, attempting to communicate on a second active channel with the master management unit. | 2011-06-30 |
20110161723 | DISASTER RECOVERY USING LOCAL AND CLOUD SPANNING DEDUPLICATED STORAGE SYSTEM - A spanning storage interface facilitates the use of cloud storage services by storage clients and may perform data deduplication. The spanning storage interface may include local storage for caching data from storage clients. A disaster recovery application includes at least first and second spanning storage interfaces at first and second network locations. The second spanning storage interface is provided for at least disaster recovery operations. The second spanning storage interface includes second local storage for improving data access performance. A copy of the local cache of the first spanning storage interface is transferred to the second local storage while the first network location is operating. In the event of a disaster affecting the first network location, the second spanning storage interface can provide data access to the first network location's data with improved performance from using the copy of local cache in the second local storage. | 2011-06-30 |
20110161724 | DATA MANAGEMENT APPARATUS, MONITORING APPARATUS, REPLICA APPARATUS, CLUSTER SYSTEM, CONTROL METHOD AND COMPUTER-READABLE MEDIUM - A data management apparatus, which is connected to a monitoring apparatus that monitors an operating state of a service, and which provides a service for managing data, comprises: a status management unit which manages a status of a service provided by itself; a notification unit which periodically notifies the monitoring apparatus of a status of the service; a receiving unit which receives a request from an application to which the service is provided; and a rejecting unit which rejects, when the request received by the receiving unit is an update request of data, the update request if a status associated with updating of the service managed by the status management unit is a limited status. | 2011-06-30 |
20110161725 | DYNAMICALLY TRACKING VIRTUAL LOGICAL STORAGE UNITS - In virtualized environments, storage may be managed dynamically due to the changing data storage requirements. In such environments, logical storage unit identifiers (LUN IDs) may be modified as a result of deleting an existing mapping between physical storage and a virtualization server and recreating the mapping. This can result in I/O request failure. Techniques for resolving errors resulting from LUN ID modifications can be time-intensive and labor-intensive and can disrupt a communication path between a host device and the physical storage. Functionality can be implemented to dynamically identify the LUN ID modifications, determine valid LUN IDs, and retransmit failed I/O requests. This can help minimize I/O request failures due to LUN ID modifications without disrupting the communication path between the host device and the physical storage. | 2011-06-30 |
20110161726 | SYSTEM RAS PROTECTION FOR UMA STYLE MEMORY - In some embodiments, the invention involves a system and method relating to system recovery in a fault resilient manner by isolating errors associated with the management engine (ME) UMA memory. BIOS logs errors occurring on memory within the system. The ME UMA is invisible to the host OS, so the OS will not be notified about the errors occurring in the ME UMA range. When an error threshold has been reached for a memory unit in which ME UMA resides, ME UMA data is migrated to a previously reserved backup region of memory and the ME is notified of the new ME UMA location. The faulty memory is flagged for replacement at a next maintenance cycle. Embodiments may be applied to workstations that utilize ECC memory protection which utilize AMT (Active Management Technology) and ME UMA. Other embodiments are described and claimed. | 2011-06-30 |
20110161727 | SOLID STATE STORAGE SYSTEM FOR CONTROLLING RESERVED AREA AND METHOD OF CONTROLLING THE SAME - A solid state storage system includes a flash memory region comprising a plurality of memory blocks and a plurality of replacement blocks corresponding to error-occurred blocks when errors occur in the memory blocks; and a memory controller configured to perform a control operation to replace the error-occurred blocks with the replacement blocks, wherein the error-occurred blocks comprise correctable blocks and uncorrectable blocks, and wherein the memory controller determines whether the error-occurred blocks are the correctable blocks or the uncorrectable blocks and controls zones of the replacement blocks, replaced in correspondence to the correctable blocks, to be allocated a plurality of times. | 2011-06-30 |
20110161728 | DISK ARRAY APPARATUS AND METHOD FOR CONTROLLING THE SAME - A disk array apparatus capable of reducing a disk drive fault rate where a time-out failure has occurred. The disk array apparatus includes a plurality of disk drives, and a control unit for performing data input/output processing of the disk drives in response to a data input/output request from a host system. The control unit includes: a memory for storing control information for specifying a failure of at least one of the disk drives, and failure information of the faulty disk drive, a circuit for specifying, from the failure information, the disk drive in which a time-out failure has occurred, and issuing an instruction to retry a control command to the disk drive, and a circuit for outputting a control signal to the faulty disk drive in order to hard reset the disk drive if the disk drive does not recover from the failure. | 2011-06-30 |
20110161729 | PROCESSOR REPLACEMENT - Techniques for transparently replacing a processor, that receives interrupts in a partitioned computing device, with a replacement processor, are disclosed. In at least some embodiments, methods are discussed for directing the interrupts to an unchangeable identifier mapped to the processor's identifier and replacing the processor with the replacement processor. An intermediary, such as an I/O APIC, is used for storing the unchangeable identifier. The mapping may use logical mode delivery, physical mode delivery, or interrupt mapping. | 2011-06-30 |
20110161730 | SYSTEMS, METHODS, AND APPARATUS TO DEBUG A NETWORK APPLICATION - Methods and apparatus to debug a network application are described. A described example network includes a live control network to collect control messages to create a history of network states, the history of network states reflecting an order in which control messages are processed, the live control network to roll back from a current state to a past state upon detection of an improper sequence of messages and to process the messages in a corrected sequence, the corrected sequence to be stored in the history. The described example network further includes a virtualized network corresponding to the live control network, the virtualized network responsive to a command from an operator to step through the history to facilitate debugging. | 2011-06-30 |
20110161731 | RELOCATING BAD BLOCK RELOCATION (BBR) DIRECTORY UPON ENCOUNTERING PHYSICAL MEDIA DEFECT ON A DISK - Apparatus, method and program product for relocating Bad Block Relocation Directory (BBRD) on a disk storage pre-allocate a number of areas for BBRD in different locations of the disk storage. The locations for the BBRD are calculated based upon the size of the disk and BBRD count. If the update of BBRD fails due to defective media at the location to be updated, that location is abandon and the next pre-allocated location is used. A copy of the BBRD is stored in RAM and maintained by the kernel. By so doing, when a bad block in the BBRD is detected the kernel causes the BBRD to be written in a good one of the locations reserved for BBRD. When the number of alternate BBRD locations used hits a pre-defined threshold, this indicates a situation where many sections of the disk are going bad and the disk needs replacement. If all BBRD locations are used, the disk is presumed bad and all future I/O activities to the disk is suspended. An administrator may be notified that the disk is going bad and needs to be replaced. | 2011-06-30 |
20110161732 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR SYSTEM INCLUDING THE SAME - A semiconductor device includes an internal circuit configured to perform a specified operation in response to a predetermined command; a normal data input/output section configured to input/output a normal data synchronized with a center of a source clock, in response to data input/output commands; and a data recovery information signal input/output block configured to receive and store a data recovery information signal synchronized with an edge of the source clock and having a predetermined pattern, in response to either a command of the data input/output commands or the predetermined command upon entry to a data recovery operating mode, and to output the data recovery information signal after the passage of a predetermined time period. | 2011-06-30 |
20110161733 | TRANSACTION REGIONS IN METHODS OF PROCESSING DATA - There is provided a method of processing at least one data message using a computing device having at least a processor, a memory, a display device and an input device, the method including:
| 2011-06-30 |
20110161734 | PROCESS INTEGRITY IN A MULTIPLE PROCESSOR SYSTEM - Disclosed are a method, a system and a computer program product of operating a data processing system that can include or be coupled to multiple processor cores. In one or more embodiments, an error can be determined while two or more processor cores are processing a first group of two or more work items, and the error can be signaled to an application. The application can determine a state of progress of processing the two or more work items and at least one dependency from the state of progress. In one or more embodiments, a second group of two or more work items that are scheduled for processing can be unscheduled, in response to determining the error. In one or more embodiments, the application can process at least one work item that caused the error, and the second group of two or more work items can be rescheduled for processing. | 2011-06-30 |
20110161735 | SEMICONDUCTOR DEVICE CONTROLLING DEBUG OPERATION OF PROCESSING UNIT IN RESPONSE TO PERMISSION OR PROHIBITION FROM OTHER PROCESSING UNIT - A semiconductor device is capable of being coupled to first and second debuggers, the first and second debuggers being capable of debugging a program in the semiconductor device. The semiconductor device includes a first chip, and a second chip that is coupled to the first chip. The first chip includes a first processing unit that executes a first instruction group, and a first debug control unit capable of being coupled to the first debugger to control a communication with the first debugger. The second chip includes a nonvolatile memory that stores an ID code and the program including the first and second instruction groups and, the ID code stored in the nonvolatile memory being compared with an ID code inputted from the second debugger to control permission or prohibition of a connection configuration to the second debugger, a second processing unit that executes the second instruction group, and a second debug control unit capable of being coupled to the second debugger to control a communication with the second debugger. The first debug control unit controls permission or prohibition of a connection configuration to the first debugger based on whether the connection configuration to the second debugger is permitted or not. | 2011-06-30 |
20110161736 | Debugging module to load error decoding logic from firmware and to execute logic in response to an error - A computing device includes a processor, firmware, a hardware component, and a debugging module. The firmware stores error decoding logic particular to the computing device. The hardware component detects an error in the computing device, and responsively issues an interrupt and halts the processor such that the processor cannot execute any more computer-readable code. The debugging module loads the logic from the firmware at reset and executes the logic responsive to the interrupt. The debugging module does not use the processor to execute the logic, the firmware is not part of the debugging module, and the debugging module is not part of the hardware component. The firmware may also store a mapping between registers of the hardware component and field-replaceable hardware units of the computing device, which the debugging module loads at reset and uses when executing the error decoding logic to determine which unit has caused the error. | 2011-06-30 |
20110161737 | POST CODE MONITORING SYSTEM AND METHOD - A system is configured for monitoring power-on self-test (POST) codes generated by a motherboard under a power cycling test. The system includes a recording device configured to save the POST codes and a monitoring circuit board. The monitoring circuit board is configured to receive the POST codes from the motherboard and output the POST codes to the recording device. The monitoring circuit board is capable of displaying the POST codes one by one to indicate a current running state of the motherboard and outputting the POST codes in a format that the recording device is receivable. A method for monitoring power-on self-test (POST) codes generated by a motherboard under a power cycling test is also disclosed. | 2011-06-30 |
20110161738 | DEVICE AND METHOD FOR OPTIMALLY ADJUSTING TRANSMITTER PARAMETERS - A device and a method for optimally adjusting transmitter parameters are provided to optimize transmission performance of a digital signal system. The device comprises an error signal analyzing unit and a step length adjustment unit which are connected in signal with each other; the error signal analyzing unit analyzes an error signal and makes a determination to carry out a transmitter parameter adjustment operation; the step length adjustment unit calculates and determines an adjustment direction and an adjustment step length of the transmitter parameter; and a transmitter parameter adjusting unit carries out operations of direction adjustment and step length adjustment of the transmitter parameter according to the result of the determination. | 2011-06-30 |
20110161739 | GENERATE DIAGNOSTIC DATA FOR OVERDUE THREAD IN A DATA PROCESSING SYSTEM - Disclosed is a computer implemented method, computer program product, and apparatus for generating diagnostic data for a thread. A service processor may begin by executing the computer usable program code to allocate a first thread to a monitoring function. The service processor determines if a second thread is running, wherein the second thread is associated with an operation. The service processor obtains an object pointer from a list of running threads, wherein the object pointer references a time data structure associated with the second thread, the time data structure comprising a maximum running time interval and a check time. The service processor calculates the check time as a maximum running time interval added to an initially sampled timestamp. The service processor determines if a current time exceeds the check time. In addition, the service processor generates an error log, responsive to a determination that the current time exceeds the check time. | 2011-06-30 |
20110161740 | APPARATUS AND METHOD FOR SELECTING CANDIDATE FOR FAILURE COMPONENT - An apparatus for selecting a candidate for a failure component causing errors from a plurality of components included in a network system, the apparatus includes a processor for executing a procedure. The procedure includes determining a relation class of a relation among the plurality of components on the basis of configuration information of the network system, each of the relations being classified into one of the relation classes in accordance with a direction of an error propagation, determining an investigation range for each component having an error on the basis of investigation information including an error type of an error occurred in the each component and an investigation direction corresponding to the relation class, the investigation range being a set of the components to be investigated, and selecting a component on the basis of an appearance frequency of each component in the investigation ranges as the candidate. | 2011-06-30 |
20110161741 | TOPOLOGY BASED CORRELATION OF THRESHOLD CROSSING ALARMS - Method, apparatus and computer program product for correlating performance events in a data processing system. A first event is received at one of a first device and a second device of the data processing system, and a second event is received at one of the first device and the second device. A type of a connection between the first device and the second device is identified to form an identified type of connection, and a relationship between the first event and the second event is determined based on the identified type of connection between the first device and the second device. | 2011-06-30 |
20110161742 | Efficient Monitoring in a Software System - A monitoring of a server system during an execution of a server system processing logic, includes: during collection and storage of operational metrics by a given thread in a thread-local memory, determining that a checkpoint within the server system processing logic is reached; determining whether a threshold number of checkpoints have been encountered by the given thread; in response to the threshold number of checkpoints having been encountered, determining whether a threshold time interval since a last rollup of the collected operational metrics has been exceeded; and in response to the threshold time interval being exceeded, performing a rollup of the collected operational metrics from the thread-local memory to an accumulation point in a shared memory, where the accumulation point stores aggregated operational metrics from a plurality of threads. | 2011-06-30 |
20110161743 | OPERATION MANAGEMENT DEVICE, OPERATION MANAGEMENT METHOD, AND OPERATION MANAGEMENT PROGRAM - An operation management device includes: an information collection module which collects, from a managed device, first and second performance information showing a time series change in the performance information; a correlation model generation module which derives a correlation function between the first and second performance information and creates a correlation model based on the correlation function; a correlation change analysis module which judges whether or not the current first and second performance information acquired by the information collection module satisfy the relation shown by the conversion function between the first and second performance information of the correlation model within a specific error range; and a failure period extraction module which, when the first and second performance information does not satisfy the relation shown by the conversion function of the correlation model, extracts a period of that state as a failure period. | 2011-06-30 |
20110161744 | SYSTEM AND METHOD FOR SERVICE AVAILABILITY MANAGEMENT - A service framework uses importance ranking information in making call decisions and/or wait-time decisions in connection with service requests. Each of the service requests has an importance ranking which reflects the importance of the information provided by the service to a task being performed. The health of a service may be controlled by permitting fewer (or more) service requests to be made to the service when the service is less (or more) healthy. The likelihood of a service request being made to the service may depend on the importance, ranking of the service request. When waiting for a response, a determination whether to continue waiting may be made based on the likelihood that the service has failed and based on the importance of the information to the task being performed. | 2011-06-30 |
20110161745 | Mobility PDA Surveillance Using GPS - A method for troubleshooting a mobile device operating in a network includes receiving a request from the mobile device to a network server via a global positioning system (GPS) interface; extracting a report from the network; comparing values in the report to threshold values; requesting additional data collection based on the comparing step; analyzing the additional data; and sending a report to the mobile device. The mobile device may be a personal digital assistant. The invention includes a system configured to perform the foregoing method steps. | 2011-06-30 |
20110161746 | INFORMATION PROCESSING APPARATUS, CONTROL METHOD OF INFORMATION PROCESSING APPARATUS, AND INFORMATION PROCESSING SYSTEM - A reception unit receives, in a case where an error has occurred in an image forming apparatus during execution of a designated job, error information indicating that the error has occurred. An acquisition unit acquires information indicating that it is designated to skip the error and to execute the job in the image forming apparatus. A determination unit determines, in a case where the acquisition unit acquires the information, whether or not to continue to display the error information depending on a type of the error. A control unit continues, in a case where the determination unit determines that the error information is continued to be displayed, to display the error information, and ceases, in a case where the determination unit determines that the error information is not continued to be displayed, to display the error information. | 2011-06-30 |
20110161747 | ERROR CONTROLLING SYSTEM, PROCESSOR AND ERROR INJECTION METHOD - An error controlling system includes a plurality of error generation target circuits, a plurality of pseudo error generating devices each having a pseudo error content holding register that holds directed pseudo error content, each plurality of pseudo error generating device generates a pseudo error corresponding to a pseudo error content held in a respective pseudo error content holding register in at least one of data to be written to one of the plurality of error generation target circuits and data to be read from one of the plurality of error generation target circuits upon being directed to generate the pseudo error, and a pseudo error controlling device that directs the plurality of pseudo error generating devices to generate a pseudo error corresponding to a respective pseudo error content held in each of the pseudo error content holding register provided in each of the plurality of pseudo error generating devices. | 2011-06-30 |
20110161748 | Systems, methods, and apparatuses for hybrid memory - Embodiments of the invention are generally directed to systems, methods, and apparatuses for hybrid memory. In one embodiment, a hybrid memory may include a package substrate. The hybrid memory may also include a hybrid memory buffer chip attached to the first side of the package substrate. High speed input/output (HSIO) logic supporting a HSIO interface with a processor. The hybrid memory also includes packet processing logic to support a packet processing protocol on the HSIO interface. Additionally, the hybrid memory also has one or more memory tiles that are vertically stacked on the hybrid memory buffer. | 2011-06-30 |
20110161749 | READING METHOD AND APPARATUS FOR AN INFORMATION RECORDING MEDIUM AND SPARE AREA ALLOCATION THEREOF - A reading apparatus for reading an information recording medium is provided. The information recording medium has a user data area for recording data and a spare area for recording replacements corresponding to registered defects of the user data area. The reading apparatus comprising a first storage device for storing the data read from the user data area, a second storage device for storing replacements, and a replacement controller for searching a corresponding replacement in the second storage device when a registered defect is found in the user data area, while reading the corresponding replacement and neighboring replacements thereof from the spare area of the information recording medium and storing the read replacements into the second storage device when the corresponding replacement is failed to be found in the second storage device. | 2011-06-30 |
20110161750 | Pre-Code Device, and Pre-Code System and Pre-Coding Method Thereof - A pre-code device includes firstly memory circuit, an address decoder, and an alternative logic circuit. The first memory circuit includes a number of memory blocks and at east a replacing block. The memory blocks are pointed by a number of respective physical addresses. The replacing block is pointed by a replacing address. The address decoder decodes an input address to provide a pre-code address. The alternative logic circuit looks up an address mapping table, which maps defect physical address among the physical addresses to the replacing address, to map the pre-code address to the replacing address when the pre-code address corresponds to the defect physical address. The alternative logic circuit correspondingly pre-codes the pre-code data to the replacing block. | 2011-06-30 |
20110161751 | SEMICONDUCTOR INTEGRATED CIRCUIT WITH MEMORY REPAIR CIRCUIT - A semiconductor integrated circuit which can perform repair of at least one memory circuit in RAM, etc. and can promote improvement in the degree of integration is provided. The encoding circuit | 2011-06-30 |
20110161752 | ROBUST MEMORY LINK TESTING USING MEMORY CONTROLLER - REUT (Robust Electrical Unified Testing) for memory links is introduced which speeds testing, tool development, and debug. In addition it provides training hooks that have enough performance to be used by BIOS to train parameters and conditions that have not been possible with past implementations. Address pattern generation circuitry is also disclosed. | 2011-06-30 |
20110161753 | SEMICONDUCTOR MEMORY APPARATUS INCLUDING DATA COMPRESSION TEST CIRCUIT - A semiconductor memory apparatus having stacked first and second chips includes a first chip test signal generation unit disposed in the first chip and configured to generate a first chip test signal in response to a first chip compression data determination signal in a test mode, a second chip test signal generation unit disposed in the second chip and configured to generate a second chip test signal in response to a second chip compression data determination signal in the test mode, and a final data determination unit configured to generate a final test to signal in response to the first and second chip test signals in the test mode. | 2011-06-30 |
20110161754 | REVISION SYNCHRONIZATION OF A DISPERSED STORAGE NETWORK - A method begins by a processing module receiving a write request message from a dispersed storage (DS) processing module, wherein the write request message includes a slice name, a DS processing module most-recent slice revision, a new slice revision, and an encoded directory slice of directory information regarding storage of data. The method continues with the processing module obtaining, from local memory, a DS unit most-recent slice revision based on the slice name. The method continues with the processing module storing the new slice revision as the DS unit most-recent slice revision and storing the encoded directory slice when the DS unit most-recent slice revision compares favorably to the DS processing module most-recent slice revision. | 2011-06-30 |
20110161755 | Methods of Parametric Testing in Digital Circuits - Delay-fault testing and parametric analysis systems and methods utilizing one or more variable delay time-base generators. In embodiments of the delay-fault testing systems, short-delay logic paths are provided with additional scan-chain memory elements and logic that, in conjunction with the one or more variable-delay time-base generators, provides the effect of over-clocking without the need to over-clock. Related methods provide such effective over-clocking. In embodiments of parametric analysis systems, test point sampling elements and analysis circuitry are clocked as a function of the output of the one or more variable-delay time-base generators to provide various parametric analysis functionality. Related methods address this functionality. | 2011-06-30 |
20110161756 | INTEGRATED CIRCUIT AND DIAGNOSIS CIRCUIT - A integrated circuit include: a first selection circuit selecting first data from input-data or scan-data, scan-data being for performing a diagnosis of a combinational circuit, input-data being received from a combinational circuit; a first latch circuit holding first data as first output-data in accordance with a first signal; a second latch circuit holding first output-data as second output-data in accordance with which of the first signal and a second signal, the second signal being used to force the second latch circuit to hold first output-data; a third latch circuit holding first output-data as third output-data in accordance with which of the first signal and a third signal, the third signal being used to force the third latch circuit to hold first output-data; and a second selection circuit selecting second data from among the data which include second output-data and third output-data. | 2011-06-30 |
20110161757 | TAP AND LINKING MODULE FOR SCAN ACCESS OF MULTIPLE CORES WITH IEEE 1149.1 TEST ACCESS PORTS - An architecture for testing a plurality of circuits on an integrated circuit is described. The architecture includes a TAP Linking Module located between test pins on the integrated circuit and 1149.1 Test Access Ports (TAP) of the plurality of circuits to be tested. The TAP Linking Module operates in response to 1149.1 scan operations from a tester connected to the test pins to selectively switch between 1149.1 TAPs to enable test access between the tester and plurality of circuits. The TAP Linking Module's 1149.1 TAP switching operation is based upon augmenting 1149.1 instruction patterns to affix an additional bit or bits of information which is used by the TAP Linking Module for performing the TAP switching operation. | 2011-06-30 |
20110161758 | ADAPTING SCAN-BIST ARCHITECTURES FOR LOW POWER OPERATION - A Scan-BIST architecture is adapted into a low power Scan-BIST architecture. A generator | 2011-06-30 |
20110161759 | SCAN ARCHITECTURE AND DESIGN METHODOLOGY YIELDING SIGNIFICANT REDUCTION IN SCAN AREA AND POWER OVERHEAD - A scan architecture and design methodology yielding significant reduction in scan area and power overhead is generally presented. In this regard, an apparatus is introduced comprising a plurality of combinatorial logic clouds, scan cells coupled with the combinatorial logic clouds, the scan cells to load test vectors, wherein the scan cells comprise a plurality of first type scan cells and second type scan cells sequentially coupled with separate combinatorial logic cloud outputs, and a first scan clock and a second scan clock, wherein the first scan clock controls the first type scan cells and the second scan clock controls the second type scan cells. Other embodiments are also described and claimed. | 2011-06-30 |
20110161760 | ON-CHIP FUNCTIONAL DEBUGGER AND A METHOD OF PROVIDING ON-CHIP FUNCTIONAL DEBUGGING - An on-chip functional debugger includes one or more functional blocks each providing one or more functional outputs. A hierarchical selection tree is formed by one or more selectors having the output of one of the selectors as a final output and individual selector inputs coupled either to a functional output from the functional blocks or to an output of another selector. A selection signal coupled to the select input of each of the selectors to enable a selected one of its output. An output node coupled to the final output. A method of providing on-chip functional debugging is also provided. A desired functional output from one or more available functional outputs is selected and then the selected functional output is coupled to an output node. | 2011-06-30 |