26th week of 2016 patent applcation highlights part 68 |
Patent application number | Title | Published |
20160190158 | ARRAY SUBSTRATE AND DISPLAY PANEL - The disclosure provides an array substrate and a display panel. The array substrate comprises a display region and a non-display region surrounding the display region comprising a first non-display sub region at one side of the display region. An. integrated circuit chip is arranged in the first non-display sub region. The display region comprises data lines arranged along a first direction, first conductive lines comprising gate lines or common lines and arranged along a second direction, and second conductive lines. A first insulating layer having through holes is arranged between the first conductive lines and the second conductive lines. Each of the first conductive lines electrically connects to one end of the second conductive lines through corresponding through holes, and the other end of the second conductive lines and the data lines electrically connect to the integrated circuit chip. The array substrate has a narrower bezel. | 2016-06-30 |
20160190159 | ARRAY SUBSTRATE AND METHOD FOR MANUFACTURING THE SAME, DISPLAY DEVICE - An array substrate is disclosed. The array substrate includes gate lines and data lines, and first and second signal lines. A first data line is between first and second pixel units, respectively including first and second film transistors. A first gate line is electrically connected to the gate electrodes of the first and second film transistors. The second electrode of the second film transistor is electrically connected to the first data line, and the second electrode of the first film transistor is electrically connected to the first signal line. The array substrate also includes a common electrode layer partially located between a third pixel unit and the first pixel unit, which is electrically insulated. In addition, a portion of the common electrode layer between the first pixel unit and the second pixel unit overlaps the first data line. | 2016-06-30 |
20160190160 | ARRAY SUBSTRATE FOR DISPLAY DEVICE - The array substrate for display device includes: a substrate; a signal line disposed on the substrate; a first color filter disposed on one side of the signal line; a second color filter disposed on the other side of the signal line; and an overlapping portion disposed to overlap part of the first color filter and part of the second color filter. The first color filter extends to overlap the signal line and the overlapping portion is disposed on the other side of the signal line so as not to overlap the signal line. | 2016-06-30 |
20160190161 | ARRAY SUBSTRATE AND METHOD OF MANUFACTURING THE SAME, AND DISPLAY DEVICE - The present disclosure provides an array substrate and a method of manufacturing the same, and a display device comprising the array substrate. The array substrate comprises: a substrate; gate lines and data lines arranged to intersect one another on the substrate; a gate line connection conducting wire layer provided between the gate lines and the substrate and below the gate lines; and /or, a data line connection conducting wire layer provided in regions of the array substrate corresponding to the data lines; wherein the gate line connection conducting wire layer is electrically isolated from the data line connection conducting wire layer. | 2016-06-30 |
20160190162 | ARRAY SUBSTRATE AND METHOD OF MANUFACTURING THE SAME, AND DISPLAY DEVICE - The present disclosure provides an array substrate and a method of manufacturing the same, and a display device. TA connecting portion is provided within the overlapping region between the first signal line and the second signal line, is electrically conductive and directly contacts the second signal line. Thus, even when the upper second signal line is broken due to the large step difference within the overlapping region between the first signal line and the second signal line, the connecting portion electrically connected with the broken second signal line can still electrically connect and conduct the broken second signal line, thereby avoiding transmission of signal from being adversely affected by the broken signal line within the overlapping region. | 2016-06-30 |
20160190163 | TFT ARRAY SUBSTRATE AND METHOD FOR MANUFACTURING THE SAME, AND DISPLAY DEVICE - Embodiments of the present disclosure provide a method for manufacturing a TFT array substrate. The method comprises, forming a passivation layer on a substrate formed with a data line, the passivation layer including a first portion of passivation layer over the data line and a second portion of passivation layer over regions other than the data line; and reducing the first portion of passivation layer by a first preset thickness, so that a thickness of the first portion of passivation layer is less than a thickness of the second portion of passivation layer. In abovementioned method, since a portion of passivation layer over the data line is reduced by certain thickness so that the thickness of the passivation layer over the data line is less than the thickness of the passivation layer over regions other than the data line, it achieves a smaller drop height caused by the data line, thereby alleviating or overcoming problems such as light leakage, contrast decay caused by presence of the drop height in the array substrate, and achieving better display quality. Embodiments of the present disclosure also provide a TFT array substrate and a display device comprising the abovementioned TFT array substrate. | 2016-06-30 |
20160190164 | THIN FILM TRANSISTOR CIRCUIT DEVICE AND METHOD OF MANUFACTURING THE SAME - A thin film transistor (TFT) circuit device comprises a substrate comprising a major surface; a gate line formed over the substrate and extending in a first direction when viewed in a viewing direction perpendicular to the major surface; an insulating layer formed over the gate line; an electrically conductive line formed over the insulating layer and extending in a second direction when viewed in the viewing direction, the second direction being different from the first direction, the electrically conductive line comprising a source line or a data line; and a semiconductor piece formed over the substrate. The semiconductor piece comprises a portion which is located between the substrate and the gate line and overlaps the gate line and the electrically conductive line at an intersection of the gate line and the electrically conductive line when viewed in the viewing direction. | 2016-06-30 |
20160190165 | LIQUID CRYSTAL DISPLAY DEVICE WITH OXIDE THIN FILM TRANSISTOR - A display device is discussed. The display device includes a substrate having a display area and a pad area in a periphery of the display area, the display area including a plurality of pixel regions; a thin film transistor having a channel layer, and on the substrate; a gate link line and a first common voltage line arranged to cross each other, and having a first insulation film interposed therebetween; a second common voltage line and a data link line arranged to cross each other, and having second insulation film interposed therebetween; a first pattern disposed on the first insulation film; and a second pattern disposed. on the second insulation film, wherein the channel layer, the first pattern and the second pattern are formed of the same material. | 2016-06-30 |
20160190166 | DISPLAY APPARATUS - A display apparatus includes a substrate having a display area defined in a non rectangular shape, and a non-display area surrounding the display area; an image display portion including a plurality of gate lines, a plurality of data lines and a plurality of pixels prepared on the display area; a display pad portion prepared at one side of the substrate; a plurality of data link lines for connecting the plurality of data lines to the display pad portion; and one or more dummy capacitors prepared in some data link lines among the plurality of data link lines. | 2016-06-30 |
20160190167 | THIN-FILM TRANSISTOR PANEL - Embodiments of the present disclosure provide a thin-film transistor (TFT) panel structured to prevent the deterioration of image quality due to the luminance change of backlight. According to an embodiment, the TFT panel includes: an insulating substrate; a first gate line and a first data line which are formed on the insulating substrate to be insulated from each other and cross each other; a first subpixel electrode which is formed on the insulating substrate and connected to the first gate line and the first data line by a first TFT; a second subpixel electrode which is formed on the insulating substrate and separated from the first subpixel electrode; a connecting electrode which is directly connected to any one of the first and second subpixel electrodes and capacitively coupled to the other one of the first and second subpixel electrodes; a semiconductor pattern which is formed between the connecting electrode and the insulating substrate; and a light-shielding pattern which is formed between the semiconductor pattern and the insulating substrate, is overlapped by the connecting electrode, and blocks light. | 2016-06-30 |
20160190168 | SILICON-GERMANIUM FIN FORMATION - Forming a set of semiconductor fins is disclosed. Forming the set of semiconductor fins can include forming a base structure including a silicon substrate, an insulator layer stacked on the silicon substrate, and a plurality of silicon semiconductor fins each stacked directly on the insulator layer. Forming the set of semiconductor fins can include depositing a first atomic layer of germanium atoms on a first set of semiconductor fins in the plurality of semiconductor fins and annealing the first atomic layer and the first set of semiconductor fins. Forming the set of semiconductor fins can include forming, from the annealing, a first set of silicon-germanium semiconductor fins. | 2016-06-30 |
20160190169 | LTPS TFT Substrate Structure and Method of Forming the Same - A method of forming an LTPS TFT substrate includes: Step | 2016-06-30 |
20160190170 | METHOD FOR FABRICATING A SEMICONDUCTOR DEVICE - The object of the invention is to provide a method for fabricating a semiconductor device having a peeled layer bonded to a base material with curvature. Particularly, the object is to provide a method for fabricating a display with curvature, more specifically, a light emitting device having an OLED bonded to a base material with curvature. An external force is applied to a support originally having curvature and elasticity, and the support is bonded to a peeled layer formed over a substrate. Then, when the substrate is peeled, the support returns into the original shape by the restoring force, and the peeled layer as well is curved along the shape of the support. Finally, a transfer object originally having curvature is bonded to the peeled layer, and then a device with a desired curvature is completed. | 2016-06-30 |
20160190171 | ARRAY SUBSTRATE, DISPLAY PANEL AND METHOD FOR PREPARING ARRAY SUBSTRATE - The invention provides an array substrate, a display panel and a method for preparing an array substrate. The array substrate includes multiple low temperature poly-silicon (LTPS) thin film transistors arranged in an array. Each LTPS thin film transistor includes: a substrate; a LTPS layer, a source, a drain and a first conductive layer disposed on a same surface of the substrate, the source and the drain respectively being arranged at two sides of the LTPS layer and electrically connected with the LTPS layer, the drain being electrically connected with the first conductive layer; an insulating layer disposed on the LTPS layer, the source, the drain and the first conductive layer; a gate disposed on the insulating layer and corresponding to the LTPS layer; a passivation layer disposed on the gate; and a second conductive layer disposed on the passivation layer and corresponding to the first conductive layer. | 2016-06-30 |
20160190172 | ARRAY SUBSTRATE, DISPLAY DEVICE AND METHOD FOR FABRICATING ARRAY SUBSTRATE - The invention provides an array substrate, a method therefor and a display device. The array substrate includes: a substrate, and a thin film transistor (TFT) and a pull-down capacitor disposed on the substrate. The TFT includes: a gate, a gate insulating layer, a channel layer, a source, a drain and a passivation layer. The passivation layer is disposed with a via hole corresponding to the drain, a pixel electrode is connected to the drain through the via hole. The pull-down capacitor includes: a first conductive layer, a first spacer layer, a filling layer, a second spacer layer and a second conductive layer successively stacked on the substrate. The sum of thicknesses of the filling layer and the first spacer layer is greater than the sum of thicknesses of the drain and the channel layer, to make the second conductive layer and the pixel electrode be located at different levels. | 2016-06-30 |
20160190173 | DISPLAY APPARATUS - A display apparatus includes a first pixel and a second pixel adjacent to each other, wherein a first channel region of a driving transistor of the first pixel has a reverse U-shaped pattern, and a second channel region of a driving transistor of the second pixel has a pattern opposite the pattern of the first channel region. | 2016-06-30 |
20160190174 | Driver Circuit, Display Device, And Electronic Device - To suppress malfunctions in a shift register circuit. A shift register having a plurality of flip-flop circuits is provided. The flip-flop circuit includes a transistor | 2016-06-30 |
20160190175 | METHOD FOR MANUFACTURING OXIDE SEMICONDUCTOR DEVICE - An object is to provide a semiconductor device having a structure with which parasitic capacitance between wirings can be sufficiently reduced. An oxide insulating layer serving as a channel protective layer is formed over part of an oxide semiconductor layer overlapping with a gate electrode layer. In the same step as formation of the oxide insulating layer, an oxide insulating layer covering a peripheral portion of the oxide semiconductor layer is formed. The oxide insulating layer which covers the peripheral portion of the oxide semiconductor layer is provided to increase the distance between the gate electrode layer and a wiring layer formed above or in the periphery of the gate electrode layer, whereby parasitic capacitance is reduced. | 2016-06-30 |
20160190176 | ANALOG CIRCUIT AND SEMICONDUCTOR DEVICE - An object is to obtain a semiconductor device having a high sensitivity in detecting signals and a wide dynamic range, using a thin film transistor in which an oxide semiconductor layer is used. An analog circuit is formed with the use of a thin film transistor including an oxide semiconductor which has a function as a channel formation layer, has a hydrogen concentration of 5×10 | 2016-06-30 |
20160190177 | DISPLAY DEVICE - A display device includes a pixel portion in which a pixel electrode layer is arranged in a matrix, and an inverted staggered thin film transistor having a combination of at least two kinds of oxide semiconductor layers with different amounts of oxygen is provided corresponding to the pixel electrode layer. In the periphery of the pixel portion in this display device, a pad portion is provided to be electrically connected to a common electrode layer formed on a counter substrate through a conductive layer made of the same material as the pixel electrode layer. One objection of our invention to prevent a defect due to separation of a thin film in various kinds of display devices is realized, by providing a structure suitable for a pad portion provided in a display panel. | 2016-06-30 |
20160190178 | ARRAY SUBSTRATE, MANUFACTURE METHOD THEREOF, AND DISPLAY DEVICE - An array substrate is disclosed. The Array substrate includes gate and data lines, where the gate lines and the data lines cross each other. The pixel units include pixel electrodes and common electrodes, and the common electrode comprises a first slot extending in a direction of the data lines. The first slot at least partially overlaps at least one of the pixel electrodes. In addition, the gate lines each include an aperture region, where the aperture region of each gate line at least partially overlaps at least one of the first slots. Furthermore, shielding electrodes and shielding branch electrodes are provided in the direction of the data lines, where the shielding electrodes at least partially overlap the data lines, and where the shielding branch electrodes are provided in the aperture region, and the shielding branch electrodes at least partially overlap the gate lines. | 2016-06-30 |
20160190179 | Pad Structure and Display Device Having the Same - The present disclosure provides a pad structure and associated display device. The pad structure comprises: a plurality of line on glass (LOG) lines that are arranged in parallel in a first direction and in a film bonding area, wherein each of the LOG lines includes a plurality of metal layers of which at least one extends to an outside of the film bonding area, wherein the film bonding area is in a non-active area of a substrate, and wherein the LOG lines are spaced apart from each other, wherein the pad structure further comprises an overcoat layer that is positioned in an external area of the film bonding area, and is adjacent to both boundaries of the film bonding area, wherein the overcoat layer includes a removed portion between each of the LOG lines, wherein the removed portion extends in the first direction. | 2016-06-30 |
20160190180 | Array substrate and display panel - An array substrate and a display panel. The array substrate includes an active region and a peripheral circuitry region surrounding the active region; a plurality of scan lines and a plurality of data lines intersected with and insulated from the scan lines; a plurality of pixel driving circuit units disposed at intersection areas between the scan lines and the data lines; a plurality of first electrodes respectively electrically connected to the plurality of pixel driving circuit units and disposed in the active region and the peripheral circuitry region of the array substrate; and a plurality of first connection lines configured to electrically connect the pixel driving circuit units to the corresponding first electrodes. | 2016-06-30 |
20160190181 | SEMICONDUCTOR DEVICE AND PRODUCTION METHOD THEREFOR - A semiconductor device includes: a plurality of thin film transistors including a gate electrode, a gate dielectric layer, a semiconductor layer formed on the gate dielectric layer, and a source electrode and a drain electrode provided on the semiconductor layer; a source metal layer including a global line which supplies a common signal to the plurality of thin film transistors, the global line being made of the same electrically conductive film as the source electrode and drain electrode; and a dielectric protection layer covering the plurality of thin film transistors and the source metal layer. The source metal layer includes a lower layer and an upper layer stacked on a portion of the lower layer. The global line has a first layer structure including the lower layer and the upper layer, and at least a portion of each source electrode and of each drain electrode that is located on the semiconductor layer has a second layer structure including the lower layer but not including the upper layer. | 2016-06-30 |
20160190182 | Display Panel and Display Device - A display panel includes a TFT substrate, an opposite substrate and a display layer. A TFT of the TFT substrate has a drain. A first insulating layer has a first sub-layer and a second sub-layer disposed on the drain sequentially. The first sub-layer has a first opening with a first width. The second sub-layer has a second opening with a second width on the first opening. The first and second openings form a first via, and the second width is greater than the first width. A passivation layer is disposed on the first insulating layer. A second insulating layer is disposed on the passivation layer. A pixel electrode layer is disposed on the second insulating layer and disposed in the first via to connect the drain. The display layer is disposed between the TFT substrate and the opposite substrate. | 2016-06-30 |
20160190183 | SEMICONDUCTOR DEVICE - A semiconductor device that is less influenced by variations in characteristics between transistors or variations in a load, and is efficient even for normally-on transistors is provided. The semiconductor device includes at least a transistor, two wirings, three switches, and two capacitors. A first switch controls conduction between a first wiring and each of a first electrode of a first capacitor and a first electrode of a second capacitor. A second electrode of the first capacitor is connected to a gate of the transistor. A second switch controls conduction between the gate and a second wiring. A second electrode of the second capacitor is connected to one of a source and a drain of the transistor. A third switch controls conduction between the one of the source and the drain and each of the first electrode of the first capacitor and the first electrode of the second capacitor. | 2016-06-30 |
20160190184 | THIN FILM TRANSISTOR SUBSTRATE AND METHOD FOR MANUFACTURING THE SAME - A thin film transistor (TFT) located on a thin film transistor substrate includes a first insulating film formed so as to cover a gate electrode, a channel layer that is formed at a position on the first insulating film overlapping the gate electrode and formed of an oxide semiconductor, a second insulating film formed on the channel layer, and a third insulating film formed so as to cover the second insulating film. A source electrode and a drain electrode are formed on the third insulating film. Each of the source electrode and the drain electrode is connected to the channel layer through the corresponding one of contact holes penetrating the second insulating film and the third insulating film. | 2016-06-30 |
20160190185 | SURFACE FLAW MODIFICATION FOR STRENGTHENING OF GLASS ARTICLES - Disclosed are controlled chemical etching processes used to modify the geometry of surface flaws in thin glass substrates and glass substrate assemblies formed therefrom, and in particular glass substrates suitable for the manufacture of active matrix displays that are essentially free of alkali metal oxides such as Na | 2016-06-30 |
20160190186 | THIN FILM TRANSISTOR ARRAY PANEL AND MANUFACTURING METHOD THEREOF - A thin film transistor array panel includes a substrate, an insulation layer, a first semiconductor, and a second semiconductor. The insulation layer is disposed on the substrate and includes a stepped portion. The first semiconductor is disposed on the insulation layer. The second semiconductor is disposed on the insulation layer and includes a semiconductor material different than the first semiconductor. The stepped portion is spaced apart from an edge of the first semiconductor. | 2016-06-30 |
20160190187 | IMAGING DEVICE INCLUDING UNIT PIXEL CELL - An imaging device comprising a unit pixel cell comprising: a photoelectric converter that generates an electric signal through photoelectric conversion of incident light; and a signal detection circuit that detects the electric signal, the signal detection circuit comprising a first transistor that amplifies the electric signal, a second transistor that selectively transmits output of the first transistor to outside of the unit pixel cell, and a feedback circuit that forms a feedback loop through which the electric signal is negatively fed back, the feedback loop not passing through the first transistor. | 2016-06-30 |
20160190188 | IMAGING DEVICE INCLUDING UNIT PIXEL CELL - An imaging device includes: a unit pixel cell comprising: a photoelectric converter generating an electric signal and comprising a first and second electrodes and a photoelectric conversion film located therebetween, the first electrode being located on a light receiving side of the photoelectric conversion film, a signal detection circuit detecting the electric signal and comprising a first transistor and a second transistor that are connected to the second electrode, the first transistor amplifying the electric signal, and a capacitor circuit comprising a first capacitor and a second capacitor having a capacitance value larger than that of the first capacitor that are serially connected to each other, the capacitor circuit being provided between the second electrode and a reference voltage; and a feedback circuit comprising the first transistor and an inverting amplifier and negatively feeding back the electric signal to the second transistor via the first transistor and the inverting amplifier. | 2016-06-30 |
20160190189 | PHOTOELECTRIC CONVERSION DEVICE - To provide a photoelectric conversion device which prevents a reset time from being made long when a large quantity of light is entered. There is provided a photoelectric conversion device equipped with a photodiode which causes a photoelectric current corresponding to a quantity of incident light to flow, a reset circuit which charges a parasitic capacitance of the photodiode to a reset voltage, a voltage limit circuit which prevents the voltage of the parasitic capacitance of the photodiode from being lower than a prescribed voltage, and an output circuit which outputs the voltage of the parasitic capacitance of the photodiode. | 2016-06-30 |
20160190190 | Image Sensor with Low Step Height between Back-side Metal and Pixel Array - A CMOS image sensor and a method of forming are provided. The CMOS image sensor may include a device wafer. A conductive feature may be formed on a back-side surface of the device wafer. The device wafer may include a pixel formed therein. A passivation layer may be formed over the back-side surface of the device wafer and the conductive feature. A grid film may be formed over the passivation layer. The grid film may be patterned to accommodate a color filter. The grid film pattern may align the color filter to corresponding pixel in the device wafer. A portion of the grid film formed over the conductive feature may be reduced to be substantially planar with portions of the grid film adjacent to the conductive feature. The patterning and reducing may be performed according to etching processes, chemical mechanical processes, and combinations thereof. | 2016-06-30 |
20160190191 | CMOS IMAGE SENSOR STRUCTURE WITH CROSSTALK IMPROVEMENT - A semiconductor device includes a substrate, a semiconductor layer, light-sensing devices, a transparent dielectric layer and a grid shielding layer. The semiconductor layer overlies the substrate, and has a first surface and a second surface opposite to the first surface. The semiconductor layer includes microstructures disposed on the second surface of the semiconductor layer. The light-sensing devices are disposed on the first surface of the semiconductor layer. The transparent dielectric layer is disposed on the second surface of the semiconductor layer, and covers the microstructures. The grid shielding layer extends from the first surface of the semiconductor layer toward the second surface of the semiconductor layer, and surrounds each of the light-sensing devices to separate the light-sensing devices from each other, in which a depth of the grid shielding layer is greater than two-thirds of a thickness of the semiconductor layer. | 2016-06-30 |
20160190192 | CHIP SCALE PACKAGE CAMERA MODULE WITH GLASS INTERPOSER AND METHOD FOR MAKING THE SAME - One or more embodiments disclosed herein are directed to a chip scale package camera module that includes a glass interposer between a lens and an image sensor. In some embodiments, the glass interposer is made from one or more layers of optical quality glass and includes an infrared filter coating. The glass interposer also includes electrically conductive paths to connect the image sensor, mounted on one side of the glass interposer, with other components such as capacitors, which may be mounted on a different side of the glass interposer, and the rest of the camera system. The conductive layers include traces and vias that are formed in the glass interposer in areas away from the path of light in the camera module, such that the traces and vias do not block the light between the lens and the image sensor. | 2016-06-30 |
20160190193 | TWO-DIMENSIONAL SOLID-STATE IMAGE CAPTURE DEVICE WITH POLARIZATION MEMBER AND COLOR FILTER FOR SUB-PIXEL REGIONS AND POLARIZATION-LIGHT DATA PROCESSING METHOD THEREFOR - A two-dimensional solid-state image capture device includes pixel areas arranged in a two-dimensional matrix, each pixel area being constituted by multiple sub-pixel regions, each sub-pixel region having a photoelectric conversion element. A polarization member is disposed at a light incident side of at least one of the sub-pixel regions constituting each pixel area. The polarization member has strip-shaped conductive light-shielding material layers and slit areas, provided between the strip-shaped conductive light-shielding material layers. Each sub-pixel region further has a wiring layer for controlling an operation of the photoelectric conversion element, and the polarization member and the wiring layer are made of the same material and are disposed on the same virtual plane. | 2016-06-30 |
20160190194 | PHOTODETECTOR FOCAL PLANE ARRAY SYSTEMS AND METHODS - A photodetector focal plane array system, comprising: a substrate comprising a plurality of photosensitive regions; and a microcomponent disposed adjacent to each of the plurality of photosensitive regions operable for receiving incident radiation and directing a photonic nanojet into the associated photosensitive region. Optionally, each of the microcomponents comprises one of a microsphere and a microcylinder. Each of the microcomponents has a diameter of between ˜λ and ˜100λ, where λ is the wavelength of the incident radiation. Each of the microcomponents is manufactured from a dielectric or semiconductor material. Each of the microcomponents has an index of refraction of between ˜1.4 and ˜3.5. Optionally, high-index components can be embedded in a lower index material. The microcomponents form an array of microcomponents disposed adjacent to the substrate. | 2016-06-30 |
20160190195 | OPTICAL NAVIGATION MODULE CAPABLE OF PERFORMING LATERAL DETECTION AND ADJUSTING TRACKING DISTANCE - There is provided an optical navigation module including an optical package and a light reflective element. The optical package includes an image sensor which has a sensor surface. The light reflective element is configured to reflect light propagating parallel to the sensor surface to light propagating perpendicular to the sensor surface to impinge on the sensor surface thereby performing the lateral detection. | 2016-06-30 |
20160190196 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes a first substrate, a second substrate, a plurality of through vias (TVs), and a plurality of conductive caps. The first substrate has at least one electrical component disposed thereon. The second substrate is stacked on the first substrate. The TVs extend through the second substrate to be electrically connected to the at least one electrical component of the first substrate. The conductive caps respectively cover the TVs, and the conductive caps are electrically isolated from each other. | 2016-06-30 |
20160190197 | PIXEL ARRAY AREA OPTIMIZATION USING STACKING SCHEME FOR HYBRID IMAGE SENSOR WITH MINIMAL VERTICAL INTERCONNECTS - Embodiments of a hybrid imaging sensor that optimizes a pixel array area on a substrate using a stacking scheme for placement of related circuitry with minimal vertical interconnects between stacked substrates and associated features are disclosed. Embodiments of maximized pixel array size/die size (area optimization) are disclosed, and an optimized imaging sensor providing improved image quality, improved functionality, and improved form factors for specific applications common to the industry of digital imaging are also disclosed. | 2016-06-30 |
20160190198 | IMAGE SENSOR - An image sensor includes a pixel array chip, a logic chip, and an interposed layer. The interposed layer is disposed on the pixel array chip. The logic chip is disposed on the interposed layer. The interposed layer includes a connecting part, a shielding part, and a metal-diffusion barrier layer. The connecting part electrically connects a first interconnection wire of the pixel array chip and a second interconnection wire of the logic chip. The connecting part includes a first metallic element. The shielding part is disposed spatially apart from the connecting part and electrically grounded to suppress an electrical coupling between the pixel array chip and the logic chip. The shielding part includes a second metallic element. The metal-diffusion barrier layer is disposed on top and bottom surfaces of the interposed layer to limit diffusion of electrical charges to the pixel array chip and the logic chip. | 2016-06-30 |
20160190199 | IMAGE SENSOR DEVICE WITH FIRST AND SECOND SOURCE FOLLOWERS AND RELATED METHODS - An image sensor device may include an array of image sensing pixels arranged in rows and columns. Each image sensing pixel may include an image sensing photodiode, a first source follower transistor coupled to the image sensing photodiode, and a switch coupled to the image sensing photodiode. Each image sensor device may include a second source follower transistor coupled to the switch, and a row selection transistor coupled to the first and second source follower transistors. | 2016-06-30 |
20160190200 | SOLID-STATE IMAGING DEVICE, MANUFACTURING METHOD THEREOF, AND ELECTRONIC APPARATUS - A solid-state imaging device having a backside illuminated structure, includes: a pixel region in which pixels each having a photoelectric conversion portion and a plurality of pixel transistors are arranged in a two-dimensional matrix; an element isolation region isolating the pixels which is provided in the pixel region and which includes a semiconductor layer provided in a trench by an epitaxial growth; and a light receiving surface at a rear surface side of a semiconductor substrate which is opposite to a multilayer wiring layer. | 2016-06-30 |
20160190201 | IMAGE SENSORS EMPLOYING SENSITIZED SEMICONDUCTOR DIODES - In various example embodiments, the inventive subject matter is an image sensor and methods of formation of image sensors. In an embodiment, the image sensor comprises a semiconductor substrate and a plurality of pixel regions. Each of the pixel regions includes an optically sensitive material over the substrate with the optically sensitive material positioned to receive light. A pixel circuit for each pixel region is also included in the sensor. Each pixel circuit comprises a charge store formed on the semiconductor substrate and a read out circuit. A non-metallic contact region is between the charge store and the optically sensitive material of the respective pixel region, the charge store being in electrical communication with the optically sensitive material of the respective pixel region through the non-metallic contact region. | 2016-06-30 |
20160190202 | X-RAY IMAGE SENSOR SUBSTRATE - A thin film transistor substrate ( | 2016-06-30 |
20160190203 | SEMICONDUCTOR DEVICE HAVING SOI SUBSTRATE - There is provided a semiconductor device and a method for manufacturing a semiconductor device. Within the N-type semiconductor layer formed from a high resistance N-type substrate, the P-type well diffusion layer and P-type extraction layer are formed and are fixed to ground potential. Due thereto, a depletion layer spreading on the P-type well diffusion layer side does not reach the interlayer boundary between the P-type well diffusion layer and the buried oxide film. Hence, the potential around the surface of the P-type well diffusion layer is kept at a ground potential. Accordingly, when the voltages are applied to the backside of the N-type semiconductor layer and a cathode electrode, a channel region at the MOS-type semiconductor formed as a P-type semiconductor layer is not activated. Due thereto, leakage current that may occur independently of a control due to the gate electrode of a transistor can be suppressed. | 2016-06-30 |
20160190204 | METHODS OF FORMING IMAGE SENSOR INTEGRATED CIRCUIT PACKAGES - A method of forming image sensor packages may include performing a molding process. Mold material may be formed either on a transparent substrate in between image sensor dies, or on a removable panel in between transparent substrates attached to image sensor dies. Redistribution layers may be formed before or after the molding process. Mold material may be formed after forming redistribution layers so that the mold material covers the redistribution layers. In these cases, holes may be formed in the mold material to expose solder pads on the redistribution layers. Alternatively, redistribution layers may be formed after the molding process and the redistribution layers may extend over the mold material. Image sensor dies may be attached to a glass or notched glass substrate with dam structures. The methods of forming image sensor packages may result in hermetic image sensor packages that prevent exterior materials from reaching the image sensor. | 2016-06-30 |
20160190205 | LIGHT-EMITTING DEVICE AND METHOD FOR MANUFACTURING THE SAME - A light-emitting device is provided. The light-emitting device comprises: a semiconductor structure comprising a first type semiconductor layer, a second type semiconductor layer, and an active layer between the first type semiconductor layer and the second type semiconductor layer; and an isolation region through the second type semiconductor and the active layer to separate the semiconductor structure into a first part and a second part on the first substrate; wherein the second part functions as a low-resistance resistor and loses its make diode behavior, the active layer in the first part is capable of generating light, and the active layer in the second part is incapable of generating light. | 2016-06-30 |
20160190206 | ACOUSTIC WAVE DEVICE STRUCTURE, INTEGRATED STRUCTURE OF POWER AMPLIFIER AND ACOUSTIC WAVE DEVICE, AND FABRICATION METHODS THEREOF - An integrated structure of power amplifier and acoustic wave device comprises: a compound semiconductor epitaxial substrate, a power amplifier upper structure formed on a first side of said compound semiconductor epitaxial substrate, and a film bulk acoustic resonator formed on a second side of said compound semiconductor epitaxial substrate; wherein forming an epitaxial structure on a compound semiconductor substrate to form said compound semiconductor epitaxial substrate; wherein said first side of said compound semiconductor epitaxial substrate and said power amplifier upper structure form a power amplifier; said second side of said compound semiconductor epitaxial substrate and said film bulk acoustic resonator form an acoustic wave device; the integrated structure of power amplifier and acoustic wave device on the same compound semiconductor epitaxial substrate is capable of reducing the component size, optimizing the impedance matching, and reducing the signal loss between power amplifier and acoustic wave device. | 2016-06-30 |
20160190207 | INTEGRATED CIRCUITS INCLUDING MAGNETIC TUNNEL JUNCTIONS FOR MAGNETORESISTIVE RANDOM-ACCESS MEMORY AND METHODS FOR FABRICATING THE SAME - Integrated circuits that include a magnetic tunnel junction (MTJ) for a magnetoresistive random-access memory (MRAM) and methods for fabricating such integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes forming a lower electrode on a metal interconnect. The metal interconnect is disposed above a semiconductor substrate and is aligned with a normal axis that is substantially perpendicular to the semiconductor substrate. The lower electrode includes a conductive metal plug. A MTJ stack is formed on the lower electrode aligned with the normal axis. | 2016-06-30 |
20160190208 | SELECTOR-BASED NON-VOLATILE CELL FABRICATION UTILIZING IC-FOUNDRY COMPATIBLE PROCESS - A circuit operable as a non-volatile memory cell, formed in part from a volatile selection device, is provided. The circuit can be fabricated utilizing Integrated Circuit (IC)-Foundry compatible processes to simplify manufacturing, reduce cost and improve yield. For instance, the circuit can comprise a set of transistors fabricated at least in part with front-end-of-line IC processes, and can comprise the volatile selection device and a set of interconnects fabricated at least in part with back-end-of-line IC processes. In further embodiments, the volatile selection device can be a two-terminal, volatile resistive-switching device connected at one end to a gate of an n-well transistor, and connected at a second end to a gate of a p-well transistor. | 2016-06-30 |
20160190209 | PHASE CHANGE MEMORY STACK WITH TREATED SIDEWALLS - Memory devices and methods for fabricating memory devices have been disclosed. One such memory device includes a first electrode material formed on a word line material. A selector device material is formed on the first electrode material. A second electrode material is formed on the selector device material. A phase change material is formed on the second electrode material. A third electrode material is formed on the phase change material. An adhesion species is plasma doped into sidewalls of the memory stack and a liner material is formed on the sidewalls of the memory stack. The adhesion species intermixes with an element of the memory stack and the sidewall liner to terminate unsatisfied atomic bonds of the element and the sidewall liner. | 2016-06-30 |
20160190210 | COMPLEMENTARY CARBON NANOTUBE NEURON DEVICE - A method for forming a semiconductor device includes providing a substrate structure, which includes a carbon nanotube supported by two support structures on a substrate. The carbon nanotube includes a first portion and a second portion having different conductivity types. A multi-layer film structure is formed surrounding the carbon nanotube, the multi-layer film structure including a conductive material layer sandwiched between two dielectric layers. A plurality of first electrodes are formed surrounding the multi-layer film structure surrounding a channel region of the first portion, and a plurality of second electrodes are formed surrounding the multi-layer film structure surrounding a channel region of the second portion. A third electrode is formed to contact one end of the carbon nanotube, and a fourth electrode is formed to contact the other end of the carbon nanotube. A fifth electrode is formed and coupled to a center portion of the carbon nanotube. | 2016-06-30 |
20160190211 | SOLID-STATE IMAGE PICKUP DEVICE AND MANUFACTURING AND THEREOF, AND ELECTRONIC APPARATUS - Provided is a solid-state image pickup device that makes it possible to enhance image quality, and a manufacturing method thereof, and an electronic apparatus. A solid-state image pickup device includes a pixel section that includes a plurality of pixels, the pixels each including one or more organic photoelectric conversion sections, wherein the pixel section includes an effective pixel region and an optical black region, and the organic photoelectric conversion sections of the optical black region include a light-shielding film and a buffer film on a light-incidence side. | 2016-06-30 |
20160190212 | ORGANIC LIGHT EMITTING DISPLAY DEVICE AND METHOD OF MANUFACTURING THE SAME - An organic light emitting display device includes a substrate, first electrodes disposed on the substrate; an organic light emitting layer formed on the first electrodes; a second electrode disposed on the organic light emitting layer; and a color filter layer formed on the second electrode. The color filter layer includes a first color filter, a second color filter, and a third color filter. The second color filter and the third color filter are disposed pixel blocks included in the first color filter. | 2016-06-30 |
20160190213 | LIGHT EMITTING DISPLAY DEVICE - Provided is a light emitting display device. | 2016-06-30 |
20160190214 | Light Emitting Device and Method of Manufacturing the Same - A light-emitting device structured so as to increase the amount of light taken out in a certain direction is provided as well as a method of manufacturing this light emitting device. As a result of etching treatment, an upper edge portion of an insulator ( | 2016-06-30 |
20160190215 | Light-Emitting Device, Electronic Appliance, and Lighting Device - A light-emitting device and a lighting device each of which includes a plurality of light-emitting elements exhibiting light with different wavelengths are provided. The light-emitting device and the lighting device each have an element structure in which each of the light-emitting elements emits only light with a desired wavelength, and thus the light-emitting elements have favorable color purity. In the light-emitting element emitting light (λ | 2016-06-30 |
20160190216 | DISPLAY DEVICE COMPRISING BENDING SENSOR - A display device including a bending sensor is provided. A display device including a bending sensor may include a flexible substrate including a display area and a bezel area surrounding the display area; and the bending sensor including a curved unit disposed in the bezel area and in which an electric change occurs when the flexible substrate is bent, and a detection unit detecting bending information by sensing the electric change. | 2016-06-30 |
20160190217 | ORGANIC LIGHT EMITTING DISPLAY DEVICE AND MANUFACTURING METHOD THEROF - An organic light emitting display (OLED) device, and a method for manufacturing the OLED device are discussed. The OLED device according to one embodiment includes a thin film transistor formed on a substrate; a planarization layer formed on the thin film transistor; a first bank layer including a first opening; a lower electrode formed in the first opening and connected to the thin film transistor, an end segment of the lower electrode being disposed on the first bank layer; a second bank layer formed on the first bank layer and covering the end segment of the lower electrode, the second bank layer including a second opening corresponding to the first opening; an organic emitting layer formed on the lower electrode and in the second opening; and an upper electrode formed on the organic emitting layer. | 2016-06-30 |
20160190218 | Organic light emitting display panel and method of manufacturing the same - Embodiments relate to an organic light emitting display device and a method of manufacturing the same. The organic light emitting display device includes a pixel area that includes at least a first sub pixel area. The first sub pixel area includes a color filter, a first overcoat element on the color filter, wherein a portion of the color filter at an edge portion of the first sub pixel area is not covered by the first overcoat element, and an electrode disposed on the pixel area, wherein the electrode is on the portion of the color filter not covered by the first overcoat element. | 2016-06-30 |
20160190219 | Peeling Method and Method of Manufacturing Semiconductor Device - There is provided a peeling method capable of preventing a damage to a layer to be peeled. Thus, not only a layer to be peeled having a small area but also a layer to be peeled having a large area can be peeled over the entire surface at a high yield. Processing for partially reducing contact property between a first material layer ( | 2016-06-30 |
20160190220 | MANUFACTURE METHOD OF AMOLED BACK PLATE AND STURCTURE THEREOF - The present invention provides a manufacture method of an AMOLED back plate and a structure thereof. The manufacture method of the AMOLED back plate is: sequentially deposing a buffer layer ( | 2016-06-30 |
20160190221 | THIN-FILM TRANSISTOR ARRAY SUBSTRATE AND ORGANIC LIGHT-EMITTING DISPLAY APPARATUS INCLUDING THE SAME - A thin-film transistor (TFT) array substrate includes: a driving TFT provided on a substrate; and a switching TFT provided on the substrate and including: a switching semiconductor layer including a switching channel region, a switching source region, and a switching drain region; and a switching source electrode and a switching drain electrode contacting the switching semiconductor layer. The switching source electrode includes a source contact portion contacting the switching source region, and the switching drain electrode includes a drain contact portion contacting the switching drain region. The source contact portion is doped with ions that are different from ions of the switching source region and the drain contact portion is doped with ions that are different from ions of the switching drain region. | 2016-06-30 |
20160190222 | ARRAY SUBSTRATE AND FABRICATION METHOD THEREOF, AND DISPLAY DEVICE - An array substrate and a fabrication method thereof, and a display device are provided. The array substrate comprises: a pattern of an organic light-emitting layer ( | 2016-06-30 |
20160190223 | FLEXIBLE DISPLAY - A flexible display is disclosed. In one aspect, the display includes at least one first pattern including a plurality of display elements configured to display an image and extending in a first direction. The display device also includes at least one second pattern extending in a second direction and overlapping at least a portion of the first pattern. The second pattern has a curved shape in the first direction and the second direction crosses the first direction. The first and second patterns form at least one cavity region defining a space therebetween and the first and second patterns form a mesh structure. | 2016-06-30 |
20160190224 | ORGANIC LIGHT-EMITTING DISPLAY APPARATUS AND METHOD OF MANUFACTURING THE SAME - An organic light-emitting display apparatus includes a substrate; an active layer; a gate electrode, source and drain electrodes; a first insulating layer disposed between the active layer and the gate electrode; a second insulating layer disposed between the gate electrode and the source and drain electrodes; a third insulating layer disposed over the source and drain electrodes; conductive layers disposed over the third insulating layer and electrically connected to the source and drain electrodes through the third insulating layer; a first line disposed over the second insulating layer and formed of the same material as the source and drain electrodes; a second line overlapping the first line, disposed over the third insulating layer, and formed of the same material as the conductive layer; a fourth insulating layer disposed over the third insulating layer to cover the conductive layer; and an organic light-emitting diode disposed over the fourth insulating layer. | 2016-06-30 |
20160190225 | ORGANIC LIGHT EMITTING DISPLAY DEVICE AND METHOD OF MANUFACTURING THE SAME - An organic light emitting display device and a method of manufacturing the same are provided that may reduce the resistance of a second electrode and may prevent corrosion and metal migration of a pad electrode without adding a separate mask process, or while reducing the number of mask processes. In the organic light emitting display device, an auxiliary line is connected to a second electrode through an auxiliary electrode, which is provided in the same layer as a first electrode, and a pad cover electrode is configured to cover an upper surface and a side surface of a pad connection electrode so as to prevent the pad connection electrode connected to a pad from being exposed outward. | 2016-06-30 |
20160190226 | Organic Electro-Luminescent Display Device - An organic EL display device includes an inorganic insulating film including a contact part as an opening where a contact electrode made of a conductive film is exposed, a TFT circuit layer provided on the inorganic insulating film and including a circuit including a thin film transistor, an organic EL element layer provided on the TFT circuit layer and including an organic EL element whose light emission is controlled by the circuit, and a sealing layer covering the organic EL element layer and made of an inorganic insulating material. | 2016-06-30 |
20160190227 | DISPLAY - A capacitor includes an active layer, a gate insulation layer on the active layer, a gate electrode on the gate insulation layer, an interlayer insulating layer on the gate electrode, and a first electrode on the interlayer insulating layer and connected to the active layer through at least one contact hole. | 2016-06-30 |
20160190228 | ORGANIC LIGHT EMITTING DISPLAY DEVICE - Provided is an organic light emitting display device. The organic light emitting display device includes: a plurality of sub-pixels including an anode and a cathode; an anode line configured to supply an anode voltage to the anode; and a cathode line configured to supply a cathode voltage to the cathode, and in each of the plurality of sub-pixels, a direction of an anode voltage input of the anode line and a direction of a cathode voltage input of the cathode line are different from each other and face each other in order to reduce a deviation in a potential difference between the anode and the cathode. Thus, it is possible to improve uniformity in the potential difference between the anode and the cathode caused by a line resistance. | 2016-06-30 |
20160190229 | SUBSTRATE RESISTOR WITH OVERLYING GATE STRUCTURE - A resistor device includes a resistor body disposed in a substrate and doped with a first type of dopant, an insulating layer disposed above the resistor body, and at least one gate structure disposed above the insulating layer and above the resistor body. A method includes applying a bias voltage to at least a first gate structure disposed above an insulating layer disposed above a resistor body disposed in a substrate and doped with a first type of dopant to affect a resistance of the resistor body. | 2016-06-30 |
20160190230 | Unknown - In a method for producing a capacitor, a dielectric structure is generated in a trench of a semiconductor substrate. The dielectric structure includes a plurality of adjacent dielectric layers having opposing material tensions. | 2016-06-30 |
20160190231 | SEMICONDUCTOR SWITCH - According to an embodiment, a semiconductor switch includes a first insulating film on a semiconductor substrate, a first semiconductor layer on the first insulating film, a semiconductor switch circuit on the first semiconductor layer, and a wiring on the first insulating film. The first insulating film being between the wiring and the substrate. The wiring connects the semiconductor switch circuit and a terminal. A polycrystalline semiconductor layer is between the wiring and the first insulating film. | 2016-06-30 |
20160190232 | SEMICONDUCTOR DEVICE - A highly reliable semiconductor device including an oxide semiconductor is provided. Provided is a semiconductor device including an oxide semiconductor layer, an insulating layer in contact with the oxide semiconductor layer, a gate electrode layer overlapping with the oxide semiconductor layer, and a source electrode layer and a drain electrode layer electrically connected to the oxide semiconductor layer. The oxide semiconductor layer includes a first region having a crystal whose size is less than or equal to 10 nm and a second region which overlaps with the insulating layer with the first region provided therebetween and which includes a crystal part whose c-axis is aligned in a direction parallel to a normal vector of the surface of the oxide semiconductor layer. | 2016-06-30 |
20160190233 | TRANSISTOR WITH WURTZITE CHANNEL - A device includes a source region, a drain region, and a wurtzite semiconductor between the source region and the drain region. A source-drain direction is parallel to a [01-10] direction or a [−2110] direction of the wurtzite semiconductor. The device further includes a gate dielectric over the wurtzite semiconductor, and a gate electrode over the gate dielectric. | 2016-06-30 |
20160190234 | SEMICONDUCTOR DEVICE - A semiconductor device of the embodiment includes an SiC layer of 4H-SiC structure having a surface inclined at an angle from 0 degree to 30 degrees relative to {11-20} face or {1-100} face, a gate electrode, a gate insulating film provided between the surface and the gate electrode, a n-type first SiC region provided in the SiC layer, a n-type second SiC region provided in the SiC layer, a channel forming region provided in the SiC layer between the first SiC region and the second SiC region, the channel forming region provided adjacent to the surface, and the channel forming region having a direction inclined at an angle from 60 degrees to 90 degrees relative to a <0001> direction or a <000-1> direction. | 2016-06-30 |
20160190235 | POWER SEMICONDUCTOR DEVICE - A problem associated with n-channel power MOSFETs and the like that the following is caused even by relatively slight fluctuation in various process parameters is solved: source-drain breakdown voltage is reduced by breakdown at an end of a p-type body region in proximity to a portion in the vicinity of an annular intermediate region between an active cell region and a chip peripheral portion, arising from electric field concentration in that area. To solve this problem, the following measure is taken in a power semiconductor device having a superjunction structure in the respective drift regions of a first conductivity type of an active cell region, a chip peripheral region, and an intermediate region located therebetween: the width of at least one of column regions of a second conductivity type comprising the superjunction structure in the intermediate region is made larger than the width of the other regions. | 2016-06-30 |
20160190236 | FINFET AND METHOD OF MANUFACTURING THE SAME - There is provided a method of manufacturing a Fin Field Effect Transistor (FinFET). The method may include: forming a fin on a semiconductor substrate; forming a dummy device including a dummy gate on the fin; forming an interlayer dielectric layer to cover regions except for the dummy gate; removing the dummy gate to form an opening; implanting ions to form a Punch-Though-Stop Layer (PTSL) in a portion of the fin directly under the opening, while forming reflection doped layers in portions of the fin on inner sides of source/drain regions; and forming a replacement gate in the opening. | 2016-06-30 |
20160190237 | LATCHUP REDUCTION BY GROWN ORTHOGONAL SUBSTRATES - An integrated circuit is formed by providing a heavily doped substrate of a first conductivity type, forming a lightly doped lower epitaxial layer of the first conductivity type over the substrate, implanting dopants of the first conductivity type into the lower epitaxial layer in an area for a shallow component and blocking the dopants from an area for a deep component, forming a lightly doped upper epitaxial layer over the lower epitaxial layer and activating the implanted dopants to form a heavily doped region. The shallow component is formed over the heavily doped region, and the deep component is formed outside the heavily doped region, extending through the upper epitaxial layer into the lower epitaxial layer. | 2016-06-30 |
20160190238 | NON-PLANAR SEMICONDUCTOR DEVICE WITH ASPECT RATIO TRAPPING - As disclosed herein, a semiconductor device with aspect ratio trapping including, a bulk substrate, a plurality of isolation pillars formed on the bulk substrate, wherein one or more gaps are formed between the isolation pillars, an oxide layer formed by epitaxy on the bulk substrate, between the isolation pillars, wherein the oxide layer partially fills the gaps between the isolation pillars, one or more fins formed over the oxide layer between the isolation pillars, such that the one or more fins fill the gaps between the isolation pillars, wherein the oxide layer electrically isolates the one or more fins from the bulk substrate. The size of the gaps between the isolation pillars is selected to statistically eliminate defects caused by a lattice mismatch between the bulk substrate and the oxide layer. The semiconductor device may also contain an aspect-ratio trapping layer between the bulk substrate and oxide layer. | 2016-06-30 |
20160190239 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device is provided. The semiconductor device includes a sacrificial layer formed on a substrate, an active layer formed on the sacrificial layer, a gate insulating layer and a gate electrode formed to surround a part of the active layer, a spacer disposed on at least one side of the gate electrode, a source or drain separated from the gate electrode by the spacer and disposed on the substrate, and an air gap arrange between a lower portion of the active layer and the sacrificial layer, wherein the sacrificial layer is disposed on a lower portion of the source or drain and is not disposed on a lower portion of the gate electrode. | 2016-06-30 |
20160190240 | SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF - A semiconductor structure includes a semiconductor substrate, a first active area, a second active area, a first trench, at least one raised portion, and a first dielectric. The first active area is in the semiconductor substrate. The second active area is in the semiconductor substrate. The first trench is in the semiconductor substrate and separates the first active area and the second active area from each other. The raised portion is raised from the semiconductor substrate and is disposed in the first trench. The first dielectric is in the first trench and covers the raised portion. | 2016-06-30 |
20160190241 | Semiconductor Device Including an Isolation Structure and Method of Manufacturing a Semiconductor Device - An embodiment of a semiconductor device comprises a first load terminal contact area at a first side of a semiconductor body. A second load terminal contact area is at a second side of the semiconductor body opposite to the first side. A control terminal contact area is at the second side of the semiconductor body. An isolation structure extends through the semiconductor body between the first and second sides. The isolation structure electrically isolates a first part of the semiconductor body from a second part of the semiconductor body. A first thickness of the first part of the semiconductor body is smaller than a second thickness of the second part of the semiconductor body. | 2016-06-30 |
20160190242 | Fin Recess Last Process for FinFet Fabrication - A method includes forming isolation regions extending from a top surface of a semiconductor substrate into the semiconductor substrate, and forming a hard mask strip over the isolation regions and a semiconductor strip, wherein the semiconductor strip is between two neighboring ones of the isolation regions. A dummy gate strip is formed over the hard mask strip, wherein a lengthwise direction of the dummy gate strip is perpendicular to a lengthwise direction of the semiconductor strip, and wherein a portion of the dummy gate strip is aligned to a portion of the semiconductor strip. The method further includes removing the dummy gate strip, removing the hard mask strip, and recessing first portions of the isolation regions that are overlapped by the removed hard mask strip. A portion of the semiconductor strip between and contacting the removed first portions of the isolation regions forms a semiconductor fin. | 2016-06-30 |
20160190243 | STRUCTURE AND FORMATION METHOD OF FINFET DEVICE - Structures and formation methods of a semiconductor device are provided. The semiconductor device structure includes a semiconductor substrate and a fin structure over the semiconductor substrate. The semiconductor device structure also includes a gate stack covering a portion of the fin structure and a source/drain structure over the fin structure and adjacent to the gate stack. The semiconductor device structure further includes an isolation layer between the source/drain structure and the semiconductor substrate. | 2016-06-30 |
20160190244 | ELECTRONICS DEVICE HAVING TWO-DIMENSIONAL (2D) MATERIAL LAYER AND METHOD OF MANUFACTURING THE ELECTRONIC DEVICE BY INKJET PRINTING - An electronic device includes first and second electrodes that are spaced apart from each other and a 2D material layer. The 2D material layer connects the first and second electrodes. The 2D material layer includes a plurality of 2D nanomaterials. At least some of the 2D nanomaterials overlap one another. | 2016-06-30 |
20160190245 | METHODS AND SYSTEMS FOR CHEMICALLY ENCODING HIGH-RESOLUTION SHAPES IN SILICON NANOWIRES - Methods of chemically encoding high-resolution shapes in silicon nanowires during metal nanoparticle catalyzed vapor-liquid-solid growth or vapor-solid-solid growth are provided. In situ phosphorus or boron doping of the silicon nanowires can be controlled during the growth of the silicon nanowires such that high-resolution shapes can be etched along a growth axis on the silicon nanowires. Nanowires with an encoded morphology can have high-resolution shapes with a size resolution of about 1,000 nm to about 10 nm and comprise geometrical shapes, conical profiles, nanogaps and gratings. | 2016-06-30 |
20160190246 | STRESSED NANOWIRE STACK FOR FIELD EFFECT TRANSISTOR - A disposable gate structure is formed over the alternating stack of first semiconductor material portions and second semiconductor material portions. The second semiconductor material portions are removed selective to the first semiconductor material portions to form suspended semiconductor nanowires. Isolated gate structures are formed in regions underlying the disposable gate structure by deposition and recessing of a first gate dielectric layer and a first gate conductor layer. After formation of a gate spacer, source regions, and drain regions, raised source and drain regions are formed on the source regions and the drain regions by selective deposition of a semiconductor material. The disposable gate structure is replaced with a replacement gate structure by deposition and patterning of a second gate dielectric layer and a second gate conductor layer. Distortion of the suspended semiconductor nanowires is prevented by the disposable gate structure and the isolated gate structures. | 2016-06-30 |
20160190247 | STRESSED NANOWIRE STACK FOR FIELD EFFECT TRANSISTOR - A disposable gate structure is formed over the alternating stack of first semiconductor material portions and second semiconductor material portions. The second semiconductor material portions are removed selective to the first semiconductor material portions to form suspended semiconductor nanowires. Isolated gate structures are formed in regions underlying the disposable gate structure by deposition and recessing of a first gate dielectric layer and a first gate conductor layer. After formation of a gate spacer, source regions, and drain regions, raised source and drain regions are formed on the source regions and the drain regions by selective deposition of a semiconductor material. The disposable gate structure is replaced with a replacement gate structure by deposition and patterning of a second gate dielectric layer and a second gate conductor layer. Distortion of the suspended semiconductor nanowires is prevented by the disposable gate structure and the isolated gate structures. | 2016-06-30 |
20160190248 | TRANSISTOR STRUCTURE WITH REDUCED PARASITIC SIDE WALL CHARACTERISTICS - A MOS transistor structure for matched operation in weak-inversion or sub-threshold range (e.g. input-pair of operational amplifier, comparator, and/or current-minor) is disclosed. The transistor structure may include a well region of any impurity type in a substrate (SOI is included). The well-region can even be represented by the substrate itself. At least one transistor is located in the well region, whereby the active channel-region of the transistor is independent from lateral isolation interfaces between GOX (gate oxide) and FOX (field oxide; including STI-shallow trench isolation). | 2016-06-30 |
20160190249 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes: a gate structure on a substrate; a raised source/drain region adjacent to the gate structure; a channel region under the gate structure; and a protection layer between the substrate and the raised source/drain region. The protection layer is interposed between the substrate and the raised source/drain region. An atom stacking arrangement of the protection layer is different from the substrate and the raised source/drain region. | 2016-06-30 |
20160190250 | V-Shaped Epitaxially Formed Semiconductor Layer - The present disclosure provides a method in accordance with some embodiments. The method includes forming a recess in a source/drain region of a semiconductor substrate, wherein the semiconductor substrate is formed of a first semiconductor material. The method further includes epitaxially growing a second semiconductor material within the recess to form a S/D feature in the recess, and removing a portion of the S/D feature to form a v-shaped valley extending into the S/D feature. | 2016-06-30 |
20160190251 | FINFET CONFORMAL JUNCTION AND HIGH EPI SURFACE DOPANT CONCENTRATION METHOD AND DEVICE - A method of forming a source/drain region with an abrupt, vertical and conformal junction and the resulting device are disclosed. Embodiments include forming a gate electrode over and perpendicular to a semiconductor fin; forming first spacers on opposite sides of the gate electrode; forming second spacers on opposite sides of the fin; forming a cavity in the fin adjacent the first spacers, between the second spacers; partially epitaxially growing source/drain regions in each cavity; implanting a first dopant into the partially grown source/drain regions with an optional RTA thereafter; epitaxially growing a remainder of the source/drain regions in the cavities, in situ doped with a second dopant; and implanting a third dopant in the source/drain regions. | 2016-06-30 |
20160190252 | FINFET CONFORMAL JUNCTION AND ABRUPT JUNCTION WITH REDUCED DAMAGE METHOD AND DEVICE - A method of forming a source/drain region with abrupt vertical and conformal junction and the resulting device are disclosed. Embodiments include forming a first mask over a fin of a first polarity FET and source/drain regions of the first polarity FET; forming spacers on opposite sides of a fin of a second polarity FET, the second polarity being opposite the first polarity, on each side of a gate electrode; implanting a first dopant into the fin of the second polarity FET; etching a cavity in the fin of the second polarity FET on each side of the gate electrode; removing the first mask; performing rapid thermal anneal (RTA); epitaxially growing a source/drain region of the second polarity FET in each cavity; forming a second mask over the fin of the first polarity FET and source/drain regions of the first polarity FET; and implanting a second dopant in the source/drain regions of the second polarity FET. | 2016-06-30 |
20160190253 | METHOD AND STRUCTURE OF MAKING ENHANCED UTBB FDSOI DEVICES - An integrated circuit die includes a substrate having a first layer of semiconductor material, a layer of dielectric material on the first layer of semiconductor material, and a second layer of semiconductor material on the layer of dielectric material. An extended channel region of a transistor is positioned in the second layer of semiconductor material, interacting with a top surface, side surfaces, and potentially portions of a bottom surface of the second layer of semiconductor material. A gate dielectric is positioned on a top surface and on the exposed side surface of the second layer of semiconductor material. A gate electrode is positioned on the top surface and the exposed side surface of the second layer of semiconductor material. | 2016-06-30 |
20160190254 | Semiconductor Structures Employing Strained Material Layers with Defined Impurity Gradients and Methods for Fabricating Same - Semiconductor structures and devices including strained material layers having impurity-free zones, and methods for fabricating same. Certain regions of the strained material layers are kept free of impurities that can interdiffuse from adjacent portions of the semiconductor. When impurities are present in certain regions of the strained material layers, there is degradation in device performance. By employing semiconductor structures and devices (e.g., field effect transistors or “FETs”) that have the features described, or are fabricated in accordance with the steps described, device operation is enhanced. | 2016-06-30 |
20160190255 | METHODS FOR FORMING FinFETS HAVING A CAPPING LAYER FOR REDUCING PUNCH THROUGH LEAKAGE - A method for forming FinFETs having a capping layer for reducing punch through leakage includes providing an intermediate semiconductor structure having a semiconductor substrate and a fin disposed on the semiconductor substrate. A capping layer is disposed over the fin, and an isolation fill is disposed over the capping layer. A portion of the isolation fill and the capping layer is removed to expose an upper surface portion of the fin. Tapping layer and a lower portion of the fin define an interface dipole layer barrier, a portion of the capping layer operable to provide an increased negative charge or an increased positive charge adjacent to the fin, to reduce punch-through leakage compared to a fin without the capping layer. | 2016-06-30 |
20160190256 | Semiconductor Device Including a Transistor with a Gate Dielectric Having a Variable Thickness - A semiconductor device includes a transistor in a semiconductor substrate having a main surface. The transistor includes a source region, a drain region, a channel region, a drift zone, a gate electrode, and a gate dielectric adjacent to the gate electrode. The gate electrode is disposed adjacent to at least two sides of the channel region. The channel region and the drift zone are disposed along a first direction parallel to the main surface between the source region and the drain region. The gate dielectric has a thickness that varies at different positions of the gate electrode. | 2016-06-30 |
20160190257 | GRAPHENE OPTOELECTRONIC DETECTOR AND METHOD FOR DETECTING PHOTONIC AND ELECTROMAGNETIC ENERGY BY USING THE SAME - A graphene optoelectronic detector is disclosed, which comprises: an insulating substrate with a graphene layer disposed thereon; a first electrode disposed on the graphene layer or between the graphene layer and the insulating substrate; and a second electrode disposed on the graphene layer or between the graphene layer and the insulating substrate, wherein there is a predetermined distance between the first electrode and the second electrode, and the first electrode and the second electrode are at different electrical potentials, wherein a high-drift carrier moving region is disposed between the first electrode and the second electrode, and a low-drift carrier moving region is disposed outside the high-drift carrier moving region. In addition, the present invention further provides a method for detecting photons and electromagnetic energy using the aforementioned graphene detector. | 2016-06-30 |