26th week of 2021 patent applcation highlights part 65 |
Patent application number | Title | Published |
20210202235 | Low-K Feature Formation Processes and Structures Formed Thereby - Semiconductor device structures having low-k features and methods of forming low-k features are described herein. Some examples relate to a surface modification layer, which may protect a low-k feature during subsequent processing. Some examples relate to gate spacers that include a low-k feature. Some examples relate to a low-k contact etch stop layer. Example methods are described for forming such features. | 2021-07-01 |
20210202236 | FORMING A PLANAR SURFACE OF A III-NITRIDE MATERIAL - A method of making a semiconductor device, comprising: forming a plurality of semiconductor seeds of a first Ill-nitride material through a mask provided over a substrate; growing a second Ill-nitride semiconductor material on the seeds; planarizing the grown second semiconductor material to form a cohesive structure from the plurality of discrete base elements, said cohesive structure having a substantially planar upper surface. | 2021-07-01 |
20210202237 | METHOD AND APPARATUS FOR THE CONTINUOUS VAPOR DEPOSITION OF SILICON ON SUBSTRATES - A method for the continuous vapour deposition of silicon on substrates, including the following steps: a) introducing at least one substrate into a reaction chamber; b) introducing a process gas and at least one gaseous silicon precursor compound into the reaction chamber; c) forming a gaseous mixture of at least one silicon-based intermediate product coexisting with the gaseous silicon precursor compound and the process gas; d) forming a silicon layer by vapour deposition of silicon from the gaseous silicon precursor compound and/or the silicon-based intermediate product on the substrate; e) discharging an excess of the gaseous mixture from the reaction chamber; f) returning at least one of the constituents of the excess of the gaseous mixture, selected from the silicon precursor compound, the silicon-based intermediate product and/or the process gas into the reaction chamber, wherein introducing the gaseous silicon precursor compound into the reaction chamber is regulated such that the molar ratio of the silicon-based intermediate product to the silicon precursor compound has a value of 0.2:0.8 to 0.5:0.5. | 2021-07-01 |
20210202238 | METHOD OF BREAKING THROUGH ETCH STOP LAYER - A photo resist layer is used to protect a dielectric layer and conductive elements embedded in the dielectric layer when patterning an etch stop layer underlying the dielectric layer. The photo resist layer may further be used to etch another dielectric layer underlying the etch stop layer, where etching the next dielectric layer exposes a contact, such as a gate contact. The bottom layer can be used to protect the conductive elements embedded in the dielectric layer from a wet etchant used to etch the etch stop layer. | 2021-07-01 |
20210202239 | BEVEL EDGE REMOVAL METHODS, TOOLS, AND SYSTEMS - A tool and methods of removing films from bevel regions of wafers are disclosed. The bevel film removal tool includes an inner motor nested within an outer motor and a bevel brush secured to the outer motor. The bevel brush is adjustable radially outward to allow the wafer to be inserted in the bevel brush and to be secured to the inner motor. The bevel brush is adjustable radially inward to engage one or more sections of the bevel brush and to bring the bevel brush in contact with a bevel region of the wafer. Once engaged, a solution may be dispensed at the engaged sections of the bevel brush and the inner motor and the outer motor may be rotated such that the bevel brush is rotated against the wafer such that the bevel films of the wafer are both chemically and mechanically removed. | 2021-07-01 |
20210202240 | ARRAYS OF HIGH-ASPECT-RATIO GERMANIUM NANOSTRUCTURES WITH NANOSCALE PITCH AND METHODS FOR THE FABRICATION THEREOF - Methods for fabricating thin, high-aspect-ratio Ge nanostructures from high-quality, single-crystalline Ge substrates are provided. Also provided are grating structures made using the methods. The methods utilize a thin layer of graphene between a surface of a Ge substrate, and an overlying resist layer. The graphene passivates the surface, preventing the formation of water-soluble native Ge oxides that can result in the lift-off of the resist during the development of the resist. | 2021-07-01 |
20210202241 | DIELECTRIC LAYER, INTERCONNECTION STRUCTURE USING THE SAME, AND MANUFACTURING METHOD THEREOF - A structure includes a first dielectric film and a second dielectric film. The second dielectric film is formed on and in contact with the first dielectric film, in which a first pore is formed between the first dielectric film and the second dielectric film, and a thickness of the first dielectric film is smaller than a diameter of the first pore. | 2021-07-01 |
20210202242 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, SUBSTRATE PROCESSING APPARATUS, AND RECORDING MEDIUM - There is provided a technique that includes: forming a film on a substrate in a process chamber by performing a cycle a predetermined number of times, the cycle including non-simultaneously performing: (a) supplying a precursor from a first supplier to the substrate and exhausting the precursor from an exhaust port installed opposite to the first supplier with the substrate interposed between the exhaust port and the first supplier; and (b) supplying a reactant from a second supplier to the substrate and exhausting the reactant from the exhaust port, wherein in (a), inert gas is supplied into the process chamber from a third supplier installed at a region, which is a region on a side of the exhaust port among a plurality of regions partitioned in the process chamber by a bisector perpendicular to straight line connecting the first supplier and the exhaust port in a plane view. | 2021-07-01 |
20210202243 | PLASMA DOPING OF GAP FILL MATERIALS - In a variety of processes for forming electronic devices that use spin-on dielectric materials, properties of the spin-on dielectric materials can be enhanced by curing these materials using plasma doping. For example, hardness and Young's modulus can be increased for the cured material. Other properties may be enhanced. The plasma doping to cure the spin-on dielectric materials uses a mechanism that is a combination of plasma ion implant and high energy radiation associated with the species ionized. In addition, physical properties of the spin-on dielectric materials can be modified along a length of the spin-on dielectric materials by selection of an implant energy and dopant dose for the particular dopant used, corresponding to a selection variation with respect to length. | 2021-07-01 |
20210202244 | HIGH-THROUGHPUT MULTI-STAGE MANUFACTURING PLATFORM AND METHOD FOR PROCESSING A PLURALITY OF SUBSTRATES - A high-throughput manufacturing platform and a method for processing semiconductor substrates using the platform. The platform includes a plurality of process modules that include a first process module configured for performing a blocking layer deposition process, a second process module configured for performing a film deposition process, and a third process module configured for performing an etch process, where the blocking layer deposition process requires a longer processing time for each substrate than the film deposition process and the etch process, and where the first process module is configured for simultaneously processing a greater number of substrates than the second and third process modules. A substrate metrology module is hosted on the platform, the substrate metrology module includes an inspection system operable for measuring data associated with an attribute of a substrate at least one of before or after the substrate is processed in a process module of the platform. | 2021-07-01 |
20210202245 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, SUBSTRATE PROCESSING APPARATUS, AND RECORDING MEDIUM - There is provided a technique that includes: (a) modifying a surface of a first base exposed on a surface of a substrate to be terminated with a hydrocarbon group by supplying a hydrocarbon group-containing gas to the substrate having the first base and a second base exposed on the surface of the substrate; and (b) selectively forming a film on a surface of the second base by supplying an oxygen- and hydrogen-containing gas to the substrate after modifying the surface of the first base. | 2021-07-01 |
20210202246 | SEMICONDUCTOR STRUCTURE FORMATION - Systems, apparatuses, and methods related to semiconductor structure formation are described. An example apparatus includes a structural material for a semiconductor device. The structural material includes an orthosilicate derived oligomer having a number of oxygen (O) atoms each chemically bonded to one of a corresponding number of silicon (Si) atoms and a chemical bond formed between an element from group 13 of a periodic table of elements (e.g., B, Al, Ga, In, and Tl) and the number of O atoms of the orthosilicate derived oligomer. The chemical bond crosslinks chains of the orthosilicate derived oligomer to increase mechanical strength of the structural material, relative to the structural material formed without the chemical bond to crosslink the chains, among other benefits described herein. | 2021-07-01 |
20210202247 | Methods of Reducing Gate Spacer Loss During Semiconductor Manufacturing - A method includes forming a gate spacer on sidewalls of a dummy gate structure disposed over a semiconductor substrate; performing a first implantation process to the gate spacer, wherein the first implantation process includes bombarding an upper portion of the gate spacer with silicon atoms; after performing the first implantation process, performing a second implantation process to the upper portion of the gate spacer, where the second implantation process includes bombarding the upper portion of the gate spacer with carbon atoms; and after performing the second implantation process, replacing the dummy gate structure with a high-k metal gate structure, wherein the replacing includes forming an interlayer dielectric (ILD) layer. | 2021-07-01 |
20210202248 | FILM FORMING METHOD AND FILM FORMING APPARATUS - A film forming method includes: forming a laminated film, in which an interface layer, a bulk layer, and a surface layer are laminated in this order, on a base; and crystallizing the laminated film, wherein the bulk layer is formed of a film that is easier to crystallize than the interface layer in crystallizing the laminated film, and wherein the surface layer is formed of a film that is easier to crystallize than the bulk layer in crystallizing the laminated film. | 2021-07-01 |
20210202249 | GRADED HARDMASK INTERLAYER FOR ENHANCED EXTREME ULTRAVIOLET PERFORMANCE - A patterning stack and methods are provided for semiconductor processing. The method includes forming a graded hardmask, the graded hardmask including a first material and a second material with extreme ultraviolet (EUV) absorption cross sections for absorption of EUV wavelengths, the second material configured to provide adhesion to photoresist materials. The method also includes depositing a photoresist layer over the graded hardmask. The method additionally includes patterning the photoresist layer. The method further includes etching the graded hardmask. The method also includes removing the photoresist layer | 2021-07-01 |
20210202250 | METHOD OF IMPROVING DEPOSITION INDUCED CD IMBALANCE USING SPATIALLY SELECTIVE ASHING OF CARBON BASED FILM - A method for forming features over a wafer with a carbon based deposition is provided. The carbon based deposition is pretuned, wherein the pretuning causes a non-uniform removal of some of the carbon based deposition. An oxide deposition is deposited through an atomic layer deposition process, wherein the depositing the oxide deposition causes a non-uniform removal of some of the carbon based deposition. At least one additional process is provided, wherein the at least one additional process completes formation of features over the wafer, wherein the features are more uniform than features that would be formed without pretuning. | 2021-07-01 |
20210202251 | METHOD AND DEVICE FOR BONDING SUBSTRATES - A method for bonding a first substrate with a second substrate, with the following sequence: production of a first amorphous layer on the first substrate and/or production of a second amorphous layer on the second substrate, bonding of the first substrate with the second substrate at the amorphous layer or at the amorphous layers to form a substrate stack, irradiation of the amorphous layer or the amorphous layers with radiation in such a way that the amorphous layer or the amorphous layers is/are transformed into a crystalline layer or crystalline layers. | 2021-07-01 |
20210202252 | SEMICONDUCTOR STRUCTURE AND METHOD OF MANUFACTURING THE SAME - A method of manufacturing a semiconductor structure, comprising providing a substrate; forming a fin structure over the substrate; depositing an insulation material over the fin structure; performing a plurality of ion implantations in-situ with implantation energy increased or decreased stepwise; and removing at least a portion of the insulation material to expose a portion of the fin structure. | 2021-07-01 |
20210202253 | Reduce Well Dopant Loss in FinFETs Through Co-Implantation - A method of forming a semiconductor device includes performing a first implantation process on a semiconductor substrate to form a deep p-well region, performing a second implantation process on the semiconductor substrate with a diffusion-retarding element to form a co-implantation region, and performing a third implantation process on the semiconductor substrate to form a shallow p-well region over the deep p-well region. The co-implantation region is spaced apart from a top surface of the semiconductor substrate by a portion of the shallow p-well region, and the deep-well region and the shallow p-well region are joined with each other. An n-type Fin Field-Effect Transistor (FinFET) is formed, with the deep p-well region and the shallow p-well region acting as a well region of the n-type FinFET. | 2021-07-01 |
20210202254 | DEVICE OF DIELECTRIC LAYER - A device includes a first dielectric layer, a first conductor, an etch stop layer, a second dielectric layer, and a second conductor. The first conductor is in the first dielectric layer. The etch stop layer is over the first dielectric layer. The etch stop layer has a first surface facing the first dielectric layer and a second surface facing away from the first dielectric layer, and a concentration of carbon in the etch stop layer periodically varies from the first surface to the second surface. The second dielectric layer is over the etch stop layer. The second conductor is in the second dielectric layer and the etch stop layer and electrically connected to the first conductor. | 2021-07-01 |
20210202255 | Semiconductor Device Having Hydrogen in a Dielectric Layer - Embodiment described herein provide a thermal treatment process following a high-pressure anneal process to keep hydrogen at an interface between a channel region and a gate dielectric layer in a field effect transistor while removing hydrogen from the bulk portion of the gate dielectric layer. The thermal treatment process can reduce the amount of threshold voltage shift caused by a high-pressure anneal. The high-pressure anneal and the thermal treatment process may be performed any time after formation of the gate dielectric layer, thus, causing no disruption to the existing process flow. | 2021-07-01 |
20210202256 | Silicide Films Through Selective Deposition - Methods for forming silicide films are disclosed. Methods of selectively depositing metal-containing films on silicon surfaces which are further processed to form silicide films are disclosed. Specific embodiments of the disclosure relate to the formation of silicide films on FinFET structures without the formation of a metal layer on the dielectric. | 2021-07-01 |
20210202257 | PLASMA-BASED EDGE TERMINATIONS FOR GALLIUM NITRIDE POWER DEVICES - A p-n diode includes a first electrode, a n-GaN layer on the first electrode, a p-GaN layer on the n-GaN layer, and a second electrode on a first portion of the p-GaN layer. A region of the p-GaN layer surrounding the electrode is a passivated region. Treating a GaN power device having a p-GaN layer includes covering a portion of the p-GaN layer with a metal layer, exposing the p-GaN layer to a hydrogen plasma, and thermally annealing the p-GaN layer, thereby passivating a region of the p-GaN layer proximate the metal layer. | 2021-07-01 |
20210202258 | SUBSTRATE TREATMENT APPARATUS, SUBSTRATE TREATMENT METHOD, SUBSTRATE TREATMENT SYSTEM, AND LEARNING DATA GENERATION METHOD - A substrate treatment apparatus includes a nozzle, a moving mechanism, a storage portion, and a control portion. The learned model is generated by learning, as learning data, learning target speed information indicating a moving speed of the nozzle and the amount of treatment acquired by executing a treatment on a substrate that is a learning target while causing the nozzle to move at a speed based on the learning target speed information. The control portion causes speed information at the time of treatment to be outputted from the learned model by inputting a target amount of an amount of treatment to the learned model. The control portion controls a moving mechanism such that the nozzle moves at a speed based on the speed information at the time of treatment when the treatment is executed on a substrate that is a treatment target. | 2021-07-01 |
20210202259 | SEMICONDUCTOR DEVICE MANUFACTURING METHOD - A semiconductor device manufacturing method includes the steps of etching a semiconductor material by using plasma, forming a damage layer on the semiconductor material, and removing the damage layer such that a relatively low temperature process can form a fine pattern with a vertical cross section using a compound semiconductor material or the like. | 2021-07-01 |
20210202260 | ETCHING METHOD, SUBSTRATE PROCESSING APPARATUS, AND SUBSTRATE PROCESSING SYSTEM - A technique enables etching of a film on a substrate with reduced etching on the surface of a side wall. An etching method includes forming a protective layer on a surface of aside wall defining a recess in a substrate. The protective layer contains sulfur atoms. The etching method further includes etching a film on the substrate to increase a depth of the recess after forming the protective layer. | 2021-07-01 |
20210202261 | ETCHING METHOD AND ETCHING APPARATUS - An etching method includes: providing, on a stage, a substrate including an etching film containing a silicon oxide film, and a mask formed on the etching film; setting a temperature of the stage to be 0° C. or less; and generating plasma from a gas containing fluorine, nitrogen, and carbon, and having a ratio of the number of fluorine to the number of nitrogen (F/N) in a range of 0.5 to 10, thereby etching the silicon oxide film through the mask. | 2021-07-01 |
20210202262 | SUBSTRATE PROCESSING METHOD AND SUBSTRATE PROCESSING APPARATUS - A substrate processing method includes a providing step, a forming step, and an etching step. In the providing step, a substrate including an etching target film, a first mask formed on the etching target film, and a second mask formed to cover at least a part of the first mask is provided. In the forming step, a protective film is formed on a side wall of the second mask by plasma generated from a first gas. In the etching step, the etching target film is etched with plasma generated from a second gas. | 2021-07-01 |
20210202263 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - According to an embodiment, a nonvolatile semiconductor memory device comprises a plurality of conductive layers that are stacked in plurality in a first direction via an inter-layer insulating layer, that extend in a second direction which intersects the first direction, and that are disposed in plurality in a third direction which intersects the first direction and the second direction. In addition, the same nonvolatile semiconductor memory device comprises: a semiconductor layer that has the first direction as a longitudinal direction; a tunnel insulating layer that contacts a side surface of the semiconductor layer; a charge accumulation layer that contacts a side surface of the tunnel insulating layer; and a block insulating layer that contacts a side surface of the charge accumulation layer. Furthermore, in the same nonvolatile semiconductor memory device, an end in the third direction of the plurality of conductive layers is rounded. | 2021-07-01 |
20210202264 | ETCHANT COMPOSITIONS AND METHODS OF MANUFACTURING INTEGRATED CIRCUIT DEVICES USING THE SAME - Etchant compositions described herein include etchant compositions for etching a silicon film and may include nitric acid, fluoric acid, phosphoric acid, acetic acid, a nitrogen compound, and water. The nitrogen compound may include fluorine (F), phosphorus (P), and/or carbon (C). Also described are methods of manufacturing an integrated circuit (IC) device. The methods may include providing a structure in which a silicon film doped at a first dopant concentration and an epitaxial film doped at a second dopant concentration are stacked. The second dopant concentration may be different from the first dopant concentration. The silicon film may be selectively etched from the structure by using an etchant composition. | 2021-07-01 |
20210202265 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of fabricating a semiconductor device includes applying a plasma to a portion of a metal dichalcogenide film. The metal dichalcogenide film includes a first metal and a chalcogen selected from the group consisting of S, Se, Te, and combinations thereof. A metal layer including a second metal is formed over the portion of the metal dichalcogenide film after applying the plasma. | 2021-07-01 |
20210202266 | SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING - Interconnect devices, packaged semiconductor devices and methods are disclosed herein that are directed towards embedding a local silicon interconnect (LSI) device and through substrate vias (TSVs) into system on integrated substrate (SoIS) technology with a compact package structure. The LSI device may be embedded into SoIS technology with through substrate via integration to provide die-to-die FL connection arrangement for super large integrated Fan-Out (InFO) for SBT technology in a SoIS device. Furthermore, the TSV connection layer may be formed using lithographic or photoresist-defined vias to provide eLSI P/G out to a ball-grid-array (BGA) connection interface. | 2021-07-01 |
20210202267 | TIE BAR REMOVAL FOR SEMICONDUCTOR DEVICE PACKAGING - A method of tie bar removal is provided. The method includes forming a leadframe including a tie bar and a flag. The tie bar extends from a side rail of the leadframe and has a distal portion at an angle different from a plane of the flag. A semiconductor die is attached to the flag of the leadframe. A molding compound encapsulates the semiconductor die, a portion of the leadframe, and the distal portion of the tie bar. The tie bar is separated from the molding compound with an angled cavity remaining in the molding compound. | 2021-07-01 |
20210202268 | PACKAGE DEVICE AND MANUFACTURING METHOD THEREOF - A package device and a manufacturing method thereof are provided. The manufacturing method of the package device includes providing a substrate and forming a redistribution layer on the substrate. The substrate has at least one device region and a non-device region. The redistribution layer includes at least one inspection structure and at least one wire structure. The wire structure is disposed in the device region, a part of the inspection structure and a part of the wire structure are formed of a same layer, and the inspection structure has a trench exposing the part of the inspection structure. | 2021-07-01 |
20210202269 | SEMICONDUCTOR PACKAGE WITH FLIP CHIP SOLDER JOINT CAPSULES - A semiconductor package includes a leadframe forming a plurality of leads with a die attach site, a semiconductor die including a set of die contacts mounted to the die attach site in a flip chip configuration with each die contact of the set of die contacts electrically connected to leadframe via one of a set of solder joints, a set of solder joint capsules covering each of the set of solder joints against the leadframe, a clip mounted to the leadframe over the semiconductor die with a clip solder joint. The solder joint capsules restrict flow of the solder joints of the semiconductor die contacts in the flip chip configuration such that the solder remains in place if remelted during later clip solder reflow. | 2021-07-01 |
20210202270 | THERMALLY CONDUCTIVE STRUCTURE FOR HEAT DISSIPATION IN SEMICONDUCTOR PACKAGES - A semiconductor package includes a wafer and at least one chip attached on first portions of an upper surface of the wafer. Further, the semiconductor package includes an insulating barrier layer, a thermally conductive layer, and a heat sink. The insulating barrier layer is arranged over the at least one chip attached on first portions of an upper surface of the wafer. The thermally conductive layer is arranged over the insulating barrier layer and at least partially encapsulates the at least one chip. The heat sink is arranged over the thermally conductive layer. | 2021-07-01 |
20210202271 | APPARATUS FOR TREATING SUBSTRATE AND METHOD FOR TREATING SUBSTRATE - Embodiments of the inventive concept provide an apparatus for treating a substrate. According to an exemplary embodiment, an apparatus for treating a substrate comprises a first valve and a second valve sequentially installed along a direction from a fluid supplying source to a high-pressure chamber in the supply line; a branch line branching from the supply line between the first valve and the second valve and connected to an exhaust line; a third valve installed on the branch line; an exhaust unit exhausting the process fluid inside the high-pressure chamber; and a controller, wherein the controller is configured to perform, before a transfer robot transfers the substrate to the high-pressure chamber for treating the substrate, a first operating of opening the first valve and closing the second valve and a third valve, and a second operating of closing the first valve and the second valve, and opening the third valve. | 2021-07-01 |
20210202272 | APPARATUS AND METHOD FOR DIE STACK FLUX REMOVAL - A system for removing flux from openings formed in a substrate that has openings (e.g., sized 20 microns or less) formed therein includes a spay nozzle device that has a spray nozzle arm that is formed at an angle of about 45 degrees or less for discharging fluid towards the openings in the substrate for flux removal. The angle is between about 30 degrees and 45 degrees. | 2021-07-01 |
20210202273 | CLEANING APPARATUS AND POLISHING APPARATUS - A cleaning apparatus includes: a cleaning tank that defines a cleaning space for cleaning a wafer; a wafer rotation mechanism that is arranged inside the cleaning tank and holds and rotates the wafer; a cleaning member that contacts and cleans a surface of the wafer, is rotatable around a central axis extending in a lateral direction, and has a length in an axial direction longer than a radius of the wafer; a swing mechanism that swings the cleaning member around a swing axis located inside the cleaning tank to move the cleaning member from a retracted position outside of the wafer to a cleaning position directly above the wafer; a second cleaning means that cleans the surface of the wafer; and a second swing mechanism that swings the second cleaning means around a second swing axis located inside the cleaning tank to pass directly above a center of the wafer. | 2021-07-01 |
20210202274 | LIQUID SUPPLY UNIT, AND APPARATUS AND METHOD FOR PROCESSING SUBSTRATE - An apparatus for processing a substrate includes a housing, a support unit that supports the substrate in the housing, a nozzle that dispenses a processing liquid onto the substrate, and a liquid supply unit that supplies the processing liquid to the nozzle. The liquid supply unit includes a container having a storage space in which the processing liquid is stored, a liquid supply tube through which the processing liquid flows from the container to the nozzle, and an ultrasonic-wave application member that applies ultrasonic waves to the processing liquid before the processing liquid is supplied to the nozzle. The ultrasonic-wave application member includes a liquid reservoir having an interior space in which a liquid is received and an ultrasonic generator that applies ultrasonic waves to the liquid received in the liquid reservoir. Part of the liquid supply tube is immersed in the liquid received in the liquid reservoir. | 2021-07-01 |
20210202275 | TOOLS AND METHODS FOR SUBTRACTIVE METAL PATTERNING - Disclosed herein are tools and methods for subtractively patterning metals. These tools and methods may permit the subtractive patterning of metal (e.g., copper, platinum, etc.) at pitches lower than those achievable by conventional etch tools and/or with aspect ratios greater than those achievable by conventional etch tools. The tools and methods disclosed herein may be cost-effective and appropriate for high-volume manufacturing, in contrast to conventional etch tools. | 2021-07-01 |
20210202276 | PLASMA PROCESSING METHOD, PLASMA PROCESSING APPARATUS AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE USING THE APPARATUS - In a plasma processing method, a substrate is loaded onto a lower electrode within a chamber. A plasma power is applied to form plasma within the chamber. A voltage function of a nonsinusoidal wave having a DC pulse portion and a ramp portion is generated. Generating the voltage function may include setting a slope of the ramp portion and setting a duration ratio of the ramp portion to a cycle of the voltage function in order to control an ion energy distribution generated at a surface of the substrate. A bias power of the nonsinusoidal wave is applied to the lower electrode. | 2021-07-01 |
20210202277 | SYSTEMS AND METHODS FOR TRAY CASSETTE WAREHOUSING - A system, includes, a semiconductor processing unit, an Automated Materials Handling System (AMHS) vehicle, and a warehouse apparatus, wherein the warehouse apparatus comprises at least one input port, at least one output port, and at least one load/unload port, wherein the warehouse apparatus is configured to perform one of the following: receiving a plurality of tray cassette containers from the AMHS vehicle at the at least one input port, transporting at least one tray cassette in each of a plurality of tray cassette containers to the at least one load/unload port via the at least one input port, transporting at least one first tray from the at least one tray cassette to the semiconductor processing unit via a tray feeder conveyor, and receiving at least one second tray from the semiconductor processing unit via the tray feeder conveyor. | 2021-07-01 |
20210202278 | LASER PROCESSING APPARATUS - A laser processing apparatus includes an energy distribution correcting unit that forms skirt parts of a Gaussian distribution of an energy distribution in a Y-axis direction regarding a laser beam emitted from a laser oscillator into a perpendicular distribution, an imaging lens group composed of two or more lenses that form an image of the beam shape of the laser beam for which the energy distribution has been corrected by the energy distribution correcting unit on the upper surface of the workpiece, and one cylindrical lens that adjusts the energy density in an X-axis direction regarding the laser beam for which the energy distribution has been corrected by the energy distribution correcting unit. | 2021-07-01 |
20210202279 | CHIP, HEATING CIRCUIT AND HEATING CONTROL METHOD FOR CHIP - A heating circuit is provided. The heating circuit is disposed in a chip which has a normal operation temperature range. The heating circuit includes a comparison circuit and a thermal-energy generation circuit. The comparison circuit compares a temperature voltage with a first threshold voltage. The temperature voltage represents a temperature of the chip. The thermal-energy generation circuit is controlled by the comparison circuit. When the temperature voltage is less than the first threshold voltage, the comparison circuit enables the thermal-energy generation circuit to generate thermal energy to raise the temperature of the chip. | 2021-07-01 |
20210202280 | SUBSTRATE HEATING UNIT, SUBSTRATE PROCESSING APPARATUS, AND SUBSTRATE PROCESSING METHOD - Proposed is a substrate heating unit including: a laser generator providing a laser beam for heating a substrate; and a beam shaper processing the laser beam from the laser generator and selectively providing one of a first beam having a uniform energy distribution and a second beam having an edge-enhanced energy distribution to the substrate. | 2021-07-01 |
20210202281 | PHOTOELECTRIC DEVICE - A photoelectric device includes a target substrate, a circuit pattern layer disposed on the target substrate, a plurality of micro photoelectric elements electrically connected to the circuit pattern layer, and a supplemental repair element electrically connected to the circuit pattern layer. The target substrate is configured with a plurality of connection positions and a repair position disposed with an offset with relative to a corresponding one of the connection positions. The offset is greater than or equal to zero. The micro photoelectric elements are individually disposed on at least a part of the connection positions of the target substrate. The supplemental repair element has an electrode disposed on the repair position of the target substrate, and the electrode is connected to the circuit pattern layer. On the target substrate, the supplemental repair element is arbitrary with respect to the micro photoelectric elements. | 2021-07-01 |
20210202282 | METHOD AND APPARATUS FOR TREATING A SUBSTRATE - A method of treating a substrate or of manufacturing a treated substrate includes the following steps:
| 2021-07-01 |
20210202283 | Loadlock Module and Semiconductor Manufacturing Apparatus Including the Same - A semiconductor manufacturing apparatus includes a loadlock module including a loadlock chamber in which a substrate container is received, wherein the loadlock module is configured to switch an internal pressure of the loadlock chamber between atmospheric pressure and a vacuum; and a transfer module configured to transfer a substrate between the substrate container received in the loadlock chamber and a process module for performing a semiconductor manufacturing process on the substrate, wherein the loadlock module includes a purge gas supply unit configured to supply a purge gas into the substrate container through a gas supply line connected to the substrate container; and an exhaust unit configured to discharge a gas in the substrate container through an exhaust line connected to the substrate container. | 2021-07-01 |
20210202284 | LIQUID STORAGE FOR FACILITY CHEMICAL SUPPLY SYSTEM - A lithography includes a storage tank that stores process chemical fluid, an anti-collision frame, and an integrated sensor assembly. The storage tank includes a dispensing port positioned at a lowest part of the storage tank in a gravity direction. The anti-collision frame is coupled to the storage tank. An integrated sensor assembly is disposed on at least one of the anti-collision frame and the storage tank to measure a variation in fluid quality in response to fluid quality measurement of fluid. | 2021-07-01 |
20210202285 | CHEMICAL LIQUID SUPPLYING SYSTEM AND METHOD OF SUPPLYING CHEMICAL LIQUID - In accordance with some embodiments, a method for processing semiconductor wafer is provided. The method includes connecting a drum which stores the chemical liquid with a testing pipe. The method also includes guiding the chemical liquid in the drum into the testing pipe. In addition, the method includes detecting a condition of the chemical liquid in the testing pipe. The method further includes determining if the condition of the chemical liquid is acceptable. When the condition of the chemical liquid is acceptable, supplying the chemical liquid to a processing tool at which the semiconductor wafer is processed. | 2021-07-01 |
20210202286 | PROCESSING APPARATUS FOR ELECTRONIC COMPONENT - An processing apparatus includes a first illumination portion and a first imaging portion. The first illumination portion irradiates ta second inner surface on an opposite side of a second outer surface and a third inner surface on an opposite side of a third outer surface via a first outer surface of the electronic component with irradiation light in a state where the electronic component is disposed on a first inspection position. The first imaging portion captures an image of a first internal corner portion formed by the second inner surface and the third inner surface, based on the first irradiation light emitted from the first outer surface after being specularly reflected on the second inner surface and the third inner surface. | 2021-07-01 |
20210202287 | STRUCTURE AND METHOD OF RETICLE POD HAVING INSPECTION WINDOW - The structure and methods of a reticle pod are provided. A reticle pod includes a base configured to support a reticle and a cover detachably coupled to the base. The cover includes a window that allows radiation at a wavelength between about 400 nm and about 700 nm to pass through with a transmittance of greater than 70%. | 2021-07-01 |
20210202288 | DEVICE AND METHOD FOR MANUFACTURING THIN FILM - A device and a method for manufacturing a thin film are provided. The device includes: a chamber; a substrate carrying member arranged within the chamber and configured to carry thereon a substrate on which the thin film is to be formed; a mask fixation member configured to fix a mask, wherein the mask includes a shielding region and an opening region, and a material for forming the thin film is allowed to pass through the opening region; and a position adjustment member configured to adjust a distance between the mask and the substrate to form the thin films of different sizes on the substrate, wherein orthogonal projections of the thin films of different sizes onto the substrate have different areas. | 2021-07-01 |
20210202289 | PLASMA PROCESSING APPARATUS, PLASMA PROCESSING METHOD, AND ELEMENT CHIP MANUFACTURING METHOD - A plasma processing apparatus for plasma processing a substrate held on a conveying carrier, the carrier including a holding sheet and a frame supporting an outer periphery of the holding sheet. The apparatus includes a controller that controls a plasma generator, an electrostatic adsorption mechanism, and a lifting system, to sequentially execute: an adsorption step allowing the substrate to be adsorbed electrostatically to a stage; an etching step of exposing the substrate adsorbed electrostatically to the stage to an etching plasma; a frame separation step of lifting the support, to separate the frame away from the stage, with at least part of the holding sheet kept in contact with the stage; a holding sheet separation step of separating the holding sheet away from the stage; and a static elimination step of exposing the substrate separated away from the stage to a static elimination plasma. | 2021-07-01 |
20210202290 | Info Structure with Copper Pillar Having Reversed Profile - A method includes forming a first polymer layer to cover a metal pad of a wafer, and patterning the first polymer layer to form a first opening. A first sidewall of the first polymer layer exposed to the first opening has a first tilt angle where the first sidewall is in contact with the metal pad. The method further includes forming a metal pillar in the first opening, sawing the wafer to generate a device die, encapsulating the device die in an encapsulating material, performing a planarization to reveal the metal pillar, forming a second polymer layer over the encapsulating material and the device die, and patterning the second polymer layer to form a second opening. The metal pillar is exposed through the second opening. A second sidewall of the second polymer layer exposed to the second opening has a second tilt angle greater than the first tilt angle. | 2021-07-01 |
20210202291 | SUBSTRATE SUCTION-HOLDING STRUCTURE AND SUBSTRATE TRANSFER ROBOT - A substrate suction-holding structure includes a conductive pad main body including an annular contact portion and a bottom wall portion closing a first vacuum chamber bottom surface surrounded by the contact portion, a conductive blade main body including an upper surface and a second vacuum chamber formed by depressing the upper surface, a conductive support column provided either on the second vacuum chamber or on the pad main body, causing the contact portion to be further on an upper side than the upper surface, and swingably supporting the pad main body with respect to the second vacuum chamber, a cover secured to the blade main body and covering the second vacuum chamber, and a suction path extending from the first vacuum chamber and passing through the bottom wall portion, the second vacuum chamber, and the blade main body in this order, the suction path connected to a vacuum source. | 2021-07-01 |
20210202292 | SUBSTRATE TRANSFER APPARATUS AND SUBSTRATE TRANSFER SYSTEM USING THE SAME - A substrate transfer apparatus includes: a body including a first surface to which a semiconductor substrate is suctioned and a second surface opposing the first surface, the first surface including a cavity disposed in a center region of the body and an attaching unit disposed on an edge of the body so as to surround the cavity and form negative pressure to suction the semiconductor substrate, and a connector connected to the second surface of the body and supporting the body, wherein the cavity includes a lower surface with at least one through hole penetrating the first and second surfaces of the body and connecting the cavity to an external space, and the cavity includes a side surface inclined at an angle of 2.9° to 5° with respect to the first surface at the edge of the body. | 2021-07-01 |
20210202293 | BURLS WITH ALTERED SURFACE TOPOGRAPHY FOR HOLDING AN OBJECT IN LITHOGRAPHY APPLICATIONS - Various burl designs for holding an object in a lithographic apparatus are described. A lithographic apparatus includes an illumination system, a first support structure, a second support structure, and a projection system. The illumination system is designed to receive radiation and to direct the radiation towards a patterning device that forms patterned radiation. The first support structure is designed to support the patterning device on the first support structure. The second support structure has a plurality of burls and is designed to support the substrate on the plurality of burls. A topography of a top surface of each of the plurality of burls is not substantially flat, such that a contact area between the substrate and each of the plurality of burls is reduced. The projection system is designed to receive the patterned radiation and to direct the patterned radiation towards the substrate. | 2021-07-01 |
20210202294 | SUSCEPTOR - A susceptor for supporting a disk-shaped wafer when performing a surface treatment, includes a protruding region, and at least three support parts, provided on the protruding region, and configured to support the disk-shaped wafer by making contact with a back surface of the disk-shaped wafer. A ratio of a total area of the support parts with respect to an area of the protruding region is 10% or less in a plan view of the disk-shaped wafer. | 2021-07-01 |
20210202295 | SYSTEMS AND METHODS FOR FIXED FOCUS RING PROCESSING - In an embodiment, a system includes: a base with a bore hole, wherein the base is configured to secure a wafer at a first position on the base; a pin extending through the bore hole; a focus ring horizontally surrounding the wafer at the first position and extending upwardly from the base, wherein the wafer is configured to be moved vertically between the first position and a second position above the focus ring via the pin; and a slit valve above the focus ring, wherein the wafer is configured to be moved horizontally between the second position and the slit valve via a robotic arm. | 2021-07-01 |
20210202296 | METHOD FOR LIFTING SUBSTRATE AND APPARATUS FOR TREATING SUBSTRATE - A method for lifting a substrate includes raising the substrate off a support plate having the substrate placed thereon, by using a lift pin, in which the lift pin raises the substrate off the support plate while vertically moving between a lowered position spaced apart downward from the support plate by a first distance and a raised position spaced apart upward from the support plate by a second distance, and the lift pin is brought into contact with the substrate in an interval in which the lift pin is decelerated or moved at a constant velocity. | 2021-07-01 |
20210202297 | SEMICONDUCTOR PROCESSING APPARATUS AND METHOD UTILIZING ELECTROSTATIC DISCHARGE (ESD) PREVENTION LAYER - Semiconductor processing apparatuses and methods are provided in which an electrostatic discharge (ESD) prevention layer is utilized to prevent or reduce ESD events from occurring between a semiconductor wafer and one or more components of the apparatuses. In some embodiments, a semiconductor processing apparatus includes a wafer handling structure that is configured to support a semiconductor wafer during processing of the semiconductor wafer. The apparatus further includes an ESD prevention layer on the wafer handling structure. The ESD prevention layer includes a first material and a second material, and the second material has an electrical conductivity that is greater than an electrical conductivity of the first material. | 2021-07-01 |
20210202298 | SEMICONDUCTOR DEVICE MANUFACTURING METHOD AND SEMICONDUCTOR DEVICE MANUFACTURING SYSTEM - A semiconductor device manufacturing method includes laminating a thermally-decomposable organic material on a substrate having a recess formed therein, laminating a silicon nitride film on the organic material, and heating the substrate to a predetermined temperature so as to thermally decompose the organic material, and to desorb the organic material under the silicon nitride film through the silicon nitride film so as to form an air gap between the silicon nitride film and the recess. In laminating the silicon nitride film, the silicon nitride film is laminated on the organic material with microwave plasma in a state in which a temperature of the substrate is maintained at 200 degrees C. or lower. | 2021-07-01 |
20210202299 | METHODS FOR FORMING MEMORY DEVICES, AND ASSOCIATED DEVICES AND SYSTEMS - Methods of manufacturing memory devices having memory cells and corresponding selectors, and associated systems and devices, are disclosed herein. In one embodiment, a method of manufacturing a memory device includes (a) removing a protection layer formed over the memory cells and (b) forming a cap layer over the memory cells before forming a conductive via through the memory device. The cap layer is configured to protect the memory cells during operation and can comprise a resistive material. The protection layer can be more efficiently removed with improved process margin and less device health impact using a polishing process before the conductive via is formed, thus increasing the manufacturing margin of the memory device. | 2021-07-01 |
20210202300 | FABRICATING METAL-OXIDE SEMICONDUCTOR DEVICE USING A POST-LINEAR-ANNEAL OPERATION - In accordance with embodiments of the present disclosure, a method for fabricating a Metal-Oxide Semiconductor (MOS) device may include: depositing a silicon-nitride (SiN) layer above a substrate surface of a silicon wafer; etching one or more trenches on the silicon wafer; performing a high-temperature post-liner-anneal process on the silicon wafer to reduce stress from the etched SiN layer to the silicon wafer; and filling the one or more trenches with oxide isolation material. The high-temperature post-liner-anneal process may reduce the dependence of the saturation current of the MOS device on the channel width. | 2021-07-01 |
20210202301 | METHOD FOR FORMING SEMICONDUCTOR DEVICE HAVING ISOLATION STRUCTURES WITH DIFFERENT THICKNESSES - A method includes forming a first trench in a semiconductor substrate. A mask is filled in the first trench and over the semiconductor substrate. After filling the mask in the first trench, the mask is patterned to form an opening in the mask. A second trench is formed in the semiconductor substrate. A depth of the second trench is different from a depth of the first trench. After forming the second trench in the semiconductor substrate, the mask is removed. A dielectric material is filled in both the first and second trenches. | 2021-07-01 |
20210202302 | SUBSTRATES INCLUDING USEFUL LAYERS - Substrates may include a useful layer affixed to a support substrate. A surface of the useful layer located on a side of the useful layer opposite the support substrate may include a first region and a second region. The first region may have a first surface roughness, may be located proximate to a geometric center of the surface, and may occupy a majority of an area the surface. The second region may have a second, higher surface roughness, may be located proximate to a periphery of the surface, and may occupy a minority of the area of the surface. | 2021-07-01 |
20210202303 | SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME - A method of manufacturing a semiconductor package may include forming a first substrate including a redistribution layer, providing a second substrate including a semiconductor chip and an interconnection layer on the first substrate to connect the semiconductor chip to the redistribution layer, forming a first encapsulation layer covering the second substrate, and forming a via structure penetrating the first encapsulation layer. The forming the via structure may include forming a first via hole in the first encapsulation layer, forming a photosensitive material layer in the first via hole, exposing and developing the photosensitive material layer in the first via hole to form a second encapsulation layer having a second via hole, and filling the second via hole with a conductive material. A surface roughness of a sidewall of the first encapsulation layer may be greater than a surface roughness of a sidewall of the second encapsulation layer. | 2021-07-01 |
20210202304 | SEMICONDUCTOR DEVICE HAVING CONTACT LAYERS AND MANUFACTURING METHOD - An embodiment relates to a method for manufacturing a semiconductor device. The method includes providing a semiconductor body including a first semiconductor region of a first conductivity type and a second semiconductor region of a second conductivity type interposed between the first semiconductor region and a first surface of the semiconductor body. The method further includes forming a first contact layer over the first surface of the semiconductor body. The first contact layer forms a direct electrical contact to the second semiconductor region. The method further includes forming a contact trench extending into the semiconductor body by removing at least a portion of the second semiconductor region. The method further includes forming a second contact layer in the contact trench. The second contact layer is directly electrically connected to the semiconductor body at a bottom side of the contact trench. | 2021-07-01 |
20210202305 | Semiconductor Device and Method - In an embodiment, a device includes: a semiconductor substrate; a first inter-layer dielectric (ILD) over the semiconductor substrate; a first conductive feature extending through the first ILD; a first etch stop layer over the first conductive feature and the first ILD, the first etch stop layer being a first dielectric material; a second ILD over the first etch stop layer; a contact having a first portion extending through the second ILD and a second portion extending through the first etch stop layer, the contact being physically and electrically coupled to the first conductive feature; and a first protective layer surrounding the second portion of the contact, the first portion of the contact being free from the first protective layer, the first protective layer being a second dielectric material, the second dielectric material being different from the first dielectric material. | 2021-07-01 |
20210202306 | MITIGATING PATTERN COLLAPSE - One or more techniques or systems for mitigating pattern collapse are provided herein. For example, a semiconductor structure for mitigating pattern collapse is formed. In some embodiments, the semiconductor structure includes an extreme low-k (ELK) dielectric region associated with a via or a metal line. For example, a first metal line portion and a second metal line portion are associated with a first lateral location and a second lateral location, respectively. In some embodiments, the first portion is formed based on a first stage of patterning and the second portion is formed based on a second stage of patterning. In this manner, pattern collapse associated with the semiconductor structure is mitigated, for example. | 2021-07-01 |
20210202307 | METAL INTERCONNECT STRUCTURE AND METHOD FOR FABRICATING THE SAME - A method for fabricating semiconductor device includes the steps of: forming a dielectric layer on a substrate; forming a trench in the dielectric layer; forming a first liner in the trench, wherein the first liner comprises Co—Ru alloy; forming a metal layer on the first liner; and planarizing the metal layer and the first liner to form a metal interconnection. | 2021-07-01 |
20210202309 | Electrical Connection for Semiconductor Devices - In one example, a method includes performing a first etching process to pattern a dielectric layer and expose a contact etch stop layer, performing a second etching process to remove the etch stop layer and expose a top surface of an underlying feature, performing a third etching process to laterally recess the etch stop layer, and depositing a conductive material over the underlying feature to create a conductive feature in direct contact with the underlying feature. | 2021-07-01 |
20210202310 | BI-LAYER LINER FOR METALLIZATION - A method of forming a semiconductor device includes forming an opening in a dielectric layer, and forming a barrier layer in the opening. A combined liner layer is formed over the barrier layer by first forming a first liner layer over the barrier layer, and forming a second liner layer over the first liner layer, such that the first liner layer and the second liner layer intermix. A conductive material layer is formed over the combined liner layer, and a thermal process is performed to reflow the conductive material layer. | 2021-07-01 |
20210202311 | MEMORY DEVICES - A memory device including a plurality of first conductive lines arranged on a substrate and spaced apart from each other in a first direction parallel to a top surface of the substrate; a plurality of capping liners on sidewalls of each of the plurality of first conductive lines, the plurality of capping liners having top surfaces at a vertical level equal to top surfaces of the plurality of first conductive lines, and bottom surfaces at a vertical level higher than bottom surfaces of the plurality of first conductive lines; and an insulating layer on the substrate, the insulating layer filling spaces between the plurality of first conductive lines and covering sidewalls of the plurality of capping liners. | 2021-07-01 |
20210202312 | SYSTEM, DEVICE AND METHODS OF MANUFACTURE - Systems, devices and methods of manufacturing a system on silicon wafer (SoSW) device and package are described herein. A plurality of functional dies is formed in a silicon wafer. Different sets of masks are used to form different types of the functional dies in the silicon wafer. A first redistribution structure is formed over the silicon wafer and provides local interconnects between adjacent dies of the same type and/or of different types. A second redistribution structure may be formed over the first redistribution layer and provides semi-global and/or global interconnects between non-adjacent dies of the same type and/or of different types. An optional backside redistribution structure may be formed over a second side of the silicon wafer opposite the first redistribution layer. The optional backside redistribution structure may provide backside interconnects between functional dies of different types. | 2021-07-01 |
20210202313 | FORMING SELF-ALIGNED VIAS AND AIR-GAPS IN SEMICONDUCTOR FABRICATION - A semiconductor device includes a first trench on a mandrel line through a top mask layer and stopping at a middle mask layer; and a second trench on a non-mandrel line through the top mask layer and stopping at the middle mask layer. A spacer material is removed from a structure resulting from etching the first trench and the second trench. The device includes a first via structure, formed using a removable material, in the first trench; a second via structure, formed using a removable material, in the second trench; an air-gap formed in a third trench created at a location of the spacer; a fourth trench formed by etching, to remove the first via structure and a first portion of a bottom mask layer under the first via structure; and a self-aligned line-end via on the mandrel line formed by filling the fourth trench with a conductive metal. | 2021-07-01 |
20210202314 | METHOD FOR PRODUCING AN INTERCONNECTION COMPRISING A VIA EXTENDING THROUGH A SUBSTRATE - The invention relates to a method for producing an interconnection comprising a via (V) extending through a substrate ( | 2021-07-01 |
20210202315 | SEMICONDUCTOR DEVICE AND METHODS FOR MANUFACTURING THEREOF - A semiconductor device and related manufacturing methods are provided. The semiconductor device includes one interconnection structure including: a substrate; a first insulating dielectric layer underneath a lower surface of the substrate; a second insulating dielectric layer on an upper surface of the substrate; a first connecting pad disposed within the first insulating dielectric layer; a metal connection member penetrating through a portion of the second insulating dielectric layer, the substrate and a portion of the first insulating dielectric layer to connect the first connecting pad; and a second connecting pad disposed within the second insulating dielectric layer and connecting the metal connection member. The metal connection member may be a Through-Silicon Via (TSV). The device includes a confined air gap surrounding the metal connection member, which improves the performance and reliability of the device. | 2021-07-01 |
20210202316 | METHOD OF MANUFACTURING MICROELECTRONIC DEVICES, RELATED TOOLS AND APPARATUS - A method of manufacturing a microelectronic device may include forming a wiring layer on a first surface of a wafer. The method may also include forming a modified layer along separation regions for each microelectronic device of the wafer by focusing a laser on an inside portion of the wafer. The method may also include removing material from the second surface of the wafer. The wafer may be cooled to a temperature where a low dielectric constant layer extending across the separation regions is brittle while the material is removed from the second surface of the wafer. The method may further include separating the wafer along the separation region to form separate microelectronic devices. | 2021-07-01 |
20210202317 | METHOD OF MANUFACTURING MICROELECTRONIC DEVICES, RELATED DEVICES, SYSTEMS, AND APPARATUS - A system and method for stealth dicing a semiconductor wafer. The method may include implanting dopant ions to a first depth in the semiconductor wafer through a back side of the semiconductor wafer. The method may further include focusing a laser beam at an inside portion of the wafer through the back surface of the wafer to form a modified layer in material of the semiconductor wafer proximate the first depth. The method may also include fracturing the semiconductor wafer along boundaries defined by the modified layer. | 2021-07-01 |
20210202318 | METHODS OF FORMING SEMICONDUCTOR DIES WITH PERIMETER PROFILES FOR STACKED DIE PACKAGES - The present technology is directed to methods of forming semiconductor dies with rabbeted regions. For example, the method can comprise forming a first channel along a street from a backside of the wafer to an intermediate depth between the backside of the wafer and a front side of the wafer. The first channel has a first sloped sidewall and a second sloped sidewall. A second channel is then formed by laser cutting from the intermediate depth in the wafer toward the front side of the wafer along a region between the first and second sidewalls of the first channel. The first sloped sidewall defines a rabbeted region at a side of the first semiconductor dies and the second sloped sidewall defines a rabbeted region at a side of the second semiconductor dies. | 2021-07-01 |
20210202319 | THREE-DIMENSIONAL INTEGRATED CIRCUITS (3DICS) INCLUDING UPPER-LEVEL TRANSISTORS WITH EPITAXIAL SOURCE & DRAIN MATERIAL - A monolithic three-dimensional integrated circuit may include multiple transistor levels separated by one or more levels of metallization. An upper level transistor structure may include monocrystalline source and drain material epitaxially grown from a monocrystalline channel material at a temperature low enough to avoid degradation of a lower level transistor structure and/or degradation of one or more low-k dielectric materials between the transistor levels. A highly conductive n-type silicon source and drain material may be selectively deposited at low temperatures with a high pressure CVD process. Multiple crystals of source drain material arranged in a vertically stacked multi-channel transistor structure may be contacted by a single contact metallization. | 2021-07-01 |
20210202320 | Local Gate Height Tuning by Cmp And Dummy Gate Design - The present disclosure describes fabricating devices with tunable gate height and effective capacitance. A method includes forming a first metal gate stack in a dummy region of a semiconductor substrate, the first metal gate stack including a first work function metal (WFM) layer; forming a second metal gate stack in an active device region of the semiconductor substrate, the second metal gate stack including a second WFM layer different than the first WFM layer; and performing a CMP process using a slurry including a charged abrasive nanoparticles. The charged abrasive nanoparticles include a first concentration in the active device region different from a second concentration in the dummy region causing different polish rates in the active device region and dummy region. After the performing of the CMP process, the first metal gate stack has a first height greater different from a second height of the second metal gate stack. | 2021-07-01 |
20210202321 | High Voltage Devices - Semiconductor devices and methods of forming the same are provided. In an embodiment, a semiconductor device includes a substrate including a core device region and an input/output (I/O) device region, a plurality of core devices in the core device region, each of the plurality of core devices including a first active region extending along a first direction, and a first plurality of input/output (I/O) transistors in the I/O device region, each of the first plurality of I/O transistors including a second active region extending along the first direction. The first active region includes a first width along a second direction perpendicular to the first direction and the second active region includes a second width along the second direction. The second width is greater than the first width. | 2021-07-01 |
20210202322 | SEMICONDUCTOR DEVICE - Semiconductor devices is provided. The semiconductor device includes a semiconductor substrate having a first region and an adjacent second region; a plurality of adjacent first fins in the first region of the semiconductor substrate; a plurality of adjacent second fins in the second region of the semiconductor substrate; a first type of fin sidewall spacers; a second type of fin sidewall spacers; first doped layers formed between adjacent first type of fin sidewall spacers in the first region; and second doped layers formed between adjacent first type of fin sidewall spacers in the second region. | 2021-07-01 |
20210202323 | GATE-ALL-AROUND DEVICES HAVING GATE DIELECTRIC LAYERS OF VARYING THICKNESSES AND METHOD OF FORMING THE SAME - A semiconductor device includes a substrate; an I/O device over the substrate; and a core device over the substrate. The I/O device includes a first gate structure having an interfacial layer; a first high-k dielectric stack over the interfacial layer; and a conductive layer over and in physical contact with the first high-k dielectric stack. The core device includes a second gate structure having the interfacial layer; a second high-k dielectric stack over the interfacial layer; and the conductive layer over and in physical contact with the second high-k dielectric stack. The first high-k dielectric stack includes the second high-k dielectric stack and a third dielectric layer. | 2021-07-01 |
20210202324 | Memory Arrays And Methods Used In Forming A Memory Array Comprising Strings Of Memory Cells - A method used in forming a memory array comprising strings of memory cells comprises forming a stack comprising vertically-alternating first tiers and second tiers. The stack comprises laterally-spaced memory-block regions that have horizontally-elongated trenches there-between. Sacrificial material is formed in the trenches. Vertical recesses are formed in the sacrificial material. The vertical recesses extend across the trenches laterally-between and are longitudinally-spaced-along immediately-laterally-adjacent of the memory-block regions. Bridge material is formed in the vertical recesses to line and less-than-fill the vertical recesses and form bridges there-from that have an upwardly-open cup-like shape. The sacrificial material in the trenches is replaced with intervening material that is directly under the bridges. Additional methods and structures independent of methods are disclosed. | 2021-07-01 |
20210202325 | TRI-LAYER STI LINER FOR NANOSHEET LEAKAGE CONTROL - A semiconductor structure includes a plurality of fins on a semiconductor substrate, the plurality of fins including an alternating sequence of a first nanosheet made of epitaxially grown silicon and a second nanosheet made of epitaxially grown silicon germanium, and a shallow trench isolation region within the semiconductor substrate adjacent to the plurality of fins. The shallow trench isolation region including a recess within the substrate filled with a first liner, a second liner directly above the first liner, a third liner directly above the second liner, and a dielectric material directly above the third liner. The first liner is made of a first oxide material, the third liner is made of a nitride material, and the second liner is made of a second oxide material that creates a dipole effect for neutralizing positive charges within the third liner and positive charges between the third liner and the first liner. | 2021-07-01 |
20210202326 | METHOD FOR MANUFACTURING A CFET DEVICE - A method for manufacturing a CFET device comprises forming a substrate of the double semi-conductor on insulator type, successively comprising, from the base to the surface thereof: a carrier substrate, a first electrically insulating layer, a first single-crystal semiconductor layer, a second electrically insulating layer and a second single-crystal semiconductor layer. Slices are formed into the substrate to the first electrically insulating layer so as to form at least one fin (F). A channel of a first transistor is formed in the first semiconductor layer and a channel of a second transistor is formed opposite the first transistor in the second semiconductor layer. Formation of the substrate of the double semi-conductor on insulator type, comprises: a first and a second step of transferring a layer and thermal processing at a temperature that is sufficiently high to smooth the first single-crystal semiconductor layer to a roughness lower than 0.1 nm RMS. | 2021-07-01 |
20210202327 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - In a method of manufacturing a semiconductor device, semiconductor layers, which are vertically arranged with a space between adjacent semiconductor layers, are provided over a substrate, an interfacial layer is formed around each of the semiconductor layers, a dielectric layer is formed on the interfacial layer around each of the semiconductor layers, a first conductive layer is formed on the dielectric layer, the first conductive layer is removed so that the dielectric layer is exposed, a second conductive layer is formed on the exposed dielectric layer so that the space between adjacent semiconductor layers is not fully filled by the second conductive layer, a third conductive layer is formed on the second conductive layer so that the space between adjacent semiconductor layers is filled by the third conductive layer, and the semiconductor layers are semiconductor wires or sheets. | 2021-07-01 |
20210202328 | METHODS AND APPARATUSES TO WAFER-LEVEL TEST ADJACENT SEMICONDUCTOR DIE - Wafer-level testing of multiple adjacent semiconductor die of a semiconductor wafer in parallel using built-in self-test circuitry for a memory (mBIST) and scribe lines that connect certain terminals of a semiconductor die to terminals of an adjacent semiconductor die. During the wafer-level testing, probe needles of a test setup connect to a single one of the multiple adjacent semiconductor die, and mBIST commands are passed from the single one of the multiple adjacent semiconductor die to one or more adjacent semiconductor die. In some examples, the scribe lines connect mBIST circuit terminals of one semiconductor die to mBIST circuit terminals of an adjacent semiconductor die. In some examples, the scribe lines connect I/O terminals of one semiconductor die to I/O terminals of an adjacent semiconductor die. The scribe lines may cross scribe regions of the wafer to connect the respective terminals of the adjacent semiconductor die. | 2021-07-01 |
20210202329 | SEMICONDUCTOR PACKAGE AND METHOD FOR MAKING THE SAME - A semiconductor package includes a semiconductor chip disposed over a first main surface of a first substrate, a package lid disposed over the semiconductor chip, and spacers extending from the package lid through corresponding holes in the first substrate. The spacers enter the holes at a first main surface of the first substrate and extend beyond an opposing second main surface of the first substrate. | 2021-07-01 |
20210202330 | SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor element, a heat sink on which the semiconductor element is mounted, and a case made of resin, the case being mounted on the heat sink and containing the semiconductor element. A fastening hole is formed passing through the case and the heat sink. The case includes a surface pressure absorbing member on a portion including the fastening hole in plan view, the surface pressure absorbing member having a plate shape and being higher in rigidity than the resin. | 2021-07-01 |
20210202331 | ELECTRICAL CONNECTOR ASSEMBLY - An electrical connector is essentially composed of a pair of half housings opposite to each other in a longitudinal direction to commonly form a receiving cavity for receiving a CPU. Each half housing is equipped with a plurality of contacts with corresponding contacting sections upwardly extending into the receiving cavity for mating with the CPU. A single pick-up cap includes a plate with a plurality of claws adapted to be engaged within locking recesses in exterior sides of the half housings, a plurality of positioning blocks adapted to extend into the receiving cavity so as to cooperate with the claws to sandwich the periphery wall of the housing therebetween in the longitudinal direction for securing the half housings to the pick-up cap. Therefore, both the pair of half housings may be grasped by the single pick-up cap for mounting and soldering to PCB at the same time. | 2021-07-01 |
20210202332 | Scalable Extreme Large Size Substrate Integration - Electronic packages and methods of formation are described in which an interposer is solderlessly connected with a package substrate. In an embodiment, the interposer is stacked on the package substrate and joined with a conductive film. In an embodiment the interposer is formed on the package substrate during a reconstitution sequence. | 2021-07-01 |
20210202333 | ENCAPSULATION STRUCTURE - An encapsulation structure may include a flexible substrate, a plurality of electronic elements, a first partition wall, a second partition wall, and a gas barrier layer. The flexible substrate has a device region and a non-device region. The electronic elements are disposed in the device region of the flexible substrate. The first partition wall surrounds one or more of the electronic elements. The second partition wall surrounds the first partition wall. There is at least one trench between the first partition wall and the second partition wall. The gas barrier layer covers one or more of the electronic elements and the surface of the first partition wall. The surface of the first partition wall has a higher surface energy than the surface of the second partition wall. | 2021-07-01 |
20210202334 | METHODS AND APPARATUS FOR WAFER-LEVEL PACKAGING USING DIRECT WRITING - A method of forming a semiconductor structure on a wafer includes depositing a polymer layer on the wafer in a wafer-level packaging process, forming at least one wafer-level packaging structure in the polymer layer using a direct writing process that alters a chemical property of portions of the polymer layer that have been directly written to, and removing portions of the polymer layer that have not been written to by the direct writing process revealing the at least one wafer-level packaging structure. In some embodiments, the direct writing process is a two-photon polymerization process that uses a femtosecond laser in combination with a pair of galvanometric laser scanners to solidify portions of the polymer layer to form the wafer-level packaging structure. | 2021-07-01 |
20210202335 | Packaged Semiconductor Devices and Methods of Packaging Semiconductor Devices - Packaged semiconductor devices and methods of packaging semiconductor devices are disclosed. In some embodiments, a packaged semiconductor device includes an integrated circuit die, a molding compound disposed around the integrated circuit die, and an interconnect structure disposed over the integrated circuit die and the molding compound. The molding compound is thicker than the integrated circuit die. | 2021-07-01 |