27th week of 2015 patent applcation highlights part 62 |
Patent application number | Title | Published |
20150187910 | METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES AND ELECTRONIC DEVICES - In a method of manufacturing a semiconductor device, an isolation layer pattern is formed on a substrate to define a field region covered by the isolation layer pattern and first and second active regions that is not covered by the isolation layer pattern and protrudes from the isolation layer pattern. A first anti-reflective layer is formed on the isolation layer pattern. A first photoresist layer is formed on the first and second active regions of the substrate and the first anti-reflective layer. The first photoresist layer is partially etched to form a first photoresist pattern covering the first active region. Impurities are implanted into the second active region to form a first impurity region. | 2015-07-02 |
20150187911 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF - A semiconductor device includes a gate electrode formed on a sidewall of a structure extending from a semiconductor substrate. A junction region is form in the structure to a first depth from a top of the structure and formed to overlap the gate electrode. A protection layer is formed between an outer wall of the structure and the gate electrode to a second depth less than the first depth from the top of the structure. | 2015-07-02 |
20150187912 | INTEGRATED ELECTRONIC DEVICE WITH EDGE-TERMINATION STRUCTURE AND MANUFACTURING METHOD THEREOF - An embodiment of an integrated electronic device formed in a semiconductor body delimited by a lateral surface, which includes: a substrate made of a first semiconductor material; a first epitaxial region made of a second semiconductor material, which overlies the substrate and defines a first surface; a second epitaxial region made of a third semiconductor material, which overlies the first surface and is in contact with the first epitaxial region, the third semiconductor material having a bandgap narrower than the bandgap of the second semiconductor material; an active area, extending within the second epitaxial region and housing at least one elementary electronic component; and an edge structure, arranged between the active area and the lateral surface, and including a dielectric region arranged laterally with respect to the second epitaxial region, which overlies the first surface and is in contact with the first epitaxial region. | 2015-07-02 |
20150187913 | TRENCH-GATE RESURF SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD - A trench-gate device with lateral RESURF pillars has an additional implant beneath the gate trench. The additional implant reduces the effective width of the semiconductor drift region between the RESURF pillars, and this provides additional gate shielding which improves the electrical characteristics of the device. | 2015-07-02 |
20150187914 | FINFET INCLUDING IMPROVED EPITAXIAL TOPOLOGY - A semiconductor device includes a semiconductor substrate having a plurality of semiconductor fins formed on an upper surface thereof. An epitaxial material is formed on the upper surface of the semiconductor substrate and on an outer surface of the semiconductor fins. The epitaxial material includes an epi upper surface having a lower region that contacts the semiconductor fins and an upper region formed above the lower region. The upper region extends parallel with an upper surface of the semiconductor fins. | 2015-07-02 |
20150187915 | METHOD FOR FABRICATING FIN TYPE TRANSISTOR - A method for fabricating a fin type transistor uniformly implants in targeted regions. The method includes forming a fin protruding in a Z-axis direction from a substrate positioned on an XY. A first region and a second region are included in the substrate and a gate is formed crossing the second region in X-axis direction. An implantation is performed on at least a portion of the second region. The fin is rotated through a first angle, another implantation is performed on at least a portion of the second region, and the fin is rotated again through a second angle, different from the first angle. | 2015-07-02 |
20150187916 | METHOD OF MANUFACTURING ZINC OXIDE THIN FILM, METHOD OF MANUFACTURING THIN FILM TRANSISTOR, ZINC OXIDE THIN FILM, THIN FILM TRANSISTOR, AND TRANSPARENT OXIDE WIRING - A method of manufacturing a zinc oxide thin film includes: immersing a base having a conductive portion in at least part of the base, in a solution containing zinc ions, hydroxide ions, and zinc complex ions; and by applying an alternating current to the conductive portion, forming a zinc oxide thin film on a region of the base, the region including the conductive portion. | 2015-07-02 |
20150187917 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - To provide a miniaturized transistor having high electric characteristics. A conductive film to be a source electrode layer and a drain electrode layer is formed to cover an oxide semiconductor layer and a channel protection layer, and then a region of the conductive film, which overlaps with the oxide semiconductor layer and the channel protection layer, is removed by chemical mechanical polishing treatment. Precise processing can be performed accurately because an etching step using a resist mask is not performed in the step of removing part of the conductive film to be the source electrode layer and the drain electrode layer. With the channel protection layer, damage to the oxide semiconductor layer or a reduction in film thickness due to the chemical mechanical polishing treatment on the conductive film can be suppressed. | 2015-07-02 |
20150187918 | POWER SEMICONDUCTOR DEVICE - A power semiconductor device may include: a semiconductor laminate formed by stacking a plurality of semiconductor layers each having an emitter metal layer formed on a top thereof and a collector metal layer formed on a bottom thereof; an insulating layer interposed between the semiconductor layers; and a first external electrode and a second external electrode formed on sides of the semiconductor laminate. The first external electrode is electrically connected to the emitter metal layer, and the second external electrode is electrically connected to the collector metal layer. | 2015-07-02 |
20150187919 | POWER SEMICONDUCTOR DEVICE - A provided a power semiconductor device may include: a first semiconductor region of a first conductive type; a second semiconductor region of a second conductive type formed on the first semiconductor region; a plurality of trench gates formed to penetrate through the second semiconductor region and lengthily formed in one direction; and a third semiconductor region of the first conductive type formed on the second semiconductor region, formed at least partially in a length direction between the plurality of trench gates, and formed to contact one side of an adjacent trench gate in a width direction. | 2015-07-02 |
20150187920 | POWER SEMICONDUCTOR DEVICE - A power semiconductor device may include: a first conductivity-type first semiconductor region; a second conductivity-type second semiconductor region disposed above the first semiconductor region; a trench gate penetrating through the second semiconductor region and a portion of the first semiconductor region; a third semiconductor region disposed on both sides of the trench gate and disposed on an inner side of an upper portion of the second semiconductor region; and a device protective region disposed in the third semiconductor region. | 2015-07-02 |
20150187921 | POWER SEMICONDUCTOR DEVICE - A power semiconductor device may include a first semiconductor region having a first conductivity type; a second semiconductor region having a second conductivity type and formed in an upper portion of the first semiconductor region; a third semiconductor region having a first conductivity type and formed in an upper portion of the second semiconductor region; and a trench gate formed by penetrating from the third semiconductor region to the first semiconductor region. A portion of at least one of the first semiconductor region, the second semiconductor region, and the third semiconductor region may include a device protection material of which a conduction band has a main state and a satellite state in an E-k diagram, and a curvature of the device protection material in the satellite state may be lower than a curvature thereof in the main state in the E-k diagram. | 2015-07-02 |
20150187922 | POWER SEMICONDUCTOR DEVICE - A power semiconductor device may include: a first conductivity-type drift region in which a plurality of trench gates each including a gate insulating layer disposed on a surface thereof and a conductive material filling the interior thereof are disposed; a second conductivity-type body region disposed on an inner side of an upper portion of the drift region and disposed to be in contact with the trench gate; a first conductivity-type emitter region disposed on an inner side of an upper portion of the body region and disposed to be in contact with the trench gate; and a hole accumulation region disposed in the drift region, disposed below the body region, and disposed between the trench gates. | 2015-07-02 |
20150187923 | SEMICONDUCTOR ELEMENT AND SOLID-STATE IMAGING DEVICE - A semiconductor element encompasses a charge-transfer path defined in a semiconductor region ( | 2015-07-02 |
20150187924 | Low Sheet Resistance GaN Channel on Si Substrates Using InAlN and AlGaN Bi-Layer Capping Stack - Transistors or transistor layers include an InAlN and AlGaN bi-layer capping stack on a 2DEG GaN channel, such as for GaN MOS structures on Si substrates. The GaN channel may be formed in a GaN buffer layer or stack, to compensate for the high crystal structure lattice size and coefficient of thermal expansion mismatch between GaN and Si. The bi-layer capping stack an upper InAlN layer on a lower AlGaN layer to induce charge polarization in the channel, compensate for poor composition uniformity (e.g., of Al), and compensate for rough surface morphology of the bottom surface of the InAlN material. It may lead to a sheet resistance between 250 and 350 ohms/sqr. It may also reduce bowing of the GaN on Si wafers during growth of the layer of InAlN material, and provide a AlGaN setback layer for etching the InAlN layer in the gate region. | 2015-07-02 |
20150187925 | ENHANCEMENT-MODE DEVICE - An enhancement-mode device is provided. A spontaneous polarization effect and a piezoelectric effect in a crystal of nitride are greatest in a <0002> direction and do not exist or are minimal in a non-polar and a semi-polar direction, which is used to form the enhancement-mode device. A groove having a non-polar surface or a semi-polar surface is formed in an epitaxial multilayer structure, thereby interrupting two-dimensional electron gas in the groove. When a gate voltage is increased, the electron density on the non-polar and semi-polar surfaces in the groove is increased consequently, thereby realizing an enhancement-mode operation. | 2015-07-02 |
20150187926 | Group 13 Nitride Composite Substrate Semiconductor Device, and Method for Manufacturing Group 13 Nitride Composite Substrate - Provided are a group 13 nitride composite substrate allowing for the production of a semiconductor device suitable for high-frequency applications while including a conductive GaN substrate, and a semiconductor device produced using this substrate. The group 13 nitride composite substrate includes a base material of an n-conductivity type formed of GaN, a base layer located on the base material, being a group 13 nitride layer having a resistivity of 1×10 | 2015-07-02 |
20150187927 | Method to Reduce Etch Variation Using Ion Implantation - The present disclosure relates to a method of forming a transistor device. In this method, first and second well regions are formed within a semiconductor substrate. The first and second well regions have first and second etch rates, respectively, which are different from one another. Dopants are selectively implanted into the first well region to alter the first etch rate to make the first etch rate substantially equal to the second etch rate. The first, selectively implanted well region and the second well region are etched to form channel recesses having equal recess depths. An epitaxial growth process is performed to form one or more epitaxial layers within the channel recesses. | 2015-07-02 |
20150187928 | SEMICONDUCTOR DEVICE, RELATED MANUFACTURING METHOD, AND RELATED ELECTRONIC DEVICE - A semiconductor device may include a first-type substrate. The semiconductor device may further include a second-type well configured to form a PN junction with the first-type substrate. The semiconductor device may further include a diode component configured to form a diode with the second-type well. The diode may be connected to the PN junction in a reverse series connection. The second-type may be N-type if the first-type is P-type, and wherein the second-type may be P-type if the first-type is N-type. | 2015-07-02 |
20150187929 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes: a first n− type epitaxial layer disposed on a first surface of an n+ type silicon carbide substrate including a current carrying region and termination regions positioned at both sides of the current carrying region; a p type epitaxial layer disposed on the first n− type epitaxial layer; a second n− type epitaxial layer disposed on the p type epitaxial layer; a first trench disposed in the current carrying region; a second trench disposed in each termination region; a gate insulating layer disposed in the first trench; a gate electrode disposed on the gate insulating layer; and a termination insulating layer disposed in the second trench, in which a side of the termination insulating layer contacts the p type epitaxial layer and the second n− type epitaxial layer. | 2015-07-02 |
20150187930 | SEMICONDUCTOR ELEMENT - A drain drift portion is a first parallel p-n structure, largely corresponding to a portion directly below a p-type base region forming an active region, formed by first n-type regions and first p-type regions being alternately and repeatedly joined. The periphery of the drain drift portion is an edge termination region formed of a second parallel p-n structure aligned contiguously to the first parallel p-n structure and formed by second n-type regions and second p-type regions being alternately and repeatedly joined. An n-type buffer layer is provided between the first and second parallel p-n structures and an n | 2015-07-02 |
20150187931 | HIGH VOLTAGE PMOS AND THE METHOD FOR FORMING THEREOF - A high voltage PMOS replacing the lightly doped region of the drain region with a low voltage P-well adopted in the low voltage devices, so as to save a mask. In order to achieve the high breakdown voltage and the low on resistance, a thick gate oxide applied in the DMOS is inserted. The N-type well region surrounding the source region may be replaced by a low voltage N-well adopted in the low voltage device to further save a mask. | 2015-07-02 |
20150187932 | POWER SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A power semiconductor device and a method for fabricating the same are provided. The power semiconductor device includes a substrate and an active layer on the substrate. A gate electrode is disposed on the active layer. A first electrode and a second electrode are disposed on the active layer, on opposite sides of the gate electrode. A first metal pattern is coupled to the first electrode. A second metal pattern is coupled to the second electrode. A first insulating layer is disposed on the first and second metal patterns. A third metal pattern covers the first insulating layer, coupled to the second metal pattern. An interface between the third metal pattern and the first insulating layer is a substantially planar surface. | 2015-07-02 |
20150187933 | LATERAL DOUBLE-DIFFUSED METAL-OXIDE-SEMICONUDCTOR TRANSISTOR DEVICE AND LAYOUT PATTERN FOR LDMOS TRANSISTOR DEVICE - A LDMOS transistor device includes a substrate including a first insulating structure formed therein, a gate formed on the substrate and covering a portion of the first insulating structure, a drain region and a source region formed in the substrate at two respective sides of the gate, a base region encompassing the source region, and a doped layer formed under the base region. The drain region and the source region include a first conductivity type, the base region and the doped layer include a second conductivity type, and the second conductivity type is complementary to the first conductivity type. A top of the doped layer contacts a bottom of the base region. A width of the doped layer is larger than a width of the base region. | 2015-07-02 |
20150187934 | HIGH VOLTAGE MULTIPLE CHANNEL LDMOS - An integrated circuit and method having an LDMOS transistor with multiple current channels. A first current channel is above a buried p-type diffusion and a second one current channel is below the buried p-type diffusion. | 2015-07-02 |
20150187935 | SEMICONDUCTOR DEVICE INCLUDING PILLAR TRANSISTORS - A first pillar transistor and a second pillar transistor are arranged with no other pillar transistor therebetween, a distance between a first silicon pillar in the first pillar transistor and a second silicon pillar in the second pillar transistor is smaller than a distance between a third silicon pillar in a third pillar transistor and the first silicon pillar. | 2015-07-02 |
20150187936 | QUASI-VERTICAL STRUCTURE HAVING A SIDEWALL IMPLANTATION FOR HIGH VOLTAGE MOS DEVICE - A semiconductor device includes a buried layer in a substrate, the buried layer having a first dopant type. The semiconductor device further includes a first layer over the buried layer, the first layer having the first dopant type. The semiconductor device further includes at least one first well in the first layer, the at least one first well having a second dopant type. The semiconductor device further includes an implantation region in a sidewall of the first layer, the implantation region having the second dopant type, wherein the implantation region is below the at least one first well. The semiconductor device further includes a metal electrode extending from the buried layer to a drain contact, wherein the metal electrode is insulated from the first layer and the at least one first well by an insulation layer. | 2015-07-02 |
20150187937 | LDMOS CHC RELIABILITY - An integrated circuit on a rotated substrate with an LDMOS transistor. A method of enhancing the CHC performance of an LDMOS transistor by growing a second STI liner oxide. A method of enhancing the CHC performance of an LDMOS transistor building the LDMOS transistor on a rotated substrate and growing a second STI liner oxide. | 2015-07-02 |
20150187938 | LOW COST DEMOS TRANSISTOR WITH IMPROVED CHC IMMUNITY - An integrated circuit and method includes a DEMOS transistor with improved CHC reliability that has a lower resistance surface channel under the DEMOS gate that transitions to a lower resistance subsurface channel under the drain edge of the DEMOS transistor gate. | 2015-07-02 |
20150187939 | Metal Gate Transistor and Method for Tuning Metal Gate Profile - A semiconductor device having arrays of metal gate transistors is fabricated by forming a number of dummy gate structures including a first gate dielectric layer and a dummy gate material layer overlying the first gate dielectric layer, depositing a tensile ILD layer between the dummy gate structures, stressing the tensile ILD layer, removing at least the dummy gate material to form a number of trenches, and depositing a metal gate material in the trenches, which have a tapered profile. | 2015-07-02 |
20150187940 | SEMICONDUCTOR DEVICE STRUCTURE AND METHOD FOR MANUFACTURING THE SAME - Embodiments for forming a semiconductor device structure are provided. The semiconductor device structure includes a substrate and a gate stack structure formed on the substrate. The semiconductor device structure also includes gate spacers formed on sidewalls of the gate stack structure. The semiconductor device structure further includes an isolation structure formed in the substrate and a source/drain stressor structure formed adjacent to the isolation structure. The source/drain stressor structure includes a capping layer which is formed along the (311) and (111) crystal orientations. | 2015-07-02 |
20150187941 | TRANSISTOR AND METHOD FOR FORMING THE SAME - Various embodiments provide transistors and methods for forming the same. In an exemplary method, a substrate can be provided. A gate structure can be formed on the substrate. A stress layer can be formed in the substrate on both sides of the gate structure. Barrier ions can be doped in the stress layer to form a barrier layer in the stress layer. The barrier layer can have a preset distance from a surface of the stress layer. An electrical contact layer can be formed using a portion of the stress layer on the barrier layer by a salicide process. The electrical contact layer can contain a first metal element. The first metal element can have a resistivity lower than a resistivity of a silicidation metal. The barrier layer can prevent atoms of the first metal element from diffusing to a bottom of the stress layer. | 2015-07-02 |
20150187942 | SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME - The present invention discloses a semiconductor structure and a method for manufacturing the same, which comprises providing a substrate, and forming a stress layer, a buried oxide layer, and an SOI layer on the substrate; forming a doped region of the stress layer arranged in a specific position in the stress layer; forming an oxide layer and a nitride layer on the SOI layer, and forming a first trench that etches the nitride layer, the oxide layer, the SOI layer, and the buried oxide layer, and stops on the upper surface of the stress layer, and exposes at least part of the doped region of the stress layer; forming a cavity by wet etching through the first trench to remove the doped region of the stress layer; forming a polycrystalline silicon region of the stress layer and a second trench by filling the cavity with polycrystalline silicon and etching back; forming an isolation region by filling the second trench. The semiconductor structure and the method for manufacturing the same disclosed in the present invention provide a favorable stress for the channel of the semiconductor device by introducing a stress layer and a stress induced zone set at specific positions depending on device type to help improving the performance of the semiconductor device. | 2015-07-02 |
20150187943 | Source/Drain Structure of Semiconductor Device - The disclosure relates to a semiconductor device having an isolation structure with a top surface over a substrate major surface; a cavity having a convex bottom surface below the top surface; and a strained material in the cavity and extending above the top surface. The strained material has an upper portion having a rhombus shape and a lower portion having substantially vertical sidewalls; and a pair of tapered spacers adjoining a portion of the substantially vertical sidewalls above the top surface. | 2015-07-02 |
20150187944 | Semiconductor Liner of Semiconductor Device - The disclosure relates to a fin field effect transistor (FinFET). An exemplary FinFET comprises a substrate comprising a major surface; a fin structure protruding from the major surface comprising a lower portion, an upper portion, and a middle portion between the lower portion and upper portion, wherein the fin structure comprises a first semiconductor material having a first lattice constant; a pair of notches extending into opposite sides of the middle portion; and a semiconductor liner adjoining the lower portion comprising a second semiconductor material having a second lattice constant greater than the first lattice constant. | 2015-07-02 |
20150187945 | SALICIDE PROTECTION DURING CONTACT METALLIZATION AND RESULTING SEMICONDUCTOR STRUCTURES - A semiconductor transistor has a structure including a semiconductor substrate, a source region, a drain region and a channel region in between the source region and the drain region. A gate is provided above the channel region. A silicon nitride protective layer is provided over the source region and the drain region, along with a silicon nitride cap over the gate region. The silicon nitride protective layer is configured to allow punch-through of the protective layer after source and drain openings are created, while preventing etching through the cap above the gate. The self-aligned source, drain and gate contacts are formed while protecting the source and drain salicide using the silicon nitride protective layer and gate cap. | 2015-07-02 |
20150187946 | SEMICONDUCTOR DEVICES INCLUDING TRENCH WALLS HAVING MULTIPLE SLOPES - A semiconductor device includes a gate spacer defining a trench. The trench includes a first part and a second part sequentially positioned on a substrate. An inner surface of the first part has a slope of an acute angle and an inner surface of the second part has a slope of a right angle or obtuse angle with respect to the substrate. A gate electrode fills at least a portion of the trench. | 2015-07-02 |
20150187947 | FINFET WITH ACTIVE REGION SHAPED STRUCTURES AND CHANNEL SEPARATION - A semiconductor structure in fabrication includes a n-FinFET and p-FinFET. Stress inducing materials such as silicon and silicon germanium are epitaxially grown into naturally diamond-shaped structures atop the silicon fins of the n-FinFET and p-FinFET areas. The diamond structures act as the source, drain and channel between the source and drain. The diamond structures of the channel are selectively separated from the fin while retaining the fin connections of the diamond-shaped growth of the source and the drain. Further fabrication to complete the structure may then proceed. | 2015-07-02 |
20150187948 | SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING SAME - This semiconductor device ( | 2015-07-02 |
20150187949 | SEMICONDUCTOR DEVICE - High field-effect mobility is provided for a transistor including an oxide semiconductor. Further, a highly reliable semiconductor device including the transistor is provided. In a bottom-gate transistor including an oxide semiconductor layer, an oxide semiconductor layer functioning as a current path (channel) of the transistor is sandwiched between oxide semiconductor layers having lower carrier densities than the oxide semiconductor layer. In such a structure, the channel is formed away from the interface of the oxide semiconductor stacked layer with an insulating layer in contact with the oxide semiconductor stacked layer, i.e., a buried channel is formed. | 2015-07-02 |
20150187950 | SEMICONDUCTOR DEVICE - A transistor with stable electric characteristics is provided. An aluminum oxide film containing boron is formed in order to prevent hydrogen from diffusing into an oxide semiconductor film. | 2015-07-02 |
20150187951 | SEMICONDUCTOR DEVICE - To provide a transistor with stable electric characteristics, provide a transistor having a small current in a non-conductive state, provide a transistor having a large current in a conductive state, provide a semiconductor device including the transistor, or provide a durable semiconductor device, a semiconductor device includes a first insulator containing excess oxygen, a semiconductor over the first insulator, a second insulator over the semiconductor, and a conductor having a region overlapping with the semiconductor with the second insulator provided therebetween. A region containing boron or phosphorus is located between the first insulator and the semiconductor. | 2015-07-02 |
20150187952 | SEMICONDUCTOR DEVICE - To provide a transistor with stable electrical characteristics, a transistor with a low off-state current, a transistor with a high on-state current, a semiconductor device including the transistor, or a durable semiconductor device. The semiconductor device includes a first transistor using silicon, an aluminum oxide film over the first transistor, and a second transistor using an oxide semiconductor over the aluminum oxide film. The oxide semiconductor has a lower hydrogen concentration than silicon. | 2015-07-02 |
20150187953 | SEMICONDUCTOR DEVICE AND DISPLAY DEVICE INCLUDING THE SEMICONDUCTOR DEVICE - A novel semiconductor device including an oxide semiconductor is provided. In particular, a planar semiconductor device including an oxide semiconductor is provided. A semiconductor device including an oxide semiconductor and having large on-state current is provided. The semiconductor device includes an oxide insulating film, an oxide semiconductor film over the oxide insulating film, a source electrode and a drain electrode in contact with the oxide semiconductor film, a gate insulating film between the source electrode and the drain electrode, and a gate electrode overlapping the oxide semiconductor film with the gate insulating film. The oxide semiconductor film includes a first region overlapped with the gate electrode and a second region not overlapped with the gate electrode, the source electrode, and the drain electrode. The first region and the second region have different impurity element concentrations. The gate electrode, the source electrode, and the drain electrode contain the same metal element. | 2015-07-02 |
20150187954 | SEMICONDUCTOR DEVICE - A semiconductor device includes a first conductive layer, a first insulating layer over the first conductive layer, first and second oxide semiconductor layers over the first insulating layer, a second conductive layer over the first oxide semiconductor layer, a third conductive layer over the second oxide semiconductor layer, a fourth conductive layer over the first oxide semiconductor layer and the second oxide semiconductor layer, a second insulating layer over the second conductive layer, the third conductive layer, and the fourth conductive layer, a fifth conductive layer electrically connected to the first conductive layer over the second insulating layer, and a sixth conductive layer over the second insulating layer. Each of the first and fifth conductive layers includes an area overlapping with the first oxide semiconductor layer. The sixth conductive layer includes an area overlapping with the second oxide semiconductor layer. | 2015-07-02 |
20150187955 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - It is an object to manufacture a highly reliable semiconductor device including a thin film transistor whose electric characteristics are stable. An insulating layer which covers an oxide semiconductor layer of the thin film transistor contains a boron element or an aluminum element. The insulating layer containing a boron element or an aluminum element is formed by a sputtering method using a silicon target or a silicon oxide target containing a boron element or an aluminum element. Alternatively, an insulating layer containing an antimony (Sb) element or a phosphorus (P) element instead of a boron element covers the oxide semiconductor layer of the thin film transistor. | 2015-07-02 |
20150187956 | IGZO Devices with Increased Drive Current and Methods for Forming the Same - Embodiments described herein provide indium-gallium-zinc oxide (IGZO) devices, such as IGZO thin-film transistors (TFTs), and methods for forming such devices. A substrate is provided. A gate electrode is formed above the substrate. A gate dielectric layer is formed above the gate electrode. The gate dielectric layer includes titanium. An interface layer is formed above the gate dielectric layer. The interface layer includes silicon. An IGZO channel layer is formed above the interface layer. A source electrode and a drain electrode are formed above the IGZO channel layer. | 2015-07-02 |
20150187957 | TRANSISTOR WITH IMPROVED RADIATION HARDNESS - An integrated circuit and method with a radiation hard transistor where the gate of the radiation hard transistor does not cross the boundary between active and isolation. | 2015-07-02 |
20150187958 | IGZO Devices with Reduced Electrode Contact Resistivity and Methods for Forming the Same - Embodiments described herein provide indium-gallium-zinc oxide (IGZO) devices, such as IGZO thin-film transistors (TFTs), and methods for forming such devices. A substrate is provided. A gate electrode is formed above the substrate. An IGZO channel layer is formed above the gate electrode. A contact layer is formed above the IGZO channel layer. The contact layer includes arsenic. A source electrode and a drain electrode are formed above the contact layer. | 2015-07-02 |
20150187959 | ARRAY SUBSTRATE - An array substrate having a thin film transistor with an oxide semiconductor layer, comprising: gate and data lines formed on the array substrate and defining a pixel region, wherein the thin film transistor is located in a device area of the pixel region; a light-shielding pattern arranged on the array substrate in the device area; an auxiliary line connected to the light-shielding pattern and supplying a constant voltage to the light-shielding pattern, wherein the auxiliary line is parallel to and spaced apart from one of the gate and data lines; a buffer layer of an inorganic material and located on the light-shielding pattern and a surface of the array substrate, wherein the oxide semiconductor layer is located on the buffer layer and the light-shielding pattern; an inter-insulating layer on the buffer layer, wherein the oxide semiconductor layer includes an active portion located entirely on the light-blocking pattern and having a channel formed thereon, and conductive portions located on sides of the active portion. | 2015-07-02 |
20150187960 | Radical Oxidation Process For Fabricating A Nonvolatile Charge Trap Memory Device - A memory device is described. Generally, the memory device includes a tunnel oxide layer overlying a channel connecting a source and a drain of the memory device formed in a substrate, a multi-layer charge storing layer overlying the tunnel oxide layer and a high-temperature-oxide (HTO) layer overlying the multi-layer charge storing layer. The multi-layer charge storing layer includes an oxygen-rich, first layer comprising a nitride on the tunnel oxide layer in which a composition of the first layer results in it being substantially trap free, and an oxygen-lean, second layer comprising a nitride on the first layer in which a composition of the second layer results in it being trap dense. The HTO layer includes an oxidized portion of the second layer. Other embodiments are also described. | 2015-07-02 |
20150187961 | PIEZORESISTIVE SENSOR - The present disclosure relates to a piezoresistive sensor that improves measurement precision by using a piezoresistive pattern that increases a piezoresistive deformation rate. An embodiment of the present disclosure provides a piezoresistive sensor that may include: a semiconductor substrate, four beams formed as a cross-shape with reference to a central body of the semiconductor substrate, and sixteen piezoresistive patterns formed on a top of the four beams, wherein sixteen piezoresistive patterns are formed as an “X” shape and are disposed on the four beams so as to form four piezoresistive pattern groups. | 2015-07-02 |
20150187962 | SCHOTTKY BARRIER DIODE AND METHOD OF MANUFACTURING THE SAME - A Schottky barrier diode includes: an n− type epitaxial layer disposed on a first surface of an n+ type silicon carbide substrate; a first p+ region disposed on the n− type epitaxial layer; an n type epitaxial layer disposed on the n− type epitaxial layer and the first p+ region; a second p+ region disposed on the n type epitaxial layer, and being in contact with the first p+ region; a Schottky electrode disposed on the n type epitaxial layer and the second p+ region; and an ohmic electrode disposed on a second surface of the n+ type silicon carbide substrate. Also, the first p+ region has a lattice shape including a plurality of vertical portions and horizontal portions connecting both ends of the respective vertical portions to each other. | 2015-07-02 |
20150187963 | MICRO OPTICAL PACKAGE STRUCTURE WITH FILTRATION LAYER AND METHOD FOR MAKING THE SAME - A micro optical package structure with filtration layers includes a substrate having a light-emitting area and a light-receiving area, a light-emitting chip being deposited in a light-emitting area, a light-receiving chip being deposited in a light-receiving area, two packaging resin bodies for enclosing the light-emitting chip and the light-receiving chip, respectively, and being separately deposited in the light-emitting area and the light-receiving area, respectively, and the filtration layers formed on the packaging resin bodies surface for filtering out lights of different wavelengths. The micro optical package structure needs neither barrier nor protective cover between or outside the packaging resin bodies, so can be microminiaturized. The micro optical package structure can filter out visible lights of specific wavelengths without using any additional filters. | 2015-07-02 |
20150187964 | METHOD OF NON-BEZEL ARRAY OF SOLAR CELLS - The present invention provides a solar cell array having no bezel between solar cell modules and a method for fabricating the solar cell array. The method for fabricating the solar cell array provides advantages, particularly when a solar cell panel is installed on the top of a panoramic roof in a vehicle, by minimizing the connection gaps between the solar cell modules, having transparent connection wires between solar cell modules, and maximizing openness and improved sight of the panoramic roof. | 2015-07-02 |
20150187965 | PROCESS FOR THE PRODUCTION OF SOLAR CELLS HAVING A LOCAL BACK SURFACE FIELD (LBSF) - The present invention relates to a method for producing solar cells with local back surface field (LBSF) using an alkaline etching paste which allows the back surface to be polished and the back surface edges to be insulated in a single process step. | 2015-07-02 |
20150187966 | MWT ARCHITECTURE FOR THIN SI SOLAR CELLS - Methods of fabricating metal wrap through solar cells and modules for thin silicon solar cells, including epitaxial silicon solar cells, are described. These metal wrap through solar cells have a planar back contact geometry for the base and emitter contacts. Fabrication of a metal wrap through solar cell may comprise: providing a photovoltaic device attached at the emitter side of the device to a solar glass by an encapsulant, the device including busbars on the device emitter; forming vias through the device base and emitter, the vias terminating in the busbars; depositing a conformal dielectric film over the surface of the vias and the back surface of the base; removing portions of the conformal dielectric film from the ends of the vias for exposing the busbars and from field areas of the base; and forming separate electrical contacts to the busbars and the field areas on the back surface of the solar cell. The solar cells may comprise epitaxially deposited silicon and may include an epitaxially deposited back surface field. | 2015-07-02 |
20150187967 | METHOD FOR MANUFACTURING A SOLAR CELL - A method of manufacturing a solar cell, including providing a patterned silicon wafer having a covered area and an uncovered area, and forming at least one electrode layer in the uncovered area in a low-temperature process. | 2015-07-02 |
20150187968 | METHOD FOR MANUFACTURING AN INTERDIGITATED BACK CONTACT SOLAR CELL - A method for manufacturing an interdigitated back contact solar cell, comprising steps of: (a) providing a doped silicon substrate; (b) doping the rear surface of the substrate homogeneously with boron in a blanket pattern, thereby forming a p+ region on the rear surface of the silicon substrate; (c) forming a silicon dioxide layer on the front and rear surface; (d) depositing a phosphorus-containing doping paste on the rear surface in a second pattern; (e) heating the silicon substrate to locally diffuse phosphorus into the rear surface of the silicon substrate, thereby forming an n+ region on the rear surface of the silicon substrate through the second pattern, wherein the p+ region and the n+ region on the rear surface collectively form an interdigitated pattern; and (f) removing the second silicon dioxide layer from the silicon substrate. | 2015-07-02 |
20150187969 | SYSTEMS AND METHODS FOR MONOLITHICALLY ISLED SOLAR PHOTOVOLTAIC CELLS - The monolithically isled solar cell comprises a semiconductor layer having a light receiving frontside and a passivated backside opposite the frontside. A first metal layer on the semiconductor layer passivated backside comprises base and emitter metallization islands corresponding to monolithic isled semiconductor regions. An insulating support backplane is attached to the first metal layer and portions of the semiconductor layer passivated backside. Trenches formed through the semiconductor layer to the insulating support backplane in a trench isolation pattern electrically isolate the semiconductor layer into monolithic isled semiconductor regions arranged on the insulating support backplane. Conductive vias through the insulating support backplane contact portions of each of the first metal layer base and emitter metallization islands. A second metal layer base and emitter metallization on the insulating support backplane contacts the first metal layer base and emitter metallization islands. The second metal layer electrically interconnects the monolithic isled semiconductor regions. | 2015-07-02 |
20150187970 | OPTICALLY-TRIGGERED LINEAR OR AVALANCHE SOLID STATE SWITCH FOR HIGH POWER APPLICATIONS - The present invention relates to a solid state switch that may be used as in optically-triggered switch in a variety of applications. In particular, the switch may allow for the reduction of gigawatt systems to approximately shoebox-size dimension. The optically-triggered switches may be included in laser triggered systems or antenna systems. | 2015-07-02 |
20150187971 | LASER POWER CONVERTER - A Laser Power Converter (LPC) device ( | 2015-07-02 |
20150187972 | SEMICONDUCTOR PHOTODETECTOR ELEMENT AND METHOD - A semiconductor photodetector element includes a semiconductor substrate having a first conductivity type; a columnar structure formed on a first surface of the semiconductor substrate, the columnar structure being composed of a semiconductor of the first conductivity type; a light absorption layer formed so as to surround the columnar structure; and a semiconductor layer formed so as to surround the light absorption layer. | 2015-07-02 |
20150187973 | SOLAR CELL AND MANUFACTURING METHOD THEREOF - A solar cell includes a semiconductor substrate of a first conductivity; a pillar-shaped structure constituted by a semiconductor of the first conductivity, the pillar-shaped structure being formed on the semiconductor substrate; a superlattice layer including a barrier layer and a quantum structure layer that are alternately deposited on a side wall of the pillar-shaped structure, the quantum structure layer being constituted by a material having a smaller energy bandgap than that of the barrier layer, the quantum structure layer including a wurtzite type crystal part and a zinc blende type crystal part that are alternately arranged along an axial direction of the pillar-shaped structure; and a semiconductor layer of a second conductivity that is formed so as to surround the superlattice layer, the second conductivity being an opposite conductivity to that of the first conductivity. | 2015-07-02 |
20150187974 | SOLAR CELL MODULE AND MANUFACTURING METHOD THEREOF - Solar cell module includes a solar cell panel; a protective substrate on the solar cell panel; a buffer part between the solar cell panel and the protective substrate; and a frame receiving the solar cell panel. The frame includes a side surface part surrounding side surfaces of the solar cell panel and protective substrate, and an inserting part bent from the side surface part. Method of manufacturing solar cell module includes preparing a solar cell panel; placing a buffer part on the solar cell panel; placing the solar cell panel and buffer part in a frame; placing a protective substrate on the buffer part; laminating the buffer part. The frame includes a side surface part and an inserting part crossing the side surface part, the solar cell panel is placed at low portion of the inserting part, and the protective substrate is placed at upper portion of the inserting part. | 2015-07-02 |
20150187975 | SUN TRACKING SOLAR POWER SYSTEM HARDWARE AND METHOD OF ASSEMBLY - A solar energy collection system can include improved mounting hardware for reducing hardware costs and labor required for assembly. For example, mounting hardware can include surfaces for supporting part or all of the weight of a solar module as it is brought into contact with mounting hardware and then moved into a final engaged position. In some systems, a torque tube can include saddle mount assemblies that allow a solar module to be partially engaged and a registered with the saddle mount while being pivoted into a final locked engagement. Some systems can include arrangements sufficient to support the full weight of a solar module in a disengaged position, and as it is moved into a final engaged position. Some systems can include a configuration of apertures and interference or snap-fit features for providing tool-less connections, thereby simplifying the assembly process. | 2015-07-02 |
20150187976 | Composition of an Encapsulation Film for a Solar Cell Module - A composition of an encapsulation film for a solar cell module comprises 80˜99 weight percent of transparent resin, 0.5˜10 weight percent of granular polymer particles and 0.1˜5 weight percent of additives, wherein light refraction is controlled by a diffusion mechanism of the granular polymer particles, so that the probability of light incidence on the solar cell is increased and thus the photoelectric conversion efficiency of the solar cell is improved. | 2015-07-02 |
20150187977 | SOLAR CELL MODULE - To provide a solar cell module formed by a lamination structure in which a lower sealing portion ( | 2015-07-02 |
20150187978 | FLEXIBLE LIGHTING-PHOTOVOLTAIC COMPOSITE MODULE AND MANUFACTURING METHOD THEREOF - The present invention provides a flexible lighting-photovoltaic composite module and a manufacturing method thereof. The flexible lighting-photovoltaic composite module comprises: at least one light source; a photovoltaic module electrically connected with the light source and including at least one photovoltaic cell; and a flexible light guide element, wherein the light source is embedded in the flexible light guide element, and the photovoltaic module is embedded in the flexible light guide element or fixed on at least one side of the flexible light guide element to form the flexible lighting-photovoltaic composite module. | 2015-07-02 |
20150187979 | HETEROJUNCTION SOLAR CELL WITH EPITAXIAL SILICON THIN FILM AND METHOD FOR PREPARING THE SAME - A heterojunction solar cell with an epitaxial silicon thin film and a method for preparing the same are revealed. Low-cost upgraded metallurgical grade silicon (UMG-Si) wafers have been used as the substrates to manufacture solar cells so as to reduce the amount of high-purity silicon materials used. First an epitaxial silicon thin film is disposed over a UMG-Si wafer. Then other layers such as an amorphous silicon thin film, a transparent conductive film, etc. are arranged to form a solar cell having heterojunction with an intrinsic thin-layer (HIT) structure. Due to reduce in using high-purity silicon materials, the manufacturing cost of the heterojunction solar cell with an epitaxial silicon thin film is significantly decreased. | 2015-07-02 |
20150187980 | OPTICAL DEVICE - A high-performance optical device is provided. An optical device includes a first transmitting portion that is disposed at the center of a predetermined area in a first substrate, a light-receiving portion that receives light passing through the first transmitting portion, N light-emitting portions (N is an integer of 2 or more) that are disposed around the first transmitting portion in the predetermined area, and a control circuit that controls the light-emitting portions. The control circuit is functionally divided into N control portions, namely, first to N-th control portions. The N control portions are disposed in areas overlapping the N light-emitting portions, respectively, when viewed from above. The optical device can reduce noise light and achieve a high S/N ratio, and also the sensitivity of the optical device can be improved. | 2015-07-02 |
20150187981 | Method for Deposition - Embodiments of the present invention include a method. The method includes producing a first vapor from a solid source material, reacting hydrogen telluride to form a second vapor comprising tellurium, and depositing on a support a coating material comprising tellurium within a deposition environment, the deposition environment comprising the first vapor and the second vapor. Another embodiment is a system. The system includes a deposition chamber disposed to contain a deposition environment in fluid communication with a support; a solid source material disposed in fluid communication with the deposition chamber; and a hydrogen telluride source in fluid communication in fluid communication with the deposition chamber. | 2015-07-02 |
20150187982 | Zinc Blende Cadmium-Manganese-Telluride with Reduced Hole Compensation Effects and Methods for Forming the Same - Embodiments provided herein describe methods for forming cadmium-manganese-telluride (CMT), such as for use in photovoltaic devices. A substrate including a material with a zinc blende crystalline structure is provided. CMT is formed above the substrate. During the formation of the CMT, cation-rich processing conditions are maintained. The resulting CMT may be more readily provided with p-type dopants when compared to conventionally-formed CMT. | 2015-07-02 |
20150187983 | METHOD FOR FORMING A TRANSPARENT CONDUCTIVE FILM WITH METAL NANOWIRES HAVING HIGH LINEARITY - Metal nanowires with high linearity can be produced using metal salts at a relatively low temperature. A transparent conductive film can be formed using the metal nanowires. Particularly, the transparent conductive film has high transmittance, low sheet resistance, and good thermal, chemical and mechanical stability. The transparent conductive film has a high electrical conductivity due to the high linearity of the metal nanowires. The metal nanowires take up 5% or less of the volume of the transparent conductive film, ensuring high transmittance of the transparent conductive film. Furthermore, the metal nanowires are useful as replacements for existing conductive materials, such as ITO, conductive polymers, carbon nanotubes and graphene. The metal nanowires can be applied to flexible substrates and other various substrates due to their good adhesion and high applicability to the substrates. Moreover, the metal nanowires can find application in various fields, such as displays and solar cell devices. | 2015-07-02 |
20150187984 | METHOD OF MANUFACTURING DISPLAY DEVICE - To provide a method of manufacturing a display device having an excellent impact resistance property with high yield, in particular, a method of manufacturing a display device having an optical film that is formed using a plastic substrate. The method of manufacturing a display device includes the steps of: laminating a metal film, an oxide film, and an optical filter on a first substrate; separating the optical filter from the first substrate; attaching the optical filter to a second substrate; forming a layer including a pixel on a third substrate; and attaching the layer including the pixel to the optical filter. | 2015-07-02 |
20150187985 | Method for Producing an Optoelectronic Semiconductor Chip and Optoelectronic Semiconductor Chip - In at least one embodiment, the method is designed to produce an optoelectronic semiconductor chip. The method includes at least the following steps in the stated sequence: A) providing a growth substrate with a growth side, B) depositing at least one nucleation layer based on Al | 2015-07-02 |
20150187986 | OPTOELECTRONIC DEVICE AND METHOD FOR MANUFACTURING THE SAME - A method of fabricating an optoelectronic device, comprising: providing a substrate, wherein the substrate comprises a first major surface and a second major surface opposite to the first major surface; forming a light emitting stack on the second major surface of the substrate; forming a supporting layer covering the light emitting stack; forming a plurality of first modified regions in the substrate by employing a first energy into the substrate after forming the supporting layer; and cleaving the substrate. | 2015-07-02 |
20150187987 | METHOD OF MANUFACTURING A QUANTUM DOT OPTICAL COMPONENT AND BACKLIGHT UNIT HAVING THE QUANTUM DOT OPTICAL COMPONENT - A method of manufacturing a quantum dot optical component is provided. By the method, a plurality of quantum dot lines are formed on a first substrate, an encapsulation member that encapsulates the quantum dot lines is formed on the first substrate, a second substrate is laminated on the encapsulation member, and the first and second substrates are cut into a plurality of quantum dot optical components each including at least one of the quantum dot lines. | 2015-07-02 |
20150187988 | LIGHT-EMITTING DEVICE, LIGHT-EMITTING DEVICE PACKAGE, AND LIGHT UNIT - A light-emitting device, according to one embodiment, comprises: a light-emitting structure comprising a first conductive semiconductor layer, an active layer which is underneath the first conductive semiconductor layer, and a second conductive semiconductor layer which is underneath the active layer; a first electrode which is arranged under the light-emitting structure and is electrically connected to the second conductive semiconductor layer; a reflection layer which is arranged inside the second conductive semiconductor layer and arranged apart from the first electrode and the active layer; and a second electrode which is electrically connected to the first conductive semiconductor layer. | 2015-07-02 |
20150187989 | LIGHT SOURCE AND DISPLAY DEVICE USING THE LIGHT SOURCE - The display device is arranged with a pair of reflection layers arranged facing each other and which function as an anode and cathode of a light emitting layer, a light emitting layer sandwiched between the pair of reflection layers and arranged in a pixel of a display region, a transparent conductive layer contacting the light emitting layer and arranged so as to overlap an aperture part seen from a planar view, wherein the aperture part is arranged in one of the pair of reflection layers and is arranged with a color filter including a pigment layer therein. | 2015-07-02 |
20150187990 | Light-Emitting Diode and Fabrication Method Thereof - A light-emitting diode includes a substrate; a light-emitting epitaxial layer, laminated by semiconductor material layers and formed over the substrate; a first current spreading layer over the light-emitting epitaxial layer; an adhesive layer with alternating second current spreading layers and first metal barrier layers over the first current spreading layer, including three structure layers; a second metal barrier layer over the adhesive layer with alternating second current spreading layers and metal barrier layers; and a metal electrode layer over the second metal barrier layer. | 2015-07-02 |
20150187991 | LED WITH INTERNALLY CONFINED CURRENT INJECTION AREA - Methods and structures for forming arrays of LED devices are disclosed. The LED devices in accordance with embodiments of the invention may include an internally confined current injection area to reduce non-radiative recombination due to edge effects. Several manners for confining current may include etch removal of a current distribution layer, etch removal of a current distribution layer and active layer followed by mesa re-growth, isolation by ion implant or diffusion, quantum well intermixing, and oxide isolation. | 2015-07-02 |
20150187992 | LIGHT-EMITTING DEVICES ON TEXTURED SUBSTRATES - A device includes a textured substrate, which further includes a plurality of trenches. Each of the plurality of trenches includes a first sidewall and a second sidewall opposite the first sidewall. A plurality of reflectors configured to reflect light is formed, with each of the plurality of reflectors being on one of the first sidewalls of the plurality of trenches. The second sidewalls of the plurality of trenches are substantially free from any reflector. | 2015-07-02 |
20150187993 | SEMICONDUCTOR LIGHT-EMITTING DEVICE AND METHOD FOR MANUFACTURING THE SAME - The disclosed invention relates to a semiconductor light-emitting element comprising: a plurality of semiconductor layers which are provided with a growth substrate eliminating surface on the side where a first semiconductor layer is located; a support substrate which is provided with a first electrical pathway and a second electrical pathway; a joining layer which joins a first surface side of the support substrate with a second semiconductor layer side of the plurality of semiconductor layers, and is electrically linked with the first electrical pathway; a joining layer eliminating surface which is formed on the first surface, and in which the second electrical pathway is exposed, and which is open towards the plurality of semiconductor layers; and an electrical link for electrically linking the plurality of semiconductor layers with the second electrical pathway exposed in the joining layer eliminating surface. | 2015-07-02 |
20150187994 | LIGHT EMITTING DEVICE - Disclosed is a light emitting device. A light emitting device comprises a plurality of N-type semiconductor layers including a first N-type semiconductor layer and a second N-type semiconductor layer on the first N-type semiconductor layer, an active layer on the second N-type semiconductor layer, and a P-type semiconductor layer on the active layer, wherein the first N-type semiconductor layer comprises a Si doped Nitride layer and the second N-type semiconductor layer comprises a Si doped Nitride layer, and wherein the first and second N-type semiconductor layers have a Si impurity concentration different from each other. | 2015-07-02 |
20150187995 | LIGHT EMITTING DEVICE - A light emitting device is constituted with a semiconductor light emitting element on which a support member is disposed on one surface provided with a p-side electrode and an n-side electrode and a fluorescent material layer is disposed on the other surface which is an opposite side of the one surface. The support member includes a resin layer, an electrode for p-side external connection and an electrode for n-side external connection disposed exposed at a surface opposite side of a surface where the resin layer is in touch with a light emitting element, and internal wirings disposed in the resin layer and electrically connecting between a p-side electrode and the electrode for p-side external connection respectively. The internal wirings include a metal wire and a metal plated layer, and a metal wire and a metal plated layer respectively connected in series. | 2015-07-02 |
20150187996 | LIGHT EMITTING DIODE HAVING ELECTRODE PADS - A substrate, a first conductive type semiconductor layer arranged on the substrate, a second conductive type semiconductor layer arranged on the first conductive type semiconductor layer, an active layer disposed between the first conductive type semiconductor layer and the second conductive type semiconductor layer, a first electrode pad electrically connected to the first conductive type semiconductor layer, a second electrode pad arranged on the second conductive type semiconductor layer, an insulation layer disposed between the second conductive type semiconductor layer and the second electrode pad, and at least one upper extension electrically connected to the second electrode pad, the at least one upper extension being electrically connected to the second conductive type semiconductor layer. | 2015-07-02 |
20150187997 | LIGHT-EMITTING DIODE CHIP - A light-emitting diode (LED) chip is disclosed. The LED chip includes a substrate and a LED stack on the substrate. The LED stack includes a first-type semiconductor layer, an active layer covering a portion and exposing another portion of the first-type semiconductor layer, and a second-type semiconductor layer on the active layer. A current spreading layer is formed on the second-type semiconductor layer. A first electrode is formed on the exposed portion of the first-type semiconductor layer, and a second electrode is formed on the current spreading layer. The current spreading layer includes a first portion having a first thickness and a second portion having a second thickness. A vertical projection of the second portion onto the first-type semiconductor layer surrounds a vertical projection of a portion of the first electrode onto the first-type semiconductor layer. The first thickness is greater than the second thickness. | 2015-07-02 |
20150187998 | PACKAGE STRUCTURE AND METHOD FOR MANUFACTURING THE SAME - A package structure applied for method for a solid-state lighting apparatus is disclosed in the present invention and at least comprises a frame, a light emitting member, an encapsulant and a plurality of fluorescent powders. The light emitting member is disposed in the frame. The encapsulant is provided to fill the frame for packing the light emitting member therein, and the fluorescent powders are dispersed in the encapsulant. Furthermore, there is a plurality of scattering particles doped into the encapsulant. | 2015-07-02 |
20150187999 | SUBSTRATES FOR PACKAGING FLIP-CHIP LIGHT EMITTING DEVICE AND FLIP-CHIP LIGHT EMITTING DEVICE PACKAGE STRUCTURES - A substrate for packaging flip-chip light emitting device (LED) includes a substrate including a chip mount region, a first metal pattern overlapping a part of the chip mount region and disposed on the substrate, a second metal pattern disposed in a region including the chip mount region that is not overlapped with the first metal pattern, at an outer side of the first metal pattern, a third metal pattern disposed at an outer side of the second metal pattern, a first isolation line defined in a boundary between the first metal pattern and the second metal pattern, a second isolation line defined in a boundary between the second metal pattern and the third metal pattern, a lower pad disposed on a bottom of the substrate, and a via disposed to connect the first and second metal patterns to the lower pad in the substrate. | 2015-07-02 |
20150188000 | LIGHT EMITTING DIODE PACKAGE AND LIGHT EMITTING DIODE MODULE - A light emitting diode (LED) package includes at least one light emitting unit having a first electrode and a second electrode, a first molding compound covering a part of the light emitting unit to expose the first electrode and the second electrode, and a first light transmissive plate disposed on the first molding compound opposite the light emitting unit. A side surface of the first molding compound and a side surface of the first light transmissive plate are coplanar or have even adjoined edges. | 2015-07-02 |
20150188001 | LED WITH CERAMIC GREEN PHOSPHOR AND PROTECTED RED PHOSPHOR LAYER - A ceramic green wavelength conversion element ( | 2015-07-02 |
20150188002 | LIGHT EMITTING DEVICES HAVING RARE EARTH AND TRANSITION METAL ACTIVATED PHOSPHORS AND APPLICATIONS THEREOF - Light emitting devices and applications thereof. The light emitting devices include a light emitting device having an active layer of a semi-conductor and a phosphor having the general formula Ca | 2015-07-02 |
20150188003 | OPTOELECTRONIC SYSTEM - An embodiment of the invention discloses an optoelectronics system. The optoelectronic system includes an optoelectronic element having a first width; an adhesive material enclosing the optoelectronic element and having a second width larger than the first width; a phosphor structure formed between the optoelectronic element and the adhesive material; and a transparent substrate formed on the adhesive material. | 2015-07-02 |
20150188004 | SEMICONDUCTOR LIGHT EMITTING DEVICE - A light emitting device includes a substrate, a light emitting element mounted on the substrate, a light transmissive member placed on an upper surface of the light emitting element, and a sealing member which seals the light emitting element and the light transmissive member. The light transmissive member is a plate-shaped member not containing a phosphor and is larger than the light emitting element when viewed from above. The sealing member includes a first sealing member which is formed of a light reflecting member for reflecting light emitted from the light emitting element and covers side surfaces of the light emitting element, and a second sealing member which contains a phosphor for converting the light emitted from the light emitting element into light having wavelength different from wavelength of the light emitted from the light emitting element and covers at least an upper surface of the light transmissive member. | 2015-07-02 |
20150188005 | LIGHT EMITTING DIODE PACKAGE AND METHOD OF MANUFACTURING SAME - A method for packaging an light emitting diode, includes: arranging one or more light emitting diode dies on a film; encapsulating the one or more light emitting diode dies on the film; removing the film from the one or more encapsulated light emitting diode dies to expose a surface of the one or more encapsulated light emitting diode dies; forming an isolating layer on the exposed surface encapsulation surface portion of the one or more encapsulated light emitting diode dies so as to define a plurality of recesses; and forming a plurality of leads in the plurality of recesses of the one or more encapsulated light emitting diode dies, with each one of the plurality of leads being connected to one of the un-encapsulated electrodes of the one or more light emitting diode dies. | 2015-07-02 |
20150188006 | SILAZANE-CONTAINING MATERIALS FOR LIGHT EMITTING DIODES - LEDs comprising polysilazane/polysiloxane copolymers and curable compositions containing same are disclosed. Methods of providing thermal and UV degradation resistance to said LED's, as well as increased luminous flux, is provided. | 2015-07-02 |
20150188007 | SEALING MATERIAL FOR LIGHT EMITTING DEVICE, LIGHT EMITTING DEVICE USING THE SAME, AND MANUFACTURING METHOD FOR LIGHT EMITTING DEVICE - The present invention is intended to provide a sealing material for a light emitting device, which is able achieve both the adhesiveness and the crack resistance, have the high sulfurization resistance and the wet heat resistance, and seal the light emitting element. The sealing material for a light emitting device for sealing a light emitting element is characterized in that in a solid Si-nuclear magnetic resonance spectrum, a peak has a peak top in a chemical shift within a range of −120 ppm or more and −90 ppm or less, and a half width of 5 ppm or more and 12 ppm or less; in the solid Si-nuclear magnetic resonance spectrum, a peak has a peak top in a chemical shift within a range of −80 ppm or more and −40 ppm or less, and a half width of 5 ppm or more and 12 ppm or less; and a silanol content ratio is 11% by weight or more and 30% by weight or less. | 2015-07-02 |
20150188008 | CURABLE RESIN COMPOSITION, CURABLE RESIN COMPOSITION TABLET, MOLDED BODY, SEMICONDUCTOR PACKAGE, SEMICONDUCTOR COMPONENT AND LIGHT EMITTING DIODE - The present invention aims to provide a curable resin composition which gives a cured product having a low linear expansion coefficient. The curable resin composition of the present invention contains, as essential components, (A) an organic compound having at least two carbon-carbon double bonds reactive with SiH groups per molecule, (B) a compound containing at least two SiH groups per molecule, (C) a hydrosilylation catalyst, (D) a silicone compound having at least one carbon-carbon double bond reactive with a SiH group per molecule, and (E) an inorganic filler. | 2015-07-02 |
20150188009 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - The present disclosure provides a method of manufacturing a semiconductor device, including providing a semiconductor structure including a sequential stack of an n-type semiconductor layer, an active layer, and a p-type semiconductor layer. A first metal layer and a second metal layer on the first metal layer are formed on the semiconductor structure. A heat treatment process is performed, such that the first metal layer is oxidized to form a first metal oxide layer and the second metal layer is reversed to form a second metallic compound layer between the first metal oxide layer and the p-type semiconductor layer. The first metal oxide layer and the second metallic compound layer are removed. A mesa etching process is performed after performing the heat treatment process, to form a mesa region exposing a part of the n-type semiconductor layer. | 2015-07-02 |