27th week of 2020 patent applcation highlights part 67 |
Patent application number | Title | Published |
20200211941 | DISPLAY PANEL - A display panel includes a substrate having an active zone, a pad zone, an external component zone, and a fan-out zone, a plurality of light-emitting elements disposed in the active zone, and a plurality of wire structures. The wire structures include a first wire structure and a second wire structure. The first wire structure includes a plurality of first inner connecting ends, a plurality of first outer connecting ends, and a first body. The second wire structure includes a plurality of second inner connecting ends, a plurality of second outer connecting ends, and a second body. The first wire structure has a first current A | 2020-07-02 |
20200211942 | SEMICONDUCTOR DEVICE PACKAGE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device package is provided, which includes a semiconductor device, a redistribution layer, an under bump metallurgy (UBM) structure, a passivation layer and a protection layer. The semiconductor device has an active surface. The redistribution layer is disposed on the active surface of the semiconductor device and electrically connected to the semiconductor device. The UBM structure is disposed on the redistribution layer. The passivation layer is disposed on the redistribution layer and surrounding the UBM structure and having a first surface. The protection layer is disposed on the redistribution layer and having a first surface. The first surface of the passivation layer is substantially coplanar with the first surface of the protection layer. | 2020-07-02 |
20200211943 | DEVICE COMPRISING FIRST SOLDER INTERCONNECTS ALIGNED IN A FIRST DIRECTION AND SECOND SOLDER INTERCONNECTS ALIGNED IN A SECOND DIRECTION - A device that includes a first die and a package substrate. The package substrate includes a dielectric layer, a plurality of vias formed in the dielectric layer, a first plurality of interconnects formed on a first metal layer of the package substrate, and a second plurality of interconnects formed on a second metal layer of the package substrate. The device includes a first series of first solder interconnects arranged in a first direction, the first series of first solder interconnects configured to provide a first electrical connection; a second series of first solder interconnects arranged in the first direction, the second series of first solder interconnects configured to provide a second electrical connection; a first series of second solder interconnects arranged in a second direction, the first series of second solder interconnects configured to provide the first electrical connection. | 2020-07-02 |
20200211944 | SEMICONDUCTOR PACKAGE STRUCTURE - A semiconductor package structure is provided. The semiconductor package structure includes a substrate, a first semiconductor die, and a second semiconductor die. The substrate includes a first substrate partition and a second substrate partition. The first substrate partition has a first wiring structure. The second substrate partition is adjacent to the first substrate partition and has a second wiring structure. The first substrate partition and the second substrate partition are surrounded by a first molding material. The first semiconductor die is disposed over the substrate and electrically coupled to the first wiring structure. The second semiconductor die is disposed over the substrate and electrically coupled to the second wiring structure. | 2020-07-02 |
20200211945 | WIRING STRUCTURE AND METHOD FOR MANUFACTURING THE SAME - A wiring structure includes an upper conductive structure, a lower conductive structure, an adhesion layer and at least one outer via. The upper conductive structure includes at least one dielectric layer and at least one circuit layer in contact with the dielectric layer. The lower conductive structure includes at least one dielectric layer and at least one circuit layer in contact with the dielectric layer. The adhesion layer is interposed between the upper conductive structure and the lower conductive structure to bond the upper conductive structure and the lower conductive structure together. The outer via extends through at least a portion of the upper conductive structure and the adhesion layer, and electrically connected to the circuit layer of the lower conductive structure | 2020-07-02 |
20200211946 | INTERCONNECT BOARD, SEMICONDUCTOR PACKAGE, AND METHOD OF FABRICATING INTERCONNECT BOARD - An interconnect board includes: a first substrate; a second substrate having an outer shape smaller than an outer shape of the first substrate and mounted on the first substrate; and an adhesive layer bonding the first substrate and the second substrate together and having a fillet contacting a side surface of the second substrate. The fillet has a raised portion raised from a level of a top surface of the second substrate to a level higher than the top surface of the second substrate. | 2020-07-02 |
20200211947 | THINNED DIE STACK - Die stacks and methods of making die stacks with very thin dies are disclosed. The die surfaces remain flat within a 5 micron tolerance despite the thinness of the die and the process steps of making the die stack. A residual flux height is kept below 50% of the spacing distance between adjacent surfaces or structures, e.g. in the inter-die spacing. | 2020-07-02 |
20200211948 | SUBSTRATE, SEMICONDUCTOR DEVICE PACKAGE AND METHOD OF MANUFACTURING THE SAME - A substrate includes a first dielectric layer having a first surface and a second dielectric layer having a first surface disposed adjacent to the first surface of the first dielectric layer. The substrate further includes a first conductive via disposed in the first dielectric layer and having a first end adjacent to the first surface of the first dielectric layer and a second end opposite the first end. The substrate further includes a second conductive via disposed in the second dielectric layer and having a first end adjacent to the first surface of the second dielectric layer. A width of the first end of the first conductive via is smaller than a width of the second end of the first conductive via, and a width of the first end of the second conductive via is smaller than the width of the first end of the first conductive via. | 2020-07-02 |
20200211949 | MICROELECTRONIC ASSEMBLIES WITH VIA-TRACE-VIA STRUCTURES - Disclosed herein are via-trace-via structures with improved alignment, and related devices and methods. For example, in some embodiments, an integrated circuit (IC) package substrate may include a conductive trace having a first surface and an opposing second surface; a first conductive via in a first dielectric layer, wherein the first conductive via is in contact with the first surface of the conductive trace; and a second conductive via in a second dielectric layer, wherein the second conductive via is in contact with the second surface of the conductive trace, wherein the second dielectric layer is on the first dielectric layer, and wherein the first conductive via, the second conductive via, and the conductive trace have a same width between 0.5 um and 25 um. | 2020-07-02 |
20200211950 | HIGH-PERFORMANCE INTEGRATED CIRCUIT PACKAGING PLATFORM COMPATIBLE WITH SURFACE MOUNT ASSEMBLY - An integrated circuit package includes a transmission line structure, wire bonds, a first post and a second post. The transmission line structure runs from a printed circuit board (PCB) to an integrated circuit (IC) and includes a center transmission line between two ground lines and sealed from exposure to air. The wire bonds connect the transmission line structure to pads on the integrated circuit from where the center transmission line exits the integrated circuit package. The wire bonds are selected to have an impedance matched to impedance of the integrated circuit. The first post supports the center transmission line where the center transmission line enters the integrated circuit package from the printed circuit board. The second post supports the center transmission line where the center transmission line exits the integrated circuit package to connect to the wire bonds. | 2020-07-02 |
20200211951 | ELECTROCONDUCTIVE SUBSTRATE, ELECTRONIC DEVICE AND DISPLAY DEVICE - An electroconductive substrate, including: a base material; a foundation layer disposed on the base material; a trench formation layer disposed on the foundation layer, and an electroconductive pattern layer including metal plating. A trench including a bottom surface to which the foundation layer is exposed, is formed. The trench is filled with the electroconductive pattern layer. The foundation layer includes a mixed region which is formed from a surface of the foundation layer on the electroconductive pattern layer side towards the inside thereof, and contains metal particles which contain a metal configuring the electroconductive pattern layer, and enter the foundation layer. | 2020-07-02 |
20200211952 | INTEGRATED CIRCUIT SUBSTRATE AND METHOD OF MAKING - According to various embodiments of the present disclosure, a substrate for an integrated circuit includes a dielectric layer. The substrate further includes a conductive layer extending in an x or y direction. The conductive layer is at least partially embedded within the dielectric layer. The conductive layer includes a via having a first end and an opposite second end. The via has a first height in a z-direction and a constant cross-sectional shape between the first end and the second end. A trace is adjacent to the via and has a second height in the z-direction that is different than the first height. | 2020-07-02 |
20200211953 | LEADFRAME WITH A METAL OXIDE COATING AND METHOD OF FORMING THE SAME - A leadframe including a metal oxide layer on at least a portion of the leadframe are disclosed. More specifically, leadframes with a metal layer and a metal oxide layer formed on one or more leads before a tin finish plating layer is formed are described. The layers of metal and metal oxide between the one or more leads and the tin finish plating layer reduce the formation of tin whiskers, thus reducing the likelihood of shorting and improving the overall reliability of the package structure and device produced. | 2020-07-02 |
20200211954 | SEMICONDUCTOR MODULE - A semiconductor module includes a plurality of semiconductor elements, a sealing resin body, a positive electrode side terminal, a negative electrode side terminal, and an output terminal. The positive electrode side terminal, the negative electrode side terminal, and the output terminal are each connected to any of the semiconductor elements, and project from a same surface of the sealing resin body. Projecting portions of the positive electrode side terminal, the negative electrode side terminal, and the output terminal are arranged next to each other in an arrangement direction so that the projecting portion of the output terminal is located at an end. | 2020-07-02 |
20200211955 | HIGH CUTOFF FREQUENCY METAL-INSULATOR-METAL CAPACITORS IMPLEMENTED USING VIA CONTACT CONFIGURATIONS - Devices and methods are provided for fabricating a metal-insulator-metal capacitor within an interconnect structure (e.g., back-end-of-line interconnect structure) to provide capacitive decoupling between positive and negative power supply voltage lines of a power distribution network. Various via contact configurations including interlevel via contacts and truncated via contacts are utilized to connect the metal-insulator-metal capacitor electrodes to power supply voltage lines of the power distribution network to provide an array of high-density, low resistance via contact connections at various locations across the capacitor electrodes to reduce the resistance of the metal-insulator-metal capacitor and, thus, enhance the transient response time and increase the cutoff frequency of the metal-insulator-metal capacitor. The truncated via contacts allow for higher density via contact connections to the capacitor electrodes in regions which have a dense array of wiring of a single polarity, where interlevel via contacts cannot be utilized to provide contacts to the capacitor electrodes. | 2020-07-02 |
20200211956 | SEMICONDUCTOR PACKAGE WITH IMPROVED INTERPOSER STRUCTURE - A semiconductor package is provided. The semiconductor package includes a semiconductor die formed over an interconnect structure, an encapsulating layer formed over the interconnect structure to cover and surround the semiconductor die, and an interposer structure formed over the encapsulating layer. The interposer structure includes an insulating base having a first surface facing the encapsulating layer, and a second surface opposite the first surface. The interposer structure includes island layers arranged on the first surface of the insulating base and corresponding to the semiconductor die. A portion of the encapsulating layer is sandwiched by at least two of the island layers. Alternatively, the interposer structure includes a passivation layer covering the second surface of the insulating base and having a recess that is extended along a peripheral edge of the insulating base. | 2020-07-02 |
20200211957 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes a plurality of lower conductive lines overlying a substrate and extending in a first direction, an insulating layer overlying the plurality of lower conductive lines, a plurality of upper conductive lines overlying the insulating layer and the first conductive lines and extending in a second direction crossing the first direction, and a plurality of vias filled with a conductive material formed in the insulating layer. The plurality of upper conductive lines are arranged in the first direction with a first pitch. The plurality of vias includes first vias and second vias. At least one via of the first vias connects at least two lines of the plurality of lower conductive lines and one line of the plurality of upper conductive lines. An average width in the first direction of the first vias is different from an average width in the first direction of the second vias. | 2020-07-02 |
20200211958 | INTEGRATED INDUCTORS FOR POWER MANAGEMENT CIRCUITS - A power supply package is disclosed, including a power management integrated circuit (PMIC) die with a plurality of switching circuits, and a plurality of integrated 3-dimensional (3D) inductors disposed around the PMIC die. Each 3D inductor corresponds to a switching circuit and is electrically coupled to first and second connections for the corresponding switching circuit. An integrated electromagnetic interference (EMI) shield is disposed between the PMIC and the 3D inductors. | 2020-07-02 |
20200211959 | INTEGRATED INDUCTOR WITH MAGNETIC MOLD COMPOUND - An integrated circuit (IC) package comprises a semiconductor die, a leadframe comprising a plurality of leads coupled to bond pads on the semiconductor die, and an electrically conductive member electrically coupled to the leadframe. A magnetic mold compound encapsulates the electrically conductive member to form an inductor. A non-magnetic mold compound encapsulates the semiconductor die, the leadframe, and the magnetic mold compound. | 2020-07-02 |
20200211960 | REDUCTION OF OHMIC LOSSES IN MONOLITHIC CHIP INDUCTORS AND TRANSFORMERS OF RADIO FREQUENCY INTEGRATED CIRCUITS - An inductor or transformer with the inductor can include one or more windings split into strands along a radial path of the winding and provide for a more uniform current distribution across a width of the winding. The winding(s) can comprise twisting components as twistings or strand crossings located at various locations along the winding. The twisting components span the winding along a winding width with a connector or crossing strand and change a position of one strand to another at points that different strands of the winding are cut or spliced. | 2020-07-02 |
20200211961 | TRANSFORMER GUARD TRACE - An electronic device includes first leads along a first side, second leads along a second side, first and second dies, and a magnetic assembly with a multilevel lamination structure with first and second windings and a conductive guard trace. The lamination structure includes the first winding in a first level, and the second winding in a different level. The guard trace is between the first patterned conductive feature and the second side of the package structure. A first set of electrical connections couple the first die, the first winding, and one of the first conductive leads in a first circuit, and a second set of electrical connections couple the second die, the second winding, the guard trace and one of the second conductive leads in an isolated second circuit. | 2020-07-02 |
20200211962 | PACKAGE STRUCTURE AND METHOD FOR FORMING THE SAME - A package structure and method for forming the same are provided. The package structure includes a die structure formed over a first interconnect structure, and the die structure includes a first region and a second region. The package structure includes a dam structure formed on the first region of the die structure, and a second interconnect structure formed over the die structure and the dam structure. The package structure also includes a package layer formed between the first interconnect structure and the second interconnect structure, and the package layer is formed on the second region of the die structure to surround the dam structure. | 2020-07-02 |
20200211963 | POWER NETWORK AND METHOD FOR ROUTING POWER NETWORK - A power network includes a plurality of power switch units disposed in a first semiconductor layer, arranged in a plurality of columns along a first direction and a plurality of rows along a second direction. The power switch units in even rows are aligned with a center point of a horizontal space between adjacent two of the power switch units in the same row of the odd rows of the power switch units in the first direction. The power switch units in even columns are aligned with a center point of a vertical space between adjacent two of the power switch units in the same column of the odd columns of the power switch units in the second direction. The power network further includes a plurality of second connecting lines disposed in a fourth semiconductor layer and extending in the second direction. | 2020-07-02 |
20200211964 | SEMICONDUCTOR STRUCTURE AND METHOD FOR FABRICATING THE SAME - A semiconductor structure includes a substrate, an epitaxial layer disposed on the substrate, a conductive feature disposed in the epitaxial layer having a protruding portion that is higher than the epitaxial layer, and a diffusion barrier layer disposed on sidewalls of the conductive feature. | 2020-07-02 |
20200211965 | INTER-DIE PASSIVE INTERCONNECTS APPROACHING MONOLITHIC PERFORMANCE - Inter-die passive interconnects are lengthened while locating I/O circuitry away from die edge, such that passive interconnect length is agglomerated toward the die edge, and inter-die communication is expedited. | 2020-07-02 |
20200211966 | CERAMIC INTERPOSERS FOR ON-DIE INTERCONNECTS - Ceramic interposers in a disaggregated-die semiconductor package allow for useful signal integrity and interconnecting components. Low-loss ceramics are used to tune ceramic interposers for a die assembly that may have components from different process-technology nodes. | 2020-07-02 |
20200211967 | REDISTRIBUTION LAYERS WITH CARBON-BASED CONDUCTIVE ELEMENTS, METHODS OF FABRICATION AND RELATED SEMICONDUCTOR DEVICE PACKAGES AND SYSTEMS - Semiconductor device packages include a redistribution layer (RDL) with carbon-based conductive elements. The carbon-based material of the RDL may have low electrical resistivity and may be thin (e.g., less than about 0.2 μm). Adjacent passivation material may also be thin (e.g., less than about 0.2 μm). Methods for forming the semiconductor device packages include forming the carbon-based material (e.g., at high temperatures (e.g., at least about 550° C.)) on an initial support wafer with a sacrificial substrate. Later or separately, components of a device region of the package may be formed and then joined to the initial support wafer before the sacrificial substrate is removed to leave the carbon-based material joined to the device region. | 2020-07-02 |
20200211968 | SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF - A semiconductor structure includes a substrate; a first conductive line and a second conductive line disposed over the substrate; a first dielectric layer disposed over the substrate and surrounding the first conductive line and the second conductive line; a first conductive via extending through the first dielectric layer and contacting the first conductive line; a third conductive line disposed over the first dielectric layer and contacting the first conductive via; and a second dielectric layer disposed over the first dielectric layer and surrounding the third conductive line, wherein the first conductive line and the second conductive line are overlaid by the third conductive line. | 2020-07-02 |
20200211969 | INTERCONNECT ARCHITECTURE WITH SILICON INTERPOSER AND EMIB - Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises, a package substrate, an interposer on the package substrate, a first die cube and a second die cube on the interposer, wherein the interposer includes conductive traces for electrically coupling the first die cube to the second die cube, a die on the package substrate, and an embedded multi-die interconnect bridge (EMIB) in the package substrate, wherein the EMIB electrically couples the interposer to the die. | 2020-07-02 |
20200211970 | DIE INTERCONNECTION SCHEME FOR PROVIDING A HIGH YIELDING PROCESS FOR HIGH PERFORMANCE MICROPROCESSORS - A method is disclosed. The method includes a plurality of semiconductor sections and an interconnection structure connecting the plurality of semiconductor sections to provide a functionally monolithic base die. The interconnection structure includes one or more bridge die to connect one or more of the plurality of semiconductor sections to one or more other semiconductor sections or a top layer interconnect structure that connects the plurality of semiconductor sections or both the one or more bridge die and the top layer interconnect structure. | 2020-07-02 |
20200211971 | WIRING BOARD - A wiring board includes an insulating layer, and a metal layer, formed on the insulating layer, and including a first pattern that includes a plurality of wirings extending parallel to each other, and a second pattern that includes a degassing hole. The insulating layer includes a groove exposed between the plurality of wirings, and a surface of the insulating layer inside the degassing hole is located above a bottom surface of the groove. | 2020-07-02 |
20200211972 | SEMICONDUCTOR PACKAGES AND DISPLAY DEVICES INCLUDING THE SAME - Semiconductor packages are provided. A semiconductor package includes a substrate including a first bonding region, a chip region, and a second bonding region. Moreover, the substrate includes first and second surfaces that are opposite to each other. The semiconductor package includes a pad group including a pad on the first surface in the chip region. The semiconductor package includes a semiconductor chip on the pad group. The semiconductor package includes a wire connecting the pad and the second bonding region. The wire includes a portion that extends along the second surface of the substrate. Related display devices are also provided. | 2020-07-02 |
20200211973 | FILM PACKAGE AND PACKAGE MODULE INCLUDING THE SAME - A film package includes a film substrate, a first semiconductor chip on a first surface of the film substrate, a second semiconductor chip on the first surface of the film substrate, and a first conductive film on the first surface of the film substrate. The first conductive film covers the first semiconductor chip and the second semiconductor chip and includes a slit(s) or a notch(es). The slit(s) or notch(es) is/are disposed in a bridge region between the first semiconductor chip and the second semiconductor chip, in a plan view of the package. | 2020-07-02 |
20200211974 | METHOD TO FABRICATE METAL AND FERROMAGNETIC METAL MULTILAYER INTERCONNECT LINE FOR SKIN EFFECT SUPPRESSION - A multilayer conductive line is disclosed. The multilayer conductive line includes a dielectric layer, a Ta barrier layer on the dielectric layer and a superlattice on the Ta barrier layer. The superlattice includes a plurality of interleaved ferromagnetic and non-ferromagnetic material. | 2020-07-02 |
20200211975 | SEMICONDUCTOR PACKAGES AND ASSOCIATED METHODS WITH SOLDER MASK OPENING(S) FOR IN-PACKAGE GROUND AND CONFORMAL COATING CONTACT - Semiconductor devices with a conformal coating in contact with a ground plane at a bottom side of the semiconductor devices and associated systems and methods are disclosed herein. In one embodiment, a semiconductor device includes a semiconductor die coupled to a first surface of a package substrate. The semiconductor device can also include a molded material covering at least a portion of the package substrate and the semiconductor die. The semiconductor device can also include a ground plane in the package substrate and exposed through an opening in a second surface of the package substrate opposite the first surface. The semiconductor device can also include a conformal coating coupled to the ground plane through the opening that can shield the semiconductor device from electromagnetic interference. | 2020-07-02 |
20200211976 | Semiconductor Device with Partial EMI Shielding Removal Using Laser Ablation - A semiconductor device has a substrate. A first component and second component are disposed over the substrate. The first component includes an antenna. A lid is disposed over the substrate between the first component and second component. An encapsulant is deposited over the substrate and lid. A conductive layer is formed over the encapsulant and in contact with the lid. A first portion of the conductive layer over the first component is removed using laser ablation. | 2020-07-02 |
20200211977 | Shielded Semiconductor Packages with Open Terminals and Methods of Making Via Two-Step Process - A semiconductor device has a substrate including a terminal and an insulating layer formed over the terminal. An electrical component is disposed over the substrate. An encapsulant is deposited over the electrical component and substrate. A portion of the insulating layer over the terminal is exposed from the encapsulant. A shielding layer is formed over the encapsulant and terminal. A portion of the shielding layer is removed to expose the portion of the insulating layer. The portion of the insulating layer is removed to expose the terminal. The portion of the shielding layer and the portion of the insulating layer can be removed by laser ablation. | 2020-07-02 |
20200211978 | PACKAGE DEVICE AND METHOD OF MANUFACTURING THE SAME - The present disclosure provides a package device and a method of manufacturing the same. The package device includes a supporting member, a main component, a sealant, and a conductive encapsulant. The supporting member includes a plurality of grounding contacts. The main component is mounted on the supporting member. The sealant covers the main component. The conductive encapsulant encases the sealant and the grounding contacts exposed through the sealant for EMI shielding. | 2020-07-02 |
20200211979 | SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF - The present disclosure relates to a semiconductor structure and a method of manufacturing the semiconductor structure. The semiconductor structure includes a substrate including a first surface and a conductive trace extending over the substrate; a die disposed over the first surface of the substrate; a molding disposed over the first surface of the substrate and covering the die; and a metallic layer surrounding the molding and the substrate, wherein the metallic layer is electrically connected to at least a portion of the conductive trace exposed through the substrate. | 2020-07-02 |
20200211980 | FAN-OUT PACKAGE WITH WARPAGE REDUCTION AND MANUFACTURING METHOD THEREOF - A fan-out package with warpage reduction has a redistribution layer (RDL), at least one bare chip and a multi-layer encapsulation. A plurality of metal bumps on an active surface of each bare chip are respectively and electrically connected to a plurality of inner pads of the RDL. The multi-layer encapsulation is formed on the RDL to encapsulate the least one bare chip and at least has two different encapsulation layers with different coefficient of thermal expansions (CTE) to encapsulate different portions of sidewalls of each bare chip. One of the encapsulation layers with the smallest CTE is close to RDL. Therefore, in a step of forming the multi-layer encapsulation at high temperature, the suitable CTEs of the encapsulation layers are selected to reduce a warpage between the encapsulation layer and a material layer thereto. | 2020-07-02 |
20200211981 | METHODS OF FORMING A SEMICONDUCTOR DEVICE AND RELATED SEMICONDUCTOR DEVICES - A method of forming a semiconductor device comprising forming a patterned resist over a stack comprising at least one material and removing a portion of the stack exposed through the patterned resist to form a stack opening. A portion of the patterned resist is laterally removed to form a trimmed resist and an additional portion of the stack exposed through the trimmed resist is removed to form steps in sidewalls of the stack. A dielectric material is formed between the sidewalls of the stack to substantially completely fill the stack opening, and the dielectric material is planarized. Additional methods are disclosed, as well as semiconductor devices. | 2020-07-02 |
20200211982 | SEMICONDUCTOR DEVICES HAVING CRACK-INHIBITING STRUCTURES - Semiconductor devices having metallization structures including crack-inhibiting structures, and associated systems and methods, are disclosed herein. In one embodiment, a semiconductor device includes a metallization structure formed over a semiconductor substrate. The metallization structure can include a bond pad electrically coupled to the semiconductor substrate via one or more layers of conductive material, and an insulating material—such as a low-κ dielectric material—at least partially around the conductive material. The metallization structure can further include a crack-inhibiting structure positioned beneath the bond pad between the bond pad and the semiconductor substrate. The crack-inhibiting structure can include (a) a metal lattice extending laterally between the bond pad and the semiconductor substrate and (b) barrier members extending vertically between the metal lattice and the bond pad. | 2020-07-02 |
20200211983 | SEMICONDUCTOR DEVICES HAVING CRACK-INHIBITING STRUCTURES - Semiconductor devices having metallization structures including crack-inhibiting structures, and associated systems and methods, are disclosed herein. In one embodiment, a semiconductor device includes a metallization structure formed over a semiconductor substrate. The metallization structure can include a bond pad electrically coupled to the semiconductor substrate via one or more layers of conductive material, and an insulating material—such as a low-low-κ dielectric material—at least partially around the conductive material. The metallization structure can further include a crack-inhibiting structure positioned beneath the bond pad between the bond pad and the semiconductor substrate. The crack-inhibiting structure can include a barrier member extending vertically from the bond pad toward the semiconductor substrate and configured to inhibit crack propagation through the insulating material. | 2020-07-02 |
20200211984 | ELECTRONIC DEVICE PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF - An electronic device package structure and a manufacturing method thereof are provided. The electronic device package structure includes a first electronic device layer, a second electronic device layer, and a filling layer disposed between the first electronic device layer and the second electronic device layer, wherein the Young's modulus of the second electronic device layer is less than or equal to the Young's modulus of the first electronic device layer, and the Young's modulus of the filling layer is less than the Young's modulus of the second electronic device layer, and the ratio of the Young's modulus of the first electronic device layer to the Young's modulus of the filling layer is 10 to 1900 and the ratio of the Young's modulus of the second electronic device layer to the Young's modulus of the filling layer is 7.6 to 1300. | 2020-07-02 |
20200211985 | INTEGRATED MAGNETIC INDUCTORS FOR EMBEDDED-MULTI-DIE INTERCONNECT BRIDGE SUBSTRATES - An embedded magnetic inductor coil is at least partially exposed in a recess that seats an embedded multi-chip interconnect bridge die on the coil. The embedded multi-chip interconnect bridge die provides a communications bridge between a dominant semiconductive device and a first semiconductive device. | 2020-07-02 |
20200211986 | COMPOUND VIA RF TRANSITION STRUCTURE IN A MULTILAYER HIGH-DENSITY INTERCONNECT - A multilayer circuit board having a central conductor and core layers between a first set of alternating layers and a second set of alternating layers. The central conductor includes a first compound via through the first set of alternating layers, and a second compound via through the second set of alternating layers. A gap extends from a first side of the multilayer circuit board to a second side of the multilayer circuit board. A first array of ground protrusions surrounds the gap and is arranged in a first pattern on the first side of the multilayer circuit board. A second array of ground protrusions surrounds the gap and is arranged in a second pattern on the second side of the multilayer circuit board. A ground path connects the first array of ground protrusions to the second array of ground protrusions. | 2020-07-02 |
20200211987 | HIGH FREQUENCY / HIGH POWER TRANSITION SYSTEM USING SIW STRUCTURE - The present disclosure relates to a transition system, which includes a monolithic microwave integrated circuit (MMIC) package and a printed-circuit-board (PCB) with a number of PCB vias. The MMIC package has a laminate-based body, which includes a substrate integrated waveguide (SIW) structure with a number of SIW vias, and a MMIC die over the laminate-based body. Herein, the SIW structure faces the PCB and is separate from the PCB with a gap in between. The SIW structure is configured to radiate radio frequency (RF) signals received from the MMIC die to the PCB. An arrangement of the PCB vias is scaling-mirrored to an arrangement of the SIW vias, such that each PCB via and a corresponding SIW via have a same relative position. The arrangement of PCB vias is about aligned with the arrangement of the SIW vias. | 2020-07-02 |
20200211988 | SEMICONDUCTOR PACKAGE HAVING A SIDEWALL CONNECTION - A fan-out wafer level package includes a semiconductor die with a redistribution layer on a sidewall of the semiconductor die. A redistribution layer positioned over the die includes an extended portion that extends along the sidewall. The semiconductor die is encapsulated in a molding compound layer. The molding compound layer is positioned between the extended portion of the redistribution layer and the sidewall of the semiconductor die. Solder contacts, for electrically connecting the semiconductor device to an electronic circuit board, are positioned on the redistribution layer. The solder contacts and the sidewall of the redistribution layer can provide electrical contact on two different locations. Accordingly, the package can be used to improve interconnectivity by providing vertical and horizontal connections. | 2020-07-02 |
20200211989 | Optimised fabrication methods for a structure to be assembled by hybridisation and a device comprising such a structure - A method of fabrication of a semiconducting structure intended to be assembled to a second support by hybridisation. The semiconducting structure comprising an active layer comprising a nitrided semiconductor. The method comprises a step for the formation of at least one first and one second insert and during this step, a nickel layer is formed in contact with the support surface, and a localised physico-chemical etching step of the active layer, a part of the active layer comprising the active region being protected by the nickel layer. | 2020-07-02 |
20200211990 | PACKAGED SEMICONDUCTOR DEVICE WITH ELECTROPLATED PILLARS - In a described example, a device includes an overcoat layer covering an interconnect; an opening in the overcoat layer exposing a portion of a surface of the interconnect; a stud on the exposed portion of the surface of the interconnect in the opening; a surface of the stud approximately coplanar with a surface of the overcoat layer; and a conductive pillar covering the stud and covering a portion of the overcoat layer surrounding the stud, the conductive pillar having a planar and un-dished surface facing away from the stud and the overcoat layer. | 2020-07-02 |
20200211991 | SEMICONDUCTOR STRUCTURE AND METHOD OF MANUFACTURING THE SAME - The present disclosure provides a semiconductor structure and a method of manufacturing the semiconductor structure. The semiconductor structure includes a substrate, a plurality of metallic pillars, a plurality of metallic protrusions, a capping layer, and a passivation layer. The metallic pillars are disposed on the substrate. The metallic protrusions extend from an upper surface of the metallic pillars. The capping layer is disposed on the metallic protrusions. The passivation layer is disposed on sidewalls of the protrusions and the capping layer. | 2020-07-02 |
20200211992 | INTERCONNECT FOR ELECTRONIC DEVICE - A semiconductor die includes a substrate and an integrated circuit provided on the substrate and having contacts. An electrically conductive layer is provided on the integrated circuit and defines electrically conductive elements electrically connected to the contacts. Electrically conductive interconnects coupled with respective electrically conductive elements. The electrically conductive interconnects have at least one of different sizes or shapes from one another. | 2020-07-02 |
20200211993 | METHODS AND SYSTEMS FOR MANUFACTURING PILLAR STRUCTURES ON SEMICONDUCTOR DEVICES - A method of manufacturing a semiconductor device having a conductive substrate having a first surface, a second surface opposite the first surface, and a passivation material covering a portion of the first surface can include applying a seed layer of conductive material to the first surface of the conductive substrate and to the passivation material, the seed layer having a first face opposite the conductive substrate. The method can include forming a plurality of pillars comprising layers of first and second materials. The method can include etching the seed layer to undercut the seed layer between the conductive substrate and the first material of at least one of the pillars. In some embodiments, a cross-sectional area of the seed layer in contact with the passivation material between the first material and the conductive substrate is less than the cross-sectional area of the second material. | 2020-07-02 |
20200211994 | CONTROL DEVICE AND CIRCUIT BOARD - A control device and a circuit board are provided. The control device can cooperate with the circuit board, and includes a ball grid array. The ball grid array includes a plurality of power balls and a plurality of ground balls, which are jointly arranged in a ball region. The power balls and the ground balls are respectively divided into a plurality of power ball groups and a plurality of ground ball groups. One of the ground ball groups includes two ground balls and is adjacent to a power ball group. A ball pitch between the two ground balls is greater than that between one of the power balls and one of the ground balls adjacent to each other. The circuit board includes a contact pad array corresponding to the ball grid array of the control device so that the control device can be disposed on the circuit board. | 2020-07-02 |
20200211995 | CREATING 3D FEATURES THROUGH SELECTIVE LASER ANNEALING AND/OR LASER ABLATION - A semiconductor device includes a solder supporting material above a substrate. The semiconductor device also includes a solder on the solder supporting material. The semiconductor device further includes selective laser annealed or laser ablated portions of the solder and underlying solder supporting material to form a semiconductor device having 3D features. | 2020-07-02 |
20200211996 | ANISOTROPIC CONDUCTIVE FILM WITH CARBON-BASED CONDUCTIVE REGIONS AND RELATED SEMICONDUCTOR ASSEMBLIES, SYSTEMS, AND METHODS - An anisotropic conductive film (ACF) is formed with an ordered array of discrete regions that include a conductive carbon-based material. The discrete regions, which may be formed at small pitch, are embedded in at least one adhesive dielectric material. The ACF may be used to mechanically and electrically interconnect conductive elements of initially-separate semiconductor dice in semiconductor device assemblies. Methods of forming the ACF include forming a precursor structure with the conductive carbon-based material and then joining the precursor structure to a separately-formed structure that includes adhesive dielectric material to be included in the ACF. Sacrificial materials of the precursor structure may be removed and additional adhesive dielectric material formed to embed the discrete regions with the conductive carbon-based material in the adhesive dielectric material of the ACF. | 2020-07-02 |
20200211997 | Method for Fastening a Semiconductor Chip on a Substrate, and Electronic Component - A method for fastening a semiconductor chip on a substrate and an electronic component are disclosed. In an embodiment a method includes providing a semiconductor chip, applying a solder metal layer sequence on the semiconductor chip, providing a substrate, applying a metallization layer sequence on the substrate, applying the semiconductor chip on the substrate via the solder metal layer sequence and the metallization layer sequence and heating the applied semiconductor chip on the substrate for fastening the semiconductor chip on the substrate. The solder metal layer may include a first metallic layer comprising an indium-tin alloy, a barrier layer arranged above the first metallic layer and a second metallic layer comprising gold arranged between the barrier layer and the semiconductor chip, wherein an amount of substance of the gold in the second metallic layer is greater than an amount of substance of tin in the first metallic layer. | 2020-07-02 |
20200211998 | RADIO-FREQUENCY MODULE AND COMMUNICATION DEVICE - A radio-frequency module includes: a transmitting circuit disposed on a mounting substrate to process a radio-frequency signal input from a transmission terminal and to output a resultant signal to a common terminal; a receiving circuit disposed on the mounting substrate to process a radio-frequency signal input from the common terminal and to output a resultant signal to a reception terminal; a first inductor included in a first transmitting circuit; and a bonding wire connected to the ground and bridging over the first inductor. | 2020-07-02 |
20200211999 | METHODS AND SYSTEMS FOR MANUFACTURING SEMICONDUCTOR DEVICES - A thermocompression bonding (TCB) apparatus can include a wall having a height measured in a first direction and configured to be positioned between a first pressing surface and a second pressing surface of a semiconductor bonding apparatus. The apparatus can include a cavity at least partially surrounded by the wall, the cavity sized to receive a semiconductor substrate and a stack of semiconductor dies positioned between the semiconductor substrate and the first pressing surface, the stack of semiconductor dies and semiconductor substrate having a combined unpressed stack height as measured in the first direction. In some embodiments, the unpressed stack height is greater than the height of the wall, and the wall is configured to be contacted by the first pressing surface to limit movement of the first pressing surface toward the second pressing surface during a semiconductor bonding process. | 2020-07-02 |
20200212000 | METHODS AND SYSTEMS FOR MANUFACTURING SEMICONDUCTOR DEVICES - A thermocompression bonding (TCB) apparatus can include a wall having a height measured in a first direction and configured to be positioned between a first pressing surface and a second pressing surface of a semiconductor bonding apparatus. The apparatus can include a cavity at least partially surrounded by the wall, the cavity sized to receive a semiconductor substrate and a stack of semiconductor dies positioned between the semiconductor substrate and the first pressing surface, the stack of semiconductor dies and semiconductor substrate having a combined unpressed stack height as measured in the first direction. In some embodiments, the unpressed stack height is greater than the height of the wall, and the wall is configured to be contacted by the first pressing surface to limit movement of the first pressing surface toward the second pressing surface during a semiconductor bonding process. | 2020-07-02 |
20200212001 | METHODS AND SYSTEMS FOR MANUFACTURING SEMICONDUCTOR DEVICES - A semiconductor manufacturing system comprises a laser and a heated bond tip and is configured to bond a die stack in a semiconductor assembly. The semiconductor assembly includes a wafer, manufacture from a material that is optically transparent to a beam emitted by the laser and configured to support a die stack comprising a plurality of semiconductor dies. A metal film is deposited on the wafer and heatable by the beam emitted by the laser. The heated bond tip applies heat and pressure to the die stack, compressing the die stack between the heated bond tip and the metal film and thermally bonding dies in the stack by heat emitted by the heated bond tip and the metal film when the metal film is heated by the beam emitted from the laser. | 2020-07-02 |
20200212002 | BOND CHUCKS HAVING INDIVIDUALLY-CONTROLLABLE REGIONS, AND ASSOCIATED SYSTEMS AND METHODS - A bond chuck having individually-controllable regions, and associated systems and methods are disclosed herein. The bond chuck comprises a plurality of individual regions configured to be individually heated independent of one another. In some embodiments, the individual regions include a first region configured to be heated to a first temperature, and a second region peripheral to the first region and configured to be heated to a second temperature different than the first temperature. In some embodiments, the bond chuck further comprises (a) a first coil disposed within the first region and configured to heat the first region to the first temperature, and (b) a second coil disposed within the second region and configured to heat the second region to the second temperature. The bond chuck can be positioned proximate a substrate of a semiconductor device such that heating the first region and/or second region affect the viscosity of an adhesive used to bond substrates of the semiconductor device to one another. Accordingly, heating the first region and/or the second region can cause the adhesive on the substrate to flow in a lateral, predetermined direction. | 2020-07-02 |
20200212003 | BOND CHUCKS HAVING INDIVIDUALLY-CONTROLLABLE REGIONS, AND ASSOCIATED SYSTEMS AND METHODS - A bond chuck having individually-controllable regions, and associated systems and methods are disclosed herein. The bond chuck comprises a plurality of individual regions that are movable relative to one another in a longitudinal direction. In some embodiments, the individual regions include a first region having a first outer surface, and a second region peripheral to the first region and including a second outer surface. The first region is movable in a longitudinal direction to a first position, and the second region is movable in the longitudinal direction to a second position, such that in the second position, the second outer surface of the second region extends longitudinally beyond the first outer surface of the first region. The bond chuck can be positioned proximate a substrate of a semiconductor device such that movement of the first region and/or second region affect a shape of the substrate, which thereby causes an adhesive on the substrate to flow in a lateral, predetermined direction. | 2020-07-02 |
20200212004 | PLASMA ACTIVATION TREATMENT FOR WAFER BONDING - Embodiments of wafer bonding methods are disclosed. In an example, a first plasma activation treatment based on oxygen or an inert gas is performed on a front surface of a first wafer and a front surface of a second wafer. After the first plasma activation treatment, a second plasma activation treatment based on water molecules is performed on the front surface of the first wafer and the front surface of the second wafer. After the second plasma activation treatment, the first wafer and the second wafer are bonded such that the treated front surface of the first wafer is in physical contact with the treated front surface of the second wafer. | 2020-07-02 |
20200212005 | SEMICONDUCTOR PACKAGE DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor package device includes a circuit layer, a first set of stacked components, a first conductive wire, a space and an electronic component. The first set of stacked components is disposed on the circuit layer. The first conductive wire electrically connects the first set of stacked components. The space is defined between the first set of stacked components and the circuit layer. The space accommodates the first conductive wire. The electronic component is disposed in the space. | 2020-07-02 |
20200212006 | PACKAGE CONTACT STRUCTURE, SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF - A package contact structure, a semiconductor package and a manufacturing method are provided. The package contact structure includes a conductive feature and a dielectric barrier. The conductive feature includes a first portion and a second portion disposed on the first portion. Materials of the first portion and the second portion are different. The dielectric barrier is sleeved on the first portion and extends to cover at least a part of the second portion. A maximum height of the dielectric barrier is less than a maximum height of the conductive feature. | 2020-07-02 |
20200212007 | Semiconductor Package - A semiconductor device is disclosed. The semiconductor device comprises a first die, a second die, and a redistribution structure. The first die and the second die are electrically connected to the redistribution structure. There are no solder bumps between the first die and the redistribution structure. There are no solder bumps between the second die and the redistribution structure. The first die and the second die have a shift with regard to each other from a top view. | 2020-07-02 |
20200212008 | APPARATUSES AND METHODS FOR ARRANGING THROUGH-SILICON VIAS AND PADS IN A SEMICONDUCTOR DEVICE - A semiconductor device may include a bond pad/probe pad pair that includes a bond pad and a probe pad positioned to be adjacent to each other to form an L shape. The device may also include a through-silicon via (TSV) pad positioned to be at least partially or entirely inside the recess area of the L shape. The bond pad and the probe pad may each have an opening, and at least a portion of the opening of the bond pad may extend into a portion of the opening of the probe pad. The arrangement of the bond pad, the probe pad and the TSV may be implemented in a wafer-on-wafer (WOW) that includes multiple stacked wafers. A method of fabricating the TSV may include etching the stacked wafers to form a TSV opening that extends through the multiple wafers, and filling the TSV opening with conductive material. | 2020-07-02 |
20200212009 | DIODE FOR USE IN TESTING SEMICONDUCTOR PACKAGES - Embodiments described herein provide techniques for testing a semiconductor package by using a diode to couple a test pad to a contact pad. In one scenario, a package comprises a die stack comprising one or more dies and a molding compound encapsulating the die stack. In this package, a substrate is over the molding compound. Also, a test pad and a contact pad are on a surface of the substrate. The contact pad is coupled to the die stack. A diode couples the test pad to the contact pad. In one example, the test pad is coupled to a P side of the diode's P-N junction and the contact pad is coupled to an N side of the diode's P-N junction. In operation, current can flow from the test pad through the contact pad (and the die stack), but current cannot flow from the contact pad through the test pad. | 2020-07-02 |
20200212010 | SEMICONDUCTOR PACKAGES WITH PASS-THROUGH CLOCK TRACES AND ASSOCIATED SYSTEMS AND METHODS - Semiconductor packages with pass-through clock traces and associated devices, systems, and methods are disclosed herein. In one embodiment, a semiconductor device includes a package substrate including a first surface having a plurality of substrate contacts, a first semiconductor die having a lower surface attached to the first surface of the package substrate, and a second semiconductor die stacked on top of the first semiconductor die. The first semiconductor die includes an upper surface including a first conductive contact, and the second semiconductor die includes a second conductive contact. A first electrical connector electrically couples a first one of the plurality of substrate contacts to the first and second conductive contacts, and a second electrical connector electrically couples a second one of the plurality of substrate contacts to the first and second conductive contacts. | 2020-07-02 |
20200212011 | MONOLITHIC CHIP STACKING USING A DIE WITH DOUBLE-SIDED INTERCONNECT LAYERS - An apparatus is provided which comprises: a first die having a first surface and a second surface, the first die comprising: a first layer formed on the first surface of the first die, and a second layer formed on the second surface of the first die; a second die coupled to the first layer; and a plurality of structures to couple the apparatus to an external component, wherein the plurality of structures is coupled to the second layer. | 2020-07-02 |
20200212012 | TSV-LESS DIE STACKING USING PLATED PILLARS/THROUGH MOLD INTERCONNECT - A device package has substrates disposed on top of one another to form a stack, and pads formed on at least one of the top surface and the bottom surface of each of the substrates. The device package has interconnects electrically coupling at least one of the top surface and the bottom surface of each substrate to at least one of the top surface and the bottom surface of another substrate. The device package has pillars disposed between at least one of the top surface and the bottom surface of one or more substrates to at least one of the top surface and the bottom surface of other substrates. The device package also has adhesive layers formed between at least one of the top surface and the bottom surface of one or more substrates to at least one of the top surface and the bottom surface of other substrates. | 2020-07-02 |
20200212013 | SYSTEMS AND METHODS FOR FLASH STACKING - A three-dimensional stacking technique performed in a wafer-to-wafer fashion reducing the machine movement in production. The wafers are processed with metallic traces and stacked before dicing into separate die stacks. The traces of each layer of the stacks are interconnected via electroless plating. | 2020-07-02 |
20200212014 | LED Filament Assembly and Lamp Including the Same - An LED filament assembly includes a frame, a first electrode disposed on a first end of the frame, and a second electrode disposed on a second end of the frame. The LED filament assembly includes a first group of LED chips capable of emitting a first color, a second group of LED chips capable of emitting a second color, and a third group of LED chips capable of emitting a third color. The first group of LED chips is disposed on the frame along a longitudinal axis, connected in series, and electrically connected to the first electrode and the second electrode. Similarly, the second and the third group of LED chips are also disposed on the frame along the longitudinal axis, connected in series, and electrically connected to the first electrode and the second electrode. A lamp including such an LED filament assembly is also disclosed. | 2020-07-02 |
20200212015 | LIGHT EMITTING DEVICE AND METHOD FOR MANUFACTURING LIGHT EMITTING DEVICE - A light emitting device includes: a plurality of light emitting elements; a plurality of light transmissive members, each located on an upper surface of a respective one of the light emitting element; a mounting board on which the light emitting elements are disposed; a first cover member located on or above the mounting board, the first cover member comprising: a first reflective material containing layer disposed between the light emitting elements and containing a first reflective material, and a light transmissive layer disposed between the light transmissive members; and a second cover member disposed around the light emitting elements and comprising a second reflective material. | 2020-07-02 |
20200212016 | METHOD OF MOUNTING SEMICONDUCTOR ELEMENTS AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of mounting semiconductor elements, including stretching a stretchable film against an elastic force into a stretched state and disposing a plurality of semiconductor elements in predetermined regions on the stretchable film in the stretched state. Each of the predetermined regions have a predetermined group of semiconductor elements spaced apart from one other at a first distance. The stretchable film is released from the stretched state by using the elastic force of the stretchable film. The first distance between adjacent semiconductor elements in each of the predetermined regions at the time of disposing the semiconductor elements on the stretchable film in the stretched state is reduced to a predetermined second distance of a predetermined mounting distance after releasing the stretchable film from the stretched state. | 2020-07-02 |
20200212017 | LED PIXEL DEVICE HAVING CHIP STACK STRUCTURE - An LED pixel device is disclosed. The LED pixel device includes a first light-transmitting substrate, a second light-transmitting substrate overlying the first light-transmitting substrate, a third light-transmitting substrate overlying the second light-transmitting substrate, a first light-emitting cell underlying the first light-transmitting substrate, a second light-emitting cell interposed between the first light-transmitting substrate and the second light-transmitting substrate, and a third light-emitting cell interposed between the second light-transmitting substrate and the third light-transmitting substrate. The first light-emitting cell, the second light-emitting cell, and the third light-emitting cell emit light of different wavelengths. | 2020-07-02 |
20200212018 | Integrated Circuit Package and Method - A packaged semiconductor device including an integrated passive device-containing package component disposed between a power module and an integrated circuit-containing package and a method of forming the same are disclosed. In an embodiment, a device includes a first package component including a first integrated circuit die; a first encapsulant at least partially surrounding the first integrated circuit die; and a redistribution structure on the first encapsulant and coupled to the first integrated circuit die; a second package component bonded to the first package component, the second package component including an integrated passive device; and a second encapsulant at least partially surrounding the integrated passive device; and a power module attached to the first package component through the second package component. | 2020-07-02 |
20200212019 | METHOD FOR FABRICATING ELECTRONIC PACKAGE - An electronic package is provided, including: a first substrate having a first insulating portion; a first electronic component disposed on the first substrate; a second substrate having a second insulating portion and stacked on the first substrate through a plurality of conductive elements; and a first encapsulant formed between the first substrate and the second substrate. The first insulating portion of the first substrate differs in rigidity from the second insulating portion of the second substrate. As such, during a high temperature process, one of the first substrate and the second substrate pulls at the other to bend toward the same direction, thereby reducing warpage deviation of the overall electronic package. The present invention further provides a method for fabricating the electronic package. | 2020-07-02 |
20200212020 | MICROELECTRONIC ASSEMBLIES HAVING AN INTEGRATED CAPACITOR - Microelectronic assemblies, related devices, and methods are disclosed herein. In some embodiments, a microelectronic assembly may include a die having a first surface and an opposing second surface; a capacitor having a surface, wherein the surface of the capacitor is coupled to the first surface of the die; and a conductive pillar coupled to the first surface of the die. In some embodiments, a microelectronic assembly may include a capacitor in a first dielectric layer; a conductive pillar in the first dielectric layer; a first die having a surface in the first dielectric layer; and a second die having a surface in a second dielectric layer, wherein the second dielectric layer is on the first dielectric layer, and wherein the surface of the second die is coupled to the capacitor, to the surface of the first die, and to the conductive pillar. | 2020-07-02 |
20200212021 | ELECTRONIC DEVICE - An electronic device is disclosed, which comprises: a substrate; a plurality of sensing elements disposed on the substrate; and a plurality of electronic modules disposed on the substrate, each electronic module comprising a plurality of electronic elements, wherein the plurality of electronic modules are arranged in a manner to expose the plurality of sensing elements. | 2020-07-02 |
20200212022 | MICRO LIGHT-EMITTING DIODE DISPLAY FABRICATION AND ASSEMBLY APPARATUS - Micro light-emitting diode display fabrication processes and assembly apparatuses are described. In an example, a micro light emitting diode pixel structure includes a backplane including a glass substrate having an insulating layer disposed thereon, and a pixel thin film transistor circuit disposed in and on the insulating layer, the pixel thin film transistor circuit including a gate electrode and a channel. The micro light emitting diode pixel structure also includes a front plane including a metal pad coupled to the pixel thin film transistor circuit of the backplane, a micro light emitting diode device bonded to the metal pad, a spacer adjacent sidewalls of the micro light emitting diode, the spacer including a high refractive index material, and an insulating layer surrounding the spacer. | 2020-07-02 |
20200212023 | SEMICONDUCTOR PACKAGE DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device package includes a first semiconductor device having a first surface, an interconnection element having a surface substantially coplanar with the first surface of the first semiconductor device, a first encapsulant encapsulating the first semiconductor device and the interconnection element, and a second semiconductor device disposed on and across the first semiconductor device and the interconnection element. | 2020-07-02 |
20200212024 | Optoelectronic Component and Assembly with such a Component - An optoelectronic component and an assembly with an optoectronic component are disclosed. In an embodiment an optoelectronic component includes an optical element with an outer surface and an inner surface that faces away from the outer surface, wherein the inner surface includes a first region of the optical element, in which the inner surface is flat, wherein the inner surface includes a second region of the optical element, wherein the second region adjoins the first region, and wherein the inner surface includes a third region of the optical element, in which the inner surface extends from the second region in the direction of a housing. | 2020-07-02 |
20200212025 | LIGHTING DEVICE COMPRISING ORGANIC LIGHT EMITTING PANEL AND INORGANIC LIGHT EMITTING DIODE - A lighting device comprises an organic light emitting panel, an inorganic light emitting diode on the organic light emitting panel, and a first lens structure at least partially surrounding the inorganic light emitting diode. The organic light emitting panel may include a base substrate, an auxiliary electrode on the base substrate, a first electrode on the auxiliary electrode, a passivation layer on the first electrode, a light emitting layer on the first electrode, a second electrode on the light emitting layer, and an encapsulation layer on the second electrode. | 2020-07-02 |
20200212026 | DISPLAY DEVICE - A display device can include a substrate on which a semiconductor element and a common electrode are disposed; a light emitting diode which is disposed on the substrate and includes an n-type layer, a light emitting layer, and a p-type layer; an insulating layer disposed on the substrate and the light emitting diode; and a first connecting electrode which is connected to the light emitting diode and the semiconductor element. Accordingly, it is possible to minimize defects which can be caused during a process of disposing the light emitting diode on the substrate. | 2020-07-02 |
20200212027 | MEMORY DEVICE AND MICROELECTRONIC PACKAGE HAVING THE SAME - The invention provides a memory device and microelectronic package having the same. The microelectronic package comprises at least one memory device which is adapted to be stacked vertically with one another, and a processing device stacked vertically and adjacently with the at least one memory device and electrically connected to the conductive interconnects. Each of the memory devices comprises a substrate and a plurality of memory units. The substrate presents a front surface and a back surface. The memory units are formed on the front surface, each of which comprises a plurality of memory cells and a plurality of conductive interconnects electrically connected to the memory cells. In each of the memory units, the conductive interconnects contribute to a plurality of signal channels each of which is dedicated to transmit signals from the processing device to one of the memory units and vice versa. | 2020-07-02 |
20200212028 | MICROCONTROLLER UNIT AND FABRICATION METHOD THEREOF - The present disclosure provides a microcontroller unit and its fabrication method. The microcontroller unit includes a logic control substrate, and also includes at least one memory die and at least one non-memory die, which are disposed on the logic control substrate. The logic control substrate includes a semiconductor device layer and an interconnection dielectric layer. A central processing unit and at least one logic controller are formed in the semiconductor device layer. All memory dies are disposed on the interconnection dielectric layer side by side or stacked one over another, and the at least one memory die is electrically connected to the central processing unit through a corresponding electrical interconnection structure in the interconnection dielectric layer. All non-memory dies are disposed on the interconnection dielectric layer side by side or stacked one over another and are electrically connected to corresponding logic controllers through corresponding electrical interconnection structures in the interconnection dielectric layer. | 2020-07-02 |
20200212029 | APPARATUS WITH A CURRENT-GAIN LAYOUT - An apparatus includes: a first substrate comprising a first channel that includes a first plurality of doped regions on the first substrate; a second substrate comprising a second channel that includes a second plurality of doped regions in the second substrate, wherein: the doped regions of the second substrate are electrically and/or physically separate from those of the first substrate, and the second channel is aligned colinearly with the first channel; and a conductive structure extending across the first substrate and the second substrate and electrically connecting matching doped regions of the first channel and the second channel. | 2020-07-02 |
20200212030 | LAYOUT PATTERN FOR MAGNETORESISTIVE RANDOM ACCESS MEMORY - A layout pattern for magnetoresistive random access memory (MRAM) includes: a first magnetic tunneling junction (MTJ) pattern on a substrate; a second MTJ pattern adjacent to the first MTJ pattern; and a first metal interconnection pattern between the first MTJ pattern and the second MTJ pattern, wherein the first MTJ pattern, the first metal interconnection pattern, and the second MTJ pattern comprise a staggered arrangement. | 2020-07-02 |
20200212031 | WAFER TRUST VIA LOCATION LOCKED CIRCUIT LAYOUT WITH MEASURABLE INTEGRITY - Techniques to determine whether the design of integrated circuit (IC) has been tampered with during wafer manufacturing by using an enhanced library and layout methodology. The enhanced library may include location sensitive cells networked together in a mesh architecture where paths through the mesh can be used to detect relative position of location sensitive cells. The techniques further include algorithms that fill any unused space on an IC with additional elements from the enhanced library to minimize the opportunity to modify the IC by including additional circuit function or manipulating the layout. By physically locking down the circuit placement such that there is no available area and gives improved ability to detect changes in the physical location behavior of the circuit, therefore reduces the risk that unauthorized circuit manipulation will go undetected. | 2020-07-02 |
20200212032 | SEMICONDUCTOR DEVICES WITH PACKAGE-LEVEL CONFIGURABILITY - A semiconductor device assembly includes a substrate and a die coupled to the substrate. The die includes a first contact pad electrically coupled to a first circuit on the die including at least one active circuit element and a second contact pad electrically coupled to a second circuit on the die including only passive circuit elements. The substrate includes a substrate contact electrically coupled to the first contact pad, and the substrate is electrically isolated from the second contact pad. | 2020-07-02 |
20200212033 | ELECTROSTATIC DISCHARGE PROTECTION APPARATUS AND INTEGRATED PASSIVE DEVICE WITH CAPACITORS - An electrostatic discharge (ESD) protection apparatus and an integrated passive device (IPD) with capacitor(s) are provided. The ESD protection apparatus includes a transistor, an impedance, and a capacitor disposed in a redistribution layer (RDL) structure of a package. The first terminal and the second terminal of the transistor are respectively coupled to a first power rail and a second power rail of the RDL structure. A first terminal of the impedance is coupled to the first power rail. A second terminal of the impedance is coupled to a control terminal of the transistor. A first terminal of the capacitor is coupled to the second terminal of the impedance. A second terminal of the capacitor is coupled to the second power rail. | 2020-07-02 |
20200212034 | INTEGRATED VERTICAL AND LATERAL SEMICONDUCTOR DEVICES - An integrated circuit die that may have one vertical transistor and one horizontal transistor is disclosed. The transistors may have substantially different breakdown voltages. The vertical transistor may be used in power circuitry applications and the horizontal transistor may be used in logic circuitry applications. | 2020-07-02 |
20200212035 | SEMICONDUCTOR DEVICES WITH FIN-SHAPED ACTIVE REGIONS AND METHODS OF FABRICATING SAME - A semiconductor device includes a first fin type pattern in a first region of a substrate. The first fin type pattern includes a plurality of spaced-apart fins having respective sidewalls defined by a first trench. A first gate structure is provided, which intersects the first fin type pattern. A second fin type pattern is provided in a second region of a substrate. The second fin type pattern includes a fin having a sidewall defined by a second trench. A second gate structure is provided, which intersects the second fin type pattern. A field insulating film fills at least a part of the first trench and at least a part of the second trench. The field insulating film has a first upper surface, which is in contact with at least one sidewall of the first fin type pattern and is spaced from a bottom of the first trench by a first height, and a second upper surface, which in contact with the sidewall of the second fin type pattern and is spaced from a bottom of the second trench by a second height different from the first height. | 2020-07-02 |
20200212036 | DUAL TRANSPORT ORIENTATION FOR STACKED VERTICAL TRANSPORT FIELD-EFFECT TRANSISTORS - A semiconductor structure includes a substrate, a vertical fin disposed over a top surface of the substrate, a first vertical transport field-effect transistor (VTFET) disposed over the top surface of the substrate surrounding a first portion of the vertical fin, an isolation layer disposed over the first VTFET surrounding a second portion of the vertical fin, and a second VTFET disposed over a top surface of the isolation layer surrounding a third portion of the vertical fin. The first portion of the vertical fin includes a first semiconductor layer with a first crystalline orientation providing a first vertical transport channel for the first VTFET, the second portion of the vertical fin includes an insulator, and the third portion of the vertical fin includes a second semiconductor layer with a second crystalline orientation providing a second vertical transport channel for the second VTFET. | 2020-07-02 |
20200212037 | MINIMUM WIDTH DEVICE FOR POWER SAVING - A semiconductor structure is provided that includes a first FinFET device for low power applications and a second FinFET device for non-low power applications. The first FinFET device has an active fin height, i.e., channel height, which is less that an active fin height of the second FinFET device. The active fin height adjustment is achieved utilizing an isolation structure that has a constant height in the region including the first FinFET device and the region including the second FinFET device. | 2020-07-02 |
20200212038 | SELF-ALIGNED STACKED GE/SI CMOS TRANSISTOR STRUCTURE - An integrated circuit structure comprises a substrate and a stacked channel of self-aligned heterogeneous materials, wherein the stacked channel of self-aligned heterogeneous materials comprises an NMOS channel material over the substrate; and a PMOS channel material stacked over and self-aligned with the NMOS channel material. A heterogeneous gate stack is in contact the both the NMOS channel material and the PMOS channel material. | 2020-07-02 |
20200212039 | NON-PLANAR SEMICONDUCTOR DEVICE HAVING DOPED SUB-FIN REGION AND METHOD TO FABRICATE SAME - Non-planar semiconductor devices having doped sub-fin regions and methods of fabricating non-planar semiconductor devices having doped sub-fin regions are described. For example, a method of fabricating a semiconductor structure involves forming a plurality of semiconductor fins above a semiconductor substrate. A solid state dopant source layer is formed above the semiconductor substrate, conformal with the plurality of semiconductor fins. A dielectric layer is formed above the solid state dopant source layer. The dielectric layer and the solid state dopant source layer are recessed to approximately a same level below a top surface of the plurality of semiconductor fins, exposing protruding portions of each of the plurality of semiconductor fins above sub-fin regions of each of the plurality of semiconductor fins. The method also involves driving dopants from the solid state dopant source layer into the sub-fin regions of each of the plurality of semiconductor fins. | 2020-07-02 |
20200212040 | METHODS AND APPARATUSES INCLUDING AN ACTIVE AREA OF A TAP INTERSECTED BY A BOUNDARY OF A WELL - Apparatuses and methods are disclosed. One such apparatus includes a well having a first type of conductivity formed within a semiconductor structure having a second type of conductivity. A boundary of the well intersects an active area of a tap to the well. | 2020-07-02 |