27th week of 2020 patent applcation highlights part 69 |
Patent application number | Title | Published |
20200212141 | DISPLAY PANEL, ASSOCIATED DISPLAY SYSTEM, AND ASSOCIATED METHOD - A display panel is disclosed. The display panel includes a plurality of pixels arranged in a pixel array, a first selecting circuit, and a control circuit. The pixel array includes a plurality of rows. The first selecting circuit is coupled to the display panel, and includes a plurality of clusters of first switch. Each first switch couples to a row, and the plurality of clusters of first switch are arranged to be sequentially and repeatedly activated, wherein a number of the row is greater than a number of first switches in one cluster. The control circuit is coupled to the first selecting circuit, and arranged to sequentially provide a pulse signal to the display panel via a cluster of first switch being activated. | 2020-07-02 |
20200212142 | Organic Electronic Component with Electron Injection Layer - A device is disclosed. In an embodiment the device includes an anode, an organic active layer above the anode, an organic layer sequence above the organic active layer, a metallic layer above the organic layer sequence and a cathode above the metallic layer, wherein the metallic layer includes Yb. | 2020-07-02 |
20200212143 | ORGANIC LIGHT-EMITTING DISPLAY APPARATUS AND METHOD OF MANUFACTURING THE SAME - An organic light-emitting display apparatus including: a substrate; a pixel electrode located on the substrate; a pixel-defining film coveting an end portion of the pixel electrode; an intermediate layer located on the pixel electrode and including an emission layer; a counter electrode located on the intermediate layer; a passivation layer located on the counter electrode and including a cover portion covering a top surface of the counter electrode and a protrusion extending from an end portion of the cover portion away from the substrate; and an encapsulation member covering the passivation layer. | 2020-07-02 |
20200212144 | ELECTROLUMINESCENT DISPLAY DEVICE AND METHOD FOR MANUFACTURING THE SAME - Display devices and, in particular, electroluminescent display devices including a lower structure of a bank causing a highly conductive hole injection layer to take on a shape so as to reduce a leakage current, and a method for manufacturing the same are described. An electroluminescent display device includes a substrate having a plurality of pixels, a bank located at a boundary between the subpixels, a first electrode in each subpixel, a separation induction layer between the bank and the first electrode, a p-type layer with a first portion on the bank and a second portion on an emission assembly of the subpixels, and at least one common layer on the p-type layer. | 2020-07-02 |
20200212145 | ORGANIC LIGHT EMITTING DISPLAY DEVICE - An organic light-emitting display comprises a substrate having a first area and second and third areas neighboring the first area in a column direction and defined in edge parts of both sides in the first area; a plurality of subpixels arranged on the substrate in the column direction and a row direction crossing the column direction; a plurality of first electrodes allocated to each of the plurality of subpixels; and a bank positioned on the first electrodes, wherein the bank comprises a first bank having a first opening exposing the plurality of first electrodes arranged in the row direction; and a second bank having a second opening exposing the plurality of first electrodes arranged in the column direction in the first area and a third opening exposing the one first electrode in at least one of the second area and the third area. | 2020-07-02 |
20200212146 | ORGANIC LIGHT-EMITTING DISPLAY DEVICE - An organic light-emitting display device comprises a substrate; a plurality of sub-pixels arranged in a first horizontal line and a second horizontal line on the substrate; at least one thin film transistor and a first electrode of an organic light-emitting diode connected to the thin film transistor, the at least one thin film transistor and the organic light-emitting diode being disposed in each of the plurality of sub-pixels; a first bank layer is disposed on the first electrode and exposing the first electrode; and a second bank layer disposed on the first bank layer and exposing the first bank layer and the first electrode, wherein the second bank layer is consecutively arranged in the first horizontal line and the second horizontal line and including a first bending portion at a boundary between the first horizontal line and the second horizontal line. | 2020-07-02 |
20200212147 | Display Device and Method for Manufacturing the Same - Disclosed is a display device. In accordance with the display device, before an organic stack of a light-emitting diode is formed, a sticker is attached to a substrate, while a camera hole-forming portion and a margin area around the same are present, to form the organic stack, and the sticker and components on top of the sticker, such as the organic stack, are removed, so that the edge of the organic stack can be aligned without any additional process using separate masks and the reliability of the display device can be improved due to the provision of the organic stack at a location spaced apart from the camera hole by the margin area. | 2020-07-02 |
20200212148 | ORGANIC LIGHT-EMITTING DISPLAY DEVICE AND METHOD OF FABRICATING THE SAME - An organic light emitting display device according to an example comprises a substrate; a plurality of first bank layers disposed on the substrate in a first direction and a second direction different from the first direction to define a plurality of pixels; a plurality of second bank layers disposed on the first bank layers in the first direction to partition pixel columns of different colors; and a third bank layer formed in each of the pixel columns in the second direction to divide each of the pixel columns into a plurality of groups each including a plurality of the pixels | 2020-07-02 |
20200212149 | DISPLAY PANEL, MANUFACTURING METHOD THEREOF AND DISPLAY DEVICE - Provided is a display panel, comprising: a substrate, and a planarization layer, an anode layer, a pixel definition layer, a cathode layer and an encapsulation layer sequentially stacked on the substrate; wherein in an edge area of the display panel, the pixel definition layer comprises a retaining wall group on the anode layer, comprising sub-retaining walls which are spaced apart, and the retaining wall group comprises a first side close to a display area and a second side away therefrom, wherein spaces of the sub-retaining walls form a path with a length greater than a straight line distance from the first side to the second side. The diffusion rate and diffusion range of the organic layer are controlled by performing anode hole optimization to form staggered sub-retaining walls, thereby reducing a number of edge retaining walls and reducing the edge area to increase a screen occupation ratio. | 2020-07-02 |
20200212150 | DISPLAY DEVICE AND FABRICATING METHOD THEREOF - A display device including an organic light emitting layer, a pixel circuit, and conductive adhesive having a first density and being in electrical communication with the organic light emitting layer and the pixel circuit, wherein during bending certain portions of the conductive adhesive are compressed to a second density higher than the first density and certain other portions of the conductive adhesive are expanded to a third density lower than the first density. | 2020-07-02 |
20200212151 | FLEXIBLE DISPLAY PANEL AND FLEXIBLE DISPLAY DEVICE - A flexible display panel and a flexible device are provided. At least one groove or at least one protrusion is disposed between two adjacent signal lines of a first metal layer of an edge of an organic layer and a total length of the edge of the organic layer between the two adjacent signal lines is increased, so that a continuous residual second metal layer between the two adjacent signal lines is reduced. A short circuit problem existed in the signal lines of the first metal layer in a laminated structure of the first metal layer/the organic layer/the second metal layer is avoided. Meanwhile, a distance between the two adjacent signal lines is not increased, and thus a signal line layout of the first metal layer is not affected. Therefore, the stability and reliability of the flexible display panel are effectively improved. | 2020-07-02 |
20200212152 | DISPLAY APPARATUS AND A METHOD OF MANUFACTURING THE SAME - A display apparatus including: a base substrate; a first active pattern disposed on the base substrate, a first insulating layer disposed on the first active pattern; a first gate electrode disposed on the first insulating layer; a second insulating layer disposed on the first gate electrode; a ring dummy pattern disposed on the second insulating layer; a third insulating layer disposed on the second insulating layer; and a first drain electrode disposed on the third insulating layer, and electrically connected to the first active pattern through a contact hole which is formed through the third insulating layer, the second insulating layer and the first insulating layer, wherein the first drain electrode is disposed in an opening of the ring dummy pattern. | 2020-07-02 |
20200212153 | ARRAY SUBSTRATE, MANUFACTURING METHOD THEREOF, AND DISPLAY APPARATUS - An array substrate, its manufacturing method, and a display apparatus are provided. The array substrate having a substrate, includes: a monocrystalline silicon substrate employed as the substrate including a central display area, a first peripheral area, and a second peripheral area; substrate circuits integrated with a scan drive circuit in the first peripheral area, a data drive circuit in the second peripheral area, and a plurality of pixel circuits in the central display area; a plurality of scan lines in the central display area and coupled to the scan drive circuit; and a plurality of data lines in the central display area and coupled to the data drive circuit. The scan drive circuit, the data drive circuit, and the plurality of pixel circuits include a plurality of transistors, each of which has an active region inside the monocrystalline silicon layer. | 2020-07-02 |
20200212154 | DISPLAY DEVICE - A display device can include a first sub pixel disposed on a substrate; a second sub pixel disposed on the substrate, the second sub pixel being adjacent to the first sub pixel; a first electrode disposed in each of the first and second sub pixels; a first capacitor disposed on the first electrode in each of the first and second sub pixels, the first capacitor being located at a periphery of the corresponding first electrode; an emission layer disposed on the first electrode in each of the first and second sub pixels; and a second electrode disposed on the emission layer in each of the first and second sub pixels. | 2020-07-02 |
20200212155 | DISPLAY DEVICE - An active side slit and an FPC side slit each extend through a second inorganic insulating film and reach a first inorganic insulating film. The active side slit is formed between an active region and an IC chip mounted region of an EL device in plan view and also, the IC chip mounted region is sandwiched between the active side slit and the FPC side slit. | 2020-07-02 |
20200212156 | DISPLAY PANEL AND DISPLAY DEVICE - Display panel and display device are provided. The display panel includes a notch region, a display region, a frame region surrounding the display region, and a first base plate. The frame region includes a first frame region and a second frame region opposite to each other. A portion of the first frame region recesses toward the display region to form the notch region. The first base plate includes an anode power bus, an anode power connection part, and anode power connection wires. The anode power wires are disposed in the display region and include first anode power wires extending along a second direction perpendicular to the first direction. At least a portion of the anode power bus is disposed in the first frame region. The anode power connection part includes a first anode power connection part to connect the anode power bus to the first anode power wires. | 2020-07-02 |
20200212157 | ORGANIC LIGHTING APPARATUS - Disclosed herein is an organic lighting apparatus that can reduce leakage current. The organic lighting apparatus includes a plurality of light-emitting portions, each of which has a first electrode including an electric current injection line, wherein the electric current injection line includes one or more fuse structures. With the electric current injection line including a fuse structure, when a short circuit occurs between first and second electrodes in a specific light-emitting portion, the fuse operates and prevents electric current from being injected into the short-circuited light-emitting portion, thereby making it possible to reduce leakage current. | 2020-07-02 |
20200212158 | Display Device - A display device includes a plurality of electrode pads which are arranged in a non-display region having a side line of a substrate; a circuit film which includes a plurality of output pads contacting the plurality of electrode pads and extending in a direction, and on which a driving IC is mounted; a plurality of test lines that extend in the direction from the side line; and a plurality of connection lines which connect the plurality of test lines to corresponding electrode pads, wherein each test line is located in a separate region between two output pads adjacent to both sides of each test line. | 2020-07-02 |
20200212159 | DISPLAY DEVICE WITH THROUGH-HOLE - A display device with a through-hole that can prevent external moisture or oxygen from permeating into a light emitting element. The display device with a through-hole includes a substrate including a display area in which pixels are disposed and a non-display area surrounding the display area, and further including a through-hole in the display area, a first dam surrounding the through-hole, a first conductive line provided along the first dam between the first dam and the pixels, and a second conductive line provided along the first dam between the first dam and the through-hole. | 2020-07-02 |
20200212160 | DISPLAY DEVICE - A display device according to an exemplary embodiment of the present invention includes: a first substrate and a second substrate; a plurality of signal lines that are formed on the first substrate or on the second substrate; and a plurality of side wires that are disposed in a side surface of a first edge of the first substrate and a side surface of a second edge of the second substrate, wherein the plurality of side wires are disposed apart from each other along a direction in which the first edge extends, and are connected with the plurality of signal lines, and a first thickness of side wires disposed at an end of the first edge and at and end of the second edge is different from a second thickness of the side wire disposed at inside of the edges of live first edge and the second edge. | 2020-07-02 |
20200212161 | ORGANIC LIGHT EMITTING DISPLAY DEVICE INCLUDING AN ORGANIC LIGHT EMITTING DIODE CONNECTED TO CONNECTION ELECTRODES - An organic light emitting display device includes a substrate having a display area and a peripheral area; a pad disposed on the substrate in the peripheral area; a first conductive pattern disposed on one side of the display area in the peripheral area and electrically connected to the pad; a second conductive pattern disposed on the substrate in the peripheral area and disposed on an opposite side of the first conductive pattern; a first connection electrode disposed on the first conductive pattern in the peripheral area and electrically connected to the first conductive pattern; and a second connection electrode disposed on the second conductive pattern in the peripheral area and electrically connected to the second conductive pattern. A cathode electrode of a light emitting diode is disposed on the first and second connection electrodes and electrically connected to the first and second connection electrodes. | 2020-07-02 |
20200212162 | DISPLAY SUBSTRATE AND METHOD OF MANUFACTURING THE SAME, AND DISPLAY PANEL - A display substrate and a method of manufacturing the same, and a display panel are provided. The display substrate includes: a base substrate, and a first electrode, a first auxiliary electrode, a boss, a pixel definition layer, an organic functional layer and a second electrode provided on the base substrate. The first auxiliary electrode includes a first conductive connection part contacting a side surface of the boss; the pixel definition layer is provided with a pixel accommodating hole and a slot; the organic functional layer is electrically connected with the first electrode through the pixel accommodating hole; and the second electrode is electrically connected with the first conductive connection part through the slot, so that the second electrode is connected with the first auxiliary electrode in parallel. | 2020-07-02 |
20200212163 | DISPLAY PANEL, DISPLAY SCREEN, AND DISPLAY TERMINAL - A display panel, a display screen, and a terminal device are provided. The display panel includes: a substrate; and a plurality of first electrodes disposed on the substrate, the plurality of the first electrodes extending in parallel with each other in a extending direction, and two adjacent first electrodes having an interval therebetween, a width of the first electrode changes continuously or intermittently in the extending direction of the first electrodes, two edges of the first electrode in the extending direction thereof are wavy lines, crests and troughs of the wavy line are both curves, and a radius of curvature of the curve at the crest is different from a radius of curvature of the curve at the trough. | 2020-07-02 |
20200212164 | DISPLAY PANELS, DISPLAY SCREENS, AND DISPLAY TERMINALS - A display panel, a display screen, and a display terminal are provided. The display panel includes a substrate and a plurality of wavy first electrodes disposed on the substrate. The plurality of first electrodes extend in parallel in the same direction and have an interval between adjacent first electrodes. In an extending direction of the first electrode, a width of the first electrode changes continuously or intermittently, and the interval changes continuously or intermittently. | 2020-07-02 |
20200212165 | ORGANIC LIGHTING APPARATUS - An organic lighting apparatus can include a substrate; and a plurality of light-emitting portions disposed in a central area of the substrate, each of the plurality of light-emitting portions has a structure including: a first electrode, an organic light-emitting layer, a second electrode, a non-light-emitting area, a light-emitting area, and an electric current injection line disposed in the non-light emitting area, in which the electric current injection lines of at least two light-emitting portions have different lengths. | 2020-07-02 |
20200212166 | 3D PRINTED SEMICONDUCTOR PACKAGE - In described examples, a method for fabricating a semiconductor device and a three dimensional structure, and packaging them together, includes: fabricating the integrated circuit on a substrate, immersing the substrate in a liquid encapsulation material, and illuminating the liquid encapsulation material to polymerize the liquid encapsulation material. Immersing the semiconductor device is performed to cover a layer of a platform in the liquid encapsulation material. The platform is a lead frame, a packaging substrate, or the substrate. The illuminating step targets locations of the liquid encapsulation material covering the layer. Illuminated encapsulation material forms solid encapsulation material that is fixedly coupled to contiguous portions of the semiconductor device and of the solid encapsulation material. The immersing and illuminating steps are repeated until a three dimensional structure is formed. The integrated circuit and the three dimensional structure are encapsulated in a single package. | 2020-07-02 |
20200212167 | IC WITH ION MILLED THIN-FILM RESISTORS - A method of fabricating an integrated circuit (IC) includes providing a substrate having a semiconductor surface layer comprising an unpatterned resistive layer. Measurements are obtained of a characteristic of the unpatterned resistive layer at each of a plurality of locations over the substrate. The unpatterned resistive layer is modified, such as by targeted removal of layer material, in response to the measurements such that the measured characteristic is more uniform across the substrate. A resistor on the IC is defined from the unpatterned resistive layer after the modifying. | 2020-07-02 |
20200212168 | SEMICONDUCTOR DEVICE INCLUDING DIELECTRIC STRUCTURE HAVING FERROELECTRIC LAYER AND NON-FERROELECTRIC LAYER - A semiconductor device according to an embodiment includes a first electrode, a dielectric layer structure disposed on the first electrode and having a ferroelectric layer and a non-ferroelectric layer, and a second electrode disposed on the dielectric structure. The ferroelectric layer has positive and negative coercive electric fields having different absolute values. The dielectric structure has a non-ferroelectric property. | 2020-07-02 |
20200212169 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A method for fabricating a semiconductor device includes forming an upper structure in which a bottom electrode, a dielectric layer, a top electrode and a plasma protection layer are sequentially stacked on a lower structure, exposing the upper structure to a plasma treatment, and exposing the plasma-treated upper structure and the lower structure to a hydrogen passivation process. | 2020-07-02 |
20200212170 | SEMICONDUCTOR DEVICE INCLUDING CAPACITOR AND METHOD OF FORMING THE SAME - A semiconductor device including one or more switches on a substrate, a first electrode connected to the one or more switches and having a helical shape defining a spiral groove, a support in contact with the first electrode, the spiral groove extending between the support and a portion of the first electrode, a capacitor dielectric layer in contact with the first electrode, and a second electrode in contact with the capacitor dielectric layer. | 2020-07-02 |
20200212171 | SEMICONDUCTOR DEVICE - A semiconductor device wherein a high-side circuit region, a low-side circuit region, and a high-voltage MOS that transmits a signal between the high-side circuit region and the low-side circuit region are provided on one semiconductor substrate, includes: a high-voltage isolation region isolating the high-side circuit region and the low-side circuit region from each other; a trench isolation isolating the high-voltage MOS and the high-voltage isolation region from each other; an N-type diffusion layer provided on an upper surface of the semiconductor substrate in the high-side circuit region and the high-voltage isolation region; and an N-type region provided on both sides of the trench isolation and having an impurity concentration lower than an impurity concentration of the N-type diffusion layer. | 2020-07-02 |
20200212172 | SEMICONDUCTOR STRUCTURE AND METHOD OF MANUFACTURING THE SAME - The present invention provides a semiconductor structure and method of manufacturing the same. The semiconductor structure includes a substrate and a gate formed on the substrate. The above manufacturing method is used to form a gate on the substrate. The above manufacturing method specifically includes: providing a substrate; forming a trench in an upper portion of the substrate; depositing a gate layer on the substrate, the gate layer including two step portions extending from the outside of the trench to the inside of the trench; etching the gate layer from two ends of the trench along the two step portions toward the center of the trench to form the gate in the trench, wherein the width of the gate is smaller than the width of the trench. The manufacturing method of the present invention can easily and efficiently form a gate having a small critical dimension and precisely controllable on a semiconductor substrate, thereby meeting increasingly stringent gate size requirements. | 2020-07-02 |
20200212173 | GALLIUM NITRIDE HIGH ELECTRON MOBILITY TRANSISTOR AND GATE STRUCTURE THEREOF - A gate structure for gallium nitride (GaN) high electron mobility transistor (HEMT) includes a heterogeneous structure, a doped GaN layer, an insulating layer, an undoped GaN layer, and a gate metal layer. The heterogeneous structure includes a channel layer and a barrier layer on the channel layer. The doped GaN layer is disposed on the barrier layer, the insulating layer is disposed on both sides of the top portion of the doped GaN layer, and the undoped GaN layer is disposed between the doped GaN layer and the insulating layer. The gate metal layer is disposed on the doped GaN layer and covers the insulating layer and the undoped GaN layer. The undoped GaN layer can protect the underlying doped GaN layer, and the insulating layer has the effect of preventing gate leakage. | 2020-07-02 |
20200212174 | VERTICAL FIN FIELD EFFECT TRANSISTOR WITH AIR GAP SPACERS - A fin field effect transistor device with air gaps, including a source/drain layer on a substrate, one or more vertical fin(s) in contact with source/drain layer, a gate metal fill that forms a portion of a gate structure on each of the one or more vertical fin(s), and a bottom void space between the source/drain layer and the gate metal fill. | 2020-07-02 |
20200212175 | Semiconductor Constructions, Memory Arrays, Electronic Systems, and Methods of Forming Semiconductor Constructions - The invention includes semiconductor constructions having trenched isolation regions. The trenches of the trenched isolation regions can include narrow bottom portions and upper wide portions over the bottom portions. Electrically insulative material can fill the upper wide portions while leaving voids within the narrow bottom portions. The trenched isolation regions can be incorporated into a memory array, and/or can be incorporated into an electronic system. The invention also includes methods of forming semiconductor constructions. | 2020-07-02 |
20200212176 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - A terrace insulating film (SL) to be overridden by a gate electrode (G) of an nLDMOS device is configured by LOCOS, and a device isolation portion (SS) is configured by STI. Furthermore, on an outermost periphery of an active region where a plurality of nLDMOS devices are formed, a guard ring having the same potential as that of a drain region (D) is provided. And, via this guard ring, the device isolation portion (SS) is formed in a periphery of the active region, thereby not connecting but isolating the terrace insulating film (SL) and the device isolation portion (SS) from each other. | 2020-07-02 |
20200212177 | High Voltage Power Device with Hybrid Schottky Trenches and Method of Fabricating the Same - A silicon carbide diode that contains a silicon carbide substrate, a silicon carbide layer on top of the silicon carbide substrate, two first lower barrier metal portions disposed on the silicon carbide layer and separated from each other along a top surface of the silicon carbide layer, and a first higher barrier metal portion connected to the two lower barrier metal portions. The silicon carbide layer is thinner and having lower doping than the silicon carbide substrate. The first higher barrier metal portion is located between the two first lower barrier metal portions on the silicon carbide layer along a direction of the top surface of the silicon carbide layer. By reducing the leakage current at the junction barrier, the reverse breakdown voltage of the silicon carbide diode is significantly improved. | 2020-07-02 |
20200212178 | NANOROD PRODUCTION METHOD AND NANOROD PRODUCED THEREBY - Provided is a method of manufacturing a nanorod. The method comprising comprises the steps of: providing a growth substrate and a support substrate; epitaxially growing a nanomaterial layer onto one surface of the growth substrate; forming a sacrificial layer on one surface of the support substrate; bonding the nanomaterial layer with the sacrificial layer; separating the growth substrate from the nanomaterial layer; flattening the nanomaterial layer; forming a nanorod by etching the nanomaterial layer; and separating the nanorod by removing the sacrificial layer. | 2020-07-02 |
20200212179 | METHOD OF FABRICATION OF A SEMICONDUCTOR DEVICE INCLUDING ONE OR MORE NANOSTRUCTURES - A method of fabrication of a semiconductor device including implementation of fabrication of at least one stack made on a substrate, including at least one first portion of a first semiconductor and at least one second portion of a second semiconductor which is different from the first semiconductor, so the thickness of at least the first portion is substantially equal to the thickness of at least one nanostructure, and wherein the first or second semiconductor is capable of being selectively etched relative to the second or first semiconductor, respectively, fabrication, on a part of the stack, of external spacers and at least one dummy gate, etching of the stack such that the remaining parts of the first and second portions are arranged beneath the dummy gate and beneath the external spacers and form a stack of nanowires, after the etching of the stack, thermal treatment of the stack of nanowires. | 2020-07-02 |
20200212180 | III-NITRIDE DEVICES INCLUDING A GRADED DEPLETING LAYER - A III-N device includes a III-N layer structure including a III-N channel layer, a III-N barrier layer over the III-N channel layer, and a graded III-N layer over the III-N barrier layer having a first side adjacent to the III-N barrier layer and a second side opposite the first side; a first power electrode and a second power electrode; and a gate between the first and second power electrodes, the gate being over the III-N layer structure. A composition of the graded III-N layer is graded so the bandgap of the graded III-N layer adjacent to the first side is greater than the bandgap of the graded III-N layer adjacent to the second side. A region of the graded III-N layer is (i) between the gate and the second power electrode, and (ii) electrically connected to the first power electrode and electrically isolated from the second power electrode. | 2020-07-02 |
20200212181 | STRAINED AND UNSTRAINED SEMICONDUCTOR DEVICE FEATURES FORMED ON THE SAME SUBSTRATE - Embodiments of the invention are directed to a configuration of semiconductor devices having a substrate and a first feature formed on the substrate, wherein the first feature includes a first preserve region having compressive strain that extends throughout the first preserve region, and wherein the first feature further includes a cut region that includes a converted dielectric. The converted dielectric is a dielectric material that has been converted to the dielectric from another material. | 2020-07-02 |
20200212182 | SYSTEMS AND METHODS FOR INTEGRATED DIODE FIELD-EFFECT TRANSISTOR SEMICONDUCTOR DEVICES - A silicon carbide (SiC) semiconductor device may include a CB layer defined in a first epitaxial (epi) layer having a first conductivity type. The CB layer may include a plurality of CB regions having a second conductivity type. The SiC semiconductor device may further include a device epi layer having the first conductivity type disposed on the CB layer. The device epi layer may include a plurality of regions having the second conductivity type. Additionally, the SiC semiconductor device may include an ohmic contact disposed on the device epi layer and a rectifying contact disposed on the device epi layer. A field-effect transistor (FET) of the device may include the ohmic contact, and a diode of the device may include the rectifying contact, where the diode and the FET are integrated in the device. | 2020-07-02 |
20200212183 | SILICON CARBIDE SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING A SILICON CARBIDE SEMICONDUCTOR DEVICE - A p-type base region is configured by a p | 2020-07-02 |
20200212184 | CRYSTALLINE OXIDE SEMICONDUCTOR - A crystalline oxide semiconductor with excellent crystalline qualities that is useful for semiconductors requiring heat dissipation is provided. A crystalline oxide semiconductor including a first crystal axis, a second crystal axis, a first side, and a second side that is shorter than the first side, a linear thermal expansion coefficient of the first crystal axis is smaller than a linear thermal expansion coefficient of the second crystal axis, a direction of the first side is parallel and/or substantially parallel to a direction of the first crystal axis, and a direction of the second side is parallel and/or substantially parallel to a direction of the second crystal axis. | 2020-07-02 |
20200212185 | Semiconductor Device and Memory Device - A semiconductor device having favorable electrical characteristics is provided. The semiconductor device includes an oxide semiconductor, a first insulator in contact with the oxide semiconductor, and a second insulator in contact with the first insulator. The first insulator includes excess oxygen. The second insulator has a function of trapping or fixing hydrogen. Hydrogen in the oxide semiconductor is bonded to the excess oxygen. The hydrogen bonded to the excess oxygen passes through the first insulator and is trapped or fixed in the second insulator. The excess oxygen bonded to the hydrogen remains in the first insulator as the excess oxygen. | 2020-07-02 |
20200212186 | ALUMINUM INDIUM PHOSPHIDE SUBFIN GERMANIUM CHANNEL TRANSISTORS - Embodiments related to transistors and integrated circuits having aluminum indium phosphide subfins and germanium channels, systems incorporating such transistors, and methods for forming them are discussed. | 2020-07-02 |
20200212187 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device and manufacturing method includes a well structure, a gate stack structure spaced apart from the well structure, the gate stack structure being disposed over the well structure, and a source contact structure facing a sidewall of the gate stack structure. The semiconductor device further includes a channel pattern having pillar parts penetrating the gate stack structure, a first connecting part extending along a bottom surface of the gate stack structure from the pillar parts, and a second connecting part extending from the first connecting part to contact a first surface of the source contact structure facing the well structure. | 2020-07-02 |
20200212188 | LDMOS WITH HIGH-K DRAIN STI DIELECTRIC - A laterally diffused metal oxide silicon (LDMOS) transistor and a method of making the LDMOS transistor are disclosed. The LDMOS transistor includes a drain drift region formed in a substrate and containing a drain contact region. A gate structure overlies a channel region in the substrate and a first shallow-trench isolation (STI) structure located between the drain contact region and the channel region. The first STI structure contains a high-k dielectric and a second STI structure contains silicon oxide. | 2020-07-02 |
20200212189 | CONTACT OVER ACTIVE GATE STRUCTURES WITH CONDUCTIVE GATE TAPS FOR ADVANCED INTEGRATED CIRCUIT STRUCTURE FABRICATION - Contact over active gate (COAG) structures with conductive gate taps are described. In an example, an integrated circuit structure includes a plurality of gate structures above a substrate, each of the gate structures including a gate insulating layer thereon. Each of the plurality of gate structures includes a conductive tap structure protruding through the corresponding gate insulating layer. A plurality of conductive trench contact structures is alternating with the plurality of gate structures, each of the conductive trench contact structures including a trench insulating layer thereon. An interlayer dielectric material is above the trench insulating layers and the gate insulating layers. An opening is in the interlayer dielectric material and exposes the conductive tap structure of one of the plurality of gate structures. A conductive structure is in the opening and is in direct contact with the conductive tap structure of one of the plurality of gate structures. | 2020-07-02 |
20200212190 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - The semiconductor device includes, in plan view, a gate electrode having a first portion located on a side surface portion where a plurality of emitter regions are formed, and a gate electrode having a second portion located between the plurality of emitter regions. The second portion of the gate electrode has a length shorter than first portion in the direction from the main surface to the back surface of the gate electrode of the semiconductor substrate. | 2020-07-02 |
20200212191 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes a field effect transistor (FET). The FET includes a first channel, a first source and a first drain; a second channel, a second source and a second drain; and a gate structure disposed over the first and second channels. The gate structure includes a gate dielectric layer and a gate electrode layer. The first source includes a first crystal semiconductor layer and the second source includes a second crystal semiconductor layer. The first source and the second source are connected by an alloy layer made of one or more Group IV element and one or more transition metal elements. The first crystal semiconductor layer is not in direct contact with the second crystal semiconductor layer. | 2020-07-02 |
20200212192 | METHOD OF FORMING AIR-GAP SPACERS AND GATE CONTACT OVER ACTIVE REGION AND THE RESULTING DEVICE - A device including a substrate and at least one fin formed over the substrate. At least one transistor is integrated with the fin at a top portion of the fin. The transistor includes an active region comprising a source, a drain and a channel region between the source and drain. A gate structure is formed over the channel region, and the gate structure includes a HKMG and air-gap spacers formed on opposite sidewalls of the HKMG. Each of the air-gap spacers includes an air gap that is formed along a trench silicide region, and the air-gap is formed below a top of the HKMG. A gate contact is formed over the active region. | 2020-07-02 |
20200212193 | PIEZO-RESISTIVE TRANSISTOR BASED RESONATOR WITH ANTI-FERROELECTRIC GATE DIELECTRIC - Describe is a resonator that uses anti-ferroelectric (AFE) materials in the gate of a transistor as a dielectric. The use of AFE increases the strain/stress generated in the gate of the FinFET. Along with the usual capacitive drive, which is boosted with the increased polarization, additional current drive is also achieved from the piezoelectric response generated to due to AFE material. In some embodiments, the acoustic mode of the resonator is isolated using phononic gratings all around the resonator using the metal line above and vias' to body and dummy fins on the side. As such, a Bragg reflector is formed above or below the AFE based transistor. Increased drive signal from the AFE results in larger output signal and larger bandwidth. | 2020-07-02 |
20200212194 | PIEZO-RESISTIVE TRANSISTOR BASED RESONATOR WITH FERROELECTRIC GATE DIELECTRIC - Describe is a resonator that uses ferroelectric (FE) materials in the gate of a transistor as a dielectric. The use of FE increases the strain/stress generated in the gate of the FinFET. Along with the usual capacitive drive, which is boosted with the increased polarization, FE material expands or contacts depending on the applied electric field on the gate of the transistor. As such, acoustic waves are generated by switching polarization of the FE materials. In some embodiments, the acoustic mode of the resonator is isolated using phononic gratings all around the resonator using the metal line above and vias' to body and dummy fins on the side. As such, a Bragg reflector is formed above the FE based transistor. | 2020-07-02 |
20200212195 | SEMICONDUCTOR STRUCTURE AND METHOD FOR THE FORMING SAME - A semiconductor structure and a method for forming same, the forming method including: providing a base, where the base includes a device region for forming devices and isolation regions located on two sides of the device region; patterning the base to form a substrate and fins protruding from the substrate; forming, on two sides of the device region, first dummy fins protruding from the substrate of the isolation region; and forming an isolation layer on the substrate exposed by the fins and the first dummy fins, where the isolation layer covers a part of side walls of the fin. In some implementations of the present disclosure, the setting of the first dummy fins improves the uniformity of pattern density in peripheral regions for each fin, which is advantageous for improving the thickness uniformity of an isolation layer in the device region, reducing the probability that the fin is bent or tilted, and improving electrical properties of the semiconductor structure. | 2020-07-02 |
20200212196 | SCHOTTKY ELECTRODE STRUCTURE AND SCHOTTKY DIODE AND MANUFACTURING METHOD THEREOF - Provided is a Schottky electrode structure, the electrode structure including: a first N-type semiconductor layer; a P-type semiconductor layer covering the first N-type semiconductor layer; a second N-type semiconductor layer or a semi-insulting semiconductor layer covering the P-type semiconductor layer. By using the Schottky electrode structure, the reverse withstand voltage of the diode can be effectively improved, and the reliability of the diode is effectively improved. | 2020-07-02 |
20200212197 | METHOD OF MANUFACTURING GATE STRUCTURE FOR GALLIUM NITRIDE HIGH ELECTRON MOBILITY TRANSISTOR - A method of manufacturing a gate structure for gallium nitride (GaN) high electron mobility transistor (HEMT) includes orderly forming a channel layer, a barrier layer, a doped GaN layer, an undoped GaN layer, and an insulating layer on a substrate, and then removing a portion of the insulating layer to form a trench. A gate metal layer is formed on the substrate to cover the insulating layer and the trench, and then a mask layer aligned with the trench is formed on the gate metal layer, wherein the mask layer partially overlaps the insulating layer. By using the mask layer as an etching mask, the exposed gate metal layer and the underlying insulating layer, the undoped GaN layer and the doped GaN layer are removed, and then the mask layer is removed. | 2020-07-02 |
20200212198 | METHOD OF MAKING HETEROEPITAXIAL STRUCTURES AND DEVICE FORMED BY THE METHOD - A method for making a heteroepitaxial layer. The method comprises providing a semiconductor substrate. A seed area delineated with a selective growth mask is formed on the semiconductor substrate. The seed area comprises a first material and has a linear surface dimension of less than 100 nm. A heteroepitaxial layer is grown on the seed area, the heteroepitaxial layer comprising a second material that is different from the first material. Devices made by the method are also disclosed. | 2020-07-02 |
20200212199 | Semiconductor Device and a Method for Forming a Semiconductor Device - A semiconductor device and a method for forming such are provided, the device including: a substrate, a plurality of parallel active semiconductor patterns that extend through a drain-side region and a source-side region, a metal drain contact in the drain-side region, an active gate pattern, a first dummy gate pattern, and a second dummy gate pattern that all extend across the active semiconductor patterns, and a metal interconnect structure located in a region between the first and the second dummy gate patterns. The active semiconductor patterns are doped with a dopant in portions exposed by the dummy gates in dummy gate regions that include the gate cut regions of the first and second dummy gate patterns. The metal interconnect structure connects each of a second subset of the active semiconductor patterns to a respective at least one of a first subset of the active semiconductor patterns. | 2020-07-02 |
20200212200 | GATE CUT AND FIN TRIM ISOLATION FOR ADVANCED INTEGRATED CIRCUIT STRUCTURE FABRICATION - Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, a method includes forming a plurality of fins and forming a plurality of gate structures over the plurality of fins. A dielectric material structure is formed between adjacent ones of the plurality of gate structures. A portion of a first of the plurality of gate structures is removed to expose a first portion of each of the plurality of fins, and a portion of a second of the plurality of gate structures is removed to expose a second portion of each of the plurality of fins. The exposed first portion of each of the plurality of fins is removed, but the exposed second portion of each of the plurality of fins is not removed. | 2020-07-02 |
20200212201 | HIGH VOLTAGE SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A high voltage semiconductor device and a manufacturing method thereof are provided in the present invention. A recess is formed in a semiconductor substrate, and a gate dielectric layer and a main gate structure are formed in the recess. Therefore, the high voltage semiconductor device formed by the manufacturing method of the present invention may include the main gate structure lower than a top surface of an isolation structure formed in the semiconductor substrate. Problems about integrated manufacturing processes of the high voltage semiconductor device and other kinds of semiconductor devices when the gate structure is relatively high because of the thicker gate dielectric layer required in the high voltage semiconductor device may be improved accordingly. | 2020-07-02 |
20200212202 | APPROACH TO BOTTOM DIELECTRIC ISOLATION FOR VERTICAL TRANSPORT FIN FIELD EFFECT TRANSISTORS - A vertical transport fin field effect transistor (VT FinFET), including one or more vertical fins on a surface of a substrate, an L-shaped or U-shaped spacer trough on the substrate adjacent to at least one of the one or more vertical fins, and a gate dielectric layer on the sidewalls of the at least one of the one or more vertical fins and the L-shaped or U-shaped spacer trough. | 2020-07-02 |
20200212203 | Method of Manufacturing a Trench Oxide in a Trench for a Gate Structure in a Semiconductor Substrate - A method of manufacturing a trench oxide in a trench for a gate structure in a semiconductor substrate is described. The method includes: generating the trench in the semiconductor substrate; generating an oxide layer over opposing sidewalls of the trench; damaging at least a portion of the oxide layer by ion implantation; coating the oxide layer with an etching mask; generating at least one opening in the etching mask adjacent to one of the opposing sidewalls; and partly removing the oxide layer by etching the oxide layer beneath the etching mask down to an etching depth at the one of the opposing sidewalls by introducing an etching agent into the opening. | 2020-07-02 |
20200212204 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF - Fabrication method and semiconductor device are provided. The method includes: providing a base substrate including a first region and a second region adjacent to the first region, with first fins disposed on the base substrate in the first region and on the base substrate in the second region, and initial openings disposed between adjacent first fins; forming sidewall spacers on sidewalls of the first fins to form openings from the initial openings; and forming the second fins in the openings of the second region. | 2020-07-02 |
20200212205 | SEMICONDUCTOR FIN STRUCTURE AND METHOD OF FABRICATING THE SAME - According to one aspect, a method of fabricating a semiconductor structure includes cutting a semiconductor fin extending along a substrate. Cutting the semiconductor fin can comprise forming a fin cut mask. The fin cut mask can define a number of masked regions and a number of cut regions. The method can include cutting the fin into a number of fin parts by etching the fin in the cut regions. The method can further comprise forming an epitaxial semiconductor capping layer on the fin prior to forming the fin cut mask or on the fin parts subsequent to cutting the fin. A capping layer material and a fin material can be lattice mismatched. According to another aspect, a corresponding semiconductor structure comprises fin parts. | 2020-07-02 |
20200212206 | NONVOLATILE MEMORY DEVICE AND METHOD OF FABRICATING THE SAME - In a method of fabricating a nonvolatile memory device according an embodiment, a first tunnel oxide layer, a nitrogen supply layer, and a second tunnel oxide layer having a density lower than that of the first tunnel oxide layer are formed on a substrate. Nitrogen in the nitrogen supply layer is diffused into the second tunnel oxide layer to convert at least a portion of the second tunnel oxide layer into an oxynitride layer. | 2020-07-02 |
20200212207 | MANUFACTURING METHOD OF JUNCTION FIELD EFFECT TRANSISTOR - A manufacturing method of a junction field effect transistor (JFET) includes: providing a substrate having a first conductivity type, forming a channel region having a second conductive type, forming a field region having the first conductivity type, forming a gate having the first conductivity type, forming a source having the second conductive type, forming a drain having the second conductive type, and forming a lightly doped region having the second conductive type. The channel region is formed by a first ion implantation process step, and the lightly doped region is formed by a second ion implantation process step. The second ion implantation process step implants first conductivity type impurities into a part of the channel region. | 2020-07-02 |
20200212208 | INSULATED GATE BIPOLAR TRANSISTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - An insulated gate bipolar transistor (IGBT) device and a method for manufacturing the same are provided. The present disclosure relates to power semiconductor devices. In order to relieve the problem of wafer warping caused by trench stress in an IGBT manufacturing process without affecting other performance parameters of the IGBT, it provides the following technical solution: optimizing the design of arrangement densities and arrangement regions of device trenches. The present disclosure can alleviate the problem of wafer warping caused by trench stress in the IGBT manufacturing process, improve the product yield of IGBT chips, and enhance the latch-up immunity of the IGBT, so that the IGBT is more robust and durable. | 2020-07-02 |
20200212209 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device having an IE-type IGBT structure is disclosed. Concretely, the semiconductor device comprises a stripe-shaped trench gate, a stripe-shaped trench emitter arranged to face the trench gate, an N-type emitter layer and a P-type base layer surrounded by the trench gate and the trench emitter, and a P-type base contact layer arranged on one side of the trench emitter, formed in a semiconductor substrate. The p-type base contact layer, the emitter layer, and the trench emitter are commonly connected with an emitter electrodes, and the trench emitter is formed deeper than the trench gate in a thickness direction of the semiconductor substrate. | 2020-07-02 |
20200212210 | QUANTUM DOT DEVICES - Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a base; a fin extending away from the base, wherein the fin includes a quantum well layer; an insulating material at least partially above the fin, wherein the insulating material includes a trench above the fin; and a gate metal on the insulating material and extending into the trench. | 2020-07-02 |
20200212211 | GROUP III-NITRIDE DEVICES WITH IMPROVED RF PERFORMANCE AND THEIR METHODS OF FABRICATION - A device including a III-N material is described. The device includes a transistor structure having a first layer including a first group III-nitride (III-N) material, a polarization charge inducing layer above the first layer, the polarization charge inducing layer including a second III-N material, a gate electrode above the polarization charge inducing layer and a source structure and a drain structure on opposite sides of the gate electrode. The device further includes a plurality of peripheral structures adjacent to transistor structure, where each of the peripheral structure includes the first layer, but lacks the polarization charge inducing layer, an insulating layer above the peripheral structure and the transistor structure, wherein the insulating layer includes a first dielectric material. A metallization structure, above the peripheral structure, is coupled to the transistor structure. | 2020-07-02 |
20200212212 | SEMICONDUCTOR DEVICES AND METHODS FOR FORMING THE SAME - A semiconductor device includes a substrate, a channel layer, a barrier layer, a compound semiconductor layer, a source/drain pair, a fluorinated region, and a gate. The channel layer is disposed over the substrate. The barrier layer is disposed over the channel layer. The compound semiconductor layer is disposed over the barrier layer. The source/drain pair is disposed over the substrate, wherein the source and the drain are located on opposite sides of the compound semiconductor layer. The fluorinated region is disposed in the compound semiconductor layer. The gate is disposed on the compound semiconductor layer. | 2020-07-02 |
20200212213 | RF DEVICE INTEGRATED ON AN ENGINEERED SUBSTRATE - A substrate for RF devices includes a polycrystalline ceramic core and an interlayer structure. The interlayer structure includes a first silicon oxide layer coupled to the polycrystalline ceramic core, a polysilicon layer coupled to the first silicon oxide layer, a second silicon oxide layer coupled to the polysilicon layer, a barrier layer coupled to the second silicon oxide layer, a third silicon oxide layer coupled to the barrier layer, and a substantially single crystalline silicon layer coupled to the third silicon oxide layer. | 2020-07-02 |
20200212214 | RF DEVICE INTEGRATED ON AN ENGINEERED SUBSTRATE - A substrate for RF devices includes a polycrystalline ceramic core and an interlayer structure. The interlayer structure includes a first silicon oxide layer coupled to the polycrystalline ceramic core, a polysilicon layer coupled to the first silicon oxide layer, a second silicon oxide layer coupled to the polysilicon layer, a barrier layer coupled to the second silicon oxide layer, a third silicon oxide layer coupled to the barrier layer, and a substantially single crystalline silicon layer coupled to the third silicon oxide layer. | 2020-07-02 |
20200212215 | CONTACTS FOR SEMICONDUCTOR DEVICES - In an example embodiment, a method comprises: forming first spacers adjacent to a memory cell formed on a substrate, each of the first spacers being formed in direct contact with the substrate, where forming the memory cell includes forming a control gate electrode and a tunnel oxide layer over the substrate and subsequently etching completely at least the control gate electrode and the tunnel oxide layer that are disposed beyond the memory cell; forming an interlayer dielectric layer over the memory cell and the first spacers; forming a contact hole through the interlayer dielectric layer to at least reach the substrate; subsequent to forming the contact hole, forming a second spacer adjacent to one of the first spacers, where a height of the second spacer is greater than a height of the first spacers, the second spacer substantially contacting the substrate and the interlayer dielectric layer; and forming a contact in the contact hole. | 2020-07-02 |
20200212216 | FABRICATING METHOD OF TRANSISTOR STRUCTURE - A fabricating method of a transistor structure includes providing a substrate with a doped well disposed within the substrate. Later, a gate structure is formed to be disposed on the doped well. Next, a hexagonal-shaped trench is formed to be embedded in the doped well at one side of the gate structure. Subsequently, a first epitaxial layer is formed to be disposed inside the hexagonal-shaped trench and contact the hexagonal-shaped trench, wherein the first epitaxial layer includes first type dopants. Finally, a second epitaxial layer including second-type dopants is formed to be disposed in the hexagon-shaped trench, wherein the first epitaxial layer surrounds the second epitaxial layer, the second epitaxial layer serves as a source/drain doped region of the transistor structure, and the first-type dopants and the second-type dopants are different conductive types. | 2020-07-02 |
20200212217 | STRUCTURE AND METHOD FOR PROVIDING LINE END EXTENSIONS FOR FIN-TYPE ACTIVE REGIONS - A semiconductor structure includes an isolation feature formed in the semiconductor substrate and a first fin-type active region. The first fin-type active region extends in a first direction. A dummy gate stack is disposed on an end region of the first fin-type active region. The dummy gate stack may overlie an isolation structure. In an embodiment, any recess such as formed for a source/drain region in the first fin-type active region will be displaced from the isolation region by the distance the dummy gate stack overlaps the first fin-type active region. | 2020-07-02 |
20200212218 | VERTICAL TRENCH GATE MOSFET WITH DEEP WELL REGION FOR JUNCTION TERMINATION - A trench gate metal oxide semiconductor field effect transistor (MOSFET) device includes an epitaxial layer on a substrate both doped a first conductivity type. Active area trenches have polysilicon gates over a double shield field plate. A junction termination trench includes a single shield field plate in a junction termination area which encloses the active area that includes a retrograde dopant profile of the second conductivity type into the epitaxial layer in the junction termination area. Pbody regions of a second conductivity type are between active trenches and between the outermost active trench and the junction termination trench. Source regions of the first conductivity type are in the body regions between adjacent active trenches. Metal contacts are over contact apertures that extend through a pre-metal dielectric layer reaching the body region under the source region, the single shield field plate, and that couples together the polysilicon gates. | 2020-07-02 |
20200212219 | VERTICAL TRENCH GATE MOSFET WITH INTEGRATED SCHOTTKY DIODE - An integrated circuit includes a trench gate MOSFET including MOSFET cells. Each MOSFET cell includes an active trench gate in an n-epitaxial layer oriented in a first direction with a polysilicon gate over a lower polysilicon portion. P-type body regions are between trench gates and are separated by an n-epitaxial region. N-type source regions are located over the p-type regions. A gate dielectric layer is between the polysilicon gates and the body regions. A metal-containing layer contacts the n-epitaxial region to provide an anode of an embedded Schottky diode. A dielectric layer over the n-epitaxial layer has metal contacts therethrough connecting to the n-type source regions, to the p-type body regions, and to the anode of the Schottky diode. | 2020-07-02 |
20200212220 | REPLACEMENT METAL GATE PROCESS FOR VERTICAL TRANSPORT FIELD-EFFECT TRANSISTOR WITH SELF-ALIGNED SHARED CONTACTS - A semiconductor structure includes a substrate, a bottom source/drain region disposed on a top surface of the substrate, and a plurality of fins disposed over a top surface of the bottom source/drain region. The fins provide vertical transport channels for one or more vertical transport field-effect transistors. The semiconductor structure also includes at least one self-aligned shared contact disposed between an adjacent pair of the plurality of fins. The adjacent pair of the plurality of fins includes a first fin providing a first vertical transport channel for a first vertical transport field-effect transistor and a second fin providing a second vertical transport channel for a second vertical transport field-effect transistor. | 2020-07-02 |
20200212221 | THIN FILM TRANSISTOR COMPRISING ACTIVE LAYER HAVING THICKNESS DIFFERENCE AND DISPLAY APPARATUS COMPRISING THE SAME - A thin film transistor includes an active layer including a channel portion; a gate electrode spaced apart from the active layer and overlapping at least a part of the active layer; and source and drain electrodes connected with the active layer and spaced apart from each other, wherein the channel portion includes, a first boundary portion connected with one of the source and drain electrodes; a second boundary portion connected with the other one of the source and drain electrodes; and a main channel portion interposed between the first boundary portion and the second boundary portion, and wherein at least a part of the second boundary portion has a thickness smaller than a thickness of the main channel portion. | 2020-07-02 |
20200212222 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - An embodiment is a semiconductor device which includes a first oxide semiconductor layer over a substrate having an insulating surface and including a crystalline region formed by growth from a surface of the first oxide semiconductor layer toward an inside; a second oxide semiconductor layer over the first oxide semiconductor layer; a source electrode layer and a drain electrode layer which are in contact with the second oxide semiconductor layer; a gate insulating layer covering the second oxide semiconductor layer, the source electrode layer, and the drain electrode layer; and a gate electrode layer over the gate insulating layer and in a region overlapping with the second oxide semiconductor layer. The second oxide semiconductor layer is a layer including a crystal formed by growth from the crystalline region. | 2020-07-02 |
20200212223 | SEMICONDUCTOR DEVICE - A semiconductor device includes a gate electrode, a gate insulating film which includes oxidized material containing silicon and covers the gate electrode, an oxide semiconductor film provided to be in contact with the gate insulating film and overlap with at least the gate electrode, and a source electrode and a drain electrode electrically connected to the oxide semiconductor film. In the oxide semiconductor film, a first region which is provided to be in contact with the gate insulating film and have a thickness less than or equal to 5 nm has a silicon concentration lower than or equal to 1.0 at. %, and a region in the oxide semiconductor film other than the first region has lower silicon concentration than the first region. At least the first region includes a crystal portion. | 2020-07-02 |
20200212224 | FERROELECTRIC TRANSISTORS TO STORE MULTIPLE STATES OF RESISTANCES FOR MEMORY CELLS - Embodiments herein describe techniques for a semiconductor device including a gate stack with a ferroelectric-oxide layer above a channel layer and in contact with the channel layer, and a top electrode above the ferroelectric-oxide layer. The ferroelectric-oxide layer includes a domain wall between an area under a nucleation point of the top electrode and above a separation line of the channel layer between an ON state portion and an OFF state portion of the channel layer. A resistance between a source electrode and a drain electrode is modulated in a range between a first resistance value and a second resistance value, dependent on a position of the domain wall within the ferroelectric-oxide layer, a position of the ON state portion of the channel layer, and a position of the OFF state portion of the channel layer. Other embodiments may be described and/or claimed. | 2020-07-02 |
20200212225 | STRUCTURE OF OXIDE THIN FILM TRANSISTOR - A structure of an oxide thin film transistor includes: an oxide semiconducting layer, an etching stopper layer on the oxide semiconducting layer, and a source and a drain on the etching stopper layer. Two vias are formed in the etching stopper layer. The oxide semiconducting layer includes two recesses formed therein to extend through a skin layer of the oxide semiconducting layer and respectively corresponding to the two vias. The two recesses are respectively connected with and in communication with the two vias. The source and the drain are respectively filled in the two vias and the two recesses connected with the two vias to directly connect to and physically contact the oxide semiconducting layer. | 2020-07-02 |
20200212226 | AREA-EFFICIENT INVERTER USING STACKED VERTICAL TRANSISTORS - An inverter that includes an n-type field effect transistor (nFET) and a p-type field effect transistor (pFET) vertically stacked one atop the other and containing a buried metal semiconductor alloy strap that connects a drain region of the nFET to a drain region of the pFET is provided. Also, provided is a cross-coupled inverter pair with nFETs and pFETs stacked vertically. | 2020-07-02 |
20200212227 | THIN FILM TRANSISTOR, MANUFACTURING METHOD THEREOF, ARRAY SUBSTRATE, DISPLAY DEVICE - A thin film transistor, a manufacturing method thereof, an array substrate and a display device are disclosed. The thin film transistor includes an active layer, as well as a source and a drain above the active layer, wherein the active layer includes a carrier trapping portion configured to trap photo-generated majority carriers. | 2020-07-02 |
20200212228 | TILTED NANOWIRE TRANSISTOR - A tilted nanowire structure is provided which has an increased gate length as compared with a horizontally oriented semiconductor nanowire at the same pitch. Such a structure avoids complexity required for vertical transistors and can be fabricated on a bulk semiconductor substrate without significantly changing/modifying standard transistor fabrication processing. | 2020-07-02 |
20200212229 | SEMICONDUCTOR DEVICE WITH DEEP TRENCH ISOLATION AND TRENCH CAPACITOR - A semiconductor device with an isolation structure and a trench capacitor, each formed using a single resist mask for etching corresponding first and second trenches of different widths and different depths, with dielectric liners formed on the trench sidewalls and polysilicon filling the trenches and deep doped regions surrounding the trenches, including conductive features of a metallization structure that connect the polysilicon of the isolation structure trench to the deep doped region to form an isolation structure. | 2020-07-02 |
20200212230 | LEAKAGE PATHWAY LAYER FOR SOLAR CELL - Leakage pathway layers for solar cells and methods of forming leakage pathway layers for solar cells are described. | 2020-07-02 |
20200212231 | EVALUATION METHOD ON ANION PERMEABILITY OF GRAPHENE-CONTAINING MEMBRANE AND PHOTOELECTRIC CONVERSION DEVICE - The present embodiment provide a method for evaluating anion permeability of a graphene-containing membrane and also to provide a photoelectric conversion device employing a graphene-containing membrane having controlled anion permeability. The method comprises: | 2020-07-02 |
20200212232 | PHOTOSENSITIVE REFLECTOR, LASER INDUCED TOUCH DEVICE AND LASER TOUCH DETECTION METHOD - A photosensitive reflector, a laser induced touch device and a laser touch detection method are provided. The photosensitive reflector, comprising a reflection layer and a photosensitive element, wherein the photosensitive element is disposed on or in the reflection layer and configured to sense at least one of light running through the reflection layer, light incident on the reflection layer, or light reflected by the reflection layer. | 2020-07-02 |
20200212233 | SOLAR CELL MODULE INCLUDING SOLAR CELLS - The finger electrode is formed by hard-soldered silver paste. The melting point of the first type solder layer provided on the surface of the terminal wiring member is higher than the melting point of the second type solder layer provided on the surface of the wire. The first width, in the first direction, of the second type solder layer in the first portion where the wire is connected to the terminal wiring member is larger than the second width, in the first direction, of the second type solder layer in the second portion where the wire is connected to the finger electrode. | 2020-07-02 |
20200212234 | SOLAR CELL WITH REDUCED BASE DIFFUSION AREA - In one embodiment, a solar cell has base and emitter diffusion regions formed on the back side. The emitter diffusion region is configured to collect minority charge carriers in the solar cell, while the base diffusion region is configured to collect majority charge carriers. The emitter diffusion region may be a continuous region separating the base diffusion regions. Each of the base diffusion regions may have a reduced area to decrease minority charge carrier recombination losses without substantially increasing series resistance losses due to lateral flow of majority charge carriers. Each of the base diffusion regions may have a dot shape, for example. | 2020-07-02 |
20200212235 | FLEXIBLE SOLAR CELL AND METHOD - A flexible solar cell includes an interdigitated back contact having a first electrode coupled to a first plurality of contacts and a second electrode coupled to a second plurality of contacts. The first plurality of contacts run in a first direction from the first electrode towards the second electrode and the second plurality of contacts run in a second direction from the second electrode towards the first electrode. The flexible solar cell also includes a plurality of light-collecting segments coupled to the first and second plurality of contacts of the interdigitated back contact. Adjacent ones of the plurality of light-collecting segments are spaced apart from each other in the first or second direction. A length of each of the plurality of light-collecting segments runs along the interdigitated back contact in a third direction, which is perpendicular to the first and second directions. | 2020-07-02 |
20200212236 | PHOTOELECTRIC CONVERSION ELEMENT, METHOD FOR MANUFACTURING SAME, AND IMAGING APPARATUS - A photoelectric conversion element includes: a first compound semiconductor layer | 2020-07-02 |
20200212237 | SHORT WAVELENGTH INFRARED OPTOELECTRONIC DEVICES HAVING A DILUTE NITRIDE LAYER - Semiconductor optoelectronic devices having a dilute nitride active layer are disclosed. In particular, the semiconductor devices have a dilute nitride active layer with a bandgap within a range from 0.7 eV and 1 eV. Photodetectors comprising a dilute nitride active layer have a responsivity of greater than 0.6 A/W at a wavelength of 1.3 μm. | 2020-07-02 |
20200212238 | Toughened Semiconductor Substrates Devices Produced With Toughened Semiconductor Substrates and Methods of Producing Same - Semiconductor substrates and semiconductor devices produced from such substrates, such as photovoltaic (PV) cells, may exhibit toughened physical characteristics making them more suitable for use in mechanically challenging or stressful environments. Semiconductor substrates and semiconductor devices produced from such substrates, such as photovoltaic (PV) cells, may exhibit toughened thermal characteristics making them more suitable for use in environmentally challenging applications. Semiconductor substrates and semiconductor devices produced from such substrates, such as photovoltaic (PV) cells, may exhibit sufficiently toughened characteristics and increase impact resistance to permit packaging in non-rigid and light weight encapsulating layer(s). Semiconductor substrates and semiconductor devices produced from such substrates may exhibit sufficient flexibility to permit for rolling up during shipment and or for non-destructive deformation during deployment over uneven surfaces. Semiconductor devices produced from such substrates may exhibit sufficient flexibility to permit repeated mechanical and/or thermal stresses without failure. | 2020-07-02 |
20200212239 | MULTIJUNCTION SOLAR CELL HAVING PATTERNED EMITTER AND METHOD OF MAKING THE SOLAR CELL - A multijunction solar cell includes a base substrate comprising a Group IV semiconductor and a dopant of a first carrier type. A patterned emitter is formed at a first surface of the base substrate. The patterned emitter comprises a plurality of well regions doped with a dopant of a second carrier type in the Group IV semiconductor. The base substrate including the patterned emitter form a first solar subcell. The multijunction solar cell further comprises an upper structure comprising one or more additional solar subcells over the first solar subcell. Methods of making a multijunction solar cell are also described. | 2020-07-02 |
20200212240 | LUMINESCENT SOLAR CONCENTRATOR USING PEROVSKITE STRUCTURES - A luminescent solar concentrator having a glass or plastics matrix containing or covered with perovskites having luminescence from intra-gap states is provided. | 2020-07-02 |