27th week of 2012 patent applcation highlights part 46 |
Patent application number | Title | Published |
20120171774 | CHEMICAL SENSOR WITH REPLACEABLE SAMPLE COLLECTION CHIP - A chemical sensor is provided on a first semiconductor die. A potentiostat is provided on a second semiconductor die. An analog to digital converter and a microcontroller are provided on a third semiconductor die. The first die is configured to be connected to the second die. The second die is configured to be connected to the third die. The chemical sensor detects a chemical in the surrounding environment and outputs a signal to the analog to digital converter. The analog to digital converter converts the signal to a digital signal and outputs the digital signal to the microcontroller. The microcontroller provides a measurement of the concentration of the chemical in the surrounding environment. | 2012-07-05 |
20120171775 | MULTI-DIMENSIONAL INTEGRATED DETECTION AND ANALYSIS SYSTEM (MIDAS) BASED ON MICROCANTILVERS - The present invention is a multidimensional integrated detection and analysis system (MIDAS) for any gas or fluid that transfers or accepts electronic charge (including but not limited to CH | 2012-07-05 |
20120171776 | METHOD FOR DETECTING AN ANALYTE - The disclosure relates to a method of detecting analytes using non-aromatic dendritic macromolecules. The inherent photoluminescence of dendrimers are utilized to detect analytes which are electron deficient in nature. | 2012-07-05 |
20120171777 | TAPERED CUVETTE AND METHOD OF COLLECTING MAGNETIC PARTICLES - A vessel for use in clinical analysis including an open top, a closed bottom, and at least four tapered sides. A method for collecting magnetic particles in a fluid comprising the steps of providing a magnet and a vessel containing magnetic particles in a fluid, attracting the magnetic particles to the magnet, and moving the magnetic particles with the magnet out of the fluid. | 2012-07-05 |
20120171778 | FUNCTIONALIZATION OF NANOFLUIDIC CHANNELS - A functionalized nanofluidic channel and method for functionalization that provides control over the ionic environment and geometry of the nanofluidic channel with the immobilization of biomolecules on the inner surface of the channel and use of high ionic concentration solutions. In one embodiment, the surface charge of the nanochannel is controlled with the immobilization of a protein such as streptavidin in the nanochannel. In another embodiment, the biomolecules are receptors and changes in nanochannel conductance indicates ligand binding events. The functionalized nanofluidic channel can be easily adapted for use with microchannel arrays. | 2012-07-05 |
20120171779 | ANTIBODIES THAT SPECIFICALLY BIND HEDGEHOG-DERIVED POLYPEPTIDES - The present invention provides two novel polypeptides, referred to as the “N” and “C” fragments of hedgehog, or N-terminal and C-terminal fragments, respectively, which are derived after specific cleavage at a G′ CF site recognized by the autoproteolytic domain in the native protein. Also included are sterol-modified hedgehog polypeptides and functional fragments thereof. Methods of identifying compositions which affect hedgehog activity based on inhibition of cholesterol modification of hedgehog protein are described. | 2012-07-05 |
20120171780 | FLUORESCENT POLYMERS AND METHODS FOR SOLID-PHASE EXTRACTION - The apparatus of the present invention comprises a fluorescent polymer contained within a solid-phase extraction (SPE) carrier. The fluorescent polymer is capable of adsorbing an analyte by means of functional monomers. In use of the apparatus, a sample, such as a foodstuff sample, is applied to the fluorescent polymer. If the sample comprises the analyte, adsorption of the analyte onto the fluorescent polymer causes quenching of the fluorescence of the fluorescent polymer. Fluorescence quenching can be detected using a fluorometer or transillumination system. The method can be used to determine whether mycotoxins are present in foodstuff samples. | 2012-07-05 |
20120171781 | HIGHLY SENSITIVE IMMUNOASSAY WITH LARGE PARTICLE LABELS - The present invention is related to an immunoassay for the detection of an analyte in a sample, said assay comprising a plurality of moieties capable of binding to said analyte, wherein capture moieties which are not specific for the same epitope are bound to a solid substrate, and at least one epitope-specific detection moiety is bound to a detectable marker, and wherein the detectable marker to which the epitope-specific detection moiety is bound is a large particle marker having a particle size of ≧50 nm and ≦5000 nm. | 2012-07-05 |
20120171782 | MASS SPECTROMETRIC IMMUNOASSAY - Rapid mass spectrometric immunoassay methods for detecting and/or quantifying antibody and antigen analytes utilizing affinity capture to isolate the analytes and internal reference species (for quantification) followed by mass spectrometric analysis of the isolated analyte/internal reference species. Quantification is obtained by normalizing and calibrating obtained mass spectrum against the mass spectrum obtained for an antibody/antigen of known concentration. | 2012-07-05 |
20120171783 | FERROELECTRIC MEMORY AND MANUFACTURING METHOD THEREOF, AND MANUFACTURING METHOD OF FERROELECTRIC CAPACITOR - Provided is a ferroelectric memory including a silicon substrate, a transistor formed on the silicon substrate, and a ferroelectric capacitor formed above the transistor. The ferroelectric capacitor includes a lower electrode, a ferroelectric film formed on the lower electrode, an upper electrode formed on the ferroelectric film, and a metal film formed on the upper electrode. | 2012-07-05 |
20120171784 | MAGNETRON-SPUTTERING FILM-FORMING APPARATUS AND MANUFACTURING METHOD FOR A SEMICONDUCTOR DEVICE - A magnetron-sputtering film-forming apparatus includes: a vacuum film-forming chamber ( | 2012-07-05 |
20120171785 | MANUFACTURING METHOD OF A SEMICONDUCTOR DEVICE - There are provided a capacitor lower electrode formed on an adhesive layer, whose surface roughness is 0.79 nm or less, and having a (111) orientation that is inclined from a perpendicular direction to an upper surface of a substrate by 2.3° or less, a ferroelectric layer having a structure the (111) orientation of which is inclined from the perpendicular direction to the upper surface of the substrate by 3.5° or less, and a capacitor upper electrode. | 2012-07-05 |
20120171786 | APPARATUS FOR MANUFACTURING SOLAR CELLS AND PROCESS FOR OPERATING SUCH APPARATUS - Apparatus ( | 2012-07-05 |
20120171787 | Method for Forming a Pixel of an Electroluminescence Device having Storage Capacitors - A method is provided for forming a pixel of an electroluminescence device. The method provides a substrate; defines at least a first area for capacitors, a second area for a transistor on the substrate and a third area for an organic light-emitting diode (OLED) on the substrate; forms first conductive, first dielectric, second conductive, second dielectric, and third conductive layers over the first area; forming a third conductive layer over the second dielectric layer over the first area; wherein the first conductive layer over the first area is directly connected to a power supply voltage, wherein the second conductive layer is electrically connected to a fourth conductive layer and wherein the first conductive layer, the first dielectric layer, and the second conductive layer over the first area collectively form a first one of the capacitors over the first area, the second conductive layer, the second dielectric layer. | 2012-07-05 |
20120171788 | IC CARD AND BOOKING-ACCOUNT SYSTEM USING THE IC CARD - It is an object of the present invention to provide a highly sophisticated functional IC card that can ensure security by preventing forgery such as changing a picture of a face, and display other images as well as the picture of a face. An IC card comprising a display device and a plurality of thin film integrated circuits; wherein driving of the display device is controlled by the plurality of thin film integrated circuits; a semiconductor element used for the plurality of thin film integrated circuits and the display device is formed by using a polycrystalline semiconductor film; the plurality of thin film integrated circuits are laminated; the display device and the plurality of thin film integrated circuits are equipped for the same printed wiring board; and the IC card has a thickness of from 0.05 mm to 1 mm. | 2012-07-05 |
20120171789 | SOLID ELEMENT DEVICE AND METHOD FOR MANUFACTURING THE SAME - A method of making a solid element device that includes a solid element, an element mount part on which the solid element is mounted and which has a thermal conductivity of not less than 100 W/mK, an external terminal provided separately from the element mount part and electrically connected to the solid element, and a glass sealing part directly contacting and covering the solid element for sealing the solid element, includes pressing a glass material at a temperature higher than a yield point of the glass material for forming the glass sealing part. | 2012-07-05 |
20120171790 | SURFACE EMITTING LASER, METHOD FOR PRODUCING SURFACE EMITTING LASER, AND IMAGE FORMING APPARATUS - A surface emitting laser includes a lower multilayer mirror, an active layer, and an upper multilayer mirror stacked onto a substrate. A first current confinement layer having a first electrically conductive region and a first insulating region is formed above or below the active layer using a first trench structure. A second current confinement layer having a second electrically conductive region and a second insulating region is formed above or below the first current confinement layer using a second trench structure. The first and second trench structures extend from a top surface of the upper multilayer mirror towards the substrate such that the second trench structure surrounds the first trench structure. When the surface emitting laser is viewed in an in-plane direction of the substrate, a boundary between the first electrically conductive region and the first insulating region is disposed inside the second electrically conductive region. | 2012-07-05 |
20120171791 | METHOD FOR FABRICATING LIGHT EMITTING DIODE CHIP - A method for fabricating an LED chip is provided. Firstly, a SiO | 2012-07-05 |
20120171792 | METHOD OF FABRICATING A PIXEL ARRAY - A method of fabricating a pixel array is provided. A first metal layer is formed over a substrate. The metal layer is patterned to form a plurality of data lines and a plurality of drain patterns adjacent to each data line. The data lines and the drain patterns are separated from each other. An oxide semiconductor layer and a first insulation layer covering the oxide semiconductor layer are formed over the substrate. A second metal layer is formed on the first insulation layer and patterned to form a plurality of scan lines intersected with the data lines and the drain patterns. By using the scan lines as a mask, the oxide semiconductor layer and the first insulation layer are patterned to form a plurality of oxide semiconductor channels located under each scan line. Each oxide semiconductor channel is located between one data line and one drain pattern. | 2012-07-05 |
20120171793 | METHOD OF MANUFACTURING A DISPLAY SUBSTRATE - A method of manufacturing a display substrate includes forming a common electrode line, a gate line, a data line and a switching element connected to the gate and data lines on an insulation substrate. A first pixel electrode and an insulation layer are sequentially formed on the insulation substrate. A first photoresist pattern having a first hole and a second hole is formed from a first photoresist layer on the insulation substrate. A first transparent electrode layer is coated on the insulation substrate. A second photoresist layer is coated on the insulation substrate. The second photoresist layer is exposed and developed to form a second photoresist pattern remaining in the first hole and the second hole. The first transparent electrode layer is patterned using the second photoresist pattern, to form a second pixel electrode. | 2012-07-05 |
20120171794 | POLYSILICON THIN FILM TRANSISTOR DEVICE AND METHOD OF FABRICATING THE SAME - A polysilicon thin film transistor device includes a gate metal pattern including a gate electrode and a gate line formed on a substrate, the gate metal pattern having a stepped portion, a gate insulating film formed on the gate metal pattern, a polysilicon semiconductor layer formed on the gate insulating film, the polysilicon semiconductor layer including an active region, lightly doped drain regions, a source region, and a drain region, a source electrode connected to the source region and a drain electrode connected to the drain region on the polysilicon semiconductor layer, and a pixel electrode connected with the drain electrode. | 2012-07-05 |
20120171795 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE - A method of performing irradiation of laser light is given as a method of crystallizing a semiconductor film. However, if laser light is irradiated to a semiconductor film, the semiconductor film is instantaneously melted and expands locally. The temperature gradient between a substrate and the semiconductor film is precipitous, distortions may develop in the semiconductor film. Thus, the film quality of the crystalline semiconductor film obtained will drop in some cases. With the present invention, distortions of the semiconductor film are reduced by heating the semiconductor film using a heat treatment process after performing crystallization of the semiconductor film using laser light. Compared to the localized heating due to the irradiation of laser light, the heat treatment process is performed over the entire substrate and semiconductor film. Therefore, it is possible to reduce distortions formed in the semiconductor film and to increase the physical properties of the semiconductor film. | 2012-07-05 |
20120171796 | GAN LED ELEMENT AND LIGHT EMITTING DEVICE HAVING A STRUCTURE TO REDUCE LIGHT ABSORPTION BY A PAD ELECTRODE INCLUDED THEREIN - A first conductive film | 2012-07-05 |
20120171797 | SEASONING OF DEPOSITION CHAMBER FOR DOPANT PROFILE CONTROL IN LED FILM STACKS - Apparatus and method for seasoning an idled deposition chamber prior to growing an epitaxial layer. A dopant containing source gas, such as a Mg-containing source gas, is introduced to an MOCVD chamber after the chamber has been idled and prior to the chamber growing a film containing the dopant on a substrate. In a multi-chambered deposition system, a non-p-type epitaxial layer of an LED film stack is grown over a substrate in a first deposition chamber while a seasoning process is executed in a second deposition chamber with a p-type dopant-containing source gas. Subsequent to the seasoning process, a p-type epitaxial layer of the LED film stack is grown on the substrate in the second deposition chamber with improved control of p-type dopant concentration in the p-type epitaxial layer. | 2012-07-05 |
20120171798 | DAMASCENE PROCESS FOR USE IN FABRICATING SEMICONDUCTOR STRUCTURES HAVING MICRO/NANO GAPS - In fabricating a microelectromechanical structure (MEMS), a method of forming a narrow gap in the MEMS includes a) depositing a layer of sacrificial material on the surface of a supporting substrate, b) photoresist masking and at least partially etching the sacrificial material to form at least one blade of sacrificial material, c) depositing a structural layer over the sacrificial layer, and d) removing the sacrificial layer including the blade of the sacrificial material with a narrow gap remaining in the structural layer where the blade of sacrificial material was removed. | 2012-07-05 |
20120171799 | BYPASS DIODE FOR A SOLAR CELL - Methods of fabricating bypass diodes for solar cells are described. In one embodiment, a method includes forming a first conductive region of a first conductivity type above a substrate of a solar cell. A second conductive region of a second conductivity type is formed on the first conductive region. In another embodiment, a method includes forming a first conductive region of a first conductivity type above a substrate of a solar cell. A second conductive region of a second conductivity type is formed within, and surrounded by, an uppermost portion of the first conductive region but is not formed in a lowermost portion of the first conductive region. | 2012-07-05 |
20120171800 | METHOD OF SEALING AN ELECTRONIC DEVICE - A method of sealing an electronic device is disclosed, comprising providing an assembly comprising first and second substrates in an opposed relationship, and an electronic device positioned between the first and second substrates; positioning a glass rod against or on the edge of the first and/or second substrate; and heating and softening the glass rod to form a hermetic seal between the first and second substrates and form a hermetically sealed electronic device. | 2012-07-05 |
20120171801 | SILICONE MEMBRANE FOR LAMINATION PROCESS - A membrane includes a blend of a silicone polymer and not greater than 25 wt % of an elastomeric component. The membrane has a thickness of at least 1 mm and exhibits a tensile retention index of at least 35%. | 2012-07-05 |
20120171802 | Collector grid and interconnect structures for photovoltaic arrays and modules - An interconnected arrangement of photovoltaic cells is achieved using laminating current collector electrodes. The electrodes comprise a pattern of conductive material extending over a first surface of sheetlike substrate material. The first surface comprises material having adhesive affinity for a selected conductive surface. Application of the electrode to the selected conductive surface brings the first surface of the sheetlike substrate into adhesive contact with the conductive surface and simultaneously brings the conductive surface into firm contact with the conductive material extending over first surface of the sheetlike substrate. Use of the laminating current collector electrodes allows facile and continuous production of expansive area interconnected photovoltaic arrays. | 2012-07-05 |
20120171803 | REVERSE IMAGE SENSOR MODULE AND METHOD FOR MANUFACTURING THE SAME - A reverse image sensor module includes first and second semiconductor chips, and first and second insulation layers. The first semiconductor chip includes a first semiconductor chip body having a first surface and a second surface facing away from the first surface, photodiodes disposed on the first surface, and a wiring layer disposed on the second surface and having wiring lines electrically connected to the photodiodes and bonding pads electrically connected to the wiring lines. The second semiconductor chip includes a second semiconductor chip body having a third surface facing the wiring layer, and through-electrodes electrically connected to the bonding pads and passing through the second semiconductor chip body. The first insulation layer is disposed on the wiring layer, and the second insulation layer is disposed on the third surface of the second semiconductor chip body facing the first insulation layer and is joined to the first insulation layer. | 2012-07-05 |
20120171804 | PATTERNING OF SILICON OXIDE LAYERS USING PULSED LASER ABLATION - Various laser processing schemes are disclosed for producing various types of hetero junction and homo-junction solar cells. The methods include base and emitter contact opening, selective doping, metal ablation, annealing to improve passivation, and selective emitter doping via laser heating of aluminum. Also, laser processing schemes are disclosed that are suitable for selective amorphous silicon ablation and selective doping for hetero junction solar cells. Laser ablation techniques are disclosed that leave the underlying silicon substantially undamaged. These laser processing techniques may be applied to semiconductor substrates, including crystalline silicon substrates, and further including crystalline silicon substrates which are manufactured either through wire saw wafering methods or via epitaxial deposition processes, or other cleavage techniques such as ion implantation and heating, that are either planar or textured/three-dimensional. These techniques are highly suited to thin crystalline semiconductor, including thin crystalline silicon films. | 2012-07-05 |
20120171805 | METHOD OF FABRICATING A SOLAR CELL - A method of fabricating a solar cell is provided. A first type semiconductor substrate having a first surface and a second surface is provided. A second type doped diffusion region is formed in parts of the first type semiconductor substrate. The second type doped diffusion region extends within the first type semiconductor substrate from the first surface. An anti-reflection coating (ARC) in contact with second type doped diffusion region is formed over the first surface. A conductive paste including conductive particles and dopant is formed over the ARC. A co-firing process for enabling the conductive paste to penetrate the ARC to form a first contact conductor embedded in the ARC is performed. During the co-firing process, the dopant diffuses into the second type doped diffusion region and a second type heavily doped diffusion region is formed. A second contact conductor is formed on the second surface. | 2012-07-05 |
20120171806 | METHOD FOR MAKING SOLAR CELL HAVING CRYSTALLINE SILICON P-N HOMOJUNCTION AND AMORPHOUS SILICON HETEROJUNCTIONS FOR SURFACE PASSIVATION - A thin silicon solar cell is described. An example solar cell may be fabricated from a crystalline silicon wafer having a thickness of approximately 50 micrometers to 500 micrometers. The solar cell comprises a first region having a p-n homojunction, a second region that creates heterojunction surface passivation, and a third region that creates heterojunction surface passivation. Amorphous silicon layers are deposited on both sides of the silicon wafer. A final layer of transparent conductive oxide is formed on both sides Metal contacts are applied to the transparent conductive oxide. | 2012-07-05 |
20120171807 | METHOD AND APPARATUS FOR MASKING SUBSTRATES FOR DEPOSITION - Disclosed are methods and apparatus for masking of substrates for deposition, and subsequent lifting of the mask with deposited material. Masking materials are utilized that can be used in high temperatures and vacuum environment. The masking material has minimal outgassing once inside a vacuum chamber and withstand the temperatures during deposition process. The mask is inkjeted over the wafers and, after deposition, removed using agitation, such as ultrasonic agitation, or using laser burn off. | 2012-07-05 |
20120171808 | ELECTROCHEMICAL CELL STRUCTURE AND METHOD OF FABRICATION - An electrochemical cell and a method of manufacturing the same are provided. The electrochemical cell comprising: a first conductive layer; a metal oxide layer formed on the first conductive layer, the metal oxide layer comprising a plurality of adjacent metal oxide cells, spaced from one another; a functional dye layer formed on the metal oxide layer; a second conductive layer; and an electrolyte between the functional dye layer and the second conductive layer, wherein at least one of the first and second conductive layers is transparent, and wherein the metal oxide layer is formed from a metal oxide particle dispersion liquid. | 2012-07-05 |
20120171809 | Method and Apparatus for Forming a Thin Lamina - A method for producing a lamina from a donor body includes implanting the donor body with an ion dosage and heating the donor body to an implant temperature during implanting. The donor body is separably contacted with a susceptor assembly, where the donor body and the susceptor assembly are in direct contact. A lamina is exfoliated from the donor body by applying a thermal profile to the donor body. Implantation and exfoliation conditions may be adjusted in order to maximize the defect-free area of the lamina. | 2012-07-05 |
20120171810 | Paste Composition For Electrode of Solar Cell and Solar Cell Including the Same - A paste composition for an electrode of a solar cell according to the present invention comprises a conductive powder, an organic vehicle, and a glass frit, and the glass frit includes a first glass frit having a first glass transition temperature and a second glass frit having a second glass frit temperature lower than the first glass transition temperature. | 2012-07-05 |
20120171811 | ORGANIC SEMICONDUCTOR COMPOSITIONS WITH NANOPARTICLES - A method of fabricating a circuit includes chemically bonding a coating to a plurality of nanoparticles. The nanoparticles are dispersed in a medium comprising organic molecules. An organic semiconductor channel is formed that comprises the medium. A plurality of electrodes is formed over the substrate. The electrodes are located to function as two of a gate electrode, a drain electrode, and a source electrode of a field-effect transistor. | 2012-07-05 |
20120171812 | METHODS OF FORMING GERMANIUM-ANTIMONY-TELLURIUM MATERIALS AND METHODS OF FORMING A SEMICONDUCTOR DEVICE STRUCTURE INCLUDING THE SAME - A method of forming a material comprises conducting an ALD layer cycle of a first metal, the ALD layer cycle comprising a reactive first metal precursor and a co-reactive first metal precursor. An ALD layer cycle of a second metal is conducted, the ALD layer cycle comprising a reactive second metal precursor and a co-reactive second metal precursor. An ALD layer cycle of a third metal is conducted, the ALD layer cycle comprising a reactive third metal precursor and a co-reactive third metal precursor. The ALD layer cycles of the first metal, the second metal, and the third metal are repeated to form a material, such as a GeSbTe material, having a desired stoichiometry. Additional methods of forming a material, such as a GeSbTe material, are disclosed, as is a method of forming a semiconductor device structure including a GeSbTe material. | 2012-07-05 |
20120171813 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - Electric characteristics and reliability of a thin film transistor are impaired by diffusion of an impurity element into a channel region. The present invention provides a thin film transistor in which aluminum atoms are unlikely to be diffused to an oxide semiconductor layer. A thin film transistor including an oxide semiconductor layer including indium, gallium, and zinc includes source or drain electrode layers in which first conductive, layers including aluminum as a main component and second conductive layers including a high-melting-point metal material are stacked. An oxide semiconductor layer | 2012-07-05 |
20120171814 | SEMICONDUCTOR PACKAGES AND METHODS OF FABRICATING THE SAME - Provided are a semiconductor package and a method of fabricating the same. In one embodiment, to fabricate a semiconductor package, a wafer having semiconductor chips fabricated therein is provided. A heat sink layer is formed over the wafer. The heat sink layer contacts top surfaces of the semiconductor chips. Thereafter, the plurality of semiconductor chips are singulated from the wafer. | 2012-07-05 |
20120171815 | CVD APPARATUS AND METHOD OF FORMING SEMICONDUCTOR SUPERLATTICE STRUCTURE USING THE SAME - Provided is a chemical vapor deposition (CVD) apparatus, including: a reaction chamber including an inner pipe having an internal space, and an external pipe configured to cover the inner pipe so as to maintain a sealing state thereof; a wafer holder disposed within the inner pipe and receiving a plurality of wafers stacked therein; and a gas supplier including at least one stem pipe disposed at the outside of the reaction chamber so as to supply a reactive gas thereto, a plurality of branch pipes connected to the stem pipe to introduce the reactive gas from the outside of the reaction chamber into the reaction chamber, and a plurality of spray nozzles provided with the branch pipes to spray the reactive gas to the plurality of respective wafers. | 2012-07-05 |
20120171816 | INTEGRATED CIRCUIT PACKAGE AND METHOD OF MAKING SAME - An integrated circuit package includes a first dielectric layer comprising a dielectric film having a first side and a second side, the first side having a plurality of contact locations and a plurality of non-contact locations. The package includes a plurality of components, each component having a first surface and a second surface, wherein the first surface of each of the plurality of components is affixed to a corresponding one of the plurality of contact locations of the dielectric film absent a layer of adhesive therebetween that is distinct from a material of the dielectric film. | 2012-07-05 |
20120171817 | SINGLE DIE OUTPUT POWER STAGE USING TRENCH-GATE LOW-SIDE AND LDMOS HIGH-SIDE MOSFETS, STRUCTURE AND METHOD - A voltage converter includes an output circuit having a high-side device and a low-side device which can be formed on a single die (a “PowerDie”). The high-side device can include a lateral diffused metal oxide semiconductor (LDMOS) while the low-side device can include a trench-gate vertical diffused metal oxide semiconductor (VDMOS). The voltage converter can further include a controller circuit on a different die which can be electrically coupled to, and co-packaged with the output circuit. | 2012-07-05 |
20120171818 | HYBRID BONDING INTERFACE FOR 3-DIMENSIONAL CHIP INTEGRATION - Each of a first substrate and a second substrate includes a surface having a diffusion resistant dielectric material such as silicon nitride. Recessed regions are formed in the diffusion resistant dielectric material and filled with a bondable dielectric material. The patterns of the metal pads and bondable dielectric material portions in the first and second substrates can have a mirror symmetry. The first and second substrates are brought into physical contact and bonded employing contacts between metal pads and contacts between the bondable dielectric material portions. Through-substrate-via (TSV) structures are formed through bonded dielectric material portions. The interface between each pair of bonded dielectric material portions located around a TSV structure is encapsulated by two diffusion resistant dielectric material layers so that diffusion of metal at a bonding interface is contained within each pair of bonded dielectric material portions. | 2012-07-05 |
20120171819 | ADAPTIVE INTERCONNECT STRUCTURE - An array of contact pads on a semiconductor structure has a pitch less than twice an overlay tolerance of a bonding process employed to vertically stack semiconductor structures. A set of contact pads within the area of overlay variation for a matching contact pin may be electrically connected to an array of programmable contacts such that one programmable contact is connected to each contact pad within the area of overlay variation. One contact pad may be provided with a plurality of programmable contacts. The variability of contacts between contact pins and contact pads is accommodated by connecting or disconnecting programmable contacts after the stacking of semiconductor structures. Since the pitch of the array of contact pins may be less than twice the overlay variation of the bonding process, a high density of interconnections is provided in the vertically stacked structure. | 2012-07-05 |
20120171820 | STRAINED MOS DEVICE AND METHODS FOR ITS FABRICATION - A method is provided for fabricating a strained MOS device having a silicon germanium on insulator (SGOI) substrate that includes a layer of monocrystalline silicon germanium material characterized by a first lattice constant. A strained silicon layer is formed over the layer of monocrystalline silicon germanium material. A layer of gate electrode material is patterned to form a gate electrode overlying a channel region. The strained silicon layer is disposed between the gate electrode and the channel region. First recess and second recesses are etched into the layer of monocrystalline silicon germanium material. A layer of monocrystalline semiconductor material is then epitaxially grown to fill the first and second recesses such that it is embedded at the opposing sides of the channel region. The layer of monocrystalline semiconductor material comprises silicon and germanium, and is characterized by a second lattice constant less than the first lattice constant. | 2012-07-05 |
20120171821 | METHOD AND STRUCTURE FOR FORMING CAPACITORS AND MEMORY DEVICES ON SEMICONDUCTOR-ON-INSULATOR (SOI) SUBSTRATES - A device is provided that includes memory, logic and capacitor structures on a semiconductor-on-insulator (SOI) substrate. In one embodiment, the device includes a semiconductor-on-insulator (SOI) substrate having a memory region and a logic region. Trench capacitors are present in the memory region and the logic region, wherein each of the trench capacitors is structurally identical. A first transistor is present in the memory region in electrical communication with a first electrode of at least one trench capacitor that is present in the memory region. A second transistor is present in the logic region that is physically separated from the trench capacitors by insulating material. In some embodiments, the trench capacitors that are present in the logic region include decoupling capacitors and inactive capacitors. A method for forming the aforementioned device is also provided. | 2012-07-05 |
20120171822 | MANUFACTURING METHOD FOR LTPS TFT ARRAY SUBSTRATE - A manufacturing method for a low temperature polysilicon (LTPS) thin film transistor (TFT) array substrate, comprising: forming a polysilicon layer on a substrate; forming a gate insulating layer on the polysilicon layer; forming a gate metal layer on the gate insulating layer; and patterning the gate metal layer, the gate insulating layer and the polysilicon layer by using a half tone mask (HTM) or a gray tone mask (GTM) so as to obtain a gate electrode and a polysilicon semiconductor pattern in a single mask process, a central part of the polysilicon semiconductor pattern is covered by the gate electrode, and the polysilicon semiconductor pattern has two parts, which are not covered by the gate electrode at two sides of the gate electrode, for forming a source region and a drain region. | 2012-07-05 |
20120171823 | METHOD OF FABRICATING THIN FILM TRANSISTOR - A thin film transistor (TFT), including a crystalline semiconductor pattern on a substrate, a gate insulating layer on the crystalline semiconductor pattern, the gate insulating layer having two first source/drain contact holes and a semiconductor pattern access hole therein, a gate electrode on the gate insulating layer, the gate electrode being between the two first source/drain contact holes, an interlayer insulating layer covering the gate electrode, the interlayer insulating layer having two second source/drain contact holes therein, and source and drain electrodes on the interlayer insulating layer, each of the source and drain electrodes being insulated from the gate electrode, and having a portion connected to the crystalline semiconductor pattern through the first and second source/drain contact holes. | 2012-07-05 |
20120171824 | HETEROSTRUCTURE DEVICE AND ASSOCIATED METHOD - A method of manufacturing a heterostructure device is provided that includes implantation of ions into a portion of a surface of a multi-layer structure. Iodine ions are implanted between a first region and a second region to form a third region. A charge is depleted from the two dimensional electron gas (2DEG) channel in the third region to form a reversibly electrically non-conductive pathway from the first region to the second region. On applying a voltage potential to a gate electrode proximate to the third region allows electrical current to flow from the first region to the second region. | 2012-07-05 |
20120171825 | SEMICONDUCTOR STRUCTURE AND METHOD OF FABRICATING THE SEMICONDUCTOR STRUCTURE - In contrast to a conventional planar CMOS technique in design and fabrication for a field-effect transistor (FET), the present invention provides an SGT CMOS device formed on a conventional substrate using various crystal planes in association with a channel type and a pillar shape of an FET, without a need for a complicated device fabrication process. Further, differently from a design technique of changing a surface orientation in each planar FET, the present invention is designed to change a surface orientation in each SGT to achieve improvement in carrier mobility. Thus, a plurality of SGTs having various crystal planes can be formed on a common substrate to achieve a plurality of different carrier mobilities so as to obtain desired performance. | 2012-07-05 |
20120171826 | METHOD OF FABRICATING SEMICONDUCTOR DEVICE - A method of fabricating a semiconductor includes providing a substrate having a first region and a second region defined therein, forming a first gate and a first source and drain region in the first region and forming a second gate and a second source and drain region in the second region, forming an epitaxial layer in the second source and drain region, forming a first metal silicide layer in the first source and drain region, forming an interlayer dielectric layer on the first region and the second region, forming a plurality of contact holes exposing the first metal silicide layer and the epitaxial layer while penetrating the interlayer dielectric layer, forming a second metal silicide layer in the exposed epitaxial layer, and forming a plurality of contacts contacting the first and second metal silicide layers by filling the plurality of contact holes. | 2012-07-05 |
20120171827 | STRUCTURE AND METHOD TO FORM EDRAM ON SOI SUBSTRATE - A memory device is provided that in one embodiment includes a trench capacitor located in a semiconductor substrate including an outer electrode provided by the semiconductor substrate, an inner electrode provided by a conductive fill material, and a node dielectric layer located between the outer electrode and the inner electrode; and a semiconductor device positioned centrally over the trench capacitor. The semiconductor device includes a source region, a drain region, and a gate structure, in which the semiconductor device is formed on a semiconductor layer that is separated from the semiconductor substrate by a dielectric layer. A first contact is present extending from an upper surface of the semiconductor layer into electrical contact with the semiconductor substrate, and a second contact from the drain region of the semiconductor device in electrical contact to the conductive material within the at least one trench. | 2012-07-05 |
20120171828 | Method of Forming a FET Having Ultra-low On-resistance and Low Gate Charge - In accordance with an exemplary embodiment of the invention, a substrate of a first conductivity type silicon is provided. A substrate cap region of the first conductivity type silicon is formed such that a junction is formed between the substrate cap region and the substrate. A body region of a second conductivity type silicon is formed such that a junction is formed between the body region and the substrate cap region. A trench extending through at least the body region is then formed. A source region of the first conductivity type is then formed in an upper portion of the body region. An out-diffusion region of the first conductivity type is formed in a lower portion of the body region as a result of one or more temperature cycles such that a spacing between the source region and the out-diffusion region defines a channel length of the field effect transistor. | 2012-07-05 |
20120171829 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - Recesses are formed in a pMOS region | 2012-07-05 |
20120171830 | ASYMMETRIC TRANSISTOR DEVICES FORMED BY ASYMMETRIC SPACERS AND TILTED IMPLANTATION - An asymmetric transistor configuration is disclosed in which asymmetric extension regions and/or halo regions may be combined with an asymmetric spacer structure which may be used to further adjust the overall dopant profile of the asymmetric transistor. | 2012-07-05 |
20120171831 | ASYMMETRIC FET INCLUDING SLOPED THRESHOLD VOLTAGE ADJUSTING MATERIAL LAYER AND METHOD OF FABRICATING SAME - A method of forming a semiconductor structure is provided. The method includes providing a structure including at least one dummy gate region located on a surface of a semiconductor substrate and a dielectric material layer located on sidewalls of the at least one dummy gate region. Next, a portion of the dummy gate region is removed exposing an underlying high k gate dielectric. A sloped threshold voltage adjusting material layer is then formed on an upper surface of the high k gate dielectric, and thereafter a gate conductor is formed atop the sloped threshold voltage adjusting material layer. | 2012-07-05 |
20120171832 | FINFET WITH STRESSORS - A fin type transistor includes a dielectric layer on a substrate surface which serves to isolate the gate of the transistor from the substrate. The dielectric layer includes a non-selectively etched surface to produce top portions of fin structures which have reduced height variations across the wafer. The fin type transistor may also include a buried stressor and/or raised or embedded raised S/D stressors to cause a strain in the channel to improve carrier mobility. | 2012-07-05 |
20120171833 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - The present application discloses a method for manufacturing a semiconductor device, comprising the steps of: forming a semiconductor substrate, a gate stack and a second protection layer in sequence on a first insulating layer; after defining a gate region and removing portions of the second protection layer and the gate stack outside the gate region, while keeping portions of the stop layer, the semiconductor layer and the second insulating layer which covers sidewalls of the patterned semiconductor layer outside the gate region and exposing the sacrificial layer, performing source/drain ion implementation in the semiconductor layer; after forming a second sidewall spacer so as to cover at least the exposed portion of the sacrificial layer, removing the first protection layer and the second protection layer so as to expose the semiconductor layer and the gate stack; and forming a contact layer on the exposed portion of the semiconductor layer and the gate stack; performing planarization so as to expose the first protection layer, and then removing the first protection layer, the sacrificial layer, the stop layer and the semiconductor layer with the first sidewall spacer and the second sidewall spacer as a mask, so as to form a cavity which exposes the first insulating layer. It facilitates reduction of short channel effects, resistance of source/drain regions, and parasite capacitance. | 2012-07-05 |
20120171834 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes a MOS transistor, a source electrode and a drain electrode on the MOS transistor each include a first carbon doped silicon layer including carbon at a first carbon concentration and phosphorus at a first phosphorus concentration and a second carbon doped silicon layer over the first silicon carbide layer, which includes phosphorus at a second phosphorus concentration higher than the first phosphorus concentration, and which includes carbon at a second carbon concentration less than or equal to the first carbon concentration. | 2012-07-05 |
20120171835 | METHOD FOR PROCESSING A GLASS SUBSTRATE - A method for processing a glass substrate is disclosed. A glass substrate including a first surface, a second surface, and a side surface between the first surface and the second surface is provided. An opaque conductive layer is formed on the second surface and a part of the side surface close to the second surface. Thereafter, a semiconductor process is performed on the first surface. Thereafter, the opaque conductive layer on the second surface and the part of the side surface close to the second surface is removed. The problem of transporting a transparent glass substrate by some semiconductor tools is solved without increasing tool cost by enabling the sensing and transportation of glass substrates with optical sensor and/or electrical chuck. The fabrication of devices with a glass substrate is also achieved. | 2012-07-05 |
20120171836 | Method for Forming MEMS Variable Capacitors - A method for fabricating an out-of-plane variable overlap MEMS capacitor comprises: providing a substrate ( | 2012-07-05 |
20120171837 | Semiconductor Memory Devices And Methods Of Fabricating The Same - Provided are semiconductor memory devices and the methods of fabricating the same. The method may include forming a plurality of diode patterns in each of a plurality of first trenches, each of the plurality of first trenches including at least two active regions, the plurality of diode patterns occupying a plurality of spaces, treating the plurality of diode patterns to form a plurality of semiconductor patterns in each of the plurality of spaces, removing portions of the plurality of semiconductor patterns to form a recess in each of the plurality of spaces, treating the of the plurality of semiconductor patterns to form a plurality of diodes in each of the plurality of spaces, forming a bottom electrode on each of the plurality of diodes, forming a plurality of memory elements on each of the bottom electrodes, and forming a plurality of upper interconnection lines on the plurality of memory elements. | 2012-07-05 |
20120171838 | RESISTOR STRUCTURE OF PHASE CHANGE MATERIAL AND TRIMMING METHOD THEREOF - An embodiment of a resistor formed by at least one first portion and one second portion, electrically coupled to one another and with different crystalline phases. The first portion has a positive temperature coefficient, and the second portion has a negative temperature coefficient. The first portion has a first resistivity, and the second portion has a second resistivity, and the portions are coupled so that the resistor has an overall temperature coefficient that is approximately zero. | 2012-07-05 |
20120171839 | FABRICATION OF SEMICONDUCTOR STACKS WITH RUTHENIUM-BASED MATERIALS - This disclosure provides a method of fabricating a semiconductor stack and associated device such as a capacitor and DRAM cell. In particular, a bottom electrode upon which a dielectric layer is to be grown may have a ruthenium-based surface. Lattice matching of the ruthenium surface with the dielectric layer (e.g., titanium oxide, strontium titanate or barium strontium titanate) helps promote the growth of rutile-phase titanium oxide, thereby leading to higher dielectric constant and lower effective oxide thickness. The ruthenium-based material also provides a high work function material, leading to lower leakage. To mitigate nucleation delay associated with the use of ruthenium, an adherence or glue layer based in titanium may be employed. A pretreatment process may be further employed so as to increase effective capacitor plate area, and thus promote even further improvements in dielectric constant and effective oxide thickness (“EOT”). | 2012-07-05 |
20120171840 | CAPACITOR AND METHOD FOR FABRICATING THE SAME - A method for fabricating a capacitor is provided. The method for fabricating a capacitor includes forming a dielectric layer over a lower electrode on a substrate, forming an upper electrode over the dielectric layer, forming a hard mask over the upper electrode, etching the hard mask to form a hard mask pattern, etching the upper electrode to make the dielectric layer remain on the lower electrode in a predetermined thickness, forming an isolation layer along an upper surface of the remaining dielectric layer and the hard mask pattern, leaving the isolation layer having a shape of a spacer on one sidewall of the hard mask pattern, the upper electrode, and the dielectric layer, and etching the lower electrode to be isolated. | 2012-07-05 |
20120171841 | BODY CONTACTED TRANSISTOR WITH REDUCED PARASITIC CAPACITANCE - A body contacted semiconductor-on-insulator (SOI) metal gate containing transistor that has a reduced parasitic gate capacitance is provided in which a metal portion of a gate stack is removed over the body contact region and a silicon-containing material is formed that contacts the gate dielectric in the body contact region of an SOI substrate. This causes an increase of the effective gate dielectric thickness on the body contact region by greater than 5 angstroms (Å). This results in a lower parasitic capacitance at the body contact region. | 2012-07-05 |
20120171842 | STRESS-GENERATING SHALLOW TRENCH ISOLATION STRUCTURE HAVING DUAL COMPOSITION - A shallow trench isolation structure containing a first shallow trench isolation portion comprising the first shallow trench material and a second shallow trench isolation portion comprising the second shallow trench material is provided. A first biaxial stress on at least one first active area and a second bidirectional stress on at least one second active area are manipulated separately to enhance charge carrier mobility in middle portions of the at least one first and second active areas by selection of the first and second shallow trench materials as well as adjusting the type of the shallow trench isolation material that each portion of the at least one first active area and the at least one second active area laterally abut. | 2012-07-05 |
20120171843 | MICROSTRUCTURE, MICROMACHINE, AND MANUFACTURING METHOD OF MICROSTRUCTURE AND MICROMACHINE - Without sacrificial layer etching, a microstructure and a micromachine are manufactured. A separation layer | 2012-07-05 |
20120171844 | DICING DIE BONDING FILM, SEMICONDUCTOR WAFER, AND SEMICONDUCTOR DEVICE - A dicing die bonding film including a bonding layer; and a pressure-sensitive adhesive layer adjoining the bonding layer, the pressure-sensitive adhesive layer having a storage modulus of about 400 to about 600 kPa at 25° C. and a peel strength of about 200 to about 350 mN/25 mm with respect to the bonding layer as measured according to KS-A-01107 standard. | 2012-07-05 |
20120171845 | CHUCK FOR CHEMICAL VAPOR DEPOSITION SYSTEMS AND RELATED METHODS THEREFOR - The present invention provides chucks having a well that supports rods produced during chemical vapor deposition. The chucks can utilize slats and windows around the well up to which the rod can grow and become supported. | 2012-07-05 |
20120171846 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE WITH BURIED BIT LINES - A method for fabricating a semiconductor device includes etching a substrate to form trenches that separate active regions, forming an insulation layer having an opening to open a portion of a sidewall of each active region, forming a silicon layer pattern to gap-fill a portion of each trench and cover the opening in the insulation layer, forming a metal layer over the silicon layer pattern, and forming a metal silicide layer as buried bit lines, where the metal silicide layer is formed when the metal layer reacts with the silicon layer pattern. | 2012-07-05 |
20120171847 | THIN-FILM DEVICES FORMED FROM SOLID PARTICLES - Methods and devices are provided for forming thin-films from solid group IIIA-based particles. In one embodiment of the present invention, a method is described comprising of providing a first material comprising an alloy of a) a group IIIA-based material and b) at least one other material. The material may be included in an amount sufficient so that no liquid phase of the alloy is present within the first material in a temperature range between room temperature and a deposition or pre-deposition temperature higher than room temperature, wherein the group IIIA-based material is otherwise liquid in that temperature range. The other material may be a group IA material. A precursor material may be formulated comprising a) particles of the first material and b) particles containing at least one element from the group consisting of: group IB, IIIA, VIA element, alloys containing any of the foregoing elements, or combinations thereof. | 2012-07-05 |
20120171848 | Method and System for Manufacturing Silicon and Silicon Carbide - The present invention provides a method of manufacturing silicon and a manufacturing system for manufacturing and extracting silicon by grinding silicon carbide and silica, mixing each at predetermined ratio after cleaning them, housing them in a crucible, heating this by a heating unit to make them react, oxidizing the silicon carbide with the silica and further, reducing the silica with the silicon carbide. The present invention further provides a method of simultaneously manufacturing silicon and silicon carbide and a manufacturing system for producing silicon carbide by forming a silicon carbide film by vapor phase epitaxy using active gas generated in heating for reaction for material and recovering the silicon carbide film. | 2012-07-05 |
20120171849 | APPARATUS FOR FORMING DEPOSITED FILM AND METHOD FOR FORMING DEPOSITED FILM - In order to form a high quality film without causing in-plane nonuniformity in film quality, an apparatus for forming deposited film according to an aspect of the present invention includes: a chamber; a first electrode located in the chamber; a second electrode that is located in the chamber with a predetermined spacing from the first electrode and includes a plurality of supply parts configured to supply material gases; an introduction path connected to the supply parts, through which the material gases are introduced; a heater located in the introduction path; and a cooling mechanism configured to cool the second electrode. | 2012-07-05 |
20120171850 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device includes the steps of forming a semiconductor layer made of SiC on an SiC substrate, forming a film on the semiconductor layer, and forming a groove in the film. The semiconductor device including a chip having an interlayer insulating film includes a groove formed in the interlayer insulating film to cross the chip. | 2012-07-05 |
20120171851 | Patterned Substrate for Hetero-epitaxial Growth of Group-III Nitride Film - A circuit structure includes a substrate and a film over the substrate and including a plurality of portions allocated as a plurality of rows. Each of the plurality of rows of the plurality of portions includes a plurality of convex portions and a plurality of concave portions. In each of the plurality of rows, the plurality of convex portions and the plurality of concave portions are allocated in an alternating pattern. | 2012-07-05 |
20120171852 | REMOTE HYDROGEN PLASMA SOURCE OF SILICON CONTAINING FILM DEPOSITION - Methods for forming and treating a silicon containing layer in a thin film transistor structure or solar cell devices are provided. In one embodiment, a method for forming a silicon containing layer on a substrate includes providing a substrate into a processing chamber, providing a gas mixture having a silicon containing gas into the processing chamber, providing a hydrogen containing gas from a remote plasma source coupled to the processing chamber, applying a RF power less than 17.5 mWatt/cm | 2012-07-05 |
20120171853 | DEFECT-FREE JUNCTION FORMATION USING OCTADECABORANE SELF-AMORPHIZING IMPLANTS - A method and apparatus for implanting a semiconductor substrate with boron clusters. A substrate is implanted with octadecaborane by plasma immersion or ion beam implantation. The substrate surface is then annealed to completely dissociate and activate the boron clusters. The annealing may take place by melting the implanted regions or by a sub-melt annealing process. | 2012-07-05 |
20120171854 | METHOD FOR FORMING METAL GATE - A method for forming a metal gate includes providing a substrate, subsequently forming a dummy gate on the substrate, forming spacers on sidewalls of the dummy gate, forming a stop layer on the substrate, the dummy gate and spacers of the dummy gate, and forming a sacrificial dielectric layer on the dummy gate and the stop layer. The method further includes removing a part of the sacrificial dielectric layer and the stop layer until the dummy gate is exposed and, removing a residual sacrificial dielectric layer, depositing an interlayer dielectric layer on the dummy gate and the stop layer, polishing the interlayer dielectric layer until the dummy gate is exposed, removing the dummy gate to form a trench, and forming a metal gate in the trench. The interlayer dielectric layer is flat and substantially flush with the dummy gate, so that no recesses are formed thereon. | 2012-07-05 |
20120171855 | METHODS TO ADJUST THRESHOLD VOLTAGE IN SEMICONDUCTOR DEVICES - Methods for forming a device on a substrate are provided herein. In some embodiments, a method of forming a device on a substrate may include providing a substrate having a partially fabricated first device disposed on the substrate, the first device including a first film stack comprising a first dielectric layer and a first high-k dielectric layer disposed atop the first dielectric layer; depositing a first metal layer atop the first film stack; and modifying a first upper surface of the first metal layer to adjust a first threshold voltage of the first device, wherein the modification of the first upper surface does not extend through to a first lower surface of the first metal layer. | 2012-07-05 |
20120171856 | NONVOLATILE SEMICONDUCTOR MEMORY AND MANUFACTURING METHOD THEREOF - A nonvolatile semiconductor memory includes a memory cell string having a plurality of memory cell transistors connected in series, a selection gate transistor connected in series with one end of the memory cell string, and having a gate electrode provided on a gate insulating film on a semiconductor substrate, and an element isolation insulating layer which is provided in the semiconductor substrate. The gate electrode includes a first gate electrode provided on the gate insulating film, a first and second insulating films provided on the first gate electrode, and a second gate electrode provided on the second insulating film and the element isolation insulating layer, and electrically connected to the first gate electrode. An first upper surface portion of the element isolation insulating layer below the second gate electrode is leveled with an upper surface of the first gate electrode. | 2012-07-05 |
20120171857 | ELECTRICALLY PROGRAMMABLE FUSE USING ANISOMETRIC CONTACTS AND FABRICATION METHOD - A fabrication method for fabricating an electrically programmable fuse method includes depositing a polysilicon layer on a substrate, patterning an anode contact region, a cathode contact region and a fuse link conductively connecting the cathode contact region with the anode contact region, which is programmable by applying a programming current, depositing a silicide layer on the polysilicon layer, and forming a plurality of anisometric contacts on the silicide layer of the cathode contact region and the anode contact region in a predetermined configuration, respectively. | 2012-07-05 |
20120171858 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device, wherein a first substrate where first electrode pads are formed and a second substrate where second electrode pads are formed are stacked and the first electrode pads and the corresponding second electrode pads are electrically connected thereby forming the semiconductor device is disclosed. The method includes steps of performing a first hydrophilic treatment with respect to the first electrode pads; supplying liquid to a surface where the first electrode pads are formed in the first substrate; and placing the second substrate on the first substrate to which the liquid is supplied so that the surface where the first electrode pads are formed opposes a surface where the second electrode pads are formed, thereby aligning the first electrode pads and the second electrode pads by the liquid that gathers in the first electrode pads that have been subject to the first hydrophilic treatment. | 2012-07-05 |
20120171859 | CREATION OF VIAS AND TRENCHES WITH DIFFERENT DEPTHS - Embodiments of the invention provide a method of creating vias and trenches with different length. The method includes depositing a plurality of dielectric layers on top of a semiconductor structure with the plurality of dielectric layers being separated by at least one etch-stop layer; creating multiple openings from a top surface of the plurality of dielectric layers down into the plurality of dielectric layers by a non-selective etching process, wherein at least one of the multiple openings has a depth below the etch-step layer; and continuing etching the multiple openings by a selective etching process until one or more openings of the multiple openings that are above the etch-stop layer reach and expose the etch-stop layer. Semiconductor structures made thereby are also provided. | 2012-07-05 |
20120171860 | METAL CAP FOR BACK END OF LINE (BEOL) INTERCONNECTS, DESIGN STRUCTURE AND METHOD OF MANUFACTURE - A structure is provided with a metal cap for back end of line (BEOL) interconnects that substantially eliminates electro-migration (EM) damage, a design structure and a method of manufacturing the IC. The structure includes a metal interconnect formed in a dielectric material and a metal cap selective to the metal interconnect. The metal cap includes RuX, where X is at Boron, Phosphorous or a combination of Boron and Phosphorous. | 2012-07-05 |
20120171861 | METHODS OF FABRICATING THREE-DIMENSIONAL SEMICONDUCTOR DEVICE - A method of fabricating a three-dimensional semiconductor device includes forming a stacked structure, and the stacked structure includes a first layer, a second layer, a third layer, and a fourth layer sequentially stacked on a substrate. The method also includes forming a sacrificial spacer on a sidewall of the stacked structure such that the sacrificial spacer exposes a sidewall of the third layer, and recessing the exposed sidewall of the third layer thereby forming a recess region between the second and fourth layers. | 2012-07-05 |
20120171862 | INTERCONNECT STRUCTURE AND METHOD OF MAKING SAME - An interconnect structure and method of fabricating the same is provided. More specifically, the interconnect structure is a defect free capped interconnect structure. The structure includes a conductive material formed in a trench of a planarized dielectric layer which is devoid of cap material. The structure further includes the cap material formed on the conductive material to prevent migration. The method of forming a structure includes selectively depositing a sacrificial material over a dielectric material and providing a metal capping layer over a conductive layer within a trench of the dielectric material. The method further includes removing the sacrificial material with any unwanted deposited or nucleated metal capping layer thereon. | 2012-07-05 |
20120171863 | METAL SILICIDE FILM FORMING METHOD - There is provided a metal silicide film forming method that includes providing a substrate having thereon a silicon part (process 1); forming a metal film on a surface of the silicon part of the substrate by a CVD process using a nitrogen-containing metal compound as a film forming source material (process 2); performing an annealing process on the substrate under a hydrogen gas atmosphere; and forming a metal silicide by a reaction between the metal film and the silicon part (process 3). Here, the nitrogen-containing metal compound as the film forming source material is metal amidinate. Further, the metal film is a nickel (Ni) film. Furthermore, the metal amidinate is nickel amidinate. | 2012-07-05 |
20120171864 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - The method of manufacturing the semiconductor device comprises the steps of forming a MOS transistor | 2012-07-05 |
20120171865 | METHOD FOR FABRICATING FINE PATTERNS - A method for fabricating fine patterns includes forming a first photomask including first line patterns and first assist features and forming a second photomask including second line patterns extending to a portion corresponding to the first assist features in a direction perpendicular to the first line patterns. A first resist layer may be exposed through a first exposure process by using the first photomask, and a first resist pattern formed to open regions following the shape of the first line patterns. The first resist pattern may be frozen and a second resist layer may be formed to fill the opened regions of the first resist pattern. The second resist layer may be exposed through a second exposure process by using the second photomask, and a second resist pattern formed to open regions corresponding to the intersections between the first and second line patterns with the first resist pattern. | 2012-07-05 |
20120171866 | SUBSTRATE STRUCTURE INCLUDING FUNCTIONAL REGION AND METHOD FOR TRANSFERRING FUNCTIONAL REGION - According to a method for transferring a functional region, at least part of functional regions on separation layers arranged on a first substrate is transferred onto a second substrate, the separation layers being capable of being brought into a separable state by treatment. In a first bonding step, the first substrate is bonded to the second substrate with a dry film resist arranged between the second substrate and the at least part of the functional regions above the first substrate. In an exposure step, at least part of the dry film resist is exposed. In a patterning step, the exposed dry film resist is patterned. | 2012-07-05 |
20120171867 | METHOD FOR FABRICATING FINE PATTERN BY USING SPACER PATTERNING TECHNOLOGY - A method for fabricating a fine pattern includes forming a line-shaped partition pattern on an underlayer, adhering a first spacer to the sides of the partition pattern, dividing the first spacer into two line patterns where one line pattern has one end bent by selectively etching the first spacer portion with a division region, adhering a second spacer, which has a connection protrusion filling the division region and connecting to the partition pattern, to the outer side of the two line patterns, and selectively removing the two line patterns. | 2012-07-05 |
20120171868 | RESIST UNDERLAYER FILM COMPOSITION AND PATTERNING PROCESS USING THE SAME - There is disclosed A resist underlayer film composition, wherein the composition contains a polymer obtained by condensation of, at least, one or more compounds represented by the following general formulae (1-1) and/or (1-2), one or more kinds of a compound represented by the following general formula (2), and one or more kinds of a compound, represented by the following general formula (3), and/or an equivalent body thereof. There can be provided an underlayer film composition, especially for a trilayer resist process, that can form an underlayer film having reduced reflectance, (namely, an underlayer film having optimum n-value and k-value as an antireflective film), excellent filling-up properties, high pattern-antibending properties, and not causing line fall or wiggling after etching especially in a high aspect line that is thinner than 60 nm, and a patterning process using the same. | 2012-07-05 |
20120171869 | ETCHING METHOD - There is provided an etching method which can form trenches or via holes having desired aspect ratios and shapes in a to-be-processed object made of silicon. The etching method includes: a hydrogen halide-containing gas-based etching step of etching a silicon substrate by introducing a hydrogen halide-containing gas into a vacuum chamber; a fluorine-containing gas-based etching step of etching the silicon substrate by introducing a fluorine-containing gas into the vacuum chamber; a protective film formation step forming a protective film on the silicon substrate by sputtering a solid material; and a protective film removal step of removing part of the protective film by applying radio frequency bias power to a substrate electrode. The fluorine-containing gas-based etching step, the protective film formation step, and the protective film removal step are repeatedly performed in this order. | 2012-07-05 |
20120171870 | WAFER PROCESSING WITH CARRIER EXTENSION - Apparatus for treating wafers using a wafer carrier rotated about an axis is provided with a ring which surrounds the wafer carrier during operation. Treatment gasses directed onto a top surface of the carrier flow outwardly away from the axis over the carrier and over the ring, and pass downstream outside of the ring. The outwardly flowing gasses form a boundary over the carrier and ring. The ring helps to maintain a boundary layer of substantially uniform thickness over the carrier, which promotes uniform treatment of the wafers. | 2012-07-05 |
20120171871 | COMPOSITE SHOWERHEAD ELECTRODE ASSEMBLY FOR A PLASMA PROCESSING APPARATUS - A showerhead electrode for a plasma processing apparatus includes an interface gel between facing surfaces of an electrode plate and a backing plate. The interface gel maintains thermal conductivity during lateral displacements generated during temperature cycling due to mismatch in coefficients of thermal expansion. The interface gel comprises, for example, a silicone based composite filled with aluminum oxide microspheres. The interface gel can conform to irregularly shaped features and maximize surface contact area between mating surfaces. The interface gel can be pre-applied to a consumable upper electrode. | 2012-07-05 |
20120171872 | CLAMPED SHOWERHEAD ELECTRODE ASSEMBLY - An electrode assembly for a plasma reaction chamber used in semiconductor substrate processing. The assembly includes an upper showerhead electrode which includes an inner electrode mechanically attached to a backing plate by a clamp ring and an outer electrode attached to the backing plate by a series of spaced apart cam locks. A guard ring surrounds the backing plate and is movable to positions at which openings in the guard ring align with openings in the backing plate so that the cam locks can be rotated with a tool to release cam pins extending upward from the upper face of the outer electrode. To compensate for differential thermal expansion, the clamp ring can include expansion joins at spaced locations which allow the clamp ring to absorb thermal stresses. | 2012-07-05 |
20120171873 | THIN FILM TRANSISTOR PRINTING APPARATUS AND THIN FILM TRANSISTOR PRINTING METHOD USING THE SAME - According to an example embodiment, a thin film transistor (TFT) printing apparatus includes a stage having a TFT substrate loaded thereon, a stage moving device configured to move the stage according to a printing vector set to correspond to a print pattern, and a print head on an upper side of the stage and including a plurality of nozzles in a matrix shape. | 2012-07-05 |