27th week of 2010 patent applcation highlights part 35 |
Patent application number | Title | Published |
20100173428 | Protein Phosphorylation By Basophillic Serine/Threonine Kinases - The invention discloses 461 novel phosphorylation sites identified in basophilic Ser/Thr kinase signaling pathways, peptides (including AQUA peptides) comprising a phosphorylation site of the invention, antibodies specifically bind to a novel phosphorylation site of the invention, and diagnostic and therapeutic uses of the above. | 2010-07-08 |
20100173429 | METHODS USING NOVEL CHEMILUMINESCENT LABELS - Methods using chemiluminescent label compounds and chemiluminescent labeled conjugates are provided. The compounds comprise an acridan ring bearing an exocyclic ketene dithioacetal group and further contain a labeling substituent which permits attachment to compounds of interest. The novel chemiluminescent compounds and labeled conjugates are convenient to prepare, are highly stable, and generate chemiluminescence rapidly on demand. The compounds and conjugates are useful in assays of an analyte in a sample and in assays employing labeled specific binding pairs. | 2010-07-08 |
20100173430 | CYSTEINE-TAGGED STAPHYLOCOCCAL PROTEIN G VARIANT - The present invention relates to an N-terminal cysteine-tagged Streptococcal protein G variant. Since the variant binds in a directional manner to a surface of a biochip or a biosensor, the variant provides a biochip and a biosensor having an improved antibody-immobilizing capability, compared with an untagged protein G variant. | 2010-07-08 |
20100173431 | WAFER RECLAMATION METHOD AND WAFER RECLAMATION APPARATUS - Provided is a wafer reclamation method for reclaiming a semiconductor wafer, on which a different material layer is formed, by removing the different material layer. The wafer reclamation method includes a physically removing step of physically removing the different material layer, a film forming step of forming a film on a surface of the semiconductor wafer from which the different material layer has been removed in the physically removing step, and a dry etching step of etching the semiconductor wafer by plasma together with the film formed in the film forming step. | 2010-07-08 |
20100173432 | GAP MAINTENANCE FOR OPENING TO PROCESS CHAMBER - A semiconductor processing apparatus includes a reaction chamber, a movable susceptor, a movement element, and a control system. The reaction chamber includes a baseplate. The baseplate includes an opening. The movable susceptor is configured to hold a workpiece. The movable element is configured to move a workpiece held on the susceptor towards the opening of the baseplate. The control system is configured to space the susceptor from the baseplate by an unsealed gap during processing of a workpiece in the reaction chamber. Purge gases may flow through the gap into the reaction chamber. Methods of maintaining the gap during processing include calibrating the height of pads and capacitance measurements when the susceptor is spaced from the baseplate. | 2010-07-08 |
20100173433 | LIQUID CRYSTAL DISPLAY PANEL AND METHOD OF MANUFACTURING THE SAME - The present invention provides a liquid crystal display panel and a method of manufacturing the liquid crystal display panel capable of reducing or eliminating metal erosion in an area in which a conductive dot is formed. In some embodiments, a display panel comprises a common electrode formed on an upper substrate, a first electrode formed on a lower substrate opposing the upper substrate and configured to receive a common voltage, a conductive dot formed between the upper substrate and the lower substrate and positioned to supply the common electrode with the common voltage, an insulating layer having a contact hole exposing the first electrode, and a second electrode formed on the insulating layer to connect the conductive dot and the first electrode, wherein a cross sectional area of the conductive dot between the upper substrate and the lower substrate is greater than a cross sectional area of an opening of the contact hole. | 2010-07-08 |
20100173434 | NANOCRYSTAL ELECTROLUMINESCENCE DEVICE AND FABRICATION METHOD THEREOF - A nanocrystal electroluminescence device comprising a polymer hole transport layer, a nanocrystal light-emitting layer and an organic electron transport layer wherein the nanocrystal light-emitting layer is independently and separately formed between the polymer hole transport layer and the organic electron transport layer. According to the nanocrystal electroluminescence device, since the hole transport layer, the nanocrystal light-emitting layer and the electron transport layer are completely separated from one another, the electroluminescence device provides a pure nanocrystal luminescence spectrum having limited luminescence from other organic layers and substantially no influence by operational conditions, such as voltage. Further, a method for fabricating the nanocrystal electroluminescence device. | 2010-07-08 |
20100173435 | ARRAY SUBSTRATE FOR IN-PLANE SWITCHING MODE LIQUID CRYSTAL DISPLAY DEVICE AND METHOD OF FABRICATING THE SAME - An array substrate for an IPS mode LCD device comprises a substrate; a gate line along a first direction; a data line along a second direction; a TFT connected to the gate and data lines; a common electrode having a plate shape on the substrate and formed of a first transparent conductive material; and a pixel electrode formed of a second transparent conductive material on the common electrode and including first and second portions and a plurality of third portions combining the first portion with the second portion. The first and second portions are parallel to the second direction and separated from each other and the plurality of third portions are oblique to the first and second portions and separated from one another. | 2010-07-08 |
20100173436 | METHOD OF MAKING BIOMEMS DEVICES - A MEMS device is manufactured by first forming a self-aligned monolayer (SAM) on a carrier wafer. Next, a first polymer layer is formed on the self-aligned monolayer. The first polymer layer is patterned form a microchannel cover, which is then bonded to a patterned second polymer layer on a device wafer to form microchannels. The carrier wafer is then released from the first polymer layer. | 2010-07-08 |
20100173437 | Method of fabricating CMUTs that generate low-frequency and high-intensity ultrasound - The present invention provides a method of fabricating low-frequency and high-intensity ultrasound CMUTs that includes using deep reactive ion (DRIE) etching to etch at least one cavity in a first surface of a conductive silicon wafer, growing an insulating layer on at least the first surface of the conductive silicon wafer, bonding a silicon layer of a SOI wafer to the insulating layer, where the SOI wafer includes a handle layer, a buried oxide layer and a conductive silicon layer. The handle layer and the buried oxide layer of the SOI wafer are removed, where the conductive layer of the SOI wafer forms a membrane across at least one cavity, and electrically isolating at least one the membrane across the at least one cavity, where at least one the low-frequency and high-intensity ultrasound CMUT is provided. | 2010-07-08 |
20100173438 | METHOD FOR MANUFACTURING THERMOELECTRIC CONVERTER - A method of manufacturing a thermoelectric converter is provided, wherein an alcohol dispersion liquid comprising a ceramic particle having the average size of 1 to 100 nm and a salt of an element constituting the thermoelectric conversion material is prepared, and thereafter the dispersion liquid is dropped into a solution containing a reducing agent to deposit a raw material particle of the thermoelectric conversion material, which is subsequently subject to heating and sintering. | 2010-07-08 |
20100173439 | Methods and systems of transferring a substrate to minimize heat loss - A method of transferring one or more substrates between process modules or load lock stations while minimizing heat loss is provided. In some embodiments the method comprising the steps of: identifying a destination location D1 for a substrate S1 present at an initial processing location P1; if the destination location D1 is occupied with a substrate S2, maintaining the substrate S1 at the initial processing location P1; and if the destination location D1 is available, transferring the substrate S1 to the destination location D1. In accordance with additional embodiments, the method is carried out on a system for processing substrates which includes two or more process modules, a substrate handling robot, a load lock chamber, and a transverse substrate handler. The transverse substrate handler includes mobile transverse chambers configured to convey substrates to process modules, wherein each mobile transverse chamber is configured to maintain a specified gas condition during the conveyance of the substrates. The transverse substrate handler further includes a rail for supporting the mobile transverse chambers, wherein the rail is positioned adjacent to entry of the process modules, and drive systems for moving the mobile transverse chambers on the rail. | 2010-07-08 |
20100173440 | Nozzle-Based, Vapor-Phase, Plume Delivery Structure for Use in Production of Thin-Film Deposition Layer - A physical vapor deposition effusion method comprising translating a strip material through a physical vapor deposition zone in a deposition chamber and providing first and second substantially closed vessels located serially along the processing path in the same deposition chamber, each vessel emitting different source materials to produce overlapping plumes and having an array of vapor delivery nozzles distributed uniformly across the vessel along the width of the zone, and configured to expel overlapping plumes to create a fog having a substantially uniform composition across the width and a varying composition across the length of the zone. Also, an elongate vapor deposition effusion vessel having an elongate lid including plural nozzles spaced from each other along its elongate axis, and a continuous heating element in the lid encircling the plural nozzles, the heating element having electrical contacts connected to an electrical source on the same side of the vessel. | 2010-07-08 |
20100173441 | METHOD FOR PROCESSING ELONGATE SUBSTRATES AND SUBSTRATE SECURING APPARATUS - A method for processing elongate substrates, including forming a plurality of parallel elongate openings ( | 2010-07-08 |
20100173442 | Image sensor and method for manufacturing the same - An image sensor and a method for manufacturing the same are provided. In the method, a photoresist is formed on a substrate including a photodiode region and a gate electrode opposite to the photodiode region on the basis of the gate electrode. An oxide layer is formed to a specific thickness on both the photodiode region and a part of the gate electrode. The photoresist is removed from the substrate and cleaned. A first oxide film is formed on the substrate, the gate electrode, and the oxide layer remaining on the photodiode region. A nitride film is formed on the first oxide film. And a second oxide film is formed on the nitride film. Blank etching is performed on the first oxide film, the nitride film, and the second oxide film to form a spacer at the side of the gate electrode. | 2010-07-08 |
20100173443 | METHOD OF MANUFACTURING A PHOTO-DETECTOR ARRAY DEVICE WITH ROIC MONOLITHICALLY INTEGRATED FOR LASER-RADAR IMAGE SIGNAL - A method of manufacturing a photo-detector array device integrated with a read-out integrated circuit (ROIC) monolithically integrated for a laser-radar image signal. A detector array device, a photodiode and control devices for selecting and outputting a laser-radar image signal are simultaneously formed on an InP substrate. In addition, after the photodiode and the control devices are simultaneously formed on the InP substrate, the photodiode and the control devices are electrically separated from each other using a polyamide, whereby a PN junction surface of the photodiode is buried to reduce surface leakage current and improve electrical reliability, and the structure of the control devices can be simplified to improve image signal reception characteristics. | 2010-07-08 |
20100173444 | MANUFACTURING METHOD OF A PHOTOELECTRIC CONVERSION DEVICE - A manufacturing method of a photoelectric conversion device comprises a first step of forming a gate electrode, a second step of forming a semiconductor region of a first conductivity type, a third step of forming an insulation film, and a fourth step of forming a protection region of a second conductivity type, which is the opposite conductivity type to the first conductivity type, by implanting ions in the semiconductor region using the gate electrode of the transfer transistor and a portion covering a side face of the gate electrode of the transfer transistor of the insulation film as a mask in a state in which the semiconductor substrate and the gate electrode of the transfer transistor are covered by the insulation film, and causing a portion of the semiconductor region of the first conductivity type from which the protection region is removed to be the charge accumulation region. | 2010-07-08 |
20100173445 | PRODUCTION METHOD FOR A SENSOR UNIT OF AN X-RAY DETECTOR - A production method for a sensor unit of an X-ray detector is disclosed, which can be implemented easily and precisely, is specified, the sensor unit including a scintillator with photodiodes integrated in its septa for lateral readout. In at least one embodiment of the method, individual scintillator strips are initially produced from a plurality of scintillator pixels adjoining one another along one dimension. Respectively one photodiode strip, made of a plurality of photodiodes in turn adjoining one another along one dimension, is attached to each of the individual scintillator strips along a longitudinal side in order to form a sensor strip. Here, respectively one photodiode is associated with each scintillator pixel for readout purposes. Finally, a plurality of such sensor strips are interconnected to form the two-dimensional sensor unit such that a longitudinal side of the one sensor strip facing away from the photodiode strip respectively rests against a rear side of the photodiode strip of the adjacent sensor strip. | 2010-07-08 |
20100173446 | Layered Contact Structure For Solar Cells - Formulations and methods of making semiconductor devices and solar cell contacts are disclosed. The invention provides a method of making a semiconductor device or solar cell contact including ink-jet printing onto a silicon wafer an ink composition, typically including a high solids loading (20-80 wt %) of glass fit and preferably a conductive metal such as silver. The wafer is then fired such that the glass frit fuses to form a glass, thereby forming a contact layer to silicon. | 2010-07-08 |
20100173447 | Solar cell and method of fabricating the same - A solar cell ( | 2010-07-08 |
20100173448 | HIGH FREQUENCY PLASMA ENHANCED CHEMICAL VAPOR DEPOSITION - The present invention generally comprises a method for forming a thin film transistor device in a capacitively coupled PECVD processing chamber. The method comprises forming an active layer on a substrate by a method comprising depositing a silicon nitride layer adjacent to the substrate with a first frequency power source, and depositing a semiconductor layer adjacent to the silicon nitride layer with a second frequency power source, and forming a passivation layer adjacent to the active layer by a method comprising depositing a silicon nitride layer adjacent to the semiconductor layer with the first frequency power source. | 2010-07-08 |
20100173449 | METHODS OF FABRICATING P-I-N DIODES, STRUCTURES FOR P-I-N DIODES AND DESIGN STRUCTURE FOR P-I-N DIODES - Methods of fabricating P-I-N diodes, structures for P-I-N diodes and design structure for P-I-N diodes. A method includes: forming a trench in a silicon substrate; forming a doped region in the substrate abutting the trench; growing an intrinsic epitaxial silicon layer on surfaces of the trench; depositing a doped polysilicon layer to fill remaining space in the trench, performing a chemical mechanical polish so top surfaces of the intrinsic epitaxial silicon layer and the doped polysilicon layer are coplanar; forming a dielectric isolation layer in the substrate; forming a dielectric layer on top of the isolation layer; and forming a first metal contact to the doped polysilicon layer through the dielectric layer and a second contact to the doped region the dielectric and through the isolation layer. | 2010-07-08 |
20100173450 | MATRIX TYPE DISPLAY DEVICE WITH OPTICAL MATERIAL AT PREDETERMINED POSITIONS AND MANUFACTURING METHOD THEREOF - An object of the invention is to improve patterning accuracy while maintaining low cost, high throughput and a high degree of freedom of an optical material in a matrix type display device and a manufacturing method thereof. | 2010-07-08 |
20100173451 | ORGANIC THIN FILM TRANSISTOR SUBSTRATE AND METHOD OF MANUFACTURING THE SAME - The present invention provides an organic thin film transistor substrate and a method of manufacturing the same capable of uniformly forming the thickness of a gate insulating layer and a protective layer and preventing overflow of an organic semiconductive layer. | 2010-07-08 |
20100173452 | METHOD TO FORM HIGH EFFICIENCY GST CELL USING A DOUBLE HEATER CUT - Embodiments of the present invention provide a method that includes providing wafer including multiple cells, each cell including at least one emitter. The method further includes performing a lithographic operation in a word line direction of the wafer across the cells to form pre-heater element arrangements, performing a lithographic operation in a bit line direction of the wafer across the pre-heater element arrangements to form a pre-heater element adjacent each emitter, and performing a lithographic operation in the word line direction across a portion of the pre-heater elements to form a heater element adjacent each emitter. Other embodiments are also described. | 2010-07-08 |
20100173453 | Three dimensional structure memory - A Three-Dimensional Structure (3DS) Memory allows for physical separation of the memory circuits and the control logic circuit onto different layers such that each layer may be separately optimized. One control logic circuit suffices for several memory circuits, reducing cost. Fabrication of 3DS memory involves thinning of the memory circuit to less than 50 μm in thickness and bonding the circuit to a circuit stack while still in wafer substrate form. Fine-grain high density inter-layer vertical bus connections are used. The 3DS memory manufacturing method enables several performance and physical size efficiencies, and is implemented with established semiconductor processing techniques. | 2010-07-08 |
20100173454 | MICROELECTRONIC PACKAGES WITH LEADFRAMES, INCLUDING LEADFRAMES CONFIGURED FOR STACKED DIE PACKAGES, AND ASSOCIATED SYSTEMS AND METHODS - Microelectronic packages with leadframes, including leadframes configured for stacked die packages, and associated systems and methods are disclosed. A system in accordance with one embodiment includes a support member having first package bond sites electrically coupled to leadframe bond sites. A microelectronic die can be carried by the support member and electrically coupled to the first packaged bond sites. A leadframe can be attached to the leadframe bond sites so as to extend adjacent to the microelectronic die, with the die positioned between the leadframe and the support member. The leadframe can include second package bond sites facing away from the first package bond sites. An encapsulant can at least partially surround the leadframe and the microelectronic die, with the first and second package bond sites accessible from outside the encapsulant. | 2010-07-08 |
20100173455 | SEMICONDUCTOR DEVICE HAVING SEALING FILM AND MANUFACTURING METHOD THEREOF - A semiconductor device includes a plurality of wiring lines which are provided on an upper side of a semiconductor substrate and which have connection pad portions, and columnar electrodes are provided on the connection pad portions of the wiring lines. A first sealing film is provided around the columnar electrodes on the upper side of the semiconductor substrate and on the wiring lines. A second sealing film is provided on the first sealing film. The first sealing film is made of a resin in which fillers are not mixed, and the second sealing film is made of a material in which fillers are mixed in a resin. | 2010-07-08 |
20100173456 | Methods of Forming Field Effect Transistors, Methods of Forming Field Effect Transistor Gates, Methods of Forming Integrated Circuitry Comprising a Transistor Gate Array and Circuitry Peripheral to the Gate Array, and Methods of Forming Integrated Circuitry Comprising a Transistor Gate Array Including First Gates and Second Grounded Isolation Gates - The invention includes methods of forming field effect transistors, methods of forming field effect transistor gates, methods of forming integrated circuitry comprising a transistor gate array and circuitry peripheral to the gate array, and methods of forming integrated circuitry comprising a transistor gate array including first gates and second grounded isolation gates. In one implementation, a method of forming a field effect transistor includes forming masking material over semiconductive material of a substrate. A trench is formed through the masking material and into the semiconductive material. Gate dielectric material is formed within the trench in the semiconductive material. Gate material is deposited within the trench in the masking material and within the trench in the semiconductive material over the gate dielectric material. Source/drain regions are formed. Other aspects and implementations are contemplated. | 2010-07-08 |
20100173457 | Highly scalable thin film transistor - Shrinking the dimensions of PMOS or NMOS thin film transistors is limited by dopant diffusion. In these devices an undoped or lightly doped channel region is interposed between heavily doped source and drain regions. When the device is built with very short gate length, source and drain dopants will diffuse into the channel, potentially shorting it and ruining the device. A suite of innovations is described which may be used in various combinations to minimize dopant diffusion during fabrication of a PMOS or NMOS polycrystalline thin film transistor, resulting in a highly scalable thin film transistor. This transistor is particularly suitable for use in a monolithic three dimensional array of stacked device levels. | 2010-07-08 |
20100173458 | LATERAL DOUBLE DIFFUSED MOSFET TRANSISTOR WITH A LIGHTLY DOPED SOURCE - Methods and systems for monolithically fabricating a lateral double-diffused MOSFET (LDMOS) transistor having a source, drain, and a gate on a substrate, with a process flow that is compatible with a CMOS process flow are described. | 2010-07-08 |
20100173459 | MULTIPLE DOPING LEVEL BIPOLAR JUNCTIONS TRANSISTORS AND METHOD FOR FORMING - A process for forming bipolar junction transistors having a plurality of different collector doping densities on a semiconductor substrate and an integrated circuit comprising bipolar junction transistors having a plurality of different collector doping densities. A first group of the transistors are formed during formation of a triple well for use in providing triple well isolation for complementary metal oxide semiconductor field effect transistors also formed on the semiconductor substrate. Additional bipolar junction transistors with different collector doping densities are formed during a second doping step after forming a gate stack for the field effect transistors. Implant doping through bipolar transistor emitter windows forms bipolar transistors having different doping densities than the previously formed bipolar transistors. According to one embodiment of the present invention, bipolar junction transistors having six different collector dopant densities (and thus six different breakdown characteristics) are formed. | 2010-07-08 |
20100173460 | VERTICAL TRANSISTOR, MEMORY CELL, DEVICE, SYSTEM AND METHOD OF FORMING SAME - A memory device, system and fabrication method relating to a vertical memory cell including a semiconducting pillar extending outwardly from an integrally connected semiconductor substrate are disclosed. A first source/drain region is formed in the substrate and a body region and a second source/drain region are formed within the pillar. A first gate is coupled to a first side of the pillar for coupling the first and second source/drain regions together when activated. The vertical memory cell also includes a storage capacitor formed on an extended end of the semiconducting pillar and electrically coupled to the second source/drain region. | 2010-07-08 |
20100173461 | METHOD OF FABRICATING SEMICONDUCTOR DEVICE - In a method of fabricating a semiconductor device having a MISFET of trench gate structure, a trench is formed from a major surface of a semiconductor layer of first conductivity type which serves as a drain region, in a depth direction of the semiconductor layer, a gate insulating film including a thermal oxide film and a deposited film is formed over the internal surface of the trench, and after a gate electrode has been formed in the trench, impurities are introduced into the semiconductor substrate of first conductivity type to form a semiconductor region of second conductivity type which serves as a channel forming region, and impurities are introduced into the semiconductor region of second conductivity type to form the semiconductor region of first conductivity type which serves as a source region. | 2010-07-08 |
20100173462 | METHOD AND APPARATUS FOR FABRICATING A CARBON NANOTUBE TRANSISTOR - A method of fabricating a nanotube field-effect transistor having unipolar characteristics and a small inverse sub-threshold slope includes forming a local gate electrode beneath the nanotube between drain and source electrodes of the transistor and doping portions of the nanotube. In a further embodiment, the method includes forming at least one trench in the gate dielectric (e.g., a back gate dielectric) and back gate adjacent to the local gate electrode. Another aspect of the invention is a nanotube field-effect transistor fabricated using such a method. | 2010-07-08 |
20100173463 | LATERAL DOUBLE DIFFUSED METAL OXIDE SEMICONDUCTOR - A lateral double diffused metal oxide semiconductor (LDMOS) transistor to allow an electric current to smoothly flow from a source to a drain. | 2010-07-08 |
20100173464 | Non-volatile memory structure and method of fabrication - A method for creating a non-volatile memory array includes implanting pocket implants in a substrate at least between mask columns of a given width and at least through an ONO layer covering the substrate, generating increased-width polysilicon columns from the mask columns, generating bit lines in the substrate at least between the increased-width polysilicon columns and depositing oxide at least between the polysilicon columns. | 2010-07-08 |
20100173465 | SEMICONDUCTOR DEVICE HAVING SILICIDE TRANSISTORS AND NON-SILICIDE TRANSISTORS FORMED ON THE SAME SUBSTRATE AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes a first MIS transistor of a non-salicide structure and a second MIS transistor of a salicide structure which are both formed on a substrate of silicon. The first MIS transistor includes a first gate electrode of silicon, first sidewalls, a first source and drain, and plasma reaction films grown in a plasma atmosphere to cover the top surfaces of the first gate electrode and first source and drain, wherein the plasma reaction film prevents silicide formation on the first MIS transistor. | 2010-07-08 |
20100173466 | METHOD FOR FABRICATING A SEMICONDUCTOR DEVICE - A method for fabricating a semiconductor device includes providing a substrate sequentially having a polysilicon layer and an insulating layer formed thereon; patterning the polysilicon layer and the insulating layer to form at least a gate structure on the substrate; forming lightly doped regions in the substrate respectively at two side of the gate structure; forming a spacer on a sidewall of the gate structure; forming barrier layers respectively on a top surface of the gate structure and surfaces of the substrate at two sides of the spacer, and forming a source/drain in the substrate respectively at two sides of the spacer. | 2010-07-08 |
20100173467 | THIN FILM AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD USING THE THIN FILM - A thin film is used in a semiconductor device manufacturing process. The thin film contains silicon, germanium, and oxygen. | 2010-07-08 |
20100173468 | PASSIVE ELEMENTS, ARTICLES, PACKAGES, SEMICONDUCTOR COMPOSITES, AND METHODS OF MANUFACTURING SAME - Systems and methods associated with semiconductor articles are disclosed, including forming a first layer of material on a substrate, etching trenches within regions defining a passive element in the first layer, forming metal regions on sidewalls of the trenches, and forming a region of dielectric or polymer material over or in the substrate. Moreover, an exemplary method may also include forming areas of metal regions on the sidewalls of the trenches such that planar strip portions of the areas form electrically conductive regions of the passive element(s) that are aligned substantially perpendicularly with respect to a primary plane of the substrate. Other exemplary embodiments may comprise various articles or methods including capacitive and/or inductive aspects, Titanium- and/or Tantalum-based resistive aspects, products, products by processes, packages and composites consistent with one or more aspects of the innovations set forth herein. | 2010-07-08 |
20100173469 | METHODS OF MANUFACTURING CHARGE TRAP-TYPE NON-VOLATILE MEMORY DEVICES - Some methods are directed to manufacturing charge trap-type non-volatile memory devices. An isolation layer pattern can be formed that extends in a first direction in a substrate. A recess unit is formed in the substrate by recessing an exposed surface of the substrate adjacent to the isolation layer pattern. A tunnel insulating layer and a charge trap layer are sequentially formed on the substrate. The tunnel insulating layer and the charge trap layer are patterned to form an isolated island-shaped tunnel insulating layer pattern and an isolated island-shaped charge trap layer pattern by etching defined regions of the substrate, the isolation layer pattern, the tunnel insulating layer, and the charge trap layer until a top surface of the charge trap layer that is disposed on a bottom surface of the recess unit is aligned with a top surface of the isolation layer pattern. A blocking insulating layer is formed that covers the charge trap layer pattern, the isolation layer pattern, and a defined region of the substrate interposed between the charge trap patterns. A gate electrode pattern is formed on the blocking insulating layer to face the charge trap layer pattern. This manufacturing process may reduce charge spreading between unit memory cells and/or may prevent/avoid reduction in the breakdown voltage of the blocking insulating layer. | 2010-07-08 |
20100173470 | Methods of forming a silicon oxide layer and methods of forming an isolation layer - In a method of forming a silicon oxide layer, a spin-on-glass (SOG) layer may be formed on an object including a recess using an SOG composition. The SOG layer may be pre-baked and then cured by contacting with at least one material selected from the group consisting of water, a basic material and an oxidant, under a pressure of from about 1.5 atm to about 100 atm. The cured SOG layer may be baked. | 2010-07-08 |
20100173471 | NONVOLATILE SEMICONDUCTOR MEMORY AND FABRICATION METHOD FOR THE SAME - A nonvolatile semiconductor memory includes a memory cell transistor including a first floating gate electrode layer formed on a first tunneling insulating film, a first inter-gate insulating film, a first and a second control gate electrode layer, and a first metallic silicide film; a high voltage transistor including a high voltage gate electrode layer formed on the high voltage gate insulating film, a second inter-gate insulating film having an aperture, a third and a fourth control gate electrode layer, and a second metallic silicide film; a low voltage transistor including a second floating gate electrode layer formed on the second tunneling insulating film, a third inter-gate insulating film having an aperture, a fifth and a sixth control gate electrode layer, and a third metallic silicide film; and a liner insulating film directly disposed on a first source and drain region of the memory cell transistor, a second source and drain region of the low voltage transistor, and a third source and drain region of the high voltage transistor. | 2010-07-08 |
20100173472 | METHOD FOR MANUFACTURING SOI SUBSTRATE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method for manufacturing an SOI substrate and a method for manufacturing a semiconductor device, in each of which peeling of a single crystal semiconductor layer from an end portion due to laser irradiation is suppressed, are provided. A fragile region is formed in a single crystal semiconductor substrate by irradiating the single crystal semiconductor substrate with an accelerated ion, the single crystal semiconductor substrate is bonded to a base substrate with an insulating layer interposed therebetween, a single crystal semiconductor layer is formed over the base substrate with the insulating layer interposed therebetween by splitting the single crystal semiconductor substrate at the fragile region, an end portion of the single crystal semiconductor layer is removed, and a surface of the single crystal semiconductor layer whose end portion has been removed is irradiated with a laser beam. | 2010-07-08 |
20100173473 | METHOD FOR MANUFACTURING SOI SUBSTRATE AND SEMICONDUCTOR DEVICE - It is an object of the present invention to provide a method for manufacturing an SOI substrate having an SOI layer that can be used in practical applications with high yield even when a flexible substrate such as a glass substrate or a plastic substrate is used. Further, it is another object of the present invention to provide a method for manufacturing a thin semiconductor device using such an SOI substrate with high yield. When a single-crystal semiconductor substrate is bonded to a flexible substrate having an insulating surface and the single-crystal semiconductor substrate is separated to manufacture an SOI substrate, one or both of bonding surfaces are activated, and then the flexible substrate having an insulating surface and the single-crystal semiconductor substrate are attached to each other. | 2010-07-08 |
20100173474 | METHOD OF MANUFACTURING SEMICONDUCTOR CHIP - In a method in which a semiconductor wafer | 2010-07-08 |
20100173475 | Method for Improving the Quality of a SiC Crystal - A method for improving the quality of a SiC layer by effectively reducing or eliminating the carrier trapping centers in the as-grown SiC crystal. The method includes the steps of: (a) carrying out ion implantation of carbon atoms, silicon atoms, hydrogen atoms, or helium atoms into a shallow surface layer of the SiC crystal layer to introduce carbon interstitials into the surface layer, and (b) growing the SiC layer upward from the edge face of the surface layer into which the carbon interstitials have been introduced, and diffusing out the carbon interstitials that have been introduced into the surface layer from the surface layer into the grown layer and combining the carbon interstitials and point defects to make the electrically active point defects in the grown layer inactive. | 2010-07-08 |
20100173476 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device according to the invention irradiates a first pulse laser beam with an irradiation energy density of 1.0 J/cm | 2010-07-08 |
20100173477 | Method of Manufacturing Semiconductor Device and Semiconductor Manufacturing Apparatus - A cause of deteriorating the hydrogen termination on the surface of a wafer is found to be water adsorbed on the surface. By exposing the wafer to an inert gas atmosphere containing an H | 2010-07-08 |
20100173478 | CONCENTRIC GATE NANOTUBE TRANSISTOR DEVICES - Single-walled carbon nanotube transistor devices, and associated methods of making such devices include a porous structure for the single-walled carbon nanotubes. The porous structure may be anodized aluminum oxide or another material. Electrodes for source and drain of a transistor are provided at opposite ends of the single-walled carbon nanotube devices. A concentric gate surrounds at least a portion of a nanotube in a pore. A transistor of the invention may be especially suited for power transistor or power amplifier applications. | 2010-07-08 |
20100173479 | VARIABLE RESISTANCE MEMORY DEVICES AND METHODS OF FORMING VARIABLE RESISTANCE MEMORY DEVICES - Provided are variable resistance memory devices and methods of forming the variable resistance memory devices. The methods can include forming an etch stop layer on an electrode, forming a molding layer on the etch stop layer, forming a recess region including a lower part having a first width and an upper part having a second width by recessing the etch stop layer and the molding layer, and forming a layer of variable resistance material in the recess region. | 2010-07-08 |
20100173480 | LASER ANNEALING APPARATUS AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD - This invention is intended to provide a laser annealing method by employing a laser annealer lower in running cost so as to deal with a large-sized substrate, for preventing or decreasing the generation of a concentric pattern and to provide a semiconductor device manufacturing method including a step using the laser annealing method. While moving a substrate at a constant rate between 20 and 200 cm/s, a laser beam is radiated aslant to a semiconductor film on a surface of the semiconductor substrate. Therefore, it is possible to radiate a uniform laser beam to even a semiconductor film on a large-sized substrate and to thereby manufacture a semiconductor device for which the generation of a concentric pattern is prevented or decreased. By condensing a plurality of laser beams into one flux, it is possible to prevent or decrease the generation of a concentric pattern and to thereby improve the reliability of the semiconductor device. | 2010-07-08 |
20100173481 | LASER MASK AND CRYSTALLIZATION METHOD USING THE SAME - A crystallization method using a mask includes providing a substrate having a semiconductor layer; positioning a mask over the substrate, the mask having first, second and third blocks, each block having a periodic pattern including a plurality of transmitting regions and a blocking region, the periodic pattern of the first block having a first position, the periodic pattern of the second block having a second position, the periodic pattern of the third block having a third position, the first, second and third positions being different from each other; and crystallizing the semiconductor layer by irradiating a laser beam through the mask. | 2010-07-08 |
20100173482 | METHOD AND APPARATUS FOR FABRICATING IB-IIIA-VIA2 COMPOUND SEMICONDUCTOR THIN FILMS - Methods and apparatus for fabricating IB-IIIA-VIA | 2010-07-08 |
20100173483 | GaN SINGLE-CRYSTAL SUBSTRATE, NITRIDE TYPE SEMICONDUCTOR EPITAXIAL SUBSTRATE, NITRIDE TYPE SEMICONDUCTOR DEVICE, AND METHODS OF MAKING THE SAME - The GaN single-crystal substrate | 2010-07-08 |
20100173484 | SAFE HANDLING OF LOW ENERGY, HIGH DOSE ARSENIC, PHOSPHORUS, AND BORON IMPLANTED WAFERS - A method of preventing toxic gas formation after an implantation process is disclosed. Certain dopants, when implanted into films disposed on a substrate, may react when exposed to moisture to form a toxic gas and/or a flammable gas. By in-situ exposing the doped film to an oxygen containing compound, dopant that is shallowly implanted into the layer stack reacts to form a dopant oxide, thereby reducing potential toxic gas and/or flammable gas formation. Alternatively, a capping layer may be formed in-situ over the implanted film to reduce the potential generation of toxic gas and/or flammable gas. | 2010-07-08 |
20100173485 | Method of manufacturing a non-volatile memory device - A method of manufacturing a non-volatile memory device providing a semiconductor layer in which a cell region and a peripheral region are defined, sequentially forming a first insulating layer, a first conductive layer, a second insulating layer, and a second conductive layer on the cell region and the peripheral region, forming a trench for exposing a portion of the first conductive layer of the peripheral region, wherein the trench is formed by removing portions of the second conductive layer and the second insulating layer in the peripheral region, performing a trimming operation for removing portions of the second conductive layer and the second insulating layer of the cell region, forming a spacer on a side surface of the trench, and forming a silicide layer that is electrically connected to the first conductive layer, wherein the silicide layer is formed by performing a silicidation process on the spacer. | 2010-07-08 |
20100173486 | SEMICONDUCTOR DEVICE WITH MUSHROOM ELECTRODE AND MANUFACTURE METHOD THEREOF - A semiconductor device has: a semiconductor substrate having a pair of current input/output regions via which current flows; an insulating film formed on the semiconductor substrate and having a gate electrode opening; and a mushroom gate electrode structure formed on the semiconductor substrate via the gate electrode opening, the mushroom gate electrode structure having a stem and a head formed on the stem, the stem having a limited size on the semiconductor substrate along a current direction and having a forward taper shape upwardly and monotonically increasing the size along the current direction, the head having a size expanded stepwise along the current direction, and the stem contacting the semiconductor substrate in the gate electrode opening and riding the insulating film near at a position of at least one of opposite ends of the stem along the current direction. | 2010-07-08 |
20100173487 | Semiconductor apparatus and method of manufacturing the semiconductor apparatus - A semiconductor apparatus wherein a device formed on a semiconductor substrate comprises a gate insulating film including a high dielectric constant film formed on the substrate and an anti-reaction film formed on the high dielectric constant film, and a gate electrode formed on the anti-reaction film, the high dielectric constant film comprises a film containing at least one of Hf and Zr, and Si and O, or a film containing at least one of Hf and Zr, and Si, O and N, the anti-reaction film comprises an SiO | 2010-07-08 |
20100173488 | NON-VOLATILE MEMORY WITH ERASE GATE ON ISOLATION ZONES - The present invention provides a non-volatile memory device and a method for manufacturing such a device. The device comprises a floating gate ( | 2010-07-08 |
20100173489 | METHOD FOR MANUFACTURING LOWER SUBSTRATE OF LIQUID CRYSTAL DISPLAY DEVICE - A method for manufacturing a lower substrate of a liquid crystal display device is disclosed. The method comprises the steps of: (a) forming a patterned first metal layer, a first insulating layer, a patterned second metal layer and a second insulating layer on a substrate in sequence; (b) coating a transparent electrode layer and a negative photo resist layer on the second insulating layer; (c) irradiating the photo resist layer from the second surface of the substrate; (d) irradiating the photo resist layer from the first surface of the substrate, wherein part of the photo resist layer superposed over the second metal layer is covered by a mask; and (e) removing un-reacted photo resist and patterning the transparent electrode. | 2010-07-08 |
20100173490 | HIGH DENSITY PLASMA CHEMICAL VAPOR DEPOSITION PROCESS - A method for depositing dielectric material into gaps between wiring lines in the formation of a semiconductor device includes the formation of a cap layer and the formation of gaps into which high density plasma chemical vapor deposition (HDPCVD) dielectric material is deposited. First and second antireflective coatings may be formed on the wiring line layer, the first and second antireflective coatings being made from different materials. Both antireflective coatings and the wiring line layer are etched through to form wiring lines separated by gaps. The gaps between wiring lines may be filled using high density plasma chemical vapor deposition. | 2010-07-08 |
20100173491 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE - A method of forming an insulating layer on an conductive layer; forming a first mask layer and a second mask layer on the insulating layer; forming a resist layer on the second mask layer; patterning the resist layer; patterning the second mask layer by using the resist layer as a mask; etching the first mask layer halfway through its thickness by using the resist layer and the second mask layer as a mask; removing the resist layer; etching a remaining portion of the first mask layer using the second mask layer as a mask; forming an interconnect groove by etching the insulating layer using the first mask layer as a mask; and forming an electrically conductive material into the interconnect groove, thereby forming an interconnect layer connected to the conductive layer. | 2010-07-08 |
20100173492 | METHOD OF FORMING SEMICONDUCTOR DEVICE PATTERNS - Provided is a method of forming patterns of a semiconductor device, whereby patterns having various widths can be simultaneously formed, and pattern density can be doubled by a double patterning process in a portion of the semiconductor device. In the method of forming patterns of a semiconductor device, a first mold mask pattern and a second mold mask patter having different widths are formed on a substrate. A pair of first spacers covering both sidewalls of the first mold mask pattern and a pair of second spacers covering both sidewalls of the second mold mask pattern are formed. The first mold mask pattern and the second mold mask pattern are removed, and a wide-width mask pattern covering the second spacer is formed. A lower layer is etched using the first spacers, the second spacers, and the wide-width mask pattern as an etch mask. | 2010-07-08 |
20100173493 | SUBSTRATE PROCESSING METHOD - The present invention provides a substrate processing method to process a substrate including at least a process layer, an intermediate layer, and a mask layer which are stacked in this order. The mask layer includes an aperture configured to expose a portion of the intermediate layer. The substrate processing method includes a material deposition step of depositing a material on a side surface of the aperture and exposing a portion of the process layer by etching the exposed portion of the intermediate layer by plasma generated from a deposit gas, and an etching step of etching the exposed portion of the process layer. | 2010-07-08 |
20100173494 | Method and apparatus for anisotropic etching - We suggest a method of anisotropic etching of the substrates, where ultra-thin and conformable layers of materials are used to passivate sidewalls of the etched features. According to an exemplary embodiment such sidewall passivation layer is a Self-assembled monolayer (SAM) material deposited in-situ etching process from a vapor phase. According to another exemplary embodiment such sidewall passivation layer is an inorganic-based material deposited using Atomic Layer Deposition (ALD) method. SAM or ALD layers deposition can be carried out in a pulsing regime alternating with an sputtering and/or etching processes using process gasses with or without plasma. Alternatively, SAM deposition process is carried out continuously, while etch or sputtering process turns on in a pulsing regime. Alternatively, SAM deposition process and etch or sputtering processes are carried out continuously. Both types of suggested passivation materials give advantage over state-of-the-art methods in ability to carefully control thickness and uniformity of the layers, thus enable anisotropic etching process for high aspect ratio nanosize features. | 2010-07-08 |
20100173495 | SUBSTRATE PROCESSING APPARATUS USING A BATCH PROCESSING CHAMBER - Aspects of the invention include a method and apparatus for processing a substrate using a multi-chamber processing system (e.g., a cluster tool) adapted to process substrates in one or more batch and/or single substrate processing chambers to increase the system throughput. In one embodiment, a system is configured to perform a substrate processing sequence that contains batch processing chambers only, or batch and single substrate processing chambers, to optimize throughput and minimize processing defects due to exposure to a contaminating environment. In one embodiment, a batch processing chamber is used to increase the system throughput by performing a process recipe step that is disproportionately long compared to other process recipe steps in the substrate processing sequence that are performed on the cluster tool. In another embodiment, two or more batch chambers are used to process multiple substrates using one or more of the disproportionately long processing steps in a processing sequence. Aspects of the invention also include an apparatus and method for delivering a precursor to a processing chamber so that a repeatable ALD or CVD deposition process can be performed. | 2010-07-08 |
20100173496 | PROFILE AND CD UNIFORMITY CONTROL BY PLASMA OXIDATION TREATMENT - A method of forming spacers from a non-silicon oxide, silicon containing spacer layer with horizontal surfaces and sidewall surfaces over a substrate is provided. A plasma oxidation treatment is provided to form a silicon oxide coating over the spacer layer, wherein the silicon oxide coating provides a horizontal coating on the horizontal surfaces and sidewall coatings on the sidewall surfaces of the spacer layer. An anisotropic main etch that selectively etches horizontal surfaces of the spacer layer and silicon oxide coating with respect to sidewall surfaces of the spacer layer and the sidewall coatings of the silicon oxide coating is provided. The spacer layer is etched, wherein the sidewall coatings of the silicon oxide coating protect sidewall surfaces of the spacer layer. | 2010-07-08 |
20100173497 | Method of fabricating semiconductor integrated circuit device - A method manufacturing a semiconductor integrated circuit device includes providing a substrate; sequentially forming a layer to be etched, a first layer, and a second layer on the substrate; forming on the first and second layers a first etch mask having a plurality of first line patterns separated from each other by a first pitch and extending in a first direction; sequentially performing first etching on the second layer and the first layer using the first etch mask to form an intermediate mask pattern with second and first patterns; forming on the intermediate mask pattern a second etch mask including a plurality of second line patterns separated from each other by a second pitch and extending in a second direction other than the first direction; performing second etching using the second etch mask on a portion of the second pattern so that the remaining portion of the second pattern is left on the first pattern; performing third etching using the second etch mask under different conditions than the second etching on the first pattern and the remaining portion of second pattern of the intermediate mask pattern and forming a final mask pattern; and patterning the layer to be etched using the final mask pattern. | 2010-07-08 |
20100173498 | TRIM PROCESS FOR CRITICAL DIMENSION CONTROL FOR INTEGRATED CIRCUITS - Methods of etching substrates employing a trim process for critical dimension control for integrated circuits are disclosed. In one embodiment, the method of etching includes providing a first hard mask layer over a target layer; providing a second hard mask layer over the first hard mask layer; providing a photoresist layer over the second hard mask layer; forming a pattern in the photoresist layer; transferring the pattern into the second hard mask layer; and trimming the second hard mask layer with the photoresist layer on top of the second hard mask layer. The top surface of the second hard mask layer is protected by the photoresist and the substrate is protected by the overlying first hard mask layer during the trim etch, which can therefore be aggressive. | 2010-07-08 |
20100173499 | LOW K DIELECTRIC SURFACE DAMAGE CONTROL - A method of removing a silicon nitride or a nitride-based bottom etch stop layer in a copper damascene structure by etching the bottom etch stop layer is disclosed, with the method using a high density, high radical concentration plasma containing fluorine and oxygen to minimize back sputtering of copper underlying the bottom etch stop layer and surface roughening of the low-k interlayer dielectric caused by the plasma. | 2010-07-08 |
20100173500 | SEMICONDUCTOR WAFER STRUCTURE WITH BALANCED REFLECTANCE AND ABSORPTION CHARACTERISTICS FOR RAPID THERMAL ANNEAL UNIFORMITY - Disclosed are embodiments of semiconductor wafer structures and associated methods of forming the structures with balanced reflectance and absorption characteristics. The reflectance and absorption characteristics are balanced by manipulating thin film interferences. Specifically, thin film interferences are manipulated by selectively varying the thicknesses of the different films. Alternatively, reflectance and absorption characteristics can be balanced by incorporating an additional reflectance layer into the wafer structure above the substrate. | 2010-07-08 |
20100173501 | SEMICONDUCTOR DEVICE PRODUCING METHOD - Disclosed is a producing method of a semiconductor device, including: loading at least one substrate formed on a surface thereof with a tungsten film into a processing chamber; and forming a silicon oxide film on the surface of the substrate which includes the tungsten film by alternately repeating following steps a plurality of times: supplying the processing chamber with a first reaction material including a silicon atom while heating the substrate at 400° C.; and supplying the processing chamber with hydrogen and water which is a second reaction material while heating the substrate at 400° C. at a ratio of the water with respect to the hydrogen of 2×10 | 2010-07-08 |
20100173502 | LOW k1 HOLE PRINTING USING TWO INTERSECTING FEATURES - A method of forming one or more features during semiconductor device fabrication can comprise exposing a photosensitive layer to a first pattern at an exposure energy which is insufficient to fully expose the photosensitive layer, then exposing the photosensitive layer to a second pattern at an exposure energy which is insufficient to fully expose the photosensitive layer At an intersection of the first and second patterns, the energy does received during the first and second exposure is sufficient to fully expose the photosensitive layer. | 2010-07-08 |
20100173503 | TRAP CHARGE EQUALIZING METHOD AND THRESHOLD VOLTAGE DISTRIBUTION REDUCING METHOD - A method reduces a threshold voltage distribution in transistors of a semiconductor memory device, where each transistor includes a nitride liner. The method includes injecting electrons into a charge trap inside and outside the nitride liner of the transistors, and partially removing the electrons injected into the charge trap inside and outside the nitride liner to equalize trapped charges in the transistors. | 2010-07-08 |
20100173504 | END OF CAR JUNCTION BOX ASSEMBLY - An End of Car (EOC) junction box assembly includes a housing wherein a plurality of female/female contact sockets couple with a corresponding plurality of male contact pins and are positioned by a fitting that enables the female/female contact sockets to interface with an EOC receptacle plug also included in the housing body, such that alternate positions of the fitting and EOC receptacle plug are available during assembly while the components included in the housing body are restrained from rotation following assembly. | 2010-07-08 |
20100173505 | Topography compensating land grid array interposer - LGA connectors are fabricated with buttons or spring contacts preformed to different heights to accommodate the initial topography of a typical module or PCB of a particular product type. This is accomplished during fabrication by measuring topographies of mating surfaces of a first electronic device and of a second electronic device; fabricating interposer contacts to form opposing non-planar sides having respective inverse topographies for contacting the mating surfaces; and sandwiching the interposer between the first and second electronic devices with the opposing sides in contact with respective mating surfaces. For those LGA types made by molding techniques such as the metal-in-polymer type (eg. Tyco Electronics MPI, or Shin Etsu RP) or the Metal-on-Elastomer type (IBM), using molds with the desired topography provides the desired LGA topography. For those LGAs made of metal springs, cantilevers, armatures and the like, the desired topography is imposed by shaping of the buttons during or after fabrication using a sizing die with the desired topography. | 2010-07-08 |
20100173506 | Substrate Connector - A substrate connector utilizes a plurality of conductive terminals, each of which are held in a single terminal-receiving cavity of a substrate. The terminals of the connector have a hook-shape with a retention portions in the form of a fork having a central slot and two free ends spaced apart from the retention portion and which protrude out of their cavities for contacting contact pads on opposing circuit boards. The retention portions engage abutments formed in the cavities to hold the terminals in place but do so in a manner that permits the terminals to move in both the vertical and horizontal directions. | 2010-07-08 |
20100173507 | ELECTRICAL CONNECTOR HAVING MULTIPLE GROUND PLANES - An electrical connector includes a first row of contacts, a second row of contacts, a first ground plane, a second ground plane, each extending in a first direction. The first row of contacts is located closer to the first ground plane than any other ground plane in the electrical connector. The second row of contacts is located closer to the second ground plane than any other ground plane in the electrical connector. The first row of contacts, the second row of contacts, the first ground plane, and the second ground plane oppose each other such that the first row of contacts, the second row of contacts, the first ground plane, and the second ground plane are arranged with respect to each other in a second direction perpendicular or substantially perpendicular to the first direction. | 2010-07-08 |
20100173508 | ELECTRICAL RECEPTACLE FOR OUTWARD FACING GROUND PLUGS - A multiplex electrical receptacle adapted for receiving at least a pair of power cords, such that the ground prongs of the power cords are directed outward from the center of the multiplex electrical receptacle in a “grounds out” configuration. The electrical receptacle of this invention includes an electrical outlet receptacle having a receptacle body, a conductive mounting strap, a conductive live blade receiving assembly, a conductive neutral blade receiving assembly, and a nonconductive housing. | 2010-07-08 |
20100173509 | LOW INDUCTANCE CONNECTOR ASSEMBLY - A busbar connector assembly for coupling first and second terminals on a two-terminal device to first and second contacts on a power module is provided. The first terminal resides proximate the first contact and the second terminal resides proximate the second contact. The assembly comprises a first bridge having a first end configured to be electrically coupled to the first terminal, and a second end configured to be electrically coupled to the second contact, and a second bridge substantially overlapping the first bridge and having a first end electrically coupled to the first contact, and a second end electrically coupled to the second terminal. | 2010-07-08 |
20100173510 | Sealable Squib Connector System - The invention relates to sealable squib connectors, in particular for airbag ignition systems. The connector including a connector housing with a plug-in projection, which plug-in projection has a mating face at its distal end; a seal expansion element; and a resilient sealing ring provided at the mating face of the plug-in projection between the mating face and the seal expansion element. The seal expansion element is being movable against the mating direction towards the mating face from an open position to a closed position thereby expanding the sealing ring. | 2010-07-08 |
20100173511 | Junction Box in Connecting Box for a Solar Module - A connection and junction box for a photovoltaic solar module having flexible flat conductor bands protruding from the surface of the solar module, wherein the connection and junction box has an insertion mouth at its side in mounting state facing the solar module, for at least one of the flexible flat conductor bands of the solar module, as well as comprising a housing for attaching to the solar module, and a connection device for the flexible flat conductor band, positioned in the housing, the connection device has a deflection arm and an electrical contact clamp, which is actuated when attaching the box to the solar module for bending and contacting the flat conductor band. | 2010-07-08 |
20100173512 | High power, single pole electrical connector - A high-power, single-pole electrical connector is disclosed. A nonconductive mounting base is used to attach the connector to an electrical distribution panel. The connector extending from the panel has a bolted together connection that is safe and secure. Other connectors of this type use a pin-and-collet configuration. The bolted together connection of the present invention may provide additional security over a pin-and-collet design. | 2010-07-08 |
20100173513 | Plug-In Connector - A plug-in connector is provided that can be released easily and reliably from an assigned mating connector, and has increased lifetime. The plug-in connector includes a plug head and a sliding sleeve. The plug head has a hollow body with at least one cable connector, and at least two locks located on at least one surface of the body. The locks are connected by a bridge, and extend in a sliding direction. Each lock includes at least one free end. The sliding sleeve includes an opening to receive the plug head in a sliding direction and is movable in an axial direction relative to the plug head. An unlocking element is located on an inner side of the opening and positioned to contact the bridge of the plug head. The unlocking element pushes against the locks when the sliding sleeve moves in the sliding direction. | 2010-07-08 |
20100173514 | CONVERTER - A converter has a casing and a plug. The casing has a mounting recess, an engaging tab and multiple mounting protrusions. The mounting recess is formed in the casing. The engaging tab is formed on and protrudes from the mounting recess. The mounting protrusions are formed on the mounting recess. The plug is detachably mounted on the casing and has an escutcheon, an engaging protrusion, multiple terminals and a pinhole. The escutcheon covers the mounting recess. The engaging protrusion is formed on the escutcheon, is mounted in the mounting recess and has an engaging hole and multiple holding grooves. The engaging hole is formed in the engaging protrusion to engage the engaging tab. The holding grooves are formed on the engaging protrusion and engage the mounting protrusions. The terminals are formed on the escutcheon. The pinhole is formed through the escutcheon and communicates with the engaging hole. | 2010-07-08 |
20100173515 | ELECTRICAL CONNECTOR - A pivoting electrical connector includes a base and housing. The base has a cavity and base partitions to receive at least two conductors. The housing is operative to pivotally connect to said base and is adapted to rotate about an axis of rotation to allow insertion of one or more conductors into said cavity and to twist the conductors into electrical contact when the housing is pivoted. The electrical connector is operative to twist one or more conductors safely within the housing. | 2010-07-08 |
20100173516 | TERMINAL BLOCK AND CONTACT ELEMENT FOR TELECOMMUNICATIONS AND DATA SYSTEMS - The invention relates to a terminal block ( | 2010-07-08 |
20100173517 | MEMORY CARD FOR AN EXPRESSCARD SLOT - A memory card is disclosed resembling a CompactFlash card, but which is compatible with an ExpressCard slot. | 2010-07-08 |
20100173518 | CONNECTOR - A connector includes contacts each having a contact portion, an elastic portion and a fulcrum portion between the contact portion and a connection portion, and a pressure receiving portion; a housing fixing the contacts; and a slider having urging portions pivotally moved between the connection and pressure receiving portions of the contacts to urging the contact portions against the circuit board, thereby achieving reliable connection and miniaturization of the connector. In an aspect, the housing is formed on the side of a board insertion opening with a recessed portion for conducting the board. In another aspect, the contact includes upper and lower contact portions one above the other arranged alternately staggered so as to be connected to a circuit board having contact portions alternately staggered, so that no defective connection occurs, even if the circuit board is inserted erroneously upside down. In a further aspect, the connector further includes locking members having an engaging portion which engages an anchoring portion of the circuit board to prevent the circuit board from being removed. In one aspect, contacts of two kinds are inserted into the housing from opposite sides, respectively so that these contacts of the two kinds are into contact with the contact portions on respective surfaces of the circuit board. In a further aspect, moreover, a plate-shaped piece is provided in opposition to the contact portions of the contacts to prevent the housing from being deformed. | 2010-07-08 |
20100173519 | Battery-Operated Appliances - Battery operated appliances are provided. Some appliances include a housing defining a chamber having an interior wall, electronics within the chamber, a battery cover, and a closing system including (a) a first electrically conductive member secured to the battery cover, and (b) a second electrically conductive member secured to the interior wall of the housing and configured to engage the first electrically conductive member and thereby mechanically secure the battery cover to the housing while also establishing electrical contact between the first and second electrically conductive members. | 2010-07-08 |
20100173520 | PANEL CONNECTOR ASSEMBLY - A panel connector assembly includes a panel, a panel connector and a mounting bracket. The panel has opposing front and rear sides and includes a connector opening and a securing hole extending through the panel. The panel connector is disposed proximate to the panel and has a mating face aligned with the connector opening in the panel. The panel connector is positioned to couple with a peripheral connector that mates with the mating face through the front side of the panel. The mounting bracket is disposed proximate to the rear side of the panel. The mounting bracket receives a securing feature of the peripheral connector that extends through the securing hole in the panel to the mounting bracket when the peripheral connector and panel connector mate with one another. The mounting bracket receives the securing feature to secure the peripheral connector to the front, side of the panel. | 2010-07-08 |
20100173521 | STEP UP PIN FOR COAX CABLE CONNECTOR - A coaxial cable connector includes a step up pin that engages the center conductor of a coax cable to increase the diameter of the center conductor to thereby make it more manageable. The pin is stored with the connector until the pin and connector are affixed to a coax cable. | 2010-07-08 |
20100173522 | ADAPTER FOR A COAXIAL CABLE - An adapter for connecting a multi-core cable to a coaxial cable is provided. Adapters according to an exemplary embodiment of the present invention may be used in an arrangement comprising several adapters that are connected to each other using of a coaxial cable. Adapters and arrangements according to an exemplary embodiment of the present invention may allow a cost-effective conversion of existing mobile radio stations to modern RRH technology. | 2010-07-08 |
20100173523 | DUAL-DIRECTION CONNECTOR AND METHOD FOR CABLE SYSTEM - A connector for connecting a coaxial cable to a components box is disclosed, the connector is adapted to receive a central conductor of the coaxial cable and to firmly connect it to a central pin in the connector using a seizing force of a springy element, without needing to use a fastening screw or the like and without needing to open the component box. The connector of the invention is further adapted to allow releasing the central conductor from the central pin without needing to unfasten a screw or opening the component box. The connector is further adapted to facilitate the connection of the coaxial cable to the connector in another orientation similarly, without needing to use a fastening screw or the like and without needing to open the component box. | 2010-07-08 |
20100173524 | ELECTRICAL CONNECTOR WITH IMPROVED CONTACTS ARRANGEMENT - An electrical connector ( | 2010-07-08 |
20100173525 | STACK ABLE PATCH CABLE FOR SPLITTING AN ELECTRICAL SIGNAL - A stack able patch cable for splitting an electrical signal is described. The patch cable includes two plug members connected via a cable. Each plug member includes a male end and a female end. The male end has a male signal contact and a male shield contact electrically isolated from the male signal contact. The female end includes a female signal contact and a female shield contact electrically isolated from the female signal contact. Additionally, the female signal contact is electrically connected with the male signal contact and the female shield contact is electrically connected with the male shield contact. Further, the female end is configured to receive a male end of a plug to electrically connect the corresponding contacts. Thus, the plug member is capable of receiving and connecting directly with another plug member to split a signal while maintaining signal quality. | 2010-07-08 |
20100173526 | CONVERTER - A converter has a casing and a plug. The casing has a mounting recess, multiple position posts, multiple conductive slices and multiple mounting protrusions. The mounting recess is formed in the casing. The position posts are formed on and protrude from the mounting recess. The conductive slices are mounted around the position posts. The mounting protrusions are formed on the mounting recess. The plug is detachably mounted on the casing and has an escutcheon, an engaging protrusion and multiple terminals. The escutcheon covers the mounting recess. The engaging protrusion is formed on the escutcheon, is mounted in the mounting recess and has a position groove and multiple holding grooves. The position is annular formed in the engaging protrusion and is mounted around the position posts. The holding grooves are formed on the engaging protrusion and engage the mounting protrusions. The terminals are formed on the escutcheon. | 2010-07-08 |
20100173527 | CARD SOCKET ASSEMBLY AND PORTABLE ELECTRONIC DEVICE USING SAME - A card socket assembly includes a printed circuit board defining a cutout and a card socket mounted to the printed circuit board. The card socket is received in the cutout. | 2010-07-08 |