28th week of 2013 patent applcation highlights part 25 |
Patent application number | Title | Published |
20130176712 | DOCK LIGHTING - The present disclosure provides a dock lighting system. One or more embodiments include a power source attached to a first dock section, a first modular lighting group attached to the first dock section, wherein the first modular lighting group is electrically connected to the power source, and a second modular lighting group attached to a second dock section, wherein the second modular lighting group is electrically connected to the first modular lighting group. | 2013-07-11 |
20130176713 | FIREFIGHTER LIGHT APPARATUS AND METHODS - A flashlight includes a housing for receiving a battery; a first light supported by the housing, the first light configured to emit light in a first direction; a second light supported by the housing, the second light configured to emit light in a second direction that is non-parallel with the first direction; and an actuation switch configured for selectively powering the first light and the second light with the battery received in the housing. | 2013-07-11 |
20130176714 | Mountable Multi-Function Multi-Mode Marker/Signaling Device - A multi-mode, multi-function marker/signaling device, capable of detachably mounting to helmets, has operating switches with positive visual and tactile cues located at opposing ends. A cover is attached to a base to provide a waterproof internal space. An electronic circuit board mounted within the waterproof space includes one or more visible and/or infrared emitters. Built-in programming provides user-defined and selectable modes of operation and multiple functions within those modes by means of serial manipulation of each switching means with a single digit. The emitters are multi-colored and/or infrared devices operating either steady ON, flashing, or coded flash, and are programmed to operate either independently or together. A replaceable battery provides power. A battery compartment is integral to and accessed from the underside (mounting surface) of the base. | 2013-07-11 |
20130176715 | MULTI-FUNCTION TELESCOPIC FLASHLIGHT WITH UNIVERSALLY-MOUNTED PIVOTAL MIRROR - A telescopic flashlight that includes a universally adjustable mirror unit for reflecting the light of the lighting unit over a universal range, which mirror unit is readily and easily attached and detached from the distal end of the flashlight apparatus via a metallic mounting collar that is magnetically retained by means of an annular magnet affixed to the distal end of the apparatus, which mounting collar itself is rotatable relative to the distal end of the flashlight apparatus in order to provide two of the three degrees of freedom on motion of the mirror proper. | 2013-07-11 |
20130176716 | MOUNTING SYSTEM FOR RETROFIT LIGHT INSTALLATION INTO EXISTING LIGHT FIXTURES - Lighting retrofit systems and methods are disclosed that can be used with different light fixtures, but that are particularly adapted for use with retrofitting troffer-style fixtures with LED based light engines. The retrofit systems being assembled without disturbing the lighting or troffer pan or housing (“troffer pan”) for the lighting system being retrofitted. Some of these embodiments can comprise a mounting fixture or frame that can be mounted in an opening in a ceiling grid, and held in place between the grid and the troffer pan edge. The fixture or frame can comprise an opening for a light engine, with the engine being quickly and easily connected to electrical power in the troffer pan and then mountable within the frame opening. These embodiments can allow for the quick and easy construction of the retrofit system without the need for adhesives and fasteners such brackets and screws. | 2013-07-11 |
20130176717 | Detachable Cover Apparatus For Compact Fluorescent Light (CFL) Bulbs That Affects Illumination Clarity, Quality, and Color - This invention describes a makeup applicator device with a built-in, portable light source that can be moved closer to the point of makeup application while the makeup is being applied. (hereinafter “Makeup Applicator with Moveable Light Source”). This apparatus provides a small battery powered LED light source built into either the applicator wand itself or into the outside casing of the applicator device. The light source is brought closer to the application point by either moving the light source closer to the point where the makeup contacts the human subject, or alternatively by moving the applicator itself closer to a stationary light source. The movements described herein are accomplished either by a twist motion on the applicator cap or a small sliding mechanism built into the cap itself. | 2013-07-11 |
20130176718 | LUMINOUS CIRCUIT AND LUMINOUS DEVICE HAVING THE SAME - A luminous circuit and a luminous device having the same are provided. The luminous circuit may include a first conducting wire and a second conducting wire connected to a positive terminal and a negative terminal of a power supply, respectively. The luminous circuit may further include N light-emitting circuits electrically and sequentially coupled between the first conducting wire and the second conducting wire in a parallel connection fashion beginning from a location in proximity of the power supply. Each of the light-emitting circuits corresponds to a light-emitting element, and jth light-emitting element is better than ith light-emitting element in lighting efficiency, wherein 1≦i2013-07-11 | |
20130176719 | Tension Mounted Lighting System - A lighting system includes a longitudinal flexible metal strip which may be helically rolled, first and second clamps securing opposite ends of the metal strip to first and second selected locations, and a longitudinally extending strip with lights such as LEDs secured to one side of the longitudinal metal strip. The first and second clamps each include a clamp arm secured to a base by a ball and socket connection. | 2013-07-11 |
20130176720 | SEAMLESS CONNECTING SHELL AND LIGHTING DEVICE USING THE SAME - The present invention provides a shell for a lighting device. The shell comprises a first lamp body, a second lamp body, a first connecting part, and a second connecting part. The ends of the second lamp body have a first end surface and a second end surface. The first connecting part lying along a first direction is set in the first end surface and threads through the first bottom surface. The second connecting part lying along a direction opposite to the first direction is set in the second end surface and threads through the second bottom surface. When the first lamp body is connected with the second lamp body, the two ends of the first lamp body are disposed extending over edges of the first end surface and the second end surface separately. | 2013-07-11 |
20130176721 | LIGHT FIXTURE WITH TEXTURED REFLECTOR - A light fixture with a textured reflector is disclosed. Embodiments of the present invention provide for a lighting system in which LEDs face, and the majority of light form the LED light source is incident on, a textured back reflector while producing minimal glare and minimal imaging of the light source. Such a reflector may be referred to as a retro-reflector. The reflector for the light fixture can be made from a relatively inexpensive material such as polycarbonate, which without texturing has a specular or semi-specular surface. Further, a diffuse white layer to provide color mixing or prevent glare and reflections is not needed. The textured reflector can be textured by way of an imprinted pattern or by roughening, and can be extruded. A prismatic texture may be used. The texturing can also be spatially varied. | 2013-07-11 |
20130176722 | LIGHT FIXTURE WITH TEXTURED REFLECTOR - A light fixture with a textured reflector surface is disclosed. Embodiments of the present invention provide for a lighting system in which LEDs face, and the majority of light form the LED light source is incident on, a textured surface of a back reflector while producing minimal glare and minimal imaging of the light source. Such a reflector may be referred to as a retro-reflector. The reflector for the light fixture can be made from a relatively inexpensive material such as polycarbonate, which without texturing has a specular or semi-specular surface. This material can be used alone or with a metal substrate to form the reflector. The textured surface can be textured by way of an imprinted pattern or by roughening, and can be extruded. A prismatic texture may be used. The texturing can also be spatially varied. | 2013-07-11 |
20130176723 | SOLID-STATE LAMPS WITH IMPROVED RADIAL EMISSION AND THERMAL PERFORMANCE - A solid-state lamp is described that includes a first light emission zone and a second light emission zone, where the first light emission zone is longitudinally spaced apart from the second light emission zone. The light emission zones comprise a photoluminescence wavelength conversion component and a solid state light emitting device. The lamp comprises a lower body, a central body, and an upper duct, where the central body, and the upper duct together define at least one passageway/duct for thermal airflow. | 2013-07-11 |
20130176724 | SOLID-STATE LAMPS WITH IMPROVED RADIAL EMISSION AND THERMAL PERFORMANCE - A solid-state lamp is described that includes a wavelength conversion component located at one end of the lamp. The solid-state lamp comprises: one or more solid-state light emitting devices (typically LEDs); a thermally conductive body; at least one duct; and a photoluminescence wavelength conversion component remote to the one or more LEDs, located at one end of the lamp. The lamp is configured such that the duct extends through the photoluminescence wavelength conversion component and defines a pathway for thermal airflow through the thermally conductive body to thereby provide cooling of the body and the one or more LEDs. | 2013-07-11 |
20130176725 | DISPLAYS HAVING BUILT-IN MO RE REDUCTION STRUCTURES - Techniques and display devices that provide a built-in Moire reduction structure in a display screen are disclosed. The built-in Moire reduction structure is configured to suppress spatial frequencies that are associated with the sub-pixel level periodicities in the light emitted by the colored sub-pixels of the display screen, and hence, reduce the Moire patterns that might otherwise be produced when images presented on the display screen are captured by a digital image capturing device having a periodic light-sensing structure. The built-in Moire reduction structure is a blur layer placed on the viewer side of the screen and separated by a spacer layer from the pixel layer of the display screen. The blurring power of the blur layer is controlled to substantially preserve the pixel-level resolution of the display screen. | 2013-07-11 |
20130176726 | LED HEAT DISSIPATION DEVICE HAVING AXIAL AND RADIAL CONVECTION HOLES - The present invention provides a LED heat dissipation device having axial and radial convection holes for meeting the heat dissipation requirement of a light emitting diode (LED), so the heat dissipation device is not only equipped with a function of dissipating heat to the exterior through the surface of the heat dissipation device, but also provided with the air flowing capable of assisting heat dissipation through the hot airflow in a heat dissipation member having axial and radial convection holes ( | 2013-07-11 |
20130176727 | SEGMENTED SPOTLIGHT HAVING NARROW BEAM SIZE AND HIGH LUMEN OUTPUT - The invention relates to an optical module comprising two or more segments positioned around an axis of symmetry of the module. Each segment includes a light collimating structure for providing a predefined light distribution of light exiting the module and a light source assembled in a cavity within the light collimating structure. The center of the cavity coincides with the optical axis of the light collimating structure and is at a distance (d) from the axis of symmetry of the module. Including two or more segments where each segment comprises its own light source allows obtaining higher lumen output compared to prior art luminaires having only one light source while arranging the segments so that the center of each cavity coincides with the optical axis of the collimating structure of the segment allows preserving narrow beamwidth collimation of the light exiting the module. | 2013-07-11 |
20130176728 | Lighting Module - A lighting module ( | 2013-07-11 |
20130176729 | LENS STRUCTURE, LIGHT SOURCE DEVICE AND LIGHT SOURCE MODULE - A lens structure, a light source device, and a light source module are provided. The light source device includes a light emitting device and a lens structure. The light emitting device is capable of emitting a light beam. The lens structure includes a first surface, a second surface opposite to the first surface and four total internal reflection surfaces connected to the second surface. Some of the total internal reflection surfaces connect to the first surface. The first surface has a recess. The light emitting device is disposed at the recess. The second surface is a free-form surface. The light beam is capable of entering the lens structure through the first surface, and leaving the lens structure through the second surface. | 2013-07-11 |
20130176730 | LIGHT SOURCE APPARATUS - A light source apparatus includes an outer casing. A light source member and a light source module having a cooling body which cools the light source member are disposed in the outer casing. A wind tunnel which surrounds a heat pipe unit as the cooling body of the light source module is provided in the outer casing. The wind tunnel includes a wind passage which allows cooling wind to pass through the heat pipe unit. An intake-opening is formed in a surface of the outer casing, and cooling wind is taken into the outer casing from outside thereof through the intake-opening. One end of the wind passage of the wind tunnel is connected to the intake-opening. | 2013-07-11 |
20130176731 | LED Lamp - An LED lamp includes a housing, a base plate combined with the housing, and a plurality of LED crystals combined with the base plate. The LED crystals are connected serially, and a total allowable voltage of the LED crystals is equal to or greater than a voltage of an external power supply. The base plate is integrally combined with the housing completely by injection molding so that the base plate and the housing are combined closely and solidly and will not detach from each other. In addition, the LED lamp does not need provision of a drive device. | 2013-07-11 |
20130176732 | HOLDER AND LED MODULE USING SAME - A holder is provided that include a base with an aperture. An LED array with an LED emitter can be positioned so that the LED emitter is in the aperture. The holder includes pads that can be soldered to surface contacts on the LED array. The holder further includes contacts that are electrically connected to the pads. The pads and contacts can be provided by terminals that insert molded into the base. The base can include an integrated connector that has the contacts of the terminals extend therein. | 2013-07-11 |
20130176733 | LED LAMP - The LED lamp includes a heat dissipating base, an LED module, a hood and a sealant. The heat dissipating base has a mount board including a first surface and a second surface. The first and second surfaces are provided with an annular trough and fins, respectively. The LED module is fixed on the mount board and surrounded by the annular trough. The hood is formed with a flange which is embedded into the annular trough to cloak the LED module. The sealant is filled in the annular trough to seal up. | 2013-07-11 |
20130176734 | LIGHT HEAD - A light head ( | 2013-07-11 |
20130176735 | LIGHTING APPARATUS - A lighting apparatus using light-emitting diodes as the light source, which has light-dispersible property, heat dissipation property, excellent waterproof property, durability and shock resistance, giving no local glares, giving soft illumination, and can be used as a guiding light and a garden light, is provided. | 2013-07-11 |
20130176736 | Light Emitting Diode (LED) Lighting Assembly With Adjustable Pin Plug Housing - A light emitting diode (LED) lighting assembly with adjustable pin plug housing is provided for differing types of G4 fixtures with plug angles of 0 degrees, 10 degrees and 90 degrees. The angular adjustment of the light assembly allows lens cover to be reinstalled when in close proximity to other objects and provides a fixture looking normal in everyday use. Due to the limited space inside of the G4 fixture, the LED bulb can use a flexible copper ribbon heat sink attached to the backside of the LED circuit board that can be hidden into a recessed area inside the G4 fixture. | 2013-07-11 |
20130176737 | ELECTRONIC TEXTILE AND METHOD OF MANUFACTURING AN ELECTRONIC TEXTILE - A method of manufacturing an electronic textile ( | 2013-07-11 |
20130176738 | TRAVEL NIGHTLIGHT WITH USB CHARGER - A nightlight charger for charging an external electronic device is mountable to a common 120 volt AC wall outlet, and includes a power supply to convert the 120 volts AC to +5 volts DC, and a charging profile configuration circuit. A charging profile selection switch is provided for the user to select a desired charging profile that is compatible with the electronic device to be charged. The nightlight includes a housing having a side wall, a portion of which is translucent. A light emitting device within the housing emits light that passes though the translucent portion of the side wall. | 2013-07-11 |
20130176739 | FLEXIBLE PRINTED CIRCUIT FOR MOUNTING LIGHT EMITTING ELEMENT, AND ILLUMINATION APPARATUS INCORPORATING THE SAME - A flexible printed circuit for mounting a light emitting element has a base film, a wiring pattern formed on a surface of the base film, and a cover film that covers the base film and the wiring pattern. At least one of the base film and the cover film has a substrate comprising a metal. The cover film has such surface properties as to produce specular reflection or diffuse reflection of light or has a substantially white reflecting film on a surface of the cover film. | 2013-07-11 |
20130176740 | LENS DEVICE FOR FOCUSING OR DIFFUSING LIGHT BEAMS - A lens device for focusing or diffusing light beams includes a lens body having a flat sheet, a first convex lens extruded away from one end of the flat sheet, a second convex lens extruded away from another end of the flat sheet, the distance between an apex of the first convex lens and the center of the bottom of the first convex lens being larger than the distance between an apex of the second convex lens and the center of the bottom of the second convex lens. Although the surface of the first convex lens is not flawless after the compression molding and light beams cannot be refracted uniformly by the first convex lens, the second convex lens refracts the light beams for pre-adjusting before the light beams are refracted by the first convex lens. | 2013-07-11 |
20130176741 | LIGHT FLUX CONTROLLING MEMBER AND ILLUMINATION DEVICE - Light flux controlling member | 2013-07-11 |
20130176742 | Recessed Luminaire - In an embodiment, a luminaire may include a housing that includes a support panel, a rotation ring supported by the support panel where the rotation ring is infinitely adjustable with a range of adjustments with respect to the support panel, a rotation drive unit configured to rotate the rotation ring with respect to the support panel, an aiming frame supported by the rotation ring, a tray system pivotally mounted to the aiming frame and configured to receive the bulb, and a tray drive configured to rotate the tray system about the pivotal mounting, whereby, in operation the rotational and angular orientation of the bulb may be adjusted while the bulb is on. | 2013-07-11 |
20130176743 | LUMINAIRE MOUNTING INTERFACE - Disclosed is a luminaire mounting interface including an interface body configured for association with a luminaire, and an interface surface of the interface body, the interface surface including at least two association points separated by 75 mm to 142 mm. | 2013-07-11 |
20130176744 | PARTITIONED HEATSINK FOR IMPROVED COOLING OF AN LED BULB - A light-emitting diode (LED) bulb has a shell. An LED is within the shell. The LED is electrically connected to a driver circuit, which is electrically connected to a base of the LED bulb. The LED bulb also has a heatsink between the shell and base. A thermal break partitions the heatsink into an upper partition adjacent the shell and a lower partition adjacent the base. | 2013-07-11 |
20130176745 | ELECTRICAL CONNECTOR APPARATUS, LIGHTING DEVICE POSITIONING APPARATUS AND METHOD OF ELECTRICALLY CONNECTING APPARATUS - A lighting device, comprising a power input assembly engagement structure that comprises a keying region, an electrical connector region and a power input assembly engagement region. A power input assembly, comprising a second electrical connector region held by, a positioning element and a holding structure, the positioning element releasably engaged with the holding structure. A lamp comprising a power input assembly and a lighting device comprising an engagement structure. A method comprising engaging a second electrical connector region of a power input assembly with a first electrical connector region of a lighting device. A lighting device positioning apparatus, comprising a lighting device mounting region, a first slide member comprising a retaining structure-receiving feature and a first slot, a second slide member comprising a second slot extending in a direction differing 20 degrees from the first slot, and a connector extending through the first and second slots. | 2013-07-11 |
20130176746 | COMPONENT BUILT-IN MODULE, ELECTRONIC DEVICE INCLUDING SAME, AND METHOD FOR MANUFACTURING COMPONENT BUILT-IN MODULE - A component built-in module of the present invention includes: a flexible substrate that includes a first surface and a second surface on an opposite side of the first surface, the first surface including a concave part recessed in a direction from the first surface toward the second surface; a plurality of electronic components that are mounted on the first surface, mounting heights of the electronic components from the first surface to respective upper surfaces of the electronic components differing from each other; and a resin that seals the first surface. Among the plurality of electronic components, at least an electronic component having a highest mounting height is mounted in the concave part. | 2013-07-11 |
20130176747 | LAMP - A lamp has a body | 2013-07-11 |
20130176748 | MODULARIZED SERVER - A modularized illuminating device includes a retaining base, a lighting module, and a light guide element. The retaining base includes an elastic positioning unit. The lighting module is removably disposed on the retaining base, and has a sliding groove and a retaining groove. The light guide element is disposed on the retaining base and faces to the lighting module. When the lighting module is installed to the retaining base along a plugging direction, the elastic positioning unit slides from the sliding groove to the retaining groove to retain the lighting module in the retaining base. | 2013-07-11 |
20130176749 | DISPLAY DEVICE AND INPUT DEVICE WITH MULTI PATTERN LAYERS - The present invention discloses an input device with multi pattern layers including an input interface, a first light emitting element for generating a first light beam, a first light guiding plate, a second light emitting element for generating a second light beam, a second light guiding plate, a first circuit board and a second circuit board. The input interface is stacked on the first light guiding plate, and the first light guiding plate is stacked on the second light guiding plate, such that a first space and a second are formed individually at the two ends of the first light guiding plate and the second light guiding plate. The first circuit board and the second circuit board block the first light beam and the second light beam individually by inserting into the first space and the second space individually. | 2013-07-11 |
20130176750 | LIGHT EMITTING APPARATUS - A lighting apparatus comprising a plurality of diodes and an electrical interface configured to receive an electrical signal and transmit the electrical signal to the plurality of diodes is provided. | 2013-07-11 |
20130176751 | METHOD AND APPARATUS FOR CONTROLLING A FREQUENCY CONVERTER - An apparatus and method of controlling a frequency converter is provided. First, subsynchronous components in the electrical grid are identified using voltage measurements of the electrical grid. The subsynchronous components of the electrical grid are then used to determine set points for damping currents. These damping currents are then added to current set points calculated by power regulation loops to generate total current set points. Thereafter, the frequency converter is controlled based on the total current set points. | 2013-07-11 |
20130176752 | ADAPTIVE POWER CONVERSION SYSTEM - A power converter includes a plurality of switches electrically coupled to each other for converting input power to output power. Each of the switches is sufficiently isolated to protect adjacent switches upon failure of one or more switches. The power converter also includes a controller for reconfiguring operation of the switches to provide at least a partial operating mode upon a switch failure. | 2013-07-11 |
20130176753 | Three Phase Active Rectifier System - A voltage source inverter comprises a rectifier converting AC power to DC power at an output. An inverter receives DC power and converts the DC power to AC power. A link circuit is connected between the rectifier circuit and the inverter circuit and comprises a DC bus. A DC bus capacitor across the DC bus smoothes voltage ripple. An active filter circuit comprises a pair of filter capacitors in series across the first and second rails to create a midpoint. Bidirectional switches are connected between the rectifier input and the midpoint. A current sensor is connected between the bidirectional switches and the midpoint. An active switch controller controls a conduction angle of the bidirectional switches to maintain DC bus voltage at a desired reference level under a wide load range. | 2013-07-11 |
20130176754 | FILTERING REACTOR STAGE AND VARIABLE-FREQUENCY DRIVING SYSTEM UTILIZING THE SAME - A filtering reactor stage and a variable-frequency driving system utilizing the same are provided. The system includes a rectifier input stage, an inverter output stage and a filter reactor stage. The filter reactor stage is coupled between the rectifier input stage and the inverter output stage. The filter reactor stage includes a magnetic core module, a first winding set, a second winding set and a third winding set. The magnetic core module includes a middle pillar and two side pillars. The first second winding sets are wound around two side pillars respectively. The first winding second winding sets are coupled to a first DC (Direct Current) bridge between the rectifier input stage and the inverter output stage. The third winding set is wound around the middle pillar and coupled to a second DC bridge between the rectifier input stage and the inverter output stage. | 2013-07-11 |
20130176755 | DIMMER CONTROL WITH SOFT START OVER-CURRENT PROTECTION - This document discloses, among other things, apparatus and methods for dimmer control. In an apparatus example, a circuit can include an input configured to receive a control signal, a controller configured to modulate a pulse width of a pulse train using the control signal when the controller is enabled, an output configured to provide the pulse train to a driver, and first and second current limit detectors configured to receive load current information of the driver and to terminate an active pulse of the controller when a value of the load current information exceeds a threshold. | 2013-07-11 |
20130176756 | MULTIPHASE TRANSFORMER RECTIFIER UNIT - A multiphase transformer rectifier unit for converting a three-phase alternating current supplied from a power distribution system to direct current supplied to at least one load. The multiphase transformer rectifier unit includes a magnetic core having a primary winding set and secondary winding set, and a rectifier circuit. The secondary winding set is arranged to generate N substantially equally distributed output phases, wherein N is an odd number multiple of 3, and N>3, and the primary winding set ( | 2013-07-11 |
20130176757 | REACTIVE ENERGY COMPENSATOR AND ASSOCIATED METHOD FOR BALANCING HALF-BUS VOLTAGES - A reactive energy compensator that can be electrically connected to an AC electrical network, including at least one input direct voltage bus, at least one voltage inverter including switches and first and second capacitors having first and second voltages at their terminals, control means for the switches, including computation means capable of generating a target control current, means for combining the target control current and the output current from the inverter, means for transmitting a control signal capable of driving the switches, and correction means for the control signals of the switches, the correction means being capable of adding a balancing current to the target control current, the balancing current being able to correct the target control current so as to reduce the difference between the values of the first and second voltages, the target control current being increased for an even harmonic of the network frequency. | 2013-07-11 |
20130176758 | MOSFET BRIDGE RECTIFIER - A bridge rectifier is established by MOSFETs instead of diodes. The MOSFET bridge rectifier includes a voltage detector to detect the voltages of two AC input terminals of the MOSFET bridge rectifier, for identifying the positive and negative half cycles of an AC voltage input to the MOSFET bridge rectifier, thereby accurately controlling the MOSFETs. | 2013-07-11 |
20130176759 | FUEL CELL SYSTEM - A fuel cell system includes: a converter disposed between a fuel cell and a load to increase an output voltage of the fuel cell; and a control unit that controls the converter at a predetermined duty ratio, wherein the control unit determines a duty command value for the converter from a feed-forward duty and a feed-back duty which are calculated using a command value of a reactor current that flows through a reactor in the converter and/or using a measurement value of the reactor current. In a low-load operation, the control unit sets, as a measurement value of the reactor current, a value obtained by multiplying a midpoint measurement value measured at an intermediate time of an on-duty period by a predetermined coefficient. | 2013-07-11 |
20130176760 | POWER CONVERTION CIRCUIT USING HIGH-SPEED CHARACTERISICS OF SWITCHING DEVICES - A power conversion circuit converting DC electric power into AC electric power and sending the AC power to an inductive load, includes a first switching device connected to the DC power supply; a second switching device connected to the DC power supply; a first inductor provided between the first switching device and the inductive load; a second inductor provided between the second switching device and the inductive load; and a clamping diode connected between a first connection point between the first switching device and the first inductor, and a second connection point between the second switching device and the second inductor. When the first and second switching devices are turned off, a current flows through the second diode, clamping diode, first inductor and inductive load to completely flow out a current in the first inductor, and then a current flows through the second diode, second inductor and inductive load. | 2013-07-11 |
20130176761 | Power Conversion Device - A power conversion device comprises a power semiconductor device, first and second conductor plates joined to the power semiconductor device, first and second insulating member, a case made of metal which stores the components, and a channel-forming structure made of metal. Part of the case is fixed to the metallic channel-forming structure via a third insulating member. Leakage current caused by the switching operation of the power semiconductor device is transmitted to the channel-forming structure via a series circuit including parasitic capacitance of the first insulating member and/or parasitic capacitance of the second insulating member and parasitic capacitance of the third insulating member. | 2013-07-11 |
20130176762 | Three Level Inverter Modulation - An apparatus, system, and method for providing three level inverter modulation. In one embodiment, control signals can be provided to control a three level inverter in a power converter based on at least one feedback signal. | 2013-07-11 |
20130176763 | STACKED MEMORY WITH REDUNDANCY - A stacked memory is disclosed including a first integrated circuit memory chip having first storage locations and stacked with a second integrated circuit memory chip. A redundant memory is shared by the first and second integrated circuit memory chips and has redundant storage locations that selectively replace corresponding storage locations in the first or second integrated circuit memory chips. The stacked memory also includes a pin interface for coupling to an external integrated circuit memory controller and respective first and second signal paths. The first signal path is formed through the first and second integrated circuit memory chips and is coupled to the redundant memory and to the pin interface. The second signal path is formed through the first and second integrated circuit memory chips and is coupled to the redundant memory and to the pin interface via the first signal path. | 2013-07-11 |
20130176764 | SEMICONDUCTOR APPARATUS - A semiconductor apparatus includes a controller, a memory, a normal line, a test line, and a path setting unit. The normal line is provided for communication between the controller and the memory. The test line is provided for a test operation of the memory. The path setting unit connects either the normal line or the test line to the memory according to a type of access mode. | 2013-07-11 |
20130176765 | ONE-TIME PROGRAMABLE CELL CIRCUIT, SEMICONDUCTOR INTEGRATED CIRCUIT INCLUDING THE SAME, AND DATA JUDGING METHOD THEREOF - Provided is a semiconductor integrated circuit including: an anti-fuse element that electrically connects a first node and a first power supply terminal when data is written and electrically disconnect the first node and the first power supply terminal when data is not written; a first switch circuit that is connected between the first node and a first data line applied with a predetermine first voltage, and enters an off state from an on state according to a first control signal; and a detection part that detects write data of the anti-fuse element according to whether a voltage of the first node is substantially the same as the first voltage or substantially the same as a supply voltage of the first power supply terminal when the first switch circuit enters the off state. | 2013-07-11 |
20130176766 | STATEFUL NEGATIVE DIFFERENTIAL RESISTANCE DEVICES - A stateful negative differential resistance device includes a first conductive electrode and a second conductive electrode. The device also includes a first material with a reversible, nonvolatile resistance that changes based on applied electrical energy and a second material comprising a differential resistance that is negative in a locally active region. The first material and second material are sandwiched between the first conductive electrode and second conductive electrode. A method for using a stateful NDR device includes applying programming energy to the stateful NDR device to set a state of the stateful NDR device to a predetermined state and removing electrical power from the stateful NDR device. Power-up energy is applied to the stateful NDR device such that the stateful NDR device returns to the predetermined state. | 2013-07-11 |
20130176767 | STORAGE ELEMENT READING USING RING OSCILLATOR - Methods and apparatus are provided for use with data storage elements. A ring oscillator is coupled to a selected element within an array such that a feedback loop is defined. A period at oscillation for the ring oscillator is compared to a reference value. A data value stored within the selected element is determined accordingly. Stored data values remain essentially unaltered when accessed and read by way of the ring oscillator. Memory arrays having memristor or other storage elements can be used according to the present teachings. | 2013-07-11 |
20130176768 | REPLACEMENT OF A FAULTY MEMORY CELL WITH A SPARE CELL FOR A MEMORY CIRCUIT - A memory integrated circuit device is provided. The device includes a plurality of regular address inputs and at least one spare address input configured for a selected mode or an unselected mode. The device includes a plurality of control inputs, a plurality of data inputs, and a plurality of data outputs. The device has a plurality of memory arrays. Each of the memory arrays comprises a plurality of memory cells. Each of the plurality of memory cells is coupled to a data input/output. The device has a spare group of memory cells comprising a plurality of spare memory cells. Each of the plurality of spare memory cells is externally (or internally) addressable using the address match table and configured with the spare address input; whereupon the spare address input is coupled to the address match table to access the spare memory cells. | 2013-07-11 |
20130176769 | 8-TRANSISTOR SRAM CELL DESIGN WITH SCHOTTKY DIODES - An 8-transistor SRAM cell which includes two pull-up transistors and two pull-down transistors in cross-coupled inverter configuration to form two inverters for storing a single data bit, wherein each of the inverters includes a Schottky diode; first and second pass gate transistors having a gate terminal coupled to a write word line and a source or drain of each of the pass gate transistors coupled to a write bit line; and first and second read transistors coupled to the two pull-up and two pull-down transistors, one of the read transistors having a gate terminal coupled to a read word line and a source or a drain coupled to a read bit line. In a preferred embodiment, the 8-transistor SRAM cell has column select writing enabled for writing a value to the 8-transistor SRAM cell without inadvertently also writing a value to another 8-transistor SRAM cell. | 2013-07-11 |
20130176770 | 8-TRANSISTOR SRAM CELL DESIGN WITH INNER PASS-GATE JUNCTION DIODES - An 8-transistor SRAM cell which includes two pull-up transistors and two pull-down transistors in cross-coupled inverter configuration for storing a single data bit; first and second pass-gate transistors having a gate terminal coupled to a write word line and a source or drain of each of the pass-gate transistors coupled to a write bit line; inner junction diodes at shared source/drain terminals of the pass-gate and pull-down transistors oriented to block charge transfer from the write bit line into the cell; and first and second read transistors coupled to the two pull-up and two pull-down transistors, one of the read transistors having a gate terminal coupled to a read word line and a source or a drain coupled to a read bit line. The 8-transistor SRAM cell is adapted to prevent the value of the bit stored in the cell from changing state. | 2013-07-11 |
20130176771 | 8-TRANSISTOR SRAM CELL DESIGN WITH OUTER PASS-GATE DIODES - An 8-transistor SRAM cell which includes two pull-up transistors and two pull-down transistors in cross-coupled inverter configuration for storing a single data bit; first and second pass-gate transistors having a gate terminal coupled to a write word line and a source or drain of each of the pass-gate transistors coupled to a write bit line through a series outer diode between the pass-gate and the write bit line oriented to block charge transfer from the write bit line into the cell; and first and second read transistors coupled to the two pull-up and two pull-down transistors, one of the read transistors having a gate terminal coupled to a read word line and a source or a drain coupled to a read bit line. The 8-transistor SRAM cell is adapted to prevent the value of the bit stored in the cell from changing state. | 2013-07-11 |
20130176772 | Electrical Screening of Static Random Access Memories at Varying Locations in a Large-Scale Integrated Circuit - A method of testing large-scale integrated circuits including multiple instances of memory arrays, and an integrated circuit structure for assisting such testing, are disclosed. In one embodiment, voltage drops due to parasitic resistance in array bias conductors are determined by extracting layout parameters, and subsequent circuit simulation that derives the voltage drops in those conductors during operation of each memory array. In another embodiment, sense lines from each memory array are selectively connected to a test sense terminal of the integrated circuit, at which the array bias voltage at each memory array is externally measured. Feedback control of the applied voltage to arrive at the desired array bias voltage can be performed. | 2013-07-11 |
20130176773 | Reference Averaging for MRAM Sense Amplifiers - A sense amplifier comprising a reference current developed from a programmed and a non-programmed reference cell is used to read a signal from a magnetic random access memory (MRAM) comprising magnetic tunnel junction (MTJ) cells. The average current is determined from reference cells in as few as one sense amplifier and as many as n sense amplifiers, and is an average current between the programmed reference cell and the non-programmed reference cell that approximates the mid point between the two states. The sense amplifier can be fully differential or a non differential sense amplifier. | 2013-07-11 |
20130176774 | SYSTEM AND METHOD OF REFERENCE CELL TESTING - Systems and methods of testing a reference cell in a memory array are disclosed. In a particular embodiment, a method includes coupling a first reference cell of a first reference cell pair of a memory array to a first input of a first sense amplifier of the memory array. The method also includes providing a reference signal to a second input of the first sense amplifier. The reference signal is associated with a second reference cell pair of the memory array. | 2013-07-11 |
20130176775 | FINDING OPTIMAL READ THRESHOLDS AND RELATED VOLTAGES FOR SOLID STATE MEMORY - An expected value associated with stored values in solid state storage, as well as a set of three or more points are obtained where the three or more points include a voltage and a value associated with stored values. Two points having ratios closest to the expected value are selected from the set. A voltage is determined based at least in part on the selected two points and the expected value. | 2013-07-11 |
20130176776 | Charge Cycling By Equalizing and Regulating the Source, Well, and Bit Line Levels During Write Operations for NAND Flash Memory: Program to Verify Transition - In non-volatile memory devices, a write typically consists of an alternating set of pulse and verify operations. At the end of a pulse, the device must be biased properly for an accurate verify, after which the device is re-biased for the next pulse. The intervals between the pulse and verify phases are considered. For the interval after a pulse, but before establishing the verify conditions, the source, bit line, and, optionally, the well levels can be equalized and then regulated at a desired DC level. After a verify phase, but before applying the biasing the memory for the next pulse, the source and bit line levels can be equalized to a DC level. | 2013-07-11 |
20130176777 | Charge Cycling By Equalizing and Regulating the Source, Well, and Bit Line Levels During Write Operations for NAND Flash Memory: Verify to Program Transition - In non-volatile memory devices, a write typically consists of an alternating set of pulse and verify operations. At the end of a pulse, the device must be biased properly for an accurate verify, after which the device is re-biased for the next pulse. The intervals between the pulse and verify phases are considered. For the interval after a pulse, but before establishing the verify conditions, the source, bit line, and, optionally, the well levels can be equalized and then regulated at a desired DC level. After a verify phase, but before applying the biasing the memory for the next pulse, the source and bit line levels can be equalized to a DC level. | 2013-07-11 |
20130176778 | CELL-LEVEL STATISTICS COLLECTION FOR DETECTION AND DECODING IN FLASH MEMORIES - Methods and apparatus are provided for collecting cell-level statistics for detection and decoding in flash memories. Data from a flash memory device is processed by obtaining one or more read values for a plurality of bits in a page of the flash memory device; and generating cell-level statistics for the flash memory device based on a probability that a data pattern was read from the plurality of bits given that a particular pattern was written to the plurality of bits. The cell-level statistics are optionally generated substantially simultaneously with a reading of the read values, for example, as part of a read scrub process. The cell-level statistics can be used to convert the read values for the plurality of bits to a reliability value for a bit among the plurality of bits. | 2013-07-11 |
20130176779 | INTER-CELL INTERFERENCE CANCELLATION IN FLASH MEMORIES - Inter-cell interference cancellation is provided for flash memory devices. Data from a flash memory device is processed by obtaining one or more quantized threshold voltage values for at least one target cell of the flash memory device; obtaining one or more hard decision read values for at least one aggressor cell of the target cell; determining an aggressor state of the at least one aggressor cell; determining an interference amount based on the aggressor state; determining an adjustment to the quantized threshold voltage values based on the determined interference amount; and adjusting the quantized threshold voltage values based on the determined adjustment. The quantized threshold voltage values for at least one target cell are optionally re-used from a previous soft read retry operation. The adjusted quantized threshold voltage values are optionally used to determine reliability values and are optionally applied to a soft decision decoder and/or a buffer. | 2013-07-11 |
20130176780 | DETECTION AND DECODING IN FLASH MEMORIES WITH ERROR CORRELATIONS FOR A PLURALITY OF BITS WITHIN A SLIDING WINDOW - Methods and apparatus are provided for detection and decoding in flash memories with error correlations for a plurality of bits within a sliding window. Data from a flash memory device is processed by obtaining one or more read values for a plurality of bits from one or more pages of the flash memory device; converting the one or more read values for the plurality of bits to a non-binary log likelihood ratio based on a probability that a given data pattern was written to the plurality of bits when a particular pattern was read from the plurality of bits; and decoding the plurality of bits using a binary decoder. The non-binary log likelihood ratio captures one or more of intra-page correlations and/or intra-cell correlations. A least significant bit and a most significant bit of a given cell can be independently converted and/or jointly converted to the non-binary log likelihood ratio. | 2013-07-11 |
20130176781 | 3D Memory Array with Read Bit Line Shielding - A memory device includes a block of memory cells having a plurality of levels. Each level includes strips of memory cells extending in a first direction between first and second ends of the block. A first bit line structure, at each level at the first end, is coupled to a first string of memory cells extending from the first end. A second bit line structure, at each level at the second end, is coupled to a second string of memory cells extending from said second end. Bit line pairs extend in the first direction with each including odd and even bit lines. Odd and even bit line connectors connect the odd and even bit lines to the second and first bit line structures, respectively. Each bit line for a series of bit line pairs are separated by a bit line of an adjacent pair of bit lines. | 2013-07-11 |
20130176782 | MEMORY DEVICE HAVING SUB-BIT LINES AND MEMORY SYSTEM - A memory device includes; a memory cell array including a memory cell connected to a bit line, a page buffer unit receiving data from the memory cell via the bit line, and a contact unit providing an electrical path through which the data is communicated from the memory cell array to the page buffer unit, wherein the contact unit comprises a sub-bit line configured to connect the bit line via a first contact with the page buffer unit via a second contact. | 2013-07-11 |
20130176783 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND WRITE-IN METHOD THEREOF - TASK: to minimize variations of the threshold voltage distribution after programming and obtain a high-speed rewriting characteristic. MEANS FOR SOLVING THE PROBLEM: A non-volatile semiconductor memory device includes a non-volatile memory cell array and a control circuit for controlling writing-in to the memory cell array, wherein before or after an erasing process where data of written-in memory cells is erased, the control circuit detects a programming speed when writing-in to the memory cell array, determines a programming start voltage corresponding to the programming speed for every block or every word line, stores the determined programming start voltage in the memory cell array and reads-out the programming start voltage from the memory cell array to write-in predetermined data. | 2013-07-11 |
20130176784 | ADJUSTING OPERATING PARAMETERS FOR MEMORY CELLS BASED ON WORDLINE ADDRESS AND CYCLE INFORMATION - Disclosed is an apparatus and method for adjusting operating parameters in a storage device. A controller in a solid state drive monitors current operating conditions for blocks of memory used to store data in the drive. When a block has been subjected to a predetermined number of program/erase cycles one or more stored bias values are retrieved from a storage location based on the wordline(s) associated with a current memory operation. The one or more parameters of the memory operation are then adjusted based on the one or more stored bias values, and the memory operation performed on the block of memory cells using the adjusted parameters. | 2013-07-11 |
20130176785 | METHOD FOR ACCESSING A FLASH MEMORY, AND ASSOCIATED FLASH MEMORY SYSTEM - A method for accessing a Flash memory and an associated Flash memory system are provided, where the Flash memory includes a plurality of blocks, each of the blocks includes a plurality of pages, and each of the pages includes a plurality of sectors. The method includes: receiving a page of data from a host; encoding a first portion of the page of data by a randomizer that operated under a first seed to generate a first encoded data; encoding a second portion of the page of data by the randomizer that operated under a second seed to generate a second encoded data, wherein the first seed is different from the second seed; and storing the first encoded data and the second encoded data to the Flash memory. An associated method and an associated Flash memory system are also provided. | 2013-07-11 |
20130176786 | 2-TRANSISTOR FLASH MEMORY AND PROGRAMMING METHOD OF 2-TRANSISTOR FLASH MEMORY - Disclosed is a 2-transistor flash memory that includes a memory cell array, a row driver, a read/write circuit, a charge pump generating a high voltage, and control logic configured to transfer the high voltage to the row driver, the read/write circuit, and the memory cell array. If programming, the row driver and the read/write circuit apply voltages such that a control gate of a cell transistor in an unselected memory cell on a different row from a selected memory cell is floated. | 2013-07-11 |
20130176787 | Method and Apparatus for Training a DLL in a Memory Subsystem - A method and apparatus for training a DLL in a memory subsystem is disclosed. In one embodiment, a memory subsystem includes a memory coupled to convey data read therefrom on one or more channels. Each memory channel may include a delay locked loop (DLL) configured to apply a desired amount of delay to a data strobe signal received from the memory during a read operation. Upon detecting a read request, a controller may initiate a training procedure in which the DLL is trained to the desired delay. During the training procedure, an input clock signal may be provided to the DLL. The delay within the DLL may be adjusted until an output clock signal has a desired phase relationship with the input clock signal. Once the desired phase relationship is attained, the training procedure may be terminated and the DLL input may be switched to receive the data strobe signal. | 2013-07-11 |
20130176788 | DEVICE SELECTION SCHEMES IN MULTI CHIP PACKAGE NAND FLASH MEMORY SYSTEM - Systems and methods are provided for perform device selection in multi-chip package NAND flash memory systems. In some embodiments, the memory controller performs device selection by command. In other embodiments, the memory controller performs device selection by input address. | 2013-07-11 |
20130176789 | MEMORY ARRAY AND METHOD FOR PROGRAMMING MEMORY ARRAY - A method for programming a memory array is provided. The memory array includes a memory cell string composed of a first transistor, a plurality of memory cells and a second transistor connected in series, and the method for programming the memory array includes following steps. In a setup phase, a switching memory cell in the memory cells is turned off, and a first voltage and a second voltage are applied to a first source/drain and a second source/drain of the switching memory cell. In a programming phase, a bit line connected to the memory cell string is floating, and a ramp signal is provided to a word line electrically connected to the switching memory cell. | 2013-07-11 |
20130176790 | Charge Cycling By Equalizing the Source and Bit Line Levels Between Pulses During No-Verify Write Operations for NAND Flash Memory - In non-volatile memory devices, a write typically consists of an alternating set of pulse and verify operations. At the end of a pulse, the device must be biased properly for an accurate verify, after which the device is re-biased for the next pulse. In some cases a non-volatile memory is programmed by an alternating set of pulses, but, for at least some pulses without any intervening verify operations. After a one pulse, but before biasing the memory for the next pulse without an intervening very, the source and bit line levels can be left to float. | 2013-07-11 |
20130176791 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND VERIFICATION CONTROL METHOD FOR THE SAME - A nonvolatile semiconductor memory device includes a memory cell array, a plurality of local sense amplifiers, a global sense amplifier and an address decoder. The address decoder is configured to switch between a first verification and a second verification. The first verification operates the plurality of local sense amplifiers and simultaneously verifies data of a plurality of memory cells connected to the plurality of local sense amplifiers. The second verification stops the plurality of local sense amplifiers, directly connects the local bit line connected to each of the local sense amplifiers with the global bit line, and simultaneously verifies data of the plurality of memory cells connected to the plurality of local sense amplifiers. | 2013-07-11 |
20130176792 | NONVOLATILE MEMORY DEVICE AND METHOD OF PROGRAMMING THE SAME - A nonvolatile memory device and a method of programming the same. The nonvolatile memory device includes a memory cell array including a plurality of memory cells and a program control logic circuit controlling the memory cell array. The program control logic circuit programs a first memory cell so that the threshold voltage of the first memory cell corresponding to data of erasure state is higher than the threshold voltage of a second memory cell corresponding to data of program state, in the memory cell array. The nonvolatile memory device controlled in this manner can provide higher reliability. | 2013-07-11 |
20130176793 | FLASH MEMORY APPARATUS - A flash memory apparatus is provided. The flash memory apparatus includes a plurality of memory cells and a plurality of programming voltage control generators. Each of the memory cells receives a programming control voltage through a control end thereof, and executes data programming operation according to the programming control voltages. Each of the programming voltage control generators includes a pre-charge voltage transmitter and a pumping capacitor. The pre-charge voltage transmitter provides pre-charge voltage to the end of each of the corresponding memory cells according to pre-charge enable signal during a first period. A pumping voltage is provided to the pumping capacitor during a second period, and the programming control voltage is generated at the control end of each of the memory cells. | 2013-07-11 |
20130176794 | METHOD OF OPERATING SEMICONDUCTOR MEMORY DEVICE - A method of operating a semiconductor memory device includes applying a program pass voltage to unselected word lines, applying a program voltage of a third level to a selected word line in order to raise threshold voltages of third memory cells, decreasing a level of the program voltage from the third level to a second level and discharging channel regions of second cell strings including second memory cells in order to raise threshold voltages of second memory cells, and decreasing a level of the program voltage from the second level to a first level and discharging channel regions of first cell strings including first memory cells in order to raise threshold voltages of first memory cells. The cell strings are disconnected from a bit line while a voltage level of the unselected word lines rises to a level of the program pass voltage. | 2013-07-11 |
20130176795 | Enhanced Power Savings for Memory Arrays - A memory array is provided that comprises a plurality of global bit lines such that each bit line is coupled to a plurality of memory cells. The memory array further comprises a plurality of precharge logic such that each precharge logic is coupled to an associated global bit line in the plurality of global bit lines. Identification logic in the memory array is coupled to the plurality of precharge logic. The identification logic provides a precharge enable signal to a subset of the plurality of precharge logic on each clock cycle such that the subset of precharge logic precharges its associated subset of global bit lines to a voltage level of a voltage source, thereby reducing the power consumption of the memory array. | 2013-07-11 |
20130176796 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF WRITING INTO SEMICONDUCTOR MEMORY DEVICE - The semiconductor memory device includes a memory cell, a pair of bit lines and a cell power line connected to the memory cell, a first switch connected to the bit lines and a power voltage line, a second switch connected to the cell power line and a write assist cell power line, and a write control circuit configured to control the bit lines, the first switch and the second switch, wherein the write control circuit applies a first voltage of a high level to one bit line and a second voltage of a low level to the other bit line, connects one bit line to the power voltage line and disconnects the other bit line from the power voltage line by the first switch, and then connects the cell power line to the write assist cell power line lower which is than the first voltage by the second switch. | 2013-07-11 |
20130176797 | DATA OUTPUT CIRCUIT - A data output circuit includes a control signal generation block configured to generate a first transfer control signal which is produced in a first read operation and a second transfer control signal which is produced in a second read operation, where the first transfer control signal and the second transfer control signal are generated upon entry into a test mode; and an enable signal generation unit configured to generate first and second enable signals for generating first and second internal clocks, in response to the first and second transfer control signals. | 2013-07-11 |
20130176798 | MECHANISM FOR PEAK POWER MANAGEMENT IN A MEMORY - A mechanism for managing peak power in a memory storage array that includes sub-array blocks may reduce the peak currents associated with read and write operations by staggering the wordline signal activation to each of the sub-array blocks. In particular, the wordline units within each sub-array block may generate the wordline signals to each sub-array block such that a read wordline signal of one sub-array block does not transition from one logic level to another logic level at the same time as the write wordline of another sub-array block. Further, the wordline units may generate the wordline signals to each sub-array block such that a read wordline of a given sub-array block does not transition from one logic level to another logic level at the same time as a read wordline signal of another sub-array block. | 2013-07-11 |
20130176799 | SEMICONDUCTOR DEVICE, SEMICONDUCTOR SYSTEM HAVING THE SAME, AND COMMAND ADDRESS SETUP/HOLD TIME CONTROL METHOD THEREFOR - A semiconductor system includes a controller configured to output a clock enable signal, first to third command/address signals, a chip select signal, first and second entry commands and an exit command, and receive an output signal; and a semiconductor device configured to latch the first and second command/address signals and transfer the output signal in response to the chip select signal and the first entry command, latch the first and third command/address signals and transfer the output signal in response to the chip select signal and the second entry command, and transfer data generated by the first to third command/address signals as the output signal in response to the clock enable signal and the exit command signal. | 2013-07-11 |
20130176800 | MEMORY CONTROLLER HAVING A WRITE-TIMING CALIBRATION MODE - A memory controller outputs address bits and a first timing signal to a DRAM, each address bit being associated with an edge of the first timing signal and the first timing signal requiring a first propagation delay time to propagate to the DRAM. The memory controller further outputs write data bits and a second timing signal to the DRAM in association with the address bits, each of the write data bits being associated with an edge of the second timing signal and the second timing signal requiring a second propagation delay time to propagate to the DRAM. The memory controller includes a plurality of series-coupled delay elements to provide respective, differently-delayed internal delayed timing signals and a multiplexer to select one of the delayed timing signals to be output as the second timing signal based on a difference between the first propagation delay time and the second propagation delay time. | 2013-07-11 |
20130176801 | PRECHARGE CIRCUIT AND SEMICONDUCTOR MEMORY DEVICE HAVING THE SAME - A semiconductor memory device includes: input/output line coupled to a first bit line of a first mat including a plurality of memory cells; a second input/output line coupled to a second bit line of a second mat including a plurality of memory cells; and a switching unit configured to couple the first input/output line and the second input/output line in response to a precharge signal. | 2013-07-11 |
20130176802 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a switching unit coupled between a local sense amplifier and a bit line sense amplifier and configured to be turned on in response to a switching signal which is enabled in synchronization with an enable signal for enabling the local sense amplifier and disabled at a time point where a preset period passes after a first power for enabling the bit line sense amplifier is precharged. | 2013-07-11 |
20130176803 | SEMICONDUCTOR MEMORY DEVICE AND REFRESH METHOD THEREOF - A semiconductor memory device and a self-refresh method of the semiconductor memory device. The semiconductor memory device includes: a memory cell array including one or more memory cells; a sense amplifier connected to a sensing line and a complementary sensing line and sensing/amplifying data stored in the one or more memory cells; and a sense amplifier control circuit sequentially supplying a first voltage and a second voltage having different levels to the sense amplifier through the sensing line during a refresh operation. | 2013-07-11 |
20130176804 | METHOD AND APPARATUS FOR REDUCING CURRENT CONSUMPTION BY MEMORY REFRESH OPERATION CONTROL - A method and apparatus for reducing current consumption by employing a memory refresh operation is provided. The method employs a refresh operation in an apparatus including a memory in which a partial refresh operation is performed. The method includes classifying data loaded in the memory into first data and second data, dividing the memory into a first area and a second area when an attempt to access the first data is not detected during a preset time, separately arranging the first data and the second data in the first area and the second area, respectively, performing a refresh operation in the second area at a preset time in order to retain data, and loading the first data into the memory when the attempt to access the first data is detected. | 2013-07-11 |
20130176805 | METHODS AND SYSTEMS INVOLVING ELECTRICALLY REPROGRAMMABLE FUSES - An electrically reprogrammable fuse comprising an interconnect disposed in a dielectric material, a sensing wire disposed at a first end of the interconnect, a first programming wire disposed at a second end of the interconnect, and a second programming wire disposed at a second end of the interconnect, wherein the fuse is operative to form a surface void at the interface between the interconnect and the sensing wire when a first directional electron current is applied from the first programming wire through the interconnect to the second programming wire, and wherein, the fuse is further operative to heal the surface void between the interconnect and the sensing wire when a second directional electron current is applied from the second programming wire through the interconnect to the first programming wire. | 2013-07-11 |
20130176806 | POWER-UP SIGNAL GENERATION CIRCUIT - A power-up signal generation circuit includes a first driving section configured to generate a pre-power-up signal by driving a first node to a first pull-up drivability or driving the first node to a first pull-down drivability in response to an internal voltage when not in an active mode, and a second driving section configured to generate the pre-power-up signal by driving the first node to a second pull-up drivability or driving the first node to a second pull-down drivability in response to the internal voltage in the active mode. The first pull-up drivability is larger than the second pull-up drivability, and the first pull-down drivability is smaller than the second pull-down drivability. | 2013-07-11 |
20130176807 | DRAM AND ACCESS AND OPERATING METHOD THEREOF - An access method for a DRAM is provided. A row address is partitioned into a first portion and a second portion. The first portion of the row address via an address bus and a first active command via a command bus are provided to the DRAM. The second portion of the row address via the address bus and a second active command via the command bus are provided to the DRAM after the first active command is provided. A column address via the address bus and an access command via the command bus are provided to the DRAM after the second active command is provided. The address bus is formed by a plurality of address lines, and a quantity of the address lines is smaller than the number of bits of the row address, and the access command is a read command or a write command. | 2013-07-11 |
20130176808 | WORD LINE BOOST CIRCUIT - A word line boost circuit including a first address transfer detector, a second address transfer detector and a boost operation unit is provided. The first address transfer detector generates a first detection pulse in response to variation of a row address signal. The second address transfer detector generates a second detection pulse in response to variation of a column address signal. Moreover, the boost operation unit generates a selection voltage by using a boost voltage according to the first detection pulse, and determines whether or not to use the boost voltage to generate the selection voltage according to a delay time between the first detection pulse and the second detection pulse. | 2013-07-11 |
20130176809 | SELF CLOCKING FOR DATA EXTRACTION - A self clocking data extraction method is shown that is tolerant of timing jitter, data skew and the presence of multiple edges per data bit. The data is sampled when the following criterion are met: There is at least one edge across any track (the clock assures this criteria is met), followed by no edges in any track for a defined period of time (T), and all edge activity must occur in a period of time less than T (to keep from detecting false samples). This method enables the handling of trace data signals with poor electrical characteristics that can not be recorded by methods known in the prior art. | 2013-07-11 |
20130176810 | GEL REDUCTION DEVICE AND GEL REDUCTION METHOD - A gel reduction device | 2013-07-11 |
20130176811 | DOUGH PREPARING MACHINE WITH DOUGH DIVIDING IN BOWL - A dough preparing machine operable to mix and divide dough so as to form a plurality of individual loaves of bread in a relatively compact space is provided. The dough preparing machine includes a compressing and dividing device, a bowl, a pivotable mixing arm, a rounder, and a sheeter molder. The dough preparing machine further includes a transfer device having a first arm and an opposable gripper operable to handle the rounded individual balls of dough. The compressing and dividing device configured to press the dough uniformly within the bowl, and divide the compressed dough into individual balls of dough. | 2013-07-11 |