28th week of 2022 patent applcation highlights part 58 |
Patent application number | Title | Published |
20220223604 | SEMICONDUCTOR STRUCTURE HAVING COMPOSITE MOLD LAYER - A semiconductor structure of the inventive concepts includes a chip region comprising a plurality of semiconductor chips on the substrate; and a peripheral region at a periphery of the chip region, the peripheral region including a mold structure. The mold structure may include a base mold layer on the substrate, and a composite mold layer on the base mold layer, the composite mold layer comprising at least one bowing sacrificial layer and at least one bowing prevention layer. | 2022-07-14 |
20220223605 | MEMORY DEVICE HAVING SHARED ACCESS LINE FOR 2-TRANSISTOR VERTICAL MEMORY CELL - Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes a memory cell and first, second, and third data lines located over a substrate. The memory cell includes a first transistor and a second transistor. The first transistor includes a charge storage structure located on a first level of the apparatus, and a first channel region electrically separated from the charge storage structure. The second transistor includes a second channel region located on a second level of the apparatus and electrically coupled to the charge storage structure. The first and second data lines are located on a third level of the apparatus and electrically coupled to the first channel region. The first level is between the substrate and the third level. The third data line is electrically coupled to the second channel region and electrically separated from the first channel region. | 2022-07-14 |
20220223606 | MEMORY DEVICE AND METHOD FOR FORMING THE SAME - A memory device includes a substrate, a first transistor and a second transistor, a first word line, a second word line, and a bit line. The first transistor and the second transistor are over the substrate and are electrically connected to each other, in which each of the first and second transistors includes first semiconductor layers and second semiconductor layers, a gate structure, and source/drain structures, in which the first semiconductor layers are in contact with the second semiconductor layers, and a width of the first semiconductor layers is narrower than a width of the second semiconductor layers. The first word line is electrically connected to the gate structure of the first transistor. The second word line is electrically connected to the gate structure of the second transistor. The bit line is electrically connected to a first one of the source/drain structures of the first transistor. | 2022-07-14 |
20220223607 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device according to an embodiment includes a substrate, first conductive layers, and an insulating layer. The first conductive layers include terraced portions. The insulating layer is provided on the terraced portions. The first conductive layers include first to third layer groups. The first layer group is located the highest among the three or more layer groups. The insulating layer includes first to third portions. The first portion is sandwiched by the first layer group. The second portion is sandwiched by the second layer group. The third portion is sandwiched by the third layer group. The second portion is shifted to one side of a direction and the third portion is shifted to the other side of the direction with respect to the first portion. | 2022-07-14 |
20220223608 | BILAYER DIELECTRIC STACK FOR A FERROELECTRIC TUNNEL JUNCTION AND METHOD OF FORMING - Bilayer stack for a ferroelectric tunnel junction and method of forming. The method includes depositing a first metal oxide film on a substrate by performing a first plurality of cycles of atomic layer deposition, where the first metal oxide film contains hafnium oxide, zirconium oxide, or both hafnium oxide and zirconium oxide, depositing a second metal oxide film on the substrate by performing a second plurality of cycles of atomic layer deposition, where the second metal oxide film contains hafnium oxide and zirconium oxide, and has a different hafnium oxide and zirconium oxide content than the first metal oxide film, and heat-treating the substrate to form a ferroelectric phase in the second metal oxide film but not in the first metal oxide film. A ferroelectric tunnel junction includes a first metal-containing electrode, the first metal oxide film, the second metal oxide film, and a second metal-containing electrode. | 2022-07-14 |
20220223609 | SEMICONDUCTOR DEVICES WITH MEMORY CELLS - The present disclosure generally relates to semiconductor devices, and more particularly, to semiconductor devices having memory cells for multi-bit programming and methods of forming the same. The present disclosure also relates to a method of forming such semiconductor devices. The disclosed semiconductor devices may achieve a smaller cell size as compared to conventional devices, and therefore increases the packing density of the disclosed devices. | 2022-07-14 |
20220223610 | Memory Architecture - Various implementations described herein relate to a device with a multi-transistor logic structure for use in memory architecture. In some applications, the multi-transistor logic structure may have a pair of P-type transistors that are arranged in a P-over-P multi-transistor stack. In other applications, the multi-transistor logic structure may have a pair of N-type transistors that are arranged in an N-over-N multi-transistor stack. | 2022-07-14 |
20220223611 | SEMICONDUCTOR DEVICE - A semiconductor device has a first conductivity type semiconductor substrate. A second conductivity type first impurity diffusion layer is disposed in a surface region of the semiconductor substrate. A resistance element is configured with a first conductivity type second impurity diffusion layer disposed in the first impurity diffusion layer in the surface region of the semiconductor substrate. In a transistor, a gate is connected to an input portion of the resistance element, a source is connected to the first impurity diffusion layer, and a drain is connected to a voltage source higher than the voltage of the input portion. A current source is connected to the source. | 2022-07-14 |
20220223612 | MEMORY STRUCTRUE AND MANUFACTURING METHOD THEREOF - A memory structure including a substrate, a first dielectric layer, a second dielectric layer, a charge storage layer, an oxide layer, and a conductive layer is provided. The first dielectric layer is disposed on the substrate. The second dielectric layer is disposed on the first dielectric layer. The charge storage layer is disposed between the first dielectric layer and the second dielectric layer. The oxide layer is located at two ends of the charge storage layer and is disposed between the first dielectric layer and the second dielectric layer. The conductive layer is disposed on the second dielectric layer. | 2022-07-14 |
20220223613 | MEMORY DEVICE INCLUDING DIFFERENT DIELECTRIC STRUCTURES BETWEEN BLOCKS - Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes levels of conductive materials interleaved with levels of dielectric materials; memory cell strings including respective pillars extending through the levels of conductive materials and the levels of dielectric materials; a first dielectric structure formed in a first slit through the levels of conductive materials and the levels of dielectric materials; a second dielectric structure formed in a second slit through the levels of conductive materials and the levels of dielectric materials; the first dielectric structure and the second dielectric structure separating the levels of conductive materials, the levels of dielectric materials, and the pillars into separate portions, and the first and second dielectric structures including different widths. | 2022-07-14 |
20220223614 | THREE-DIMENSIONAL MEMORY DEVICE WITH BACKSIDE SUPPORT PILLAR STRUCTURES AND METHODS OF FORMING THE SAME - At least one vertically alternating sequence of continuous insulating layers and continuous sacrificial material layers is formed over a substrate. Rows of backside support pillar structures are formed through the at least one vertically alternating sequence. Memory stack structures are formed through the at least one vertically alternating sequence. A two-dimensional array of discrete backside trenches is formed through the at least one vertically alternating sequence. Contiguous combinations of a subset of the backside trenches and a subset of the backside support pillar structures divide the at least one vertically alternating sequence into alternating stacks of insulating layers and sacrificial material layers. The sacrificial material layers are replaced with electrically conductive layers while the backside support pillar structures provide structural support to the insulating layers. | 2022-07-14 |
20220223615 | VERTICAL SEMICONDUCTOR DEVICES - A vertical semiconductor device includes a substrate, a cell array region and a pad region formed on the substrate, and gate patterns and respective insulation layers. The gate patterns may be stacked in a vertical direction perpendicular to an upper surface of the substrate. Each of the gate patterns may extend in a first direction parallel to the upper surface of the substrate on the cell array region and the pad region of the substrate. The gate patterns may include pads, respectively, at edge portions thereof in the first direction. The respective insulation layers may be between adjacent gate patterns in the vertical direction. The gate patterns and the insulation layer on the pad region may serve as a pad structure, and the pad structure may include a first staircase structure having a stepped shape, a second staircase structure having a stepped shape and disposed below the first staircase structure, a flat surface portion between the first and second staircase structures, and a dummy staircase structure formed on the flat surface portion. The dummy staircase structure may be spaced apart from each of the first and second staircase structures. | 2022-07-14 |
20220223616 | THREE DIMENSIONAL SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME - A three-dimensional semiconductor device and a method of forming the same are provided. The three-dimensional semiconductor device comprises a substrate including first and second areas; first and second main separation patterns, disposed on the substrate and intersecting the first and second areas; gate electrodes disposed between the first and second main separation patterns and forming a stacked gate group, the gate electrodes sequentially stacked on the first area and extending in a direction from the first area to the second area; and at least one secondary separation pattern disposed on the second area, disposed between the first and second main separation patterns, and penetrating through the gate electrodes disposed on the second area. The gate electrodes include pad portions on the second area, and the pad portions are thicker than the gate electrodes disposed on the first area and in contact with the at least one secondary separation pattern. | 2022-07-14 |
20220223617 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor memory device and a method for fabricating the same are provided. The semiconductor memory device includes a plurality of gate stacks separated by a plurality of slit structures, and each of the gate stacks includes: a first stack including three or more first conductive patterns spaced apart from one another at substantially a same level; a second stack formed on the first stack and including second conductive patterns and interlayer dielectric layers alternately stacked; and a plurality of channel structures penetrating the second stack and the first stack. | 2022-07-14 |
20220223618 | MEMORY DEVICE AND MANUFACTURING METHOD THEREOF - The present disclosure provides a semiconductor structure and a method for forming a semiconductor structure. The semiconductor structure includes a substrate, and a dielectric stack over the substrate. The dielectric stack includes a first layer over the substrate and a second layer over the first layer. The semiconductor structure further includes a gate layer including a first portion traversing the second layer and a second portion extending between the first layer and the second layer. | 2022-07-14 |
20220223619 | THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE AND METHOD OF FABRICATING THE SAME - A three-dimensional semiconductor memory device may include horizontal patterns disposed on a peripheral circuit structure and spaced apart from each other, memory structures provided on the horizontal patterns, respectively, each of the memory structures including a three-dimensional arrangement of memory cells. Penetrating insulating patterns and separation structures may isolate the horizontal patterns from one another. Through vias may extend through the penetrating insulating patterns to connect logic circuits of the peripheral circuit structure to the memory structure. | 2022-07-14 |
20220223620 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - The present technology provides a semiconductor device and a method of manufacturing the same. The semiconductor device includes a channel structure, insulating structures surrounding the channel structure and stacked to be spaced apart from each other, interlayer insulating films surrounding the insulating structures, respectively, and a gate electrode extending from between the interlayer insulating films to between the insulating structures and surrounding the channel structure. The insulating structures may include protrusion portions extending to cover edges of the interlayer insulating films facing the channel structure, and the gate electrode may extend between the protrusion portions which are adjacent to each other. | 2022-07-14 |
20220223621 | THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICES - Disclosed are three-dimensional semiconductor memory devices including an electrode structure including gate electrodes stacked in a first direction, a lower pattern group including lower vertical patterns that are in a lower portion of the electrode structure and are connected to the substrate, and an upper pattern group including upper vertical patterns that are in an upper portion of the electrode structure. The upper vertical patterns may be connected to the lower vertical patterns, respectively. The devices may also include two common source plugs spaced apart from each other in a second direction. The electrode structure may be between the two common source plugs. An upper portion of the lower pattern group has a first width in the second direction, an upper portion of the upper pattern group has a second width in the second direction, and the first width may be greater than the second width. | 2022-07-14 |
20220223622 | MEMORY STRUCTURE AND METHOD OF FORMING THE SAME - A method of forming a memory structure includes the following steps. A CMOS circuitry is formed over a semiconductor substrate. A bit line array is formed to be electrically connected to the CMOS circuitry. A memory array is formed over the bit line array. The memory array is formed by forming a word line stack, and forming first and second sets of stacked memory cells. The word line stack is formed on the bit line array and has a first side surface and a second side surface. The first sets of stacked memory cells are formed along the first side surface. The second sets of stacked memory cells are formed along the second side surface, wherein the second sets of stacked memory cells are staggered from the first sets of stacked memory cells. A source line array is formed over the memory array and electrically connected to the CMOS circuitry. | 2022-07-14 |
20220223623 | LOGIC CELL WITH SMALL CELL DELAY - A semiconductor structure is provided. A logic cell with a logic function includes a plurality of first transistors in an active region over a semiconductor substrate, a second transistor in the active region, a third transistor in the active region, and first and second isolation structures on opposite edges of the active region and extending along the first direction. Each first transistor includes a first gate electrode extending along the first direction. The second transistor includes a second gate electrode extending along the first direction. The third transistor includes a third gate electrode extending along the first direction. The first gate electrodes are disposed between the first and second isolation structures. The second gate electrode is disposed between the first gate electrodes and the first isolation structure. The third gate electrode is disposed between the first gate electrodes and the second isolation structure. | 2022-07-14 |
20220223624 | LOGIC DRIVE USING STANDARD COMMODITY PROGRAMMABLE LOGIC IC CHIPS COMPRISING NON-VOLATILE RANDOM ACCESS MEMORY CELLS - A multi-chip package includes: an interposer; a first IC chip over the interposer, wherein the first IC chip is configured to be programmed to perform a logic operation, comprising a NVM cell configured to store a resulting value of a look-up table, a sense amplifier having an input data associated with the resulting value from the NVM cell and an output data associated with the first input data of the sense amplifier, and a logic circuit comprising a SRAM cell configured to store data associated with the output data of the sense amplifier, and a multiplexer comprising a first set of input points for a first input data set for the logic operation and a second set of input points for a second input data set having data associated with the data stored in the SRAM cell, wherein the multiplexer is configured to select, in accordance with the first input data set, an input data from the second input data set as an output data for the logic operation; and a second IC chip over the interposer, wherein the first IC chip is configured to pass data associated with the output data for the logic operation to the second IC chip through the interposer. | 2022-07-14 |
20220223625 | BREAKDOWN VOLTAGE CAPABILITY OF HIGH VOLTAGE DEVICE - Various embodiments of the present disclosure are directed towards an integrated chip. The integrated chip includes a semiconductor substrate having a device substrate overlying a handle substrate and an insulator layer disposed between the device substrate and the handle substrate. A gate electrode overlies the device substrate between a drain region and a source region. A conductive via extends through the device substrate and the insulator layer to contact the handle substrate. A first isolation structure is disposed within the device substrate and comprises a first isolation segment disposed laterally between the gate electrode and the conductive via. A contact region is disposed within the device substrate between the first isolation segment and the conductive via. A conductive gate electrode directly overlies the first isolation segment and is electrically coupled to the contact region. | 2022-07-14 |
20220223626 | SEMICONDUCTOR DEVICES HAVING MULTI-CHANNEL ACTIVE REGIONS AND METHODS OF FORMING SAME - A multi-channel semiconductor-on-insulator (SOI) transistor includes a substrate having an electrically insulating layer thereon and a semiconductor active layer on the electrically insulating layer. A vertical stack of spaced-apart insulated gate electrodes, which are buried within the semiconductor active layer, is also provided. This vertical stack includes a first insulated gate electrode extending adjacent the electrically insulating layer and an (N−1)th insulated gate electrode that is spaced from a surface of the semiconductor active layer, where N is a positive integer greater than two. An Nth insulated gate electrode is provided on the surface of the semiconductor active layer. A pair of source/drain regions are provided within the semiconductor active layer. These source/drain regions extend adjacent opposing sides of the vertical stack of spaced-apart insulated gate electrodes. In some of these aspects, the semiconductor active layer extends between the pair of source/drain regions and the electrically insulating layer, whereas the first insulated gate electrode contacts the electrically insulating layer. | 2022-07-14 |
20220223627 | DISPLAY PANEL - An electronic device includes: a substrate including a first region and a second region, wherein the first region is in a middle position, and the second region is closer to an edge of the substrate than the first region; a first active layer disposed on the substrate and in the second region; a conducting electrode disposed on the substrate and in the second region, wherein the conducting electrode electrically connects to the first active layer and extends along a first direction; and a conductive layer disposed on the substrate and in the second region, wherein the conductive layer includes an opening, wherein a minimum distance from an edge of the opening to the first active layer along the first direction is different from a minimum distance from another edge of the opening to the first active layer along a second direction different from the first direction. | 2022-07-14 |
20220223628 | DISPLAY PANEL AND DISPLAY DEVICE - A display panel and a display device are provided. In a frame region, the display panel includes a first organic base substrate, an inorganic base substrate, a second organic base substrate, a first inorganic layer, and an encapsulation layer stacked in sequence, and a first groove portion passing through the first inorganic layer and a second groove portion extending to the second organic base substrate. An orthographic projection of the first groove portion projected on the first organic base substrate falls within and is less than an orthographic projection of the second groove portion projected on the first organic base substrate. | 2022-07-14 |
20220223629 | TFT ARRAY SUBSTRATE, PREPARATION METHOD THEREOF, AND DISPLAY DEVICE - A thin-film transistor (TFT) array substrate, a preparation method thereof, and a display device are provided. The TFT array substrate includes a source, a drain, and a first gate; wherein a protrusive structure is defined between the source and the drain, and the first gate is disposed inside the protrusive structure; and in a plane where a surface of the first gate is disposed, a sum of an overlapped area of a projection of the source and a projection of the first gate and an overlapped area of a projection of the drain and the projection of the first gate is less than an area threshold. | 2022-07-14 |
20220223630 | SEMICONDUCTOR DEVICE WITH MULTIPLE ZERO DIFFERENTIAL TRANSCONDUCTANCE AND METHOD OF MANUFACTURING SAME - A semiconductor device with multiple zero differential transconductance includes: a conductive substrate; a first insulating layer and a second insulating layer disposed on the conductive substrate; a first semiconductor and a second semiconductor disposed on first portions of the first insulating layer and the second insulating layer, respectively; a first buffer layer and a second buffer layer disposed on electrode contact areas of the first semiconductor and the second semiconductor, respectively; and an anode electrode and a cathode electrode disposed on second portions, which are different from the first portions, of the first insulating layer and the second insulating layer and on the first buffer layer and the second buffer layer, respectively, wherein the first semiconductor and the second semiconductor are disposed in parallel with each other and connected by the anode electrode and the cathode electrode. | 2022-07-14 |
20220223631 | LIGHT DETECTOR, LIGHT DETECTION SYSTEM, LIDAR DEVICE, MOBILE BODY, AND VEHICLE - According to one embodiment, a light detector includes a plurality of elements. Each of the elements includes a first semiconductor region, a second semiconductor region, and a third semiconductor region. The second semiconductor region is located on the first semiconductor region and has a higher first-conductivity-type impurity concentration than the first semiconductor region. The third semiconductor region is located on the second semiconductor region. The elements are arranged at a first period in a second direction crossing a first direction. The first direction is from the first semiconductor region toward the second semiconductor region. A quenching part is electrically connected with the third semiconductor region. Multiple lenses are located respectively on the elements. One of the lenses is positioned on one of the elements. A refracting layer is located between the elements and the lenses. The refracting layer has a first thickness. | 2022-07-14 |
20220223632 | LIGHT RECEIVING DEVICE AND DISTANCE MEASURING MODULE - The present technology relates to a light receiving device and a distance measuring module capable of curbing a decrease in distance measurement accuracy due to an increase in the number of pixels. | 2022-07-14 |
20220223633 | CAMERA MODULE, PHOTOSENSITIVE COMPONENT, PHOTOSENSITIVE-COMPONENT JOINED PANEL, AND FORMING DIE THEREOF AND MANUFACTURING METHOD THEREOF - Provided is a camera module and a photosensitive component thereof and a manufacturing method thereof, said photosensitive component comprising: a circuit board, a photosensitive element, and a molding base; the molding base is integrally formed on the circuit board and photosensitive element to form a light window; a first end side corresponding to the molding base adjacent to the flexible region has a first side surface facing the light window; said first side surface comprises a first partial surface arranged adjacent to the photosensitive element and a second partial surface connected to said first portion surface; a first angle between said first partial surface and the optical axis of the camera module is greater than a second angle between the second partial surface and the optical axis; a second end side opposite to and away from the flexible region of the molding base has a second side surface facing the light window; said second side surface comprises a third partial surface arranged adjacent to the photosensitive element and a fourth partial surface connected to said third portion surface; a third angle between the third partial surface and the optical axis is greater than a fourth angle between the fourth partial surface and the optical axis. | 2022-07-14 |
20220223634 | COMPOSITE DEEP TRENCH ISOLATION STRUCTURE IN AN IMAGE SENSOR - In some embodiments, the present disclosure relates to an integrated chip that includes a first image sensing element and a second image sensing element arranged over a substrate. A first micro-lens is arranged over the first image sensing element, and a second micro-lens is arranged over the second image sensing element. A composite deep trench isolation structure is arranged between the first and second image sensing elements. The composite deep trench isolation structure includes a lower portion arranged over the substrate and an upper portion arranged over the lower portion. The lower portion includes a first material, and the upper portion includes a second material that has a higher reflectivity than the first material. | 2022-07-14 |
20220223635 | SEMICONDUCTOR DEVICE INCLUDING IMAGE SENSOR AND METHOD OF FORMING THE SAME - A semiconductor device includes a substrate having a front side and a back side opposite to each other. A plurality of photodetectors is disposed in the substrate within a pixel region. An isolation structure is disposed within the pixel region and between the photodetectors. The isolation structure includes a back side isolation structure extending from the back side of the substrate to a position in the substrate. A conductive plug structure is disposed in the substrate within a periphery region. A conductive cap is disposed on the back side of the substrate and extends from the pixel region to the periphery region and electrically connects the back side isolation structure to the conductive plug structure. A conductive contact lands on the conductive plug structure, and is electrically connected to the back side isolation structure through the conductive plug structure and the conductive cap. | 2022-07-14 |
20220223636 | IMAGE SENSORS INCLUDING A PHOTODIODE - An image sensor including: a semiconductor substrate having a first surface and a second surface; a pixel device isolation film extending from the first surface of the semiconductor substrate into the semiconductor substrate, wherein the pixel device isolation film defines pixels in the semiconductor substrate, and includes a conductive layer; and a device isolation structure located inside a device isolation trench that extends from the first surface of the semiconductor substrate into the semiconductor substrate, wherein the device isolation structure includes a conductive liner electrically connected to the conductive layer, wherein a negative bias is applied to the conductive layer and the conductive liner. | 2022-07-14 |
20220223637 | SOLID-STATE IMAGING DEVICE AND MANUFACTURING METHOD THEREOF - There are provided a solid-state imaging device capable of effectively reducing color mixing and a manufacturing method thereof. A solid-state imaging device of the present disclosure includes a substrate and a photoelectric conversion unit provided in the substrate. In this solid-state imaging device, a plurality of protrusions are provided on the light incident surface of the substrate. Further, in this solid-state imaging device, the width of the protrusion becomes smaller as the distance from the center of the plurality of protrusions increases. | 2022-07-14 |
20220223638 | IMAGE SENSING DEVICE AND METHOD FOR FORMING THE SAME - An image sensing device and a method for forming the same are disclosed. The image sensing device includes a substrate including photoelectric conversion elements, and a grid structure disposed over the substrate. The grid structure includes an inner grid layer, and an outer grid layer formed outside the inner grid layer to provide air layer formed at a side surface and a top surface of the inner grid layer. | 2022-07-14 |
20220223639 | IMAGE SENSING DEVICE - An image sensing device includes a semiconductor substrate, a photoelectric conversion region structured to generate charge carriers from incident light and capture the charge carriers using an electric potential difference caused by a demodulation control signal applied to the photoelectric conversion region, and a circuit region disposed adjacent to the photoelectric conversion region, the circuit region including a plurality of pixel transistors that generate and output a pixel signal corresponding to the charge carriers captured by the photoelectric conversion region. The circuit region includes a first well region formed to have a first length in a first direction, and a second well region formed below the first well region such that a lower end of the first well region is in contact with an upper end of the second well region, and formed to have a second length shorter than the first length in the first direction. | 2022-07-14 |
20220223640 | DRIVE BACKPLANE, MANUFACTURING METHOD THEREOF, DETECTION SUBSTRATE, AND DETECTION DEVICE - A drive backplane, a manufacturing method thereof, a detection substrate and a detection device. The drive backplane includes: a base plate and multiple drive modules disposed on the base plate. Each drive module includes a reset transistor, a read transistor, an amplifier transistor and a memory capacitor; the reset transistor is connected to the memory capacitor, the memory capacitor is connected to a photosensor, the amplifier transistor is connected to the memory capacitor, and the read transistor is connected to the amplifier transistor; wherein an active layer in the amplifier transistor is made of amorphous silicon or an oxide semiconductor. | 2022-07-14 |
20220223641 | IMAGE SENSOR PACKAGE HAVING A CAVITY STRUCTURE FOR A LIGHT-TRANSMITTING MEMBER - According to an aspect, an image sensor package includes a substrate, an image sensor die coupled to the substrate, at least one conductor connected to the image sensor die and the substrate, and a light-transmitting member including a substrate member, a first leg member extending from a first edge portion of the substrate member, and a second leg member extending from a second edge portion of the substrate member, the first leg member being coupled to the substrate, the second leg member being coupled to the substrate. | 2022-07-14 |
20220223642 | IMAGE CAPTURING ELEMENT, MANUFACTURING METHOD, AND ELECTRONIC DEVICE - The present disclosure relates to an image capturing element, a manufacturing method, and an electronic device that make it possible to improve effects of reducing crosstalk. | 2022-07-14 |
20220223643 | IMAGE SENSOR COMPRISING STACKED PHOTO-SENSITIVE DEVICES - An image sensor comprises at least two vertically stacked photo-sensitive devices wherein each respective photo-sensitive device comprises a stack of a top electrode, a first charge transport layer and an active layer. Each respective stack generates electrical charges in response to a corresponding predefined range of wavelengths of light incident on the image sensor. | 2022-07-14 |
20220223644 | FLAT PANEL DETECTOR, DRIVING METHOD, DRIVING DEVICE AND FLAT PANEL DETECTION DEVICE - The present disclosure discloses a flat panel detector, a driving method, a driving device and a flat panel detection device. The flat panel detector includes: a base substrate, and a plurality of detection units located on the base substrate; each of the detection units includes a photodiode and a detection transistor; the flat panel detector further includes: a compensation semiconductor material layer including a plurality of compensation structures mutually spaced; each detection transistor is correspondingly provided with a compensation structure, and the compensation structure is located between a gate and a gate insulating layer of the corresponding detection transistor. | 2022-07-14 |
20220223645 | DISPLAY DEVICE - A display device includes a first electrode disposed on a substrate; a second electrode disposed on the substrate, the second electrode being spaced apart from, and facing, the first electrode in a first direction; and a plurality of light-emitting elements extending in a length direction and having both ends disposed on the first electrode and second electrode, respectively, wherein the first electrode includes a plurality of first patterns which are recessed from a top surface of the first electrode and from a side surface of the first electrode that faces the second electrode, and the second electrode includes a plurality of second patterns which are recessed from a top surface of the second electrode and from a side surface of the second electrode that faces the first electrode. | 2022-07-14 |
20220223646 | OPTOELECTRONIC DEVICE WITH LIGHT-EMITTING DIODES A DOPED REGION OF WHICH INCORPORATES AN EXTERNAL SEGMENT BASED ON ALUMINIUM AND GALLIUM NITRIDE - An optoelectronic device includes a substrate and wire-shaped light-emitting diodes the wire shape of which is elongate along a longitudinal axis. Each light-emitting diode has a doped first region including, over all or some of its height measured along the longitudinal axis, of a central first segment that is substantially elongate along the longitudinal axis, this segment being based on gallium nitride, and of an external second segment, this segment being based on aluminium and gallium nitride. The second segment includes an external first portion arranged laterally around the first segment ( | 2022-07-14 |
20220223647 | LIGHT EMITTING ELEMENT ARRAY - A light emitting element array is provided and includes substrate; light emitting elements arrayed to substrate; first anisotropic diffusion layer facing substrate with light emitting elements interposed between first anisotropic diffusion layer and substrate; and second anisotropic diffusion layer, wherein first anisotropic diffusion layer and second anisotropic diffusion layer are layered, first anisotropic diffusion layer and second anisotropic diffusion layer each include a region in an in-plane direction including a high refractive index region and a low refractive index region in a mixed manner, and absolute value of first angle formed by boundary between high refractive index region and low refractive index region of first anisotropic diffusion layer and direction perpendicular to substrate is different from absolute value of second angle formed by boundary between high refractive index region and low refractive index region of second anisotropic diffusion layer and direction perpendicular to substrate. | 2022-07-14 |
20220223648 | IMAGE DISPLAY DEVICE MANUFACTURING METHOD AND IMAGE DISPLAY DEVICE - An image display device manufacturing method includes: providing a first substrate that includes: a circuit including a circuit element formed on a light-transmitting substrate, and a first insulating film covering the circuit; forming, on the first insulating film, a layer including graphene; forming, on the layer v graphene, a semiconductor layer including a light-emitting layer; etching the semiconductor layer to form a light-emitting element; forming a second insulating film covering the layer including graphene, the light-emitting element, and the first insulating film; forming a via passing through the first insulating film and the second insulating film; and electrically connecting the light-emitting element and the circuit element through the via at a light-emitting surface facing a surface of the light-emitting element on a first insulating film side. | 2022-07-14 |
20220223649 | CROSS-POINT MAGNETORESISTIVE RANDOM MEMORY ARRAY AND METHOD OF MAKING THEREOF USING SELF-ALIGNED PATTERNING - A memory device includes a cross-point array of magnetoresistive memory cells. Each magnetoresistive memory cell includes a vertical stack of a selector-containing pillar structure and a magnetic tunnel junction pillar structure. The lateral spacing between neighboring pairs of magnetoresistive memory cells may be smaller along a first horizontal direction than along a second horizontal direction, and a dielectric spacer or a tapered etch process may be used to provide a pattern of an etch mask for patterning first electrically conductive lines underneath the magnetoresistive memory cells. Alternatively, a resist layer may be employed to pattern first electrically conductive lines underneath the cross-point array. Alternatively, a protective dielectric liner may be provided to protect selector-containing pillar structures during formation of the magnetic tunnel junction pillar structures. | 2022-07-14 |
20220223650 | CROSS-POINT MAGNETORESISTIVE RANDOM MEMORY ARRAY AND METHOD OF MAKING THEREOF USING SELF-ALIGNED PATTERNING - A memory device includes a cross-point array of magnetoresistive memory cells. Each magnetoresistive memory cell includes a vertical stack of a selector-containing pillar structure and a magnetic tunnel junction pillar structure. The lateral spacing between neighboring pairs of magnetoresistive memory cells may be smaller along a first horizontal direction than along a second horizontal direction, and a dielectric spacer or a tapered etch process may be used to provide a pattern of an etch mask for patterning first electrically conductive lines underneath the magnetoresistive memory cells. Alternatively, a resist layer may be employed to pattern first electrically conductive lines underneath the cross-point array. Alternatively, a protective dielectric liner may be provided to protect selector-containing pillar structures during formation of the magnetic tunnel junction pillar structures. | 2022-07-14 |
20220223651 | MEMORY DEVICE - A memory device includes a first bottom electrode, a first memory stack, and a second memory stack. The first bottom electrode has a first portion and a second portion connected to the first portion. The first memory stack is over the first portion of the first bottom electrode. The first memory stack includes a first resistive switching element and a first top electrode over the first resistive switching element. The second memory stack is over the second portion of the first bottom electrode. The second memory stack comprises a second resistive switching element and a second top electrode over the second resistive switching element. | 2022-07-14 |
20220223652 | Display Substrate and Preparation Method Thereof, and Display Apparatus - Provided is a display substrate, including: a base substrate, a light emitting structure layer disposed on the base substrate, and a color filter layer disposed on the light emitting structure layer; the base substrate having a display area and a peripheral area located at a periphery of the display area, the display area including multiple pixel driving circuits connected with the light emitting structure layer in the display area, the pixel driving circuit including a transistor which includes an active layer located in an interior of the base substrate; the color filter layer including a transition structure, the transition structure of the color filter layer being located between the display area and the peripheral area of the base substrate. | 2022-07-14 |
20220223653 | DISPLAY PANEL AND MANUFACTURING METHOD OF THE SAME - A display panel includes a display layer including a light emitting element generating a source light, a first color filter on the display layer, a first color control layer between the display layer and the first color filter and including a first surface facing the first display layer and a second surface facing the first color filter, and a plurality of capping layers encapsulating the first color control layer. Among the capping layers, a capping layer between the first surface of the first color control layer and the display layer has a first-first thickness that is different from a second-first thickness of a capping layer between the second surface of the first color control layer and the first color filter. | 2022-07-14 |
20220223654 | COLOR CONVERTING SUBSTRATE AND DISPLAY DEVICE INCLUDING SAME - A color converting substrate includes: a base part having, defined therein a first light transmitting region, a second light transmitting region spaced apart from the first light transmitting region in a first direction, and a first light blocking region between the first light transmitting region and the second light transmitting region; a first color filter positioned on one surface of the base part and overlapping the first light transmitting region; a second color filter positioned on the one surface of the base part and overlapping the second light transmitting region; a light blocking pattern overlapping the first light blocking region and positioned on the one surface of the base part; and a light transmitting pattern positioned on the first color filter, the second color filter, and the light blocking pattern, wherein the first color filter and the second color filter include a coloring material of a first color. | 2022-07-14 |
20220223655 | DISPLAY APPARATUS AND METHOD OF MANUFACTURING THE SAME - A display apparatus includes a first pixel, a second pixel, and a third pixel which emit light of different colors from one another, a first insulating layer on a first display element of the first pixel, and a second insulating layer on the first insulating layer. The first insulating layer defines a first opening portion corresponding to the first display element, the second insulating layer defines a first opening corresponding to the first opening portion, and the first opening portion has a first extension portion which extends in a first direction and at least partially exposes the second insulating layer. | 2022-07-14 |
20220223656 | DISPLAY DEVICE - A display device including: a display panel; and a touch member on the display panel and including a first touch conductive layer, a second touch conductive layer, and a first touch insulating film between the first touch conductive layer and the second touch conductive layer, wherein the first touch conductive layer includes a first touch connection pattern including a first connecting area and a second connecting area having a larger width than that of the first connecting area, wherein the second touch conductive layer includes first touch sensor patterns connected by the first touch connection pattern, second touch sensor patterns insulated from the first touch sensor patterns, and a second touch connection pattern connecting the second touch sensor patterns with one another, and wherein the second connecting area of the first touch connection pattern is between the first touch sensor pattern and the second touch sensor pattern facing each other. | 2022-07-14 |
20220223657 | TOUCH SENSIBLE ORGANIC LIGHT EMITTING DEVICE - Embodiments of the present invention generally relate to a touch sensible organic light emitting device. The organic light emitting device according to an exemplary embodiment of the present invention comprises: a substrate; a thin film transistor disposed on the substrate; an organic light emitting element connected to the thin film transistor and receiving a data voltage; a plurality of encapsulation thin films disposed on the organic light emitting element, and encapsulating the thin film transistor and the organic light emitting element; a planarization layer disposed on the encapsulation thin film; and a touch sensor disposed on the planarization layer. | 2022-07-14 |
20220223658 | ELECTRONIC DEVICE - An electronic device has a peripheral region and includes a first diode, a second diode, an auxiliary electrode and a peripheral pad. The second diode is disposed adjacent to the first diode. The auxiliary electrode is electrically connected to the first diode and the second diode. The peripheral pad is disposed in the peripheral region. The peripheral pad is electrically connected to the auxiliary electrode through a plurality of connection portions. | 2022-07-14 |
20220223659 | DISPLAY APPARATUS AND METHOD OF MANUFACTURING THE SAME - A display apparatus disposed on an object including a first surface having a first shape and a second surface having a second shape different from the first shape, the display apparatus includes a display panel arranged on the object, including a first display area extending along the first surface, a second display area extending along the second surface, a plurality of first pixels arranged with a preset interval in the first display area and a plurality of second pixels arranged with the preset interval in the second display area, where when tensile force is applied, a first elongation rate of the display panel in the first display area is different from a second elongation rate of the display panel in the second display area. | 2022-07-14 |
20220223660 | DISPLAY DEVICE - A display device includes a display panel including a first region and a second region, and a sensing module on a rear side of the display panel. The first region includes a first pixel area to display an image. The second region includes a second pixel area to display the image and a transmission area to transmit light output by the sensing module. The second region overlaps the sensing module. The second pixel area overlaps a first layer that blocks light output by the sensing module. The transmission area does not overlap the first layer. | 2022-07-14 |
20220223661 | ELECTRONIC DEVICE COMPRISING DISPLAY - An electronic device according to one embodiment of the present invention may comprise: a transparency layer; a pixel layer which is disposed under the transparency layer and comprises a plurality of pixels that can output light in a visible ray band for displaying a content through the transparency layer; a display panel which is disposed under the pixel layer and comprises a substrate layer including a plurality of switches that can operate the plurality of pixels; a bio-sensor which is disposed under at least a part of the display panel and enables acquisition of biometric information by using at least a part of reflected light obtained through reflection, by an external object, of at least a part of light output through at least some pixels among the plurality of pixels; and a coating which reflects external light in an infrared ray band that can be transmitted to the substrate layer and allows transmission of the light in a visible ray band, wherein the coating is formed between the transparency layer and the display panel. Various other embodiments are possible. | 2022-07-14 |
20220223662 | ORGANIC ELECTRONIC COMPONENT WITH ELECTRON INJECTION LAYER - A device is disclosed. In an embodiment the device includes an anode, an organic active layer above the anode, an organic layer sequence above the organic active layer, a metallic layer above the organic layer sequence and a cathode above the metallic layer, wherein the metallic layer includes Yb. | 2022-07-14 |
20220223663 | DISPLAY SUBSTRATE, ORGANIC LIGHT-EMITTING DIODE DISPLAY PANEL AND DISPLAY DEVICE - Disclosed are a display substrate, an organic light-emitting diode display panel and a display device. The display substrate includes a base substrate and a pixel defining layer located on a side of the base substrate, wherein the pixel defining layer is provided with a plurality of sub-pixel openings, outer contour shapes and sizes of all the sub-pixel openings are the same, filling parts are arranged in at least parts of the sub-pixel openings, and for different sub-pixel openings, area ratios of the filling parts to the sub-pixel openings are different. | 2022-07-14 |
20220223664 | DISPLAY DEVICE - A display device includes a substrate including a display area and a non-display area adjacent to the display area, a passivation layer disposed on the substrate, a via layer disposed on the passivation layer, sub-pixels including electrodes disposed on the via layer and light emitting elements disposed on the electrodes in the display area, a first bank disposed on the via layer and surrounding the sub-pixels in the display area, a second bank disposed on the via layer and spaced apart from the first bank in the non-display area, a third bank disposed on the via layer and spaced apart from the second bank in the non-display area, and a first valley disposed between the first bank and the second bank in the non-display area and penetrating the via layer and the passivation layer. | 2022-07-14 |
20220223665 | METHOD OF MANUFACTURING DISPLAY DEVICE - A method of manufacturing a display device includes forming a first electrode on a substrate, forming a bank layer on the first electrode, wherein the bank layer includes an opening portion exposing at least a portion of the first electrode, forming a first bank layer and a second bank layer by baking the bank layer, wherein the second bank layer is on the first bank layer and has liquid repellency, forming a first layer on the first electrode, and forming a third bank layer and a fourth bank layer by baking the first bank layer and the second bank layer, wherein the fourth bank layer is on the third bank layer and has liquid repellency, wherein the fourth bank layer is thinner than the second bank layer. | 2022-07-14 |
20220223666 | DISPLAY APPARATUS AND METHOD OF MANUFACTURING THE SAME - A display apparatus includes: a substrate including a first area and a plurality of second areas extending from the first area in different directions from each other; a light emitting device disposed on the first area and including a first electrode, a second electrode, and an intermediate layer between the first electrode and the second electrode; a first organic layer disposed on the first area, where a distance from an upper surface of the first organic layer to an upper surface of the substrate is greater than a distance from an upper surface of the first electrode to the upper surface of the substrate; and a disconnection portion disposed on the first organic layer and including a tip, an edge of an upper surface of which more protrudes away from a center of the first organic layer than an edge of the upper surface of the first organic layer. | 2022-07-14 |
20220223667 | DISPLAY DEVICE - A display device includes: a substrate comprising a display region including main pixels, and a sensor region including auxiliary pixels and transmission areas; first anodes arranged so as to correspond to the main pixels; first pixel defining layers for defining openings which partially expose the first anodes; spacers provided on the first pixel defining layers and protruding in the thickness direction; second anodes arranged so as to correspond to the auxiliary pixels; and second pixel defining layers for defining openings which partially expose the second anodes. The spacers and the second pixel defining layers are simultaneously formed of the same material. | 2022-07-14 |
20220223668 | DISPLAY SUBSTRATE AND METHOD FOR MANUFACTURING THE SAME, DISPLAY PANEL, AND DISPLAY APPARATUS - A display substrate includes a base substrate, a plurality of first electrodes, a first pixel defining layer, and a second pixel defining layer disposed on the base substrate, and light-emitting layers disposed in a plurality of second opening regions. The first pixel defining layer includes a plurality of first opening regions, and each of the first opening regions exposes at least a portion of a first electrode. The second pixel defining layer includes the plurality of second opening regions, each second opening regions corresponds to at least two first opening regions, and the orthogonal projections of the at least two first opening regions on the base substrate are located within the orthogonal projection of the second opening region on the base substrate. The light-emitting layers overspreads the plurality of second opening regions in a plane perpendicular to a thickness direction of the base substrate, respectively. | 2022-07-14 |
20220223669 | DISPLAY DEVICE - According to one embodiment, a display device includes a second insulating layer having a first opening and a second opening, a partition disposed on the second insulating layer, a first organic layer, a first upper electrode. The partition includes a first layer formed of a metal material and including a first side surface and a second side, and a second layer including a bottom surface. The first upper electrode is in contact with the first side surface, the bottom surface extends from the first side surface toward the first opening and extends from the second side surface toward the second opening. A lower portion of the second layer has an inverted tapered shape whose width increases as it is closer to top from the bottom surface. | 2022-07-14 |
20220223670 | DISPLAY DEVICE - An embodiment of the present disclosure provides a display device including a substrate, a thin film transistor on the substrate, a first electrode electrically connected to the thin film transistor, a light emitting layer and a second electrode overlapping the first electrode, a first partition wall between the first electrode and the second electrode, and a second partition wall overlapping the first partition wall, wherein the first partition wall includes at least one of a black pigment and a black dye, wherein the second partition wall includes an organic insulating material, and wherein a portion of the second partition wall overlaps the first electrode. | 2022-07-14 |
20220223671 | DISPLAY PANEL, DATA PROCESSING DEVICE AND METHOD FOR MANUFACTURING THE DISPLAY PANEL - A novel display panel that is highly convenient, useful, or reliable can be provided. The display panel includes a first light-emitting device, a second light-emitting device, a first insulating film, and a conductive film. The first light-emitting device includes a first electrode and a second electrode; the first electrode includes a first region overlapping with the second electrode and a second region outside the first region. The second light-emitting device includes a third electrode and a fourth electrode, and the third electrode includes a third region overlapping with the fourth electrode and a fourth region outside the third region. The first insulating film is in contact with the second region and the fourth region, and the first insulating film includes a first opening and a second opening. The first opening overlaps with the second electrode and the second opening overlaps with the fourth electrode. The conductive film is electrically connected to the second electrode and the fourth electrode in the first opening and in the second opening, respectively. | 2022-07-14 |
20220223672 | LIGHT EMITTING DISPLAY DEVICE - A light emitting display device including a first pixel including a first driving transistor, a first input transistor, a first initialization transistor, a first storage capacitor, and a first light emitting diode (LED); and a second pixel including a second driving transistor, a second input transistor, a second initialization transistor, a second storage capacitor, and a second light emitting diode (LED. The first pixel further includes a first gate electrode connecting member connecting a first gate electrode of the first driving transistor and the first input transistor; the second pixel further includes a second gate electrode connecting member connecting a second gate electrode of the second driving transistor and the second input transistor; the first light emitting diode (LED) includes a first anode; the second light emitting diode (LED) includes a second anode; and the first gate electrode connecting member does not overlap the second anode in a plan view. | 2022-07-14 |
20220223673 | DISPLAY PANEL AND DISPLAY APPARATUS - A display panel and a display apparatus. The display panel includes first and second display areas. The first display area includes a transparent display area and a transition display area. The display panel includes a device layer and a light-emitting element layer. The light-emitting element layer includes a first pixel structure arranged in the first display area. The first pixel structure includes a plurality of first sub-pixels, and the first sub-pixels include first electrodes. The device layer includes first driving transistors, and the first driving transistors include first gate electrodes. In a stacking direction the light-emitting element layer stacked with the device layer, an orthographic projection of a first gate electrode of one first driving transistor does not overlap with an orthographic projection of a first electrode of a first sub-pixel emitting a color different from another first sub-pixel driven by that first driving transistor. | 2022-07-14 |
20220223674 | Display Substrate and Preparation Method Thereof, and Display Apparatus - Provided are a display substrate and a preparation method thereof, and a display apparatus. The display substrate includes a substrate, an active structure layer disposed on the substrate, a first source-drain structure layer disposed on a side of the active structure layer away from the substrate, and a second source-drain structure layer disposed on a side of the first source-drain structure layer away from the substrate. The active structure layer includes a first active layer and a second active layer. The first source-drain structure layer includes a first active via and a first source-drain electrode, and the first source-drain electrode is connected to the first active layer through the first active via; and the second source-drain structure layer includes a second active via and a second source-drain electrode, and the second source-drain electrode is connected to the second active layer through the second active via. | 2022-07-14 |
20220223675 | WINDOW AND TRANSPARENT DISPLAY DEVICE - A window and a transparent display device are provided. The window includes a transparent display panel, a transparent substrate, and an ultraviolet light shielding layer. The transparent substrate is disposed on the transparent display panel. The ultraviolet light shielding layer is disposed on the transparent display panel. | 2022-07-14 |
20220223676 | DISPLAY DEVICE AND ARRAY SUBSTRATE - A display device according to an embodiment of the present invention includes: a substrate, a plurality of pixels on the substrate, a first inorganic insulating layer that covers the plurality of pixels, a conductive layer on the first inorganic insulating layer, and a second inorganic insulating layer that on the conductive layer, the conductive layer being between the first inorganic insulating layer and the second inorganic insulating layer, wherein the first inorganic insulating layer includes an area that is in direct contact with the second inorganic insulating layer, and all of the conductive layer is covered with the first inorganic insulating layer and the second inorganic insulating layer. | 2022-07-14 |
20220223677 | DISPLAY DEVICE - A display device including a substrate, a plurality of first data lines and a plurality of second data lines. The substrate includes a display area, in which a hole is formed, and a hole edge area surrounding the hole. The plurality of first data lines are disposed on the substrate, extend in a first direction in the display area, are arranged in a second direction orthogonal to the first direction, and bypass the hole along the hole edge area. The plurality of second data lines are disposed on the substrate, extend in the first direction in the display area, are arranged adjacent to the plurality of first data lines, and bypass the hole along hole edge area. In the hole edge area, each of the plurality of first data lines and the plurality of second data lines are disposed on three layers different from each other. | 2022-07-14 |
20220223678 | ARRAY SUBSTRATE AND FABRICATION METHOD THEREOF, ARRAY SUBSTRATE MOTHERBOARD AND DISPLAY DEVICE - An array substrate and a fabrication method thereof, an array substrate motherboard, and a display device are disclosed. The array substrate includes a display region and a bonding region outside the display region. The array substrate further includes: a bonding electrode, located in the bonding region and spaced apart from an outer edge of the bonding region; and an electrostatic barrier line, the electrostatic barrier line has one end electrically connected with the bonding electrode, and the other end extends to the outer edge of the bonding region, and resistivity of the electrostatic barrier line is greater than resistivity of the bonding electrode. | 2022-07-14 |
20220223679 | DISPLAY DEVICE - A display panel includes pixels and a driver IC pad area; a driver IC on the driver IC pad area of the display panel; first input pads and first output pads that overlap the driver IC pad area; a flexible printed circuit adjacent to the driver IC pad area on the display panel; first output test pads that overlap the flexible printed circuit, and are respectively extended to the first output pads; and first input extending wires that overlap the flexible printed circuit, are respectively extended to the first input pads, and are between the first output test pads. | 2022-07-14 |
20220223680 | MULTILAYER STRUCTURE AND SEMICONDUCTOR DEVICE - Provided is a laminated structure that has a crystalline film having a large area, which is useful for a semiconductor device, etc., and having a good film thickness distribution in which the film thickness is 30 μm or less, and that has excellent heat dissipation. In a laminated structure in which a crystal film containing a crystalline metal oxide as a main component is laminated on a support directly or with another layer therebetween, the support has a thermal conductivity of 100 W/m·K or more at room temperature, and the crystal film has a corundum structure. Furthermore, the film thickness of the crystal film is 1 μm to 30 μm, the area of the crystal film is 15 cm | 2022-07-14 |
20220223681 | VERTICAL MOSFET - A vertical MOSFET having a compound semiconductor layer is provided, the vertical MOSFET comprising a gate electrode, a gate insulating film provided between the gate electrode and the compound semiconductor layer, a drift region provided directly in contact with at least a part of the gate insulating film and being a part of the compound semiconductor layer, and a high resistance region provided at least in the drift region, is positioned below at least a part of the gate insulating film, and has a higher resistance value per unit length than that of the drift region. | 2022-07-14 |
20220223682 | SEMICONDUCTOR ELEMENT - Provided is a semiconductor element including; a semiconductor film; and a porous layer disposed on a first surface side of the semiconductor film or a second surface side opposite from the first surface side, a porosity of the porous layer being no more than 10%. | 2022-07-14 |
20220223683 | INTEGRATED GUARD STRUCTURE FOR CONTROLLING CONDUCTIVITY MODULATION IN DIODES - A microelectronic device includes an integrated guard structure diode on the substrate. The integrated guard structure diode includes a first terminal of the diode, a second terminal of the diode, and a guard structure. The guard structure is between the first terminal of the diode and the second terminal of the diode. The first terminal of the diode and guard structure are electrically connected to each other. An optional switching element may provide selective electrical connection between the first terminal of the diode and the guard structure. Adding a guard structure electrically connected first terminal of the diode, with the guard structure between the first terminal of the diode and the second terminal of the diode provides higher break down voltage than a diode without a guard structure. | 2022-07-14 |
20220223684 | Gate Air Spacer Protection During Source/Drain Via Hole Etching - A semiconductor device includes a gate disposed over a substrate. A source/drain is disposed in the substrate. A conductive contact is disposed over the source/drain. An air spacer is disposed between the gate and the conductive contact. A first component is disposed over the gate. A second component is disposed over the air spacer. The second component is different from the first component. | 2022-07-14 |
20220223685 | SEMICONDUCTOR STRUCTURE - A semiconductor structure includes a substrate, a passive device and an active device over the substrate. The active device is formed in the first region of the substrate, and the passive device is formed in the second region of the substrate. The semiconductor structure further includes a passivation layer that covers the top surface of the passive device. The passivation layer has an opening that exposes the active device. | 2022-07-14 |
20220223686 | SEAL MATERIAL FOR AIR GAPS IN SEMICONDUCTOR DEVICES - The present disclosure relates to a semiconductor device including first and second terminals formed on a fin region and a seal layer formed between the first and second terminals. The seal layer includes a silicon carbide material doped with oxygen. The semiconductor device also includes an air gap surrounded by the seal layer, the fin region, and the first and second terminals. | 2022-07-14 |
20220223687 | Nanoscale Thin Film Structure and Implementing Method Thereof - A nanoscale thin film structure and implementing method thereof, and, more specifically, a nanoscale thin film structure of which target structure is designed with quantized thickness, and a method to implement the nanoscale thin film structure by which the performance of the manufactured nanodevice can be implemented the same as the designed performance, thereby applicable to high sensitivity high performance electronic/optical sensor devices. | 2022-07-14 |
20220223688 | FIELD EFFECT TRANSISTOR (FET) STACK AND METHODS TO FORM SAME - The disclosure provides a field effect transistor (FET) stack with methods to form the same. The FET stack includes a first transistor over a substrate. The first transistor includes a first active semiconductor material including a first channel region between a first set of source/drain terminals, and a first gate structure over the first channel region. The first gate structure includes a first gate insulator of a first thickness above the first channel region. A second transistor is over the substrate and horizontally separated from the first transistor. A second gate structure of the second transistor may include a second gate insulator of a second thickness above a second channel region, the second thickness being greater than the first thickness. A shared gate node may be coupled to each of the first gate structure and the second gate structure. | 2022-07-14 |
20220223689 | Methods Of Forming Epitaxial Source/Drain Features In Semiconductor Devices - A semiconductor structure includes a semiconductor fin disposed over a substrate, a metal gate stack disposed over the semiconductor fin, an epitaxial source/drain (S/D) feature disposed over the semiconductor fin and adjacent to the metal gate stack, and a dielectric feature embedded in the semiconductor fin, where a bottom surface of the epitaxial S/D feature is disposed on a top surface of the dielectric feature, and where sidewalls of the epitaxial S/D feature extend to define sidewalls of the dielectric feature. | 2022-07-14 |
20220223690 | Method of Forming Fully Strained Channels - A method includes forming an N well and a P well in a substrate; depositing a first layer having silicon over the N well and the P well; depositing a first dielectric layer over the first layer; forming a resist pattern over the first dielectric layer, the resist pattern providing an opening directly above the N well; etching the first dielectric layer and the first layer through the opening, leaving a first portion of the first layer over the N well; removing the resist pattern; and epitaxially growing a second layer having silicon germanium (SiGe) over the first portion of the first layer. The epitaxially growing the second layer includes steps of (a) performing a baking process, (b) depositing a silicon seed layer, and (b) depositing a SiGe layer over the silicon seed layer, wherein the steps (a), (b), and (c) are performed under about a same temperature. | 2022-07-14 |
20220223691 | MOSFET DEVICE WITH UNDULATING CHANNEL - A SiC MOSFET device with alternating p-well widths, including an undulating channel, is described. The undulating channel provides current paths of multiple widths, which enables optimization of on-resistance, transconductance, threshold voltage, and channel length. The multi-width p-well region further defines corresponding multi-width Junction FETs (JFETs). The multi-width JFETs enable improved response to a short-circuit event. A high breakdown voltage is obtained by distributing a high electric field in a JFET of a first width into a JFET of a second width. | 2022-07-14 |
20220223692 | GALLIUM NITRIDE POWER DEVICE AND MANUFACTURING METHOD THEREOF - A gallium nitride power device, including: a gallium nitride substrate; cathodes; a plurality of gallium nitride protruding structures arranged on the gallium nitride substrate and between the cathodes, a groove is formed between adjacent gallium nitride protruding structures; an electron transport layer, covering a top portion and side surfaces of each of the gallium nitride protruding structures; a gallium nitride layer, arranged on the electron transport layer and filling each of the grooves; a plurality of second conductivity type regions, where each of the second conductivity type regions extends downward from a top portion of the gallium nitride layer into one of the grooves, and the top portion of each of the gallium nitride protruding structures is higher than a bottom portion of each of the second conductivity type regions; and an anode, arranged on the gallium nitride layer and the second conductivity type regions. | 2022-07-14 |
20220223693 | EFFECTIVE WORK FUNCTION TUNING VIA SILICIDE INDUCED INTERFACE DIPOLE MODULATION FOR METAL GATES - A method includes providing a structure having a substrate and a channel layer over the substrate; forming a high-k gate dielectric layer over the channel layer; forming a work function metal layer over the high-k gate dielectric layer; forming a silicide layer over the work function metal layer; annealing the structure such that a first portion of the work function metal layer that interfaces with the high-k gate dielectric layer is doped with silicon elements from the silicide layer; removing the silicide layer; and forming a bulk metal layer over the work function metal layer. | 2022-07-14 |
20220223694 | TRANSISTOR WITH MULTI-LEVEL SELF-ALIGNED GATE AND SOURCE/DRAIN TERMINALS AND METHODS - Disclosed are a transistor and a method for forming the transistor. The method includes concurrently forming gate and source/drain openings through an uppermost layer (i.e., a dielectric layer) in a stack of layers. The method can further include: depositing and patterning gate conductor material so that a first gate section is in the gate opening and a second gate section is above the gate opening and so that the source/drain openings are exposed; extending the depth of the source/drain openings; and depositing and patterning source/drain conductor material so that a first source/drain section is in each source/drain opening and a second source/drain section is above each source/drain opening. Alternatively, the method can include: forming a plug in the gate opening and sidewall spacers in the source/drain openings; extending the depth of source/drain openings; depositing and patterning the source/drain conductor material; and subsequently depositing and patterning the gate conductor material. | 2022-07-14 |
20220223695 | METHOD AND STRUCTURE FOR METAL GATE BOUNDARY ISOLATION - A method includes depositing a gate dielectric layer; depositing a work-function (WF) metal layer over the gate dielectric layer; and etching the WF metal layer through an etch mask, thereby removing the first portion of the WF metal layer while keeping the second portion of the WF metal layer, wherein a sidewall of the second portion of the WF metal layer is exposed. The method further includes forming a first barrier on the sidewall of the second portion of the WF metal layer and depositing a gate metal layer. A first portion of the gate metal layer is deposited over the gate dielectric layer, a second portion of the gate metal layer is deposited over the first barrier and the second portion of the WF metal layer. The first barrier is disposed between the first portion of the gate metal layer and the second portion of the WF metal layer. | 2022-07-14 |
20220223696 | METHOD FOR MANUFACTURING POWER SEMICONDUCTOR DEVICE - Disclosed is a method for manufacturing a power semiconductor device. The method includes forming a lower active layer on a substrate, forming an upper active layer on both sides of the lower active layer, forming a source electrode, a drain electrode, and a gate electrode on the upper active layer and the lower active layer, and forming a heat dissipating and electrical ground electrode penetrating the substrate and the lower active layer and connected to a lower surface of the lower active layer. The upper active layer may be epitaxially grown at a high doping concentration by a selective deposition method using a mask layer that exposes a portion of the lower active layer as a blocking layer. | 2022-07-14 |
20220223697 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURE - A semiconductor device is provided, including a substrate having a first epitaxial layer arranged thereon and a voltage blocking element arranged in the first epitaxial layer, a second epitaxial layer arranged on the first epitaxial layer, and a vertical switching element arranged in the second epitaxial layer. | 2022-07-14 |
20220223698 | WRAPAROUND CONTACT TO A BURIED POWER RAIL - An approach to form a semiconductor structure with a buried power rail. The semiconductor structure includes a buried power rail in a semiconductor substrate where a buried contact contacts to a first portion of a top surface of the buried power rail to a source/drain of a semiconductor device. Additionally, the semiconductor structure includes a first portion of a top surface of the buried contact that is below a top surface of the source/drain of the semiconductor device and a portion of a bottom surface of the buried contact that is in a cavity formed in the source/drain of the semiconductor device. | 2022-07-14 |
20220223699 | RING TRANSISTOR STRUCTURE - The present disclosure relates to a transistor device. The transistor device includes a plurality of first source/drain contacts disposed over a substrate. A plurality of gate structures are disposed over the substrate between the plurality of first source/drain contacts. The plurality of gate structures wrap around the plurality of first source/drain contacts in a plurality of closed loops. A second source/drain contact is disposed over the substrate between the plurality of gate structures. The second source/drain contact continuously wraps around the plurality of gate structures as a continuous structure. | 2022-07-14 |
20220223700 | RADIO FREQUENCY TRANSISTOR AMPLIFIERS HAVING WIDENED AND/OR ASYMMETRIC SOURCE/DRAIN REGIONS FOR IMPROVED ON-RESISTANCE PERFORMANCE - A gallium nitride-based RF transistor amplifier comprises a semiconductor layer structure comprising a barrier layer on a channel layer, first and second source/drain regions in the semiconductor layer structure, first and second source/drain contacts on the respective first and second source/drain regions, and a longitudinally-extending gate finger that is between the first and second source/drain contacts. The first and second source/drain contacts each has an inner sidewall that faces the gate finger and an opposed outer sidewall. The first source/drain region extends a first distance from a lower edge of the inner sidewall of the first source/drain contact towards the second source/drain region along a transverse axis that extends parallel to a plane defined by the upper surface of the semiconductor layer structure, and extends a second, smaller distance from a lower edge of the outer sidewall of the first source/drain contact away from the second source/drain region. | 2022-07-14 |
20220223701 | SEMICONDUCTOR STRUCTURE AND FABRICATION METHOD THEREOF - A semiconductor structure includes a base substrate including a first region and a second region. The semiconductor further includes a first fin member located over the first region, a second fin member located over the second region, a first dummy gate across a surface of the first fin member, and a second dummy gate across a surface of the second fin member. A first opening is formed in the first fin member located on each side of the first dummy gate, a second opening is formed between two adjacent first channel layers, a third opening is formed in the second fin member located at each side of the second dummy gate, and a fourth opening is formed between two second channel layers. The semiconductor structure still further includes a first inner spacer located in the second opening, and a second inner spacer located in the fourth opening. | 2022-07-14 |
20220223702 | METHOD FOR MANUFACTURING AN INTEGRATED CIRCUIT DEVICE - An integrated circuit device including a substrate; a fin-type active region protruding from the substrate; a gate line intersecting the fin-type active region and covering a top surface and side walls thereof; a gate insulating capping layer covering the gate line; source/drain regions at sides of the gate line on the fin-type active region; first conductive plugs connected to the source/drain regions; a hard mask layer covering the first conductive plugs; and a second conductive plug between the first conductive plugs, the second conductive plug connected to the gate line by passing through the gate insulating capping layer and having a top surface higher than the top surface of each first conductive plug, wherein the hard mask layer protrudes from the first conductive plugs and toward the second conductive plug so that a portion of the hard mask layer overhangs from an edge of the first conductive plugs. | 2022-07-14 |
20220223703 | METHOD FOR FORMING SHIELDING POLYSILICON SIDEWALL FOR PROTECTING SHIELDED GATE TRENCH METAL-OXIDE-SEMICONDUCTOR FIELD EFFECT TRANSISTOR - The present application provides a method for forming a sidewall protection layer in a heavily N-type doped shielding polysilicon for reducing gate to source leakage in a shielded gate trench metal-oxide-semiconductor field effect transistor (SGT MOSFET). In the process of forming a shielding polysilicon sidewall is manufactured by using a secondary oxidation layer forming process, so as to increase a thickness of an oxide in a top region of the shielding polysilicon and a thickness of an oxide of a trench sidewall in a transition region between the shielding polysilicon and an N-type doped gate polysilicon to solve the problem of serious gate to source leakage current. | 2022-07-14 |