28th week of 2010 patent applcation highlights part 22 |
Patent application number | Title | Published |
20100177514 | LED ILLUMINATING DEVICE AND LAMP UNIT THEREOF - An LED illuminating device includes a mounting module and a lamp unit mounted in the mounting module. The lamp unit includes a light-emitting module and a heat sink. The light-emitting module includes a light source having a plurality of LEDs, and a light penetrable cover located below the light source and defining a plurality of air venting holes therein. The heat sink includes an elongated base defining a plurality of air exchanging holes therein and a plurality of fins. The base has an outer convex surface and an opposite inner concave surface defining an elongated recess. The light source is received in the recess and thermally attached to the concave surface. Air flows into and out of a chamber defined between the base and the cover via the venting holes of the cover and the air exchanging holes of the base. | 2010-07-15 |
20100177515 | MODULAR LED LIGHT SYSTEM AND METHOD - A modular device and system for formation of an LED based light bulb. The formed bulb is assembled from interchangeable components which adapted it for engagement to any of a plurality of conventional bulb light fixture connectors. Diffusors and hoods are also attachable to change the diffusion and focus of light emitted from the formed bulb. A plurality of different circuit boards may be engaged to a socket positioned on a heat sink to increase or decrease emitted light. The socket will only electrically engage the circuit board if the heat sink will dissipate the anticipated heat generated by the circuit board. | 2010-07-15 |
20100177516 | Illuminated Cymbal - An illuminated cymbal, including: a light transmitting cymbal body; top and bottom coverings on opposite sides of portions of the cymbal body; a light source mounted to emit light into the cymbal body, wherein the light source is positioned such that the light is reflected between the top and bottom coverings to reflect radially outwards through the cymbal body to illuminate the cymbal body; and a striking sensor pad mounted on top of the cymbal body. | 2010-07-15 |
20100177517 | SAFETY FLAG - A safety flag includes reflective material, a light source and a controller. The safety flag meets legal requirements when used for extended loads in vehicles in day and night use. | 2010-07-15 |
20100177518 | LONG-PASS OPTICAL FILTER MADE FROM NANOFIBERS - An optical device having a mat including plural nanofibers configured to transmit light having wavelengths above a cutoff wavelength and to reject light at wavelengths below the cutoff wavelength. The nanofibers have an average fiber diameter comparable in size to the cutoff wavelength. | 2010-07-15 |
20100177519 | ELECTRO-HYDRODYNAMIC GAS FLOW LED COOLING SYSTEM - The present invention relates to cooling systems, and in particular to cooling systems providing forced convective gaseous flow for dissipating heat off of light-emitting diodes (LED). According to one aspect, a cooling system employs a heat sink in combination with an EHD pumping mechanism such as corona wind or micro-scale corona wind or by a temporally controlled ion-generation technique. For LEDs a channel-array structure can be employed to embody the heat sink. The EHD pumps are located at the inlet or outlet of the heat sink channels. Many advantages are achieved by the cooling system of the invention, including that the entire system can have similar or better performance than a conventional heat sink and fan system but with one-tenth the volume and weight and can operate silently. The present invention also relates to a method of fabricating a micro-channel heat sink employing EHD gas flow for use in LED cooling. | 2010-07-15 |
20100177520 | FOLDABLE REFLECTOR SCREEN - A foldable reflector screen includes a flexible, cloth-like reflective element having an inside and an outside, a supporting and tensioning structure arranged to support the reflective element on the outside, and a carrier element including at least one lamp and mounting the supporting and tensioning structure. The reflector screen has an open state in which the reflective element forms an essentially rotationally symmetrical body having an axis of rotation and has a light outlet opening. The reflective element comprises at least two reflective sections. The two reflective sections have in each case a different geometrical shape in a section containing the axis of rotation of the reflective element. | 2010-07-15 |
20100177521 | Led lamp - An LED lamp has a metal housing, a heat pipe and an LED. The metal housing has an outer surface, an inner surface, a bottom and an opening defined by an inner edge. The heat pipe engages the inner surface, the bottom and the inner edge of the metal housing. The LED is attached to the bottom portion of the heat pipe. The heat pipe rapidly transports heat generated by the LED to the metal housing which then transfers heat to the environment. The heat pipe makes effective heat transportation possible and allows the use of high-power LEDs or multiple LED's within one lamp. | 2010-07-15 |
20100177522 | LED LAMP - An LED lamp has a base, a tubular conductor, a bulb and at least one LED. The base is metallic and has an electrical connector. The tubular conductor is filled with a fluid and mounted on the base and has a distal end and a proximal end. The bulb is pellucid and connected to the base. The at least one LED is mounted on the distal end of the tubular conductor and electrically connected to the connector of the base. The fluid in the tubular conductor may vaporize close to operating temperatures of the LED so transports heat away from the LED quickly and efficiently so allowing high power or multiple LEDs to be implemented, so improving brightness of the LED lamp and commercial applications. | 2010-07-15 |
20100177523 | REARVIEW MIRROR ASSEMBLY INCLUDING OPTICAL FIBER SIGNALING - A rearview mirror assembly for use on a vehicle, comprises a housing configured to be coupled to the vehicle, a mirror coupled within the housing, and a first optical fiber coupled to the housing and visible from the exterior thereof for providing a warning that indicates that the vehicle is turning, braking, and the like. | 2010-07-15 |
20100177524 | Lighting Device - Lighting device for emission of light through a windshield of a vehicle consisting of at least one lighting unit intended to be temporarily mounted on the inside of a windshield with at least one fastening device. The lighting unit consists of at least one reflector, one lamp and at least one seal between the lighting unit and the windshield. The lighting unit is powered by electric energy and the lamp's on and off switch is controlled by at least one sensor designed to detect turned on high-beams which wirelessly sends control signals to the lighting unit. The lighting device consists of a function with which the light's illumination can be adjusted and with which the light can be completely or partially blocked. | 2010-07-15 |
20100177525 | VEHICLE LIGHTING DEVICE - A conventional vehicle lighting device entails difficulty in smoothly dimming a part at a downside of a cutoff line of a light distribution pattern. A shade-cum additional reflector includes a cutoff line forming portion which forms an opposite lane side cutoff line, an oblique cutoff line, and a cruising lane side cutoff line, of a light distribution pattern for passing, i.e., a horizontal portion, an inclined portion, and a corner portion, of a protrusion. Of an additional reflecting surface, in proximal to at least the horizontal portion of the protrusion, a spherical convex portion is provided as a diffusion portion for diffusing and reflecting a part of the cut off reflected light onto a side of a projecting lens. As a result, a lighting device of the present invention allows for smooth dimming of a part at a downside of at least the opposite lane side cutoff line, of a light distribution pattern for passing. | 2010-07-15 |
20100177526 | OPTICAL LENS AND VEHICLE LIGHTING DEVICE USING THE SAME - An optical lens for use in a vehicle light can be compact and less expensive and has an outer appearance that has a high commercial value and achieves a high light utilization efficiency. The optical lens can include a light incident surface that receives light from a light source and a light output surface to output the light. The light incident surface can include a center light incident surface formed at its center and being convex toward the light source with a plurality of prisms with a polygonal shape formed radially from its center to its periphery. The light output surface can include a toroidal surface corresponding to the center light incident surface and a surrounding light output surface corresponding to the prisms. | 2010-07-15 |
20100177527 | LIGHT EMITTING MODULE, FABRICATION METHOD THEREFOR, AND LAMP UNIT - In a light emitting module board, an electrode receiving the supply of current for light emission is provided in the light emitting surface of a semiconductor light emitting device. A light wavelength conversion member is a plate-like member mounted on the light emitting surface, and emits light after converting the wavelength of the light emitted by the semiconductor light emitting device. A relay electrode is provided in the surface of the light wavelength conversion member. The relay electrode extends from a position in contact with the electrode to an exposed position in the external space in a state where the light wavelength conversion member is mounted on the light emitting surface. The relay electrode is provided so that the upper part of the relay electrode, which is the exposed position, extends to a position located opposite to the lower part of the relay electrode which is the contacted position. | 2010-07-15 |
20100177528 | LED Vehicle Eyelid Apparatus - A vehicular LED headlamp eyelid apparatus is disclosed. The vehicular headlamp eyelid apparatus is attached to a vehicle's headlamp and comprises a plurality of LED lights capable of illuminating in patterns signaled by the vehicle. The occlusion resulting from one or more segments of the LED eyelids modifies the overall appearance of the headlamp. The vehicular LED headlamp eyelid is made at least in part of lightweight material such that there results in little impact upon the drag profile of the vehicle. | 2010-07-15 |
20100177529 | AUTOMOBILE BRAKE LAMP - An automobile brake lamp for an automobile having a front portion, a brake and a brake pedal adapted to actuate the brake to decelerate the automobile when depressed, the brake lamp being mounted on the front portion of the automobile in a position that is visible from the front of the automobile, and the automobile brake lamp being configured to illuminate when the brake pedal is depressed so that pedestrians who are positioned in front of the automobile may aware whether or not the automobile is braking. | 2010-07-15 |
20100177530 | VEHICLE HEADLINER MODULE - A module adapted to be mounted in a vehicle interior is disclosed which has a housing with two switch-controllable map lamps mounted symmetrically in the housing and a centrally-located aperture in the housing adapted to accept one of a speaker assembly and a dome lamp. When the vehicle is equipped with the speaker, the map lamps are switched on when a door switch indicating that a door is open, thereby fulfilling the function of the dome lamp. The map lamps are additionally activated by a switch coupled to the lamp or mounted in the module. When the vehicle is not equipped with the speaker, a dome lamp is mounted in the aperture. | 2010-07-15 |
20100177531 | MOBILE DEVICE WITH ILLUMINATION - A mobile device is provided comprising a light guide modified at a plurality of locations to let light guided in the light guide at least partially escape. Furthermore, methods and apparatuses for manufacturing such mobile devices are provided. | 2010-07-15 |
20100177532 | LED LENS - A light modifier for an LED producing light about a central axis is provided. The light modifier includes a lens defining an indentation. The indentation is angled relative to the central axis by an amount less than a complementary angle of a critical angle of the lens along the indentation. The lens can reduce the appearance of a bright spot created by the LED. | 2010-07-15 |
20100177533 | LARGE AREA LIGHT PANEL AND SCREEN - Embodiments of a panel lighting apparatus and methods of its manufacture are described. In one embodiment, the apparatus can include a light source, an at least partially transparent panel comprising a planar front surface and a planar back surface, the panel disposed in conjunction with the light source such that light from the light source is input into at least one edge of the panel and guided therein, and a plurality of light extraction dots disposed on the planar back surface, the plurality of light extraction dots configured to reflect light incident on the planar back surface and extract light from the light source propagating in the panel through the planar front surface. | 2010-07-15 |
20100177534 | BACKLIGHT PANEL EMPLOYING WHITE LIGHT EMITTING DIODE HAVING RED PHOSPHOR AND GREEN PHOSPHOR - Disclosed is a backlight panel employing a white light emitting diode. The white light emitting diode includes a blue light emitting diode chip and red and green phosphors positioned over the blue light emitting diode chip. Accordingly, since the backlighting can be performed using white light with distinct red, green and blue wavelengths, the color reproducibility can be enhanced. Further, since the white light can be implemented with a single light emitting diode, the manufacturing costs and thickness of the backlight panel can also be reduced. | 2010-07-15 |
20100177535 | SURFACE ILLUMINATING LIGHT SOURCE DEVICE AND SURFACE ILLUMINATING DEVICE - Uniform illuminating light is obtained on a surface at a prescribed distance from a radiation surface without increasing the thickness in a light radiation direction by using the light from the light source highly efficiently. A surface illuminating light source device is provided with a light source for radiating light; a light guide body propagating light from the light source and having a radiation surface at a prescribed position in the radiation direction; a casing closing the light guide body except the radiation surface and having the light source arranged substantially at the center; an inner reflection section arranged between the casing and the light guide body and having a reflection surface which reflects light propagating inside the light guide body; and a radiation side reflection section having an outer reflection section which is arranged on the radiation surface and has a reflection surface that reflects light propagating inside the light guide body at a prescribed rate and an opening section which is formed on the outer reflection section and through which reflection light reflected at least once on one of the reflection surfaces among the light from the light source passes. | 2010-07-15 |
20100177536 | DC-DC POWER SUPPLY APPARATUS METHOD FOR IMPROVING DC-DC POWER SUPPLY APPARATUS - A Direct Current to Direct Current (DC-DC) power supply apparatus includes: a transformer; a transformer primary circuit; a transformer secondary circuit, which includes a rectifier circuit capable of transformation and configured to convert a square wave voltage output by the transformer into a DC output voltage; and a control unit, which controls the transformer secondary circuit to stabilize the DC output voltage into a required value according to the DC output voltage. | 2010-07-15 |
20100177537 | POWER SUPPLY CIRCUIT AND POWER SUPPLY SYSTEM - To provide a power supply circuit which can be applied worldwide without using a high withstand voltage switching element and can supply a load device with stable power. A charging section is arranged between a turn-off capacitor and a load coil. The charging section has the anode connected to the positive terminal of a feedback coil and the cathode connected to the cathode of a zener diode. Thus, when a voltage of a commercial power supply is high, the charging section operates, the turn-off capacitor is quickly charged, an on-period of a transistor is shortened, and an excessive voltage is prevented from being applied between the drain and the source of the transistor. At the same time, an output characteristic indicating relationship between the voltage of the commercial power supply and a current flowing in the load device is permitted to be flat. | 2010-07-15 |
20100177538 | System and Method for Power Supply Testing - In one embodiment, a method of verifying a component coupled to an output of a power supply includes measuring a frequency response from a control input of the power supply to the output of the power supply. The method also includes comparing the frequency response to a predetermined metric based on the measuring. The component is determined to be valid if the frequency response falls within the predetermined metric. | 2010-07-15 |
20100177539 | ELECTRICAL APPLIANCE AND POWER SUPPLY THEREOF - A power supply includes an adapter and a delay module. The adapter is operable to receive an input voltage and convert the input voltage into a first operation voltage to power a load controlled by a control unit. The adapter includes a filter capacitor configured to smooth the first operation voltage. The delay module detects the input voltage, and supplies a second operation voltage to the control unit when receiving the input voltage. The delay module continues supplying the second operation voltage to the control unit for a predetermined time period after the input voltage is no longer supplied to the adapter. As a result, the load operates for at most the predetermined time period and the filter capacitor discharges via the load after the input voltage is removed. | 2010-07-15 |
20100177540 | POWER CONVERSION APPARATUS - In a power conversion apparatus that boosts a solar light voltage, converts it to AC and supplies AC power to a load or system, power loss is reduced and efficiency is improved. An inverter unit, in which AC sides of three single-phase inverters receive DC power from respective sources with a voltage ratio of 1:3:9 as respective inputs are connected in series. Gradational output voltage control of an output voltage is carried out using the sum of the respective generated AC voltages. Also, a solar light voltage is boosted by a chopper circuit to generate the highest voltage DC power source. When the solar light voltage exceeds a predetermined voltage, the boosting of the chopper circuit is stopped, thereby reducing power loss due to the boosting. | 2010-07-15 |
20100177541 | VOLTAGE-SOURCED HVDC SYSTEM WITH MODULATION FUNCTION - A voltage-sourced High-Voltage Direct Current (HVDC) apparatus, which converts 3-phase AC voltage from a 3-phase AC power source into high voltage DC through a rectifier including switching elements, is provided. In the apparatus, a rectifier controller receives detected 3-phase currents, apparent power, and active power and generates D and Q-axis signals. A D/Q controller receives the signals and generates active power D-axis signal and apparent power Q-axis signal. A PWM unit generates PWM on/off signals for turning on/off the switching elements based on output signals from the D/Q controller. The D/Q controller includes a rotary converter to convert the D and Q-axis signals into AC signals and D and Q-axis order units coupled thereto, and generates the D and Q-axis signals through the order units. The PWM unit converts the D and Q-axis signals into 3-phase AC signals and compares them with 3-phase triangular waves to generate on/off signals for turning on/off the switching elements. | 2010-07-15 |
20100177542 | POWER TRANSISTOR CHIP WITH BUILT-IN START-UP TRANSISTOR AND APPLICATION CIRCUIYT THEREOF - A power transistor chip with a built-in start-up transistor and an application circuit thereof provides a junction field effect transistor in association with a metal oxide semiconductor field effect transistor to act as a start-up circuit of an AC/DC voltage converter. The start-up circuit can be turned off after the PWM circuit of the AC/DC voltage converter operates normally to conserve the consumption of the power. Besides, the junction field effect transistor and the metal oxide semiconductor field effect transistor are built in the power transistor chip. Because the junction field effect transistor and the metal oxide semiconductor field effect are fabricated with the same manufacturing process as the power transistor, it is capable of simplifying the entire process and lowering the production cost due to no additional mask and manufacturing process. | 2010-07-15 |
20100177543 | Power Converter Mounting Assemblies - The present disclosure relates mounting assemblies for a vehicle DC-to-DC power converter. The mounting assemblies can include a bracket having a first end configured to be fastened to a DC-to-DC power converter housing and a second end configured to be fastened to a vehicle structural member. The mounting assemblies can be utilized in hybrid, fuel cell and/or electric vehicles. | 2010-07-15 |
20100177544 | Generating ROM bit cell arrays - A method of generating a ROM bit cell array layout is provided, the method comprising the steps of: inputting a predetermined memory architecture having a predetermined positioning of bit lines and virtual ground lines, said memory architecture comprising a plurality of columns of memory cells, each column of memory cells being located between its own associated bit line and its own associated virtual ground line, and adjacent memory cells in each column of memory cells sharing a common connection to either said associated bit line or said associated virtual ground line; evaluating a possible range of width of active area of each of said columns of memory cells, in dependence on said predetermined positioning of bit lines and virtual ground lines; selecting a final width of active area in dependence on at least one performance characteristic associated with said final width of active area; and generating said ROM bit cell array layout according to said final width of active area. Thus the system designer can reuse an existing memory architecture, yet still retain an advantageous degree of flexibility with regard to performance characteristic selection of the final ROM bit cell array. | 2010-07-15 |
20100177545 | MEMORY CIRCUITS AND ROUTING OF CONDUCTIVE LAYERS THEREOF - A memory circuit includes at least one memory cell for storing a datum. The memory cell is coupled with a word line, a bit line, a bit line bar, a first voltage line, and a second voltage line. The memory circuit includes a first conductive layer, a second conductive layer coupled with the first conductive layer, a third conductive layer coupled with the second conductive layer. The third conductive layer is routed for the word line and is free from including the bit line, the bit line bar, the first voltage line, and the second voltage line within the memory cell. | 2010-07-15 |
20100177546 | SEMICONDUCTOR DEVICE - A semiconductor device includes a memory cell array area, a peripheral circuit area on a periphery of the memory cell array area, and a boundary area having a specific width between the memory cell array area and the peripheral circuit area, the memory cell array area including a cell area including nonvolatile semiconductor memory cells, linear wirings extending from inside of the cell area to an area outside the cell area, and lower layer wirings in a lower layer than the linear wirings in the boundary area and electrically connected to the linear wirings, and wiring widths of the lower layer wirings being larger than widths of the linear wirings, the peripheral circuit area including a patterns electrically connected to the linear wirings via the lower layer wirings, the boundary area failing to be provided with the linear wirings and a wiring in same layer as the linear wirings. | 2010-07-15 |
20100177547 | MEMORY DEVICE AND MEMORY ACCESS METHOD - Provided is a memory device in which the circuit structure is simplified while the functions of a memory including an OTP memory and a memory including a pseudo-MTP memory are maintained. A memory device includes a plurality of memory sets each including a mark bit storage area for storing a mark bit, which indicates that an object is deleted data, and a data bit storage area for storing data to be stored, the memory device being built from a one time programmable (OTP) memory including an OTP memory block and a pseudo-MTP memory block, the OTP memory block containing a given number of memory sets selected out of the plurality of memory sets to operate as an OTP memory, the pseudo-MTP memory block containing the rest of the plurality of memory sets which remains after the memory sets of the OTP memory block are excluded and operates as a pseudo-MTP memory. The mark bit is written in advance in the mark bit storage area of the OTP memory block. | 2010-07-15 |
20100177548 | MULTILEVEL ONE-TIME PROGRAMMABLE MEMORY DEVICE - A multilevel one-time programmable memory device includes a plurality of memory cells, wherein each of the plurality of memory cells includes: a first electrode to which a first voltage is applied, a second electrode to which a second voltage is applied and a plurality of fuse lines performing a fusing operation according to a voltage difference between the first electrode and the second electrode. The plurality of fuse lines are connected to each other between the first electrode and the second electrode. In addition, at least one of the first electrode and the second electrode is formed such that the first electrode and the second electrode have different valid line lengths from each other therebetween so that the plurality of fuse lines have different resistances from each other. | 2010-07-15 |
20100177549 | Silicide-silicon oxide-semiconductor antifuse device and method of making - An antifuse contains a first silicide layer, a grown silicon oxide antifuse layer on a first surface of the first silicide layer, and a first semiconductor layer having a first surface in contact with the antifuse layer. | 2010-07-15 |
20100177550 | NONVOLATILE SEMICONDUCTOR MEMORY - A nonvolatile semiconductor memory according to an aspect of the invention includes a memory cell array and a power supply circuit. The memory cell array includes memory cells each having an insulating film and being programmed to store information by inflicting an electric stress on the insulating film to break the insulating film. The power supply circuit supplies to the memory cell a program voltage for the electric stress depending on a negative temperature coefficient the electric stress. | 2010-07-15 |
20100177551 | BIT SET MODES FOR A RESISTIVE SENSE MEMORY CELL ARRAY - Various embodiments of the present invention are generally directed to a method and apparatus for providing different bit set modes for a resistive sense memory (RSM) array, such as a spin-torque transfer random access memory (STRAM) or resistive random access memory (RRAM) array. In accordance with some embodiments, a group of RSM cells in a non-volatile semiconductor memory array is identified for application of a bit set operation. A bit set value is selected from a plurality of bit set values each separately writable to the RSM cells to place said cells in a selected resistive state. The selected bit set value is thereafter written to at least a portion of the RSM cells in the identified group. | 2010-07-15 |
20100177552 | TABLE-BASED REFERENCE VOLTAGE CHARACTERIZATION SCHEME - Method and apparatus for reading data from a non-volatile memory cell, such as a modified STRAM cell. In some embodiments, at least a first and second memory cell are read for a plurality of resistance values that are used to select and store a voltage reference for each memory cell. | 2010-07-15 |
20100177553 | REWRITABLE MEMORY DEVICE - Memory devices described herein are programmed and erased by physical segregation of an electrically insulating layer out of a memory material to establish a high resistance state, and by re-absorption of at least a portion of the electrically insulating layer into the memory material to establish a low resistance state. The physical mechanism of programming and erasing includes movement of structure vacancies to form voids, and/or segregation of doping material and bulk material, to create the electrically insulating layer consisting of voids and/or dielectric doping material along an inter-electrode current path between electrodes. | 2010-07-15 |
20100177554 | BIPOLAR CMOS SELECT DEVICE FOR RESISTIVE SENSE MEMORY - A resistive sense memory apparatus includes a bipolar select device having a semiconductor substrate and a plurality of transistors disposed in the semiconductor substrate and forming a row or transistors. Each transistor includes an emitter contact and a collector contact. Each collector contact is electrically isolated from each other and each emitter contact is electrically isolated from each other. A gate contact extends along a channel region between the emitter contact and a collector contact. A base contact is disposed within the semiconductor substrate such that the emitter contact and a collector contact is between the gate contact and the base contact. A resistive sense memory cells is electrically coupled to each collector contact or emitter contact and a bit line. | 2010-07-15 |
20100177555 | VARIABLE RESISTANCE NONVOLATILE STORAGE DEVICE - The variable resistance nonvolatile storage device includes a memory cell ( | 2010-07-15 |
20100177556 | ASYMMETRIC STATIC RANDOM ACCESS MEMORY - An asymmetric static random access memory (SRAM) device that includes at least one SRAM cell is provided. The SRAM cell includes the first inverter and the second inverter. The first inverter is coupled between a first power and a ground power, and includes a first output terminal coupled to a first node and a first input terminal coupled to a second node. The second inverter is coupled between the first power and the ground power, and includes a second input terminal coupled to the first node and a second output terminal coupled to the second node. When the first inverter and the second inverter receive current from the first power, the SRAM cell is programmed to a predetermined value in advance according to different conductance levels of the first inverter and the second inverter. | 2010-07-15 |
20100177557 | STT-MRAM CELL STRUCTURES - A magnetic cell structure including a nonmagnetic bridge, and methods of fabricating the structure are provided. The magnetic cell structure includes a free layer, a pinned layer, and a nonmagnetic bridge electrically connecting the free layer and the pinned layer. The shape and/or configuration of the nonmagnetic bridge directs a programming current through the magnetic cell structure such that the cross sectional area of the programming current in the free layer of the structure is less than the cross section of the structure. The decrease in the cross sectional area of the programming current in the free layer enables a lower programming current to reach a critical switching current density in the free layer and switch the magnetization of the free layer, programming the magnetic cell. | 2010-07-15 |
20100177558 | MRAM HAVING VARIABLE WORD LINE DRIVE POTENTIAL - An MRAM of a spin transfer type according to the invention is provided with a memory cell | 2010-07-15 |
20100177559 | METHOD FOR SETTING PCRAM DEVICES - Memory devices and methods for operating such devices are described herein. A method as described herein includes applying a bias arrangement to a memory cell to change the resistance state from a higher resistance state to a lower resistance state. The bias arrangement comprises a first voltage pulse and a second voltage pulse across the phase change memory element, the second voltage pulse having a voltage polarity different from that of the first voltage pulse. | 2010-07-15 |
20100177560 | NON-VOLATILE MEMORY CIRCUIT INCLUDING VOLTAGE DIVIDER WITH PHASE CHANGE MEMORY DEVICES - A memory circuit including a voltage divider with a first phase change memory (PCM) device and a second PCM device coupled to the first PCM device is described. In one embodiment, the first PCM device is in a set resistance state and the second PCM device is in a reset resistance state. Also, in one embodiment, the voltage divider further includes a first switch coupled to the first PCM device and a second switch coupled to the first switch and the second PCM device. In one embodiment, the memory circuit further includes a half latch coupled to the voltage divider and a cascade transistor coupled to the half latch and the voltage divider. | 2010-07-15 |
20100177561 | MEMORY CELL HAVING NONMAGNETIC FILAMENT CONTACT AND METHODS OF OPERATING AND FABRICATING THE SAME - A magnetic cell structure including a nonmagnetic filament contact, and methods of fabricating the structure are provided. The magnetic cell structure includes a free layer, a pinned layer, an insulative layer between the free and pinned layers, and a nonmagnetic filament contact in the insulative layer which electrically connects the free and pinned layers. The nonmagnetic filament contact is formed from a nonmagnetic source layer, also between the free and pinned layers. The filament contact directs a programming current through the magnetic cell structure such that the cross sectional area of the programming current in the free layer is less than the cross section of the structure. The decrease in the cross sectional area of the programming current in the free layer enables a lower programming current to reach a critical switching current density in the free layer and switch the magnetization of the free layer, programming the magnetic cell. | 2010-07-15 |
20100177562 | COMPUTER MEMORY DEVICE WITH MULTIPLE INTERFACES - Various embodiments are generally directed to a method and apparatus associated with operating a first memory device with multiple interfaces and a status register. In some embodiments, a first interface is engaged by a host. A memory device that has a plurality of memory cells comprised of at least a magnetic tunneling junction and a spin polarizing magnetic material is connected to a second interface. A status register is maintained by logging at least an error or busy signal during data transfer operations through the first and second interfaces. | 2010-07-15 |
20100177563 | NONVOLATILE SEMICONDUCTOR MEMORY, METHOD FOR READING OUT THEREOF, AND MEMORY CARD - A nonvolatile semiconductor memory includes: a memory cell unit including a plurality of memory cells having an electric charge accumulation layer and a control electrode, said memory cells being electrically connected in series; a plurality of word lines, each of which is electrically connected to said control electrode of said plurality of memory cells; a source line electrically connected to said memory cells at one end of said memory cell unit; a bit line electrically connected to said memory cells at the other end of said memory cell unit; and a control signal generation circuit, which during a data readout operation staggers a timing for selecting the word line connected to said memory cells of said memory cell unit from a timing for selecting a non-selected word line connected to a non-selected memory. | 2010-07-15 |
20100177564 | METHOD FOR DETECTING FLASH PROGRAM FAILURES - One or more techniques are provided for programming a flash memory device. In one embodiment, the memory device is programmed such that a data pattern written to a page in the memory device has encoded therein an expected count value corresponding to the number of times a first binary value occurs in the data pattern. The data pattern includes the program data and the expected count value, and is written to the page in a single operation. The expected count value may be stored in a count field in the management area of the page. During a page read operation, the expected count value is compared to the actual count of the number of bits having the first binary value in the data area of the page. If the expected count is equal to the actual count, then the program data is determined to be valid. | 2010-07-15 |
20100177565 | METHOD OF OPERATING A FLASH MEMORY DEVICE - A flash memory device is disclosed. The flash memory device includes a memory cell array configured to have memory cells for storing data, and store initial data in a part of the memory cells, a page buffer circuit configured to have page buffers for providing data to be programmed in the memory cell or reading data from the memory cell, a controller configured to control the page buffer circuit so that the initial data stored in the memory cell array are read when operation of the flash memory device is started, discriminate error of the read initial data, and amend the error of the initial data, and an initial data latching circuit for latching the initial data of which the error is amended by the controller. | 2010-07-15 |
20100177566 | Non-volatile memory device having stacked structure, and memory card and electronic system including the same - Provided are a non-volatile memory devices having a stacked structure, and a memory card and a system including the same. A non-volatile memory device may include a substrate. A stacked NAND cell array may have at least one NAND set and each NAND set may include a plurality of NAND strings vertically stacked on the substrate. At least one signal line may be arranged on the substrate so as to be commonly coupled with the at least one NAND set. | 2010-07-15 |
20100177567 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE WHICH CAN ELECTRICALLY REWRITE DATA AND SYSTEM THEREFOR - A nonvolatile semiconductor memory device includes a memory cell, latch circuits, and an arithmetic operation circuit. The memory cell stores data by a difference in threshold voltage. A read operation is performed twice or more on the memory cell under the same read conditions, and the latch circuits store a plurality of read data. The arithmetic operation circuit takes majority decision of the plurality of data stored in the latch circuits and decides data determined by the majority decision as data stored in the memory cell. | 2010-07-15 |
20100177568 | READ MODE FOR FLASH MEMORY - A method for reading a nonvolatile memory array including an array of memory cells, each memory cell including a substrate, a control gate, a charge storage element, a source region and a drain region, includes receiving, at an address register, a read command including an address for a memory cell in the array of memory cells and an indication regarding whether the read command is a full page read command or a partial page read command. A starting address for a page including the received address is identified, wherein the page includes multiple rows of memory cells in the array of memory cells. The address register is reset to the starting address for the page. It is determined whether all memory cells in the page are non-programmed. Data indicative of a non-programmed state of the page is output if it is determined that all memory cells in the page are non-programmed. | 2010-07-15 |
20100177569 | SINGLE POLY EEPROM ALLOWING CONTINUOUS ADJUSTMENT OF ITS THRESHOLD VOLTAGE - A single-poly EEPROM memory device comprises a control gate isolated within a well of a first conductivity type in a semiconductor body of a second conductivity type, first and second tunneling regions isolated from one another within respective wells of the first conductivity type in the semiconductor body, a read transistor isolated within a well of the first conductivity type, and a floating gate overlying a portion of the control gate, the read transistor, and the first and second tunneling regions. The memory device is configured to be electrically programmed by changing a charge on the floating gate that changes the device threshold voltage. In one embodiment, the memory device is configured to be electrically programmed by applying a first potential between the first and second tunneling regions, and a second potential to the control gate, the second potential having a value less than the first potential. | 2010-07-15 |
20100177570 | SEMICONDUCTOR MEMORY DEVICE CAPABLE OF COMPENSATING VARIATION WITH TIME OF PROGRAM VOLTAGE - A voltage generating circuit generates, at a time of write, a first voltage which is higher than a program voltage, and generates an erase voltage at a time of erase. A first transistor has a current path and a gate, and the first voltage generated by the voltage generating circuit is supplied to one end of the current path and the gate of the first transistor. The first transistor outputs the program voltage from the other end of the current path thereof. A driving transistor has one end of a current path thereof connected to a word line, and has a gate supplied with the first voltage. The driving transistor has the other end of the current path supplied with the program voltage. Stress applying portion applies the erase voltage to the other end of the current path of the first transistor at the time of erase. | 2010-07-15 |
20100177571 | MEMORY BANK SIGNAL COUPLING BUFFER AND METHOD - A memory array contains a plurality of banks coupled to each other by a plurality of data lines. Each of the data lines is divided into a plurality of segments within the array. Respective bidirectional buffers couple read data from one of the segments to another in a first direction, and to couple write data from one of the segments to another in a second direction that is opposite the first direction. The data lines may be local data read/write lines that couple different banks of memory cells to each other and to respective data terminals, digit lines that couple memory cells in a respective column to respective sense amplifiers, word lines that activate memory cells in a respective row, or some other signal line within the array. The memory array also includes precharge circuits for precharging the segments of respective data lines to a precharge voltage. | 2010-07-15 |
20100177572 | SEMICONDUCTOR DEVICE CAPABLE OF ADJUSTING PAGE SIZE - A semiconductor device includes a memory cell array comprising a plurality of banks and a page size controller. The page size controller decodes a part of a bank selection address or a power supply voltage and a remaining part of the bank selection address to enable one of the plurality of banks or enable two of the plurality of banks to set a page size of the semiconductor device. | 2010-07-15 |
20100177573 | SEMICONDUCTOR MEMORY DEVICE AND SEMICONDUCTOR MEMORY DEVICE DRIVING METHOD - A memory includes a latch circuit latching data from a first and a second bit lines to a first and a second sense nodes; a first data line reading-out the data from the first sense node to an outside; a second data line reading-out the data from the second sense node to the outside; a first write transistor connected between the first bit line and the first or second data line without via the first and second sense node; and a second write transistor connected between the second bit line and the first or second data line without via the first and second sense node, wherein in a write operation, the first write transistor transmits the data from the first or second data line to the first bit line, or the second write transistor transmits the data from the first or second data line to the second bit line. | 2010-07-15 |
20100177574 | SYSTEM AND METHOD FOR MITIGATING REVERSE BIAS LEAKAGE - The present disclosure includes devices, methods, and systems for programming memory, such as resistance variable memory. One embodiment can include an array of resistance variable memory cells, wherein the resistance variable memory cells are coupled to one or more data lines, a row decoder connected to a first side of the array, a column decoder connected to a second side of the array, wherein the second side is adjacent to the first side, a gap located adjacent to the row decoder and the column decoder, and clamp circuitry configured to control a reverse bias voltage associated with one or more unselected memory cells during a programming operation, wherein the clamp circuitry is located in the gap and is selectively coupled to the one or more data lines. | 2010-07-15 |
20100177575 | Apparatus and method for controlling write access to a group of storage elements - An apparatus and method for controlling write access to a group of storage elements is provided. Each storage element within the group is identified by an n-bit address, and the total number of storage elements in the group is less than 2 | 2010-07-15 |
20100177576 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a sense amplifier, a sense amplifier driving signal driver, and a controller. The sense amplifier is configured to sense and amplify a signal of a bit line and a signal of a complementary bit line in response to a sense amplifier driving signal. The sense amplifier driving signal driver includes a first driving signal driver configured to drive via a transmission line the sense amplifier driving signal in response to a first sense amplifier control signal, and a second driving signal driver configured to drive via the transmission line the sense amplifier driving signal in response to a second sense amplifier control signal. The controller activates the first sense amplifier control signal in response to an active command, and toggles the second sense amplifier control signal while the first sense amplifier control signal is activated. | 2010-07-15 |
20100177577 | SIGNAL TRANSFER APPARATUS AND METHODS - Some embodiments include a number of nodes configured to receive a number of signals. The signals may represent information stored in a number of memory cells of a device such as a memory device. The device may include a number of transfer paths having storage elements coupled between the nodes and an output node. The transfer paths may be configured to transfer a selected signal of the signals from one of the nodes to the output node via one of the transfer paths. The transfer paths may be configured to hold a value of the selected signal in only one of the storage elements. Each of the transfer paths may include only one of the storage elements. Other embodiments including additional apparatus, systems, and methods are disclosed. | 2010-07-15 |
20100177578 | TRI-STATE DRIVER CIRCUITS HAVING AUTOMATIC HIGH-IMPEDANCE ENABLING - Memories, driver circuits, and methods for generating an output signal in response to an input signal. One such driver circuit includes an input stage and an output stage. The input stage receives the input signal and provides a delayed input signal having a delay relative to the input signal. The output stage receives the delayed input signal and further receives the complement of the input signal. The output stage couples an output node to a first voltage in response to a complement of the input signal having a first logic level and couples the output to a second voltage in response to the complement of the input signal having a second logic level. The output stage further decouples the output from the first or second voltage in response to receiving the delayed input signal to provide a high-impedance at the output node. | 2010-07-15 |
20100177579 | SEMICONDUCTOR MEMORY DEVICE HAVING FAULTY CELLS - In response to a read command received by a system interface unit for accessing a plurality of blocks of data stored in said non-volatile semiconductor memory, a controller carries out selective read operations of blocks of data to two memories from the non-volatile semiconductor memory. The controller also carries out parallel operations of data transferring a first block of data, which has already been subjected to error detection and error correction operations by an error correction unit, from one of the two memories to a host system via said system interface unit and of data transferring of a second block of data to be subjected to the error detection and error correction operation, from said non-volatile semiconductor memory to the other of the two memories. | 2010-07-15 |
20100177580 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND OPERATING METHOD THEREOF - Even when memory capacity of a memory that uses a replica bit-line is made higher, fluctuations of a generating timing of a sense-amplifier enable signal are reduced. A semiconductor integrated circuit device comprises a plurality of word lines, a plurality of bit-lines, a plurality of ordinary memory cells, an access control circuit, a plurality of sense-amplifiers, first and second replica bit-lines, first and second replica memory cells, and first and second logic circuits. The first and second replica memory cells are connected to the first and second replica bit-lines, respectively; inputs of the first and second logic circuits are connected to the first and second replica bit-lines, respectively; a sense-amplifier enable signal is generated from an output of the second logic circuit; and this signal is supplied to a plurality of sense-amplifiers. | 2010-07-15 |
20100177581 | Very Small Swing High Performance Asynchronous CMOS Static Memory (Multi-Port Register File) With Power Reducing Column Multiplexing Scheme - The present invention relates to a multi-port register file memory or SRAM including a plurality of storage elements and other circuitry that operate synchronously or asynchronously. The storage elements are arranged in rows and columns and store data. Two read port pairs are coupled to each of the storage elements and a differential sensing device or circuit. The read port is coupled to the storage elements in an isolated manner, enabling a plurality of cells to be arranged in such rows and columns. The sensing device is adapted to sense a small voltage swing. A column mux circuit is coupled to each column and the sensing device. Performance is not degraded unusually as the power supply voltage is reduced due to bus drop or inductive effects. | 2010-07-15 |
20100177582 | Semiconductor Memory Device - A semiconductor memory device is provided. A memory cell array has a plurality of memory cells connected between a plurality of word lines and a plurality of bit-line pairs. A sense amplifier unit has a plurality of sense amplifiers connected with the bit-line pairs respectively and amplifies data of the bit-line pairs to a sensing voltage level. A command decoder decodes a command applied from the outside and outputs the decoded command. A plurality of input/output (I/O) gates electrically connects the bit-line pairs with corresponding I/O line pairs in response to a voltage level applied through a plurality of corresponding column selection lines. A column decoder decodes a column address and drives at least one of the column selection lines to a plurality of different voltages levels. | 2010-07-15 |
20100177583 | SEMICONDUCTOR MEMORY DEVICE, MEMORY SYSTEM INCLUDING MEMORY CONTROLLER, AND REFRESH CONTROL METHOD FOR A SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device has an operation mode in which a read/write operation is performed in response to a command supplied externally in synchronization with a clock, and a power-down mode in which no external read/write command is accepted. The semiconductor memory device performs a refresh operation in response to an externally supplied signal during the power-down mode. A memory system has a plurality of the semiconductor devices and a memory controller. The memory controller outputs a control signal during the power-down mode, and the plurality of semiconductor devices perform a refresh operation in response to the control signal during the power-down mode. | 2010-07-15 |
20100177584 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a plurality of banks; a peripheral circuit configured to send data to and receive data from the plurality of banks; and data lines configured to connect the plurality of banks and the peripheral circuit, wherein the plurality of banks are disposed such that a sum of lengths of data transfer paths of the data lines connecting the peripheral circuit and at least two banks, among the plurality of banks, activated at a same time is uniformly maintained. | 2010-07-15 |
20100177585 | Memory subsystem - Embodiments of the present invention are directed to memory subsystems implemented within, or connected to and accessed by, parallel, pipelined, integrated-circuit implementations of computational engines designed to solve complex computational problems. Additional embodiments of the present invention are directed to memory subsystems implemented within, or connected to and accessed by, a variety of different types of electronic devices. One embodiment of the present invention comprises a memory controller implemented in a first integrated circuit or other electronic system and one or more separate memory devices. Alternative embodiments of the present invention incorporate the memory controller within one or more memory devices that are connected to, and accessed by, an integrated-circuit-implemented computational engine or another electronic device. In alternative embodiments of the present invention, the memory controller and memory are together integrated within a computational engine or another electronic device. Alternative embodiments of the present invention include a multi-access memory that interfaces to a simpler memory controller for connection to, or integration within, a computational engine or other electronic device. | 2010-07-15 |
20100177586 | MEMORY ARCHITECTURE HAVING MULTIPLE PARTIAL WORDLINE DRIVERS AND CONTACTED AND FEED-THROUGH BITLINES - Various embodiments are disclosed relating to a memory circuit architecture. In an example embodiment, which may accommodate a change to a new memory size or cell aspect ratio, while migrating between different process nodes or the same process generation, while retaining at least a portion of the periphery circuitry, a memory circuit architecture may be employed in which the memory array is divided into an upper half and a lower half, thereby splitting the cache Ways among the two halves. The wordline may be split among the two array halves, with each half driven by a half wordline driver. Also, in another embodiment, two sets of bitlines may be provided for each column, including a contacted set of bitlines and a feed-through set of bitlines. | 2010-07-15 |
20100177587 | CIRCUIT AND METHOD FOR CONTROLLING DRAM COLUMN-COMMAND ADDRESS - The present invention provides a circuit for controlling a column-command address corresponding to a specific column of a DRAM array. The circuit includes a control unit and a FIFO register. The control unit determines a period number, and synchronously produces an input pointer and an output pointer, wherein the output pointer is lagged behind the input pointer by the period number. The FIFO register utilizes the input pointer to store the column-command address, and utilizes the output pointer to output the column-command address. | 2010-07-15 |
20100177588 | CALIBRATION CIRCUIT AND CALIBRATION METHOD - A calibration circuit includes replica buffers that have a substantially same circuit configuration as at least a part of an output buffer, an oscillator circuit that generates an internal clock in response to issuance of a calibration command, and a control circuit that controls an impedance of the replica buffers in synchronization with the internal clock. According to the present invention, because a calibration operation that does not depend on an external clock is performed, even when a frequency of the external clock is changed according to an operation mode or the like, it is possible to maintain a constant period of time given to a single adjustment step or a constant time required for a series of calibration operations. | 2010-07-15 |
20100177589 | SEMICONDUCTOR DEVICE HAVING LATENCY COUNTER - A semiconductor device includes a latency setting circuit setting the latency, an input command circuit outputting a normal-phase (reverse-phase) command signal obtained by capturing an input command signal using a normal-phase (reverse-phase) clock, first and second counter circuits each including latch circuits sequentially shifting the normal-phase (reverse-phase) command signal based on the normal-phase (reverse-phase) clock, a selector circuit controlling a signal path so that the normal-phase (reverse-phase) command signal is transmitted through the first (second) counter circuit when an even latency is set and the normal-phase (reverse-phase) command signal is transmitted so as to be shifted from the first (second) counter circuit to the second (first) counter circuit when an odd latency is set, and a control circuit controlling so that the latch circuits of the first (second) counter circuit are activated in response to the input command signal and stopped after an operation period is elapsed. | 2010-07-15 |
20100177590 | Burst mode control circuit - A burst mode control unit includes a burst period signal generation unit for generating a burst period signal which is enabled during a burst mode operation period, a burst pulse generation unit for generating a burst pulse, which is generated at every predetermined number of cycles during the enabled period of the burst period signal, in response to a read command and a write command, and a column access signal generation unit for receiving the burst signal and a clock signal and generating a column access signal which controls input and output of data during the burst mode operation period. | 2010-07-15 |
20100177591 | AIR BALANCING FOR VIBRATORY APPARATUS WITH AIR KNIFE - A system includes a vibratory apparatus with a housing having a floor with an opening and a chamber, a deck disposed in the chamber between the chamber inlet and the opening, a section of the deck having a plurality of apertures and a plenum defined beneath the deck section, and an air knife disposed between the deck section and the chamber outlet. The system includes an air handling system with a first path in communication with the plenum, a second path in communication with the air knife, a third path in communication with a space beneath the air knife, a fourth path in communication with the chamber above the deck between the inlet and the deck section, a return path from the outlet, and an air mover having an outlet in communication with the first, second, third, and fourth paths and an inlet in communication with the return path. | 2010-07-15 |
20100177592 | APPARATUS WITH AUTOMATIC BALANCING FOR MIXING PAINT DISPOSED IN CONTAINERS HAVING DIFFERENT CONFIGURATIONS - An apparatus and method are provided for mixing paint disposed in either a conventional one gallon paint container or a square paint container having a body with a handle passage extending therethrough. The apparatus includes a square bucket for holding the container. A rocker is pivotably mounted to a side wall of the bucket and includes a pair of heads aligned over a pair of openings in the side wall. A floor of the bucket has a plurality of support structures extending upwardly therefrom. When the conventional one gallon paint container is disposed in the bucket, the container rests on the floor, the vertical axis of the container is offset from the central axis of the bucket, and both heads of the rocker are disposed against the container inside the bucket. When the square paint container is disposed in the bucket, the container is supported on top of the support structures so as to be elevated above the floor, the vertical axis of the container is collinear with the central axis of the bucket, and one of the heads of the rocker is disposed in the handle passage of the container. | 2010-07-15 |
20100177593 | Stirring Apparatus - An object is to provide a stirring apparatus which can exhibit excellent mixing characteristics and shorten the mixing time. The stirring apparatus includes a stirred tank having a bottomed cylindrical shape, a rotational shaft disposed coaxially or substantially coaxially within the stirred tank, a plate-shaped bottom blade having a lower end edge shaped to conform to a bottom wall surface of the stirred tank, the bottom blade having an opening for communication between one face side and an opposite face side, of the bottom blade, the ratio (h/d) between the blade height h of the bottom blade and the impeller diameter d of the bottom blade satisfies 0.4≦h/d, and the ratio of the opening area to the projection area of the bottom blade as viewed from the rotational direction thereof (opening ratio of the bottom blade) is 10-60%. | 2010-07-15 |
20100177594 | ATTENUATION OF UNWANTED ACOUSTIC SIGNALS BY SEMBLANCE CRITERION MODIFICATION - Methods and related systems are described for modified semblance criterions based on the approach of thresholding the signal energy. A first criterion is derived by posing the problem as that of detecting a signal with energy (or amplitude) greater than the specified threshold and deriving the generalized likelihood ratio test statistic. A second criterion is derived using the same method by posing the problem as that of rejecting any signal with energy (or amplitude) below a specified threshold and detecting it if its energy is above another threshold greater than or equal to the first. These appropriately modify the original semblance criterion which is shown to be equivalent to the GLRT test statistic in the absence of any threshold on the signal amplitude. In addition simpler modifications are also described. Tests on synthetic data illustrate the effectiveness of all these modifications which perform comparably well at suppressing unwanted arrivals while accurately processing the desired signals. | 2010-07-15 |
20100177595 | Using Seismic Attributes for Data Alignment and Seismic Inversion In Joint PP/PS Seismic Analysis - Method for aligning converted wave seismic reflection data (PS data) with conventional PP seismic reflection data so that both data types may be used to more accurately image the subsurface for hydrocarbon exploration or field development. Amplitude vs. angle (AVA) or amplitude vs. offset (AVO) attributes of PP and PS seismic data are identified and defined, which attributes are theoretically expected to be in phase and optimize seismic resolution in the data. In one embodiment of the invention, such attributes are calculated ( | 2010-07-15 |
20100177596 | Adaptive Carrier Modulation for Wellbore Acoustic Telemetry - Systems and methods of adaptive carrier modulation for acoustic telemetry. A method of transmitting an acoustic signal through a wellbore medium includes propagating the acoustic signal through the wellbore medium, the acoustic signal including symbols modulated on a carrier frequency, and the carrier frequency being changed during transmission of each of the symbols. A wellbore acoustic telemetry system includes a transmitter which propagates an acoustic signal through a wellbore medium in a manner such that the acoustic signal includes symbols modulated on a carrier frequency, with the carrier frequency being changed during transmission of each of the symbols. | 2010-07-15 |
20100177597 | AROMA ALARM CLOCK - An aroma alarm clock includes an outer case in which are mounted a time setting module, an aroma module, and a power supply module. The outer case has a plurality of air inlets and a plurality of air outlets. The time setting module includes a plurality of button switches and a microcontroller chip. The aroma module has a fan and a fan cover. The fan is mounted to a first side of the fan cover and a container compartment is defined between the fan cover and the outer case for storing an aroma substance. The microcontroller chip is operated to control time display, alarm setting, aroma diffusion, time setting for releasing an aroma, and illumination. The air is drawn in the outer case, through the aroma substance in the container compartment and released out of the outer case at a preset time to wake up the user. | 2010-07-15 |
20100177598 | Methods and Apparatuses for a Network Enabled Alarm Clock - An electronic alarm clock connected to one or more networks comprises: a network communications device, wherein the network device receives content from the networks; a touch screen; one or more speakers; and a local storage device, wherein a clock function is provided, wherein an alarm function is provided that plays user specified content at a user specified time on said screen and the speakers, and wherein a physical button is disposed on the clock to manage the alarm function during an alarm. | 2010-07-15 |
20100177599 | DETERMINING LOCATION AND SURVIVABILITY OF A TRAPPED PERSON UNDER A DISASTER SITUATION BY USE OF A WIRST WEARABLE DEVICE - A wrist wearable computing and communication device for an emergency occasion is disclosed. The device, for example, is useful for a trapped person under a mound of debris created by a fallen building during an earthquake or a terrorist attack. The invention is based upon a conventional wrist electronic watch with an additional sensory unit for sensing survivability of the trapped person and a communication unit for communicating with an external device. The invention is characterized by that an authorized signal delivered by a nearby mobile rescue station will switch on the sensory unit of the wearable device to provide the information with regard to trapped person's status. In one embodiment, a pressure sensor on the backside of the wearable device is used to measure the wrist induced pressure to confirm if the device is worn and a temperature sensor to measure the body temperature of the trapped person after the confirmation. In another embodiment, a motion sensor is used to measure the movement of the wrist after an alerting signal is triggered by the mobile rescue station. | 2010-07-15 |
20100177600 | SYSTEM AND METHOD OF INCREASING BATTERY LIFE OF A TIMEKEEPING DEVICE - Methods and systems of extending battery life of remote battery-operated timekeeping devices by minimizing the number of required synchronizations per unit of time needed to maintain a predetermined accuracy of the devices. The number of synchronizations are minimized by first calculating a time error rate between the remote timekeeping device and a master device over a sample period. Then, a synchronization is delayed and the remote timekeeping device is compensated based on the time error rate. The compensation delays the need for a synchronization yet maintains the predetermined accuracy of the remote timekeeping device. In some embodiments, the remote timekeeping device is compensated and multiple synchronizations are delayed before a new synchronization is necessary to maintain the predetermined accuracy. | 2010-07-15 |
20100177601 | METHOD FOR PROVIDING DIGITAL COMPASS FUNCTION AND PORTABLE TERMINAL ADAPTED THERETO - A method for providing a digital compass function and a portable terminal adapted to the method are disclosed. The cardinal points, north, south, east and west, are calculated based on the celestial body, such as the sun, the moon, a constellation, a particular star, etc. using the current time information and information of a location where the portable terminal is currently located. The direction of Mecca is calculated based on the calculated cardinal points and the current location information and displayed on the display unit. | 2010-07-15 |
20100177602 | TIME INFORMATION OBTAINING APPARATUS AND RADIO WAVE TIMEPIECE - A time information obtaining apparatus, comprises: an input waveform data generating section for sampling a received signal including a time code at a predetermined sampling period to obtain sampling points every one unit time length, and generating input waveform data having one or more unit time lengths based on data having at least one unit time length including the obtained sampling points; a predicted waveform data generating section for generating a plurality of pieces of predicted waveform data with respect to each class of a standard time radio wave; a correlation value calculating section for calculating correlation values between the input waveform data and the plurality of pieces of predicted waveform data of each of the classes; a correlation value comparing section for comparing the correlation values to calculate optimum values; and a judging section for judging the class of the standard time wave based on the optimum values. | 2010-07-15 |
20100177603 | PIEZOELECTRIC DRIVE DEVICE AND ELECTRONIC DEVICE - A piezoelectric drive device includes a piezoelectric actuator and a rotation transfer device. The piezoelectric actuator includes a vibrator and a rotor that is rotated in one specific direction by the vibrator. The rotation transfer device transmits rotational energy from the rotor to a driven rotating body, and includes an elastic device that stores rotational energy and a rotation limiting device having a drive wheel and a driven wheel. The rotation transfer device allows the driven wheel to rotate a specific angle, and restricts driving the drive wheel. The elastic device and the rotation limiting device are disposed so that rotational energy transmitted from the rotor is transmitted through one to the other of the elastic device and the rotation limiting device. The rotor, the elastic device, and the rotation limiting device render a serial path for transmitting rotational energy. | 2010-07-15 |
20100177604 | Combined Watch and Bands - A timekeeping device that is positioned on the back of the hand by securing said device to the wrist and to a finger or fingers. The bands used for securing said device are adjustable to accommodate different hand, wrist and finger sizes and to maximize comfort. | 2010-07-15 |
20100177605 | MEDIA FOR HEAT ASSISTED MAGNETIC RECORDING - A method for fabricating a patterned recording medium includes providing a workpiece with a non-magnetic substrate and at least one overlying magnetic layer, laminating a thermal insulation barrier partially in a soft under layer of one of the at least one magnetic layers and forming a topographical pattern including a plurality of trenches in the soft under layer. Blocks of track triplets are formed between adjacent trenches that are magnetically and thermally insulated from other adjacent blocks of track triplets. | 2010-07-15 |
20100177606 | METHOD FOR IDENTIFING A LAYER NUMBER OF AN OPTICAL DISC - A method for identifying a layer number of an optical disc is provided. Firstly, a SA value is adjusted to a standard SA value of each of two data layers in sequence. Next, focusing courses are performed so as to enable the focus point to pass through the optical disc. Then, maximum amplitudes of focusing error signals in the focusing courses are recorded. After that, whether the maximum amplitudes of the focusing error signals recorded in the focusing courses are equal is checked. If the maximum amplitudes are equal, the optical disc is identified as a double-layered disc. If the maximum amplitudes are not equal, the optical disc is identified as a single-layered disc. | 2010-07-15 |
20100177607 | RECORDING DEVICE, RECORDING METHOD, AND COMPUTER PROGRAM - A recording apparatus and the like for creating an optical disc which is recognizable as a finalized disc even when an accidental power interruption or a serious write error occurs before finalize processing is completed is provided. | 2010-07-15 |
20100177608 | OPTICAL DISC AND METHOD FOR CONTROLLING THE SAME - In an optical disc having a multilayer structure in which recording layers are bonded to each other, the number of times additional writing can be performed is increased. A method for controlling an optical disc device according to the present invention comprises steps of calculating a displacement amount generated when the recording layers are bonded to each other; and identifying the size of a recordable area in a non-usable area predetermined on the recording layer based on the displacement amount. | 2010-07-15 |
20100177609 | METHOD AND APPARATUS FOR PERFORMING BETA PREDICTION FOR HIGH-SPEED WRITING ON UNKNOWN RECORDABLE OPTICAL DISCS - A method is disclosed for performing Beta prediction for high-speed writing on unknown recordable optical discs. Test recordings are performed in the inner ( | 2010-07-15 |
20100177610 | OPTICAL DISK DEVICE FOR MULTI-LAYER OPTICAL DISK AND MULTI-LAYER OPTICAL DISK - An optical disk device for writing data into a disk including a plurality of recording layers, wherein the disk includes a recording layer in which a track for recording the data is formed in a clockwise spiral direction, and a recording layer in which a track for recording the data is formed in a counter-clockwise spiral direction, and the optical disk device records the data into a first recording layer, and selects a layer in which the data can be recorded and of which a spiral direction is opposite to the spiral direction of the first recording layer, as a recording layer for recording the data next to the first recording layer. | 2010-07-15 |
20100177611 | SPHERICAL ABERRATION COMPENSATION ADJUSTMENT - Spherical aberration correction is provided for CD writing in a double (CD+DVD), triple (CD+DVD+BD) or quadruple (CD+DVD+BD+HD-DVD) writer, which use the same light path for CD and DVD. In an optical drive that uses numerous laser wavelengths combined into one light path each wavelength having a different numerical apertures a correction for spherical aberration is made to correct for effective numerical apertures of the light path that becomes shifted up from the original value to higher values. The correction in spherical aberration removes that effect of the higher effective NA and defects, particularly in writing, are corrected. | 2010-07-15 |
20100177612 | INFORMATION RECORDING APPARATUS AND COPY MANAGEMENT PROGRAM - An information recording apparatus mutually communicates with a number-of-copying-times management server via a communication network, the server performing management by correlating medium identification information that enables unique identification of an information recording medium, with information related to number of allowable copying times of digital contents recorded on the information recording medium. The apparatus acquires the medium identification information of the inserted information recording medium, and acquires information related to the number of allowable copying times correlated with the acquired medium identification information, from the number-of-copying-times management server, for recordation in a storage unit. When a user's request is received to display the information related to the number of allowable copying times, the information related to the number of allowable copying times recorded in the storage unit is correlated with the medium identification information and outputted to and displayed on a display unit. | 2010-07-15 |
20100177613 | Access Controlled Optical Disc and Method Therefor - An optical disc is disclosed having a set of primary tracks and a set of alternate tracks. At least some of the primary and alternate tracks are associated. When a CD-DA reader accesses the optical disc, it locates only the primary tracks. By contrast, when a data reader such as a CD-Rom drive accesses the disc, modifications to the Table of Contents (TOC) cause the data reader not to access a given primary track but instead to be directed to its associated alternate track. This alternate track may contain audio (CD-DA) data which may or may not correspond with the CD-DA data in the associated primary track. The alternate tracks may be copy protected, and/or may include compressed (not CD-DA) data which is the subject of digital rights management. | 2010-07-15 |