29th week of 2015 patent applcation highlights part 47 |
Patent application number | Title | Published |
20150200602 | MULTILEVEL CONVERTER SYSTEMS AND METHODS WITH REDUCED COMMON MODE VOLTAGE - Sinusoidal pulse width modulation (SPWM) control techniques, computer readable mediums, and apparatus are presented for operating a multilevel converter, in which a desired AC node voltage level is determined through comparison of a plurality of carrier signals or values to at least one reference signal or value, and a switching state is selected from a plurality of redundant switching states corresponding to the desired AC node voltage level for generating switching control signals based at least partially on a switched capacitor voltage balancing goal or other control objective. | 2015-07-16 |
20150200603 | INTEGRAL INVERTER AND SOLAR CELL MODULE INCLUDING THE SAME - Discussed is an integral inverter usable with a solar cell module including a solar cell panel. The integral inverter includes a terminal connected to the solar cell panel, a bypass diode electrically connected to the terminal, an inverter member including a direct current (DC)-alternating current (AC) inverter electrically connected to the bypass diode and a case configured to integrate at least one of the terminal and the bypass diode with the DC-AC inverter located therein. | 2015-07-16 |
20150200604 | Dynamic Means for Correcting for Load Imbalance and Harmonic Distortion - A method and apparatus are directed to a dynamic means for correcting imbalance and harmonic distortion in an electrical system. In one embodiment, the device includes an imbalance and harmonics measurement module configured to measure power parameters for determining imbalance and harmonics within the electrical three-phase system. Within this system a series of capacitors are configured to respond to measured demands reported and designated to correct for imbalance and harmonics distortion. The device is networked among various source load controllers are responsible for designating master and slave relationships within the closed system. | 2015-07-16 |
20150200605 | Circuit Arrangement with a Rectifier Circuit - A rectifier circuit includes first and second load terminals, a first semiconductor device having a load path and configured to receive a drive signal, and a plurality of second semiconductor devices each having a load path and each configured to receive a drive signal. The load paths of the second semiconductor devices are connected in series, and connected in series to the load path of the first semiconductor device. A series circuit with the first semiconductor device and the second semiconductor devices is connected between the load terminals. Each of the second semiconductor devices is configured to receive as a drive voltage either a load-path voltage of at least one of the second semiconductor devices, or a load-path of at least the first semiconductor device. The first semiconductor device is configured to receive as a drive voltage a load-path-voltage of at least one of the second semiconductor devices. | 2015-07-16 |
20150200606 | INVERTER DEVICE, PLASMA GENERATING DEVICE, SHEET-MEMBER REFORMING DEVICE, AND ALTERNATING-CURRENT VOLTAGE OUTPUT METHOD - An inverter device includes: multiple inverters that switch input voltages by turning on and off respective switching elements to thereby apply excitation currents to primary excitation windings of respective boosting transformers and output alternating-current voltages from secondary output windings of the respective boosting transformers, the multiple inverters having the same output characteristics, and a common control circuit, on/off control of the switching elements of the inverters being performed by the same switching signal output from the common control circuit. | 2015-07-16 |
20150200607 | POWER CONVERTER - A power converter includes a power conversion circuit including a switching element, a device including an inductance and provided on an AC side of the power conversion circuit, an output-amount measuring module configured to measure an output amount of an output from the power conversion circuit, and a switching frequency determining module configured to determine a switching frequency at which the switching element is switched to reduce a loss including a loss due to the device, based on the output amount measured by the output-amount measuring module. | 2015-07-16 |
20150200608 | POWER CONVERTER - A power converter includes a wave generator, a low pass filter, a first control circuit, and a second control circuit. The wave generator receives an input voltage, and converts the input signal into a wave signal according to a first control signal and a second control signal. The low pass filter filters the wave signal to generate an output voltage. The first control circuit generates the first control signal according to the wave signal and the output voltage. The second control circuit generates the second control signal according to the wave signal and the output voltage. | 2015-07-16 |
20150200609 | COMBINED POWER TRANSMISSION AND HEATING SYSTEMS AND METHOD OF OPERATING THE SAME - A combined direct current DC power transmission and heating system is provided. The system includes a rectifier station configured to generate a DC link current. The system also includes a downstream converter station positioned remotely from the rectifier station. The downstream converter station is configured to generate power supplied to an electrical load using at least a portion of the DC link current. The system also includes a return conductor electrically coupled to the rectifier station and the downstream converter station. The return conductor is configured to transmit a return current from the downstream converter station to the rectifier station. The return conductor is also configured to generate heat from resistive losses induced by the return current; and conduct the heat generated by the return current to a fluid being transported from a proximity of the downstream converter station to a proximity of the rectifier station. | 2015-07-16 |
20150200610 | ULTRASONIC WAVE MOTOR AND ULTRASONIC WAVE MOTOR-EQUIPPED DEVICE - A driving device having a vibration element, a friction member, and a pressing member for applying pressure in a direction in which the vibration element and the friction member make contact with each other, causing the vibration element and the friction member to make a relative movement by vibration generated in the vibration element. The device includes a connection member configured to transmit a driving force caused by the relative movement to a holding member of another member, wherein the holding member makes a movement caused by the transmitted driving force, and a guide member configured to guide the holding member in a moving direction when the vibration element and the friction member make the relative movement. The connection member connects the holding member to the vibration element or the friction member so as not to apply a reaction force caused by the pressing member to the holding member. | 2015-07-16 |
20150200611 | LINEAR VIBRATION-WAVE MOTOR - A linear vibration-wave motor being configured to apply a driving force to a lens barrel of an optical device includes a vibrator being operable to excite a vibration, a member to be contacted contacting the vibrator, the vibrator being arranged to move in a direction of the driving force with respect to the member to be contacted upon exciting the vibration, a vibrator support being fixed to the lens barrel and configured to support the vibrator, a pressurization member being operable to press the vibrator against the member to be contacted, a unit cover member including an opening extending in the direction of the driving force, and a unit base member having fixed thereto the member to be contacted and the unit cover member. The pressurization member is detachable from the vibrator support via the opening. | 2015-07-16 |
20150200612 | VIBRATION ACTUATOR UNIT, STAGE APPARATUS, AND OPTICAL APPARATUS - A vibration actuator unit comprises: an electromechanical converting element that converts an electric vibration of an applied actuating voltage into a mechanical vibration; and a contact portion that contacts an actuated surface of an actuating subject and a transmits a mechanical vibration of the electromechanical converting element to the actuated surface as an actuating force, wherein the electromechanical converting element periodically bends within a first vibration plane crossing the actuated surface to vibrate the contact portion within the first vibration plane, and periodically bends within a second vibration plane crossing the first vibration plane to vibrate the contact portion within the second vibration plane. | 2015-07-16 |
20150200613 | ELECTRIC VEHICLE AND CONTROL METHOD OF ELECTRIC VEHICLE - An electric vehicle driven by a synchronous motor | 2015-07-16 |
20150200614 | MAGNET TEMPERATURE ESTIMATING SYSTEM FOR SYNCHRONOUS ELECTRIC MOTOR - A magnet temperature estimating system for a synchronous electric motor having a permanent magnet includes: a superimposing unit configured to superimpose a voltage or current of a frequency different from a frequency of a fundamental wave driving the synchronous electric motor on at least a d-axis of the synchronous electric motor; a calculator configured to calculate an impedance of the synchronous electric motor from the superimposed voltage or current and a current or voltage obtained by the superimposing; and a magnet temperature estimating unit configured to estimate a temperature of the permanent magnet on the basis of the calculated impedance. | 2015-07-16 |
20150200615 | SYSTEMS AND METHODS FOR ADAPTIVE CONTROL OF EXCITATION AND GENERATOR SYSTEMS - A system includes an excitation system. The excitation system includes a memory configured to store an adaptive power system stabilizer (PSS) system configured to dynamically stabilize the operation of a generator system, and a processor communicatively coupled to the memory and configured to utilize the adaptive PSS system according to a value for one or more operational parameters of the generator system. The derived value is applied by the processor to operate the generator system when the generator system exhibits oscillations at least one of a plurality of operating frequency ranges associated with an oscillation of a power angle of the generator system. The derived value is configured to attenuate the oscillation of the power angle over the at least one of the plurality of interval operating frequency ranges. | 2015-07-16 |
20150200616 | MOTOR CONTROLLER AND METHOD FOR CONTROLLING MOTOR - A motor controller includes an evaluation value calculator and an evaluation value searcher. The evaluation value calculator calculates an evaluation value represented by a function including a q-axis current value of a torque current component of a current through an induction motor. The evaluation value has a first sign among a positive sign and a negative sign when a rotational speed of the induction motor is greater than a frequency of a voltage applied to the induction motor by a predetermined amount, and has a second sign when the rotational speed is smaller than the frequency by the predetermined amount. The evaluation value searcher performs an evaluation value search to increase or decrease the frequency based on whether the evaluation value has the positive or negative sign so as to make the frequency close to the rotational speed of the induction motor in a free run state. | 2015-07-16 |
20150200617 | D-Q Control System and Method for Controlling a Switched Reluctance Motor - A D-Q or rotating reference frame control system for a switched reluctance motor (SRM) provides a negativity removal module and a non-linear model module. As such, the control system utilizes control inputs f | 2015-07-16 |
20150200618 | Skirt and Other Devices for Photovoltaic Arrays - A skirt and other devices for photovoltaic arrays, as well as photovoltaic arrays with a skirt(s) and/or other device(s) installed, related modules, and foothold devices and systems are herein disclosed. Various such embodiments include one or more array skirt(s), T-locks, grip(s), inside and outside corner cap(s), array trim(s), pest abatement screen(s), wire clip(s), foothold(s), groove adaptor bracket(s), magnetic skirt embodiment(s), as well as other structures and embodiments which are herein disclosed. | 2015-07-16 |
20150200619 | SOLAR PANEL BALLASTED GROUND SUPPORT SYSTEMS - A structure, system and method for the in situ ballasting of solar panel ground support structures, the method, system and structures comprising the positioning of supporting posts or anchoring elements therefor within a peripherally enclosing frame constructed of removable interfitting plates, with the frame having an open top and preferably open bottom, on the ground at a final solar panel array supporting position. The supporting posts or anchoring elements therefor are vertically aligned and maintained in position relative to each other and a ballast material, such as concrete, is poured into the enclosing frame around the supporting posts or anchoring elements therefor in the final solar panel supporting position thereof with the ballast material being allowed to harden. A solar panel support structure is constructed with the solar panel support structure being ballasted, in final solar panel array position, in situ. Thereafter solar panels are placed on the ballasted support structure to provide the solar panel array. | 2015-07-16 |
20150200620 | TRAPEZOIDAL RIB MOUNTING BRACKET - A mounting bracket ( | 2015-07-16 |
20150200621 | Clamp for Solar Panel Array - A clamp for securing photovoltaic panels to a support tube of a photovoltaic panel array has a lower brace for positioning on the support tube perpendicular to the support tube. The lower brace has a central web with a pair of side walls depending from opposite edges of the web. Support shoulders are formed in the side walls. Straps have tabs on an upper end that land on the support shoulders. An upper brace has flanges for engaging upper edge surfaces of adjacent ones of the panels. At least one deflectable standoff positions the upper brace a distance from the lower brace that is selected to be greater than a thickness of the adjacent ones of the panels. Tightening bolts between the braces deflects the standoff and draws the upper brace toward the lower brace to clamp the adjacent ones of the panels between the lower and upper braces. | 2015-07-16 |
20150200622 | CONCENTRATING PHOTOELECTRIC CONVERSION DEVICE - The present disclosure provides a concentrating photoelectric conversion device that can efficiently obtain a power generation amount even if a deflection and a strain are generated. A position shift detection element group ( | 2015-07-16 |
20150200623 | PHOTOVOLTAIC MODULE - A photovoltaic module is discussed. The photovoltaic module includes a solar cell module including a plurality of solar cells and a junction box attached to a rear surface of the solar cell module, the junction box including a power conversion module to convert direct current (DC) voltage supplied from the solar cell module into alternating current (AC) voltage and to output the AC voltage, wherein the power conversion module included at least one bypass diode to receive the DC voltage from the solar cell module, a converter unit to power-convert the DC voltage from the at least one bypass diode, the converter unit including at least three interleaving converters, a capacitor to store voltage output from the converter unit, and an inverter unit to output the AC voltage using the voltage stored in the capacitor. Consequently, it is possible to stably output AC voltage. | 2015-07-16 |
20150200624 | Method And System For Controlling A Power Output Of An Inverter - According to a first aspect of the disclosure, there is provided a method of controlling a power output of an inverter. The method comprises measuring an output current of the inverter, determining a difference between the output current and a reference current, and controlling a reference input voltage of the inverter as a function of the determined difference. In a second aspect of the disclosure, there is described a system for controlling a power output of an inverter. The system comprises an inverter arranged to output a current as a function of a reference input voltage. The system further comprises a controller arranged to determine a difference between the output current and a reference current. The controller is further arranged to control the reference input voltage as a function of the determined difference. The method may allow for control of a photovoltaic inverter at a power less than its maximum capability for a given solar irradiation, which may avoid the problem of the photovoltaic array voltage rising above a level where the inverter can run. | 2015-07-16 |
20150200625 | OSCILLATOR STARTUP - A modulated signal based on a low-precision, fast startup oscillator is provided to a circuit with a high-precision, slow startup oscillator. The frequency of the modulated signal ranges around the characteristic or resonant frequency of the high precision oscillator without using feedback from the high precision oscillator circuit. An implementation can include one or more variable gain circuits that can be adjusted based on an amplitude threshold in relation to the output signal of the high precision oscillator circuit. | 2015-07-16 |
20150200626 | VCO RESTART UP CIRCUIT AND METHOD THEREOF - A circuit and a method for restarting up a VCO of a PLL are introduced herein. The VCO restart up circuit receives a power down signal, an external signal, a clock output from the VCO and generates a trigger signal to the VCO to trigger the VCO clock to leave a stable mode. In other words, if the VCO clock is in the stable mode, the VCO restart up circuit generates one or more than one pulse on a trigger signal to restart up the VCO. Oppositely, if the VCO is not in the stable mode, there is no pulse on the trigger signal generated by the VCO restart up circuit and the VCO needs not to be restarted up. | 2015-07-16 |
20150200627 | PHASE NOISE REDUCTION IN VOLTAGE CONTROLLED OSCILLATORS - A voltage controlled oscillator (VCO), a method of designing a voltage controlled oscillator, and a design structure comprising a semiconductor substrate including a voltage controlled oscillator are disclosed. In one embodiment, the VCO comprises an LC tank circuit for generating an oscillator output at an oscillator frequency, and an oscillator core including cross-coupled semiconductor devices to provide feedback to the tank circuit. The VCO further comprises a supply node, a tail node, and a noise by-pass circuit connected to the supply and tail nodes, in parallel with the tank circuit and the oscillator core. The by-pass circuit forms a low-impedance path at a frequency approximately twice the oscillator frequency to at least partially immunize the oscillator core from external noise and to reduce noise contribution from the cross-coupled semiconductor devices. | 2015-07-16 |
20150200628 | Coefficient Estimation for Digital IQ Calibration - An RF reception system and method uses IF quadrature mixing, in which there is further mixing and channel filtering in the digital domain, to isolate a frequency of interest. A coefficient estimator is used for generating a phase correction coefficient and an amplitude correction coefficient from filtered in-phase and quadrature desired signals and from filtered in-phase and quadrature image signals. | 2015-07-16 |
20150200629 | GUITAR AMPLIFIER CIRCUITRY - Amplifier circuitry that is operative to provide selective control of the amplitude of a musical signal as the signal transitions from the pre-amplifier to power amplifier components of an electric guitar amplifier. According to a preferred embodiment, at least one low variable power amplifier is integrated into the signal path from the pre-amplifier to the power amplifier components of the guitar amplifier. The low power amplifier allows for selective control of the amplitude of the musical signal such that the signal ranges from ‘zero volts’ to more than 100 DB. Such low power amplifiers may be selectively deployed in guitar amplifiers utilizing either Class A or Class A/B circuitry and enables a musician to have full control of the power amplifier from 0% gain to 100% gain at any tone selection and any power amp wattage, as may be desired. | 2015-07-16 |
20150200630 | Method and Apparatus for Adjusting Peak Power Capability - One of the embodiments of the present disclosure relates to a method for adjusting peak power capability of a power amplifier circuitry. The power amplifier circuitry comprises at least one main amplifier path and at least one peak amplifier path and is configured to output a signal combining amplified signals from the at least one main amplifier path and the at least one peak amplifier path. The method comprises calculating a PAPR of an input signal of the power amplifier circuitry; determining at least one configuration parameter of the at least one peak amplifier path depending upon the calculated PAPR of the input signal; and configuring the at least one peak amplifier path based on the determined at least one configuration parameter, thereby adjusting the peak power capability of the power amplifier circuitry. The present disclosure also relates to corresponding apparatus and wireless communication devices. | 2015-07-16 |
20150200631 | DUAL-BAND DOHERTY COMBINER/IMPEDANCE TRANSFORMER CIRCUIT AND DOHERTY POWER AMPLIFIER INCLUDING THE SAME - A dual band Doherty component circuit of a dual band Doherty amplifier, which is configured to operate at first and second operating frequencies, includes a Doherty combiner circuit, the Doherty combiner circuit including, a first input node configured to receive a first output, a combining node configured to receive a second output and combine the first output with the second output, the first output being an output of a main amplifier stage of the Doherty amplifier, the second output being an output of a peak amplifier stage of the Doherty amplifier; and a broadband impedance transformer circuit including, first, second, and third lines, the first and second lines being electrically coupled to one another, the first and third lines being connected to an input of the impedance transformer circuit, the second line being connected to an output of the impedance transformer circuit. | 2015-07-16 |
20150200632 | HYSTERESIS COMPARATOR CIRCUIT HAVING DIFFERENTIAL INPUT TRANSISTORS WITH SWITCHED BULK BIAS VOLTAGES - A first signal received at a first transistor is compared to a second signal received at a second transistor taking into account a hysteresis value to generate a comparison output. At least one of the first and second transistors has a floating bulk. A switching circuit selectively applies first and second bulk bias voltages to the floating bulk of the first or second transistor in dependence on the comparison output. A third and fourth input signals, setting the hysteresis value, are received at third and fourth transistors and compared to generate differential outputs. At least one of the third and fourth transistors has a floating bulk. A differential amplifier determines a difference between the differential outputs for application to the floating bulk of the at least one of the third and fourth transistor and further for use as one of the first and second bulk bias voltages. | 2015-07-16 |
20150200633 | QUICK COMPARISON CIRCUIT - A quick comparison circuit includes a cascaded N-stage operational amplifier, a flip-latch, a biasing circuit, and a control signal generating circuit, with N≧2, and two differential signals to be compared being inputted to an input terminal of a first stage operational amplifier, an output terminal of a Nth stage operational amplifier being connected with an input terminal of the flip-latch, the biasing circuit supplying a biasing current to each stage operational amplifier, the control signal generating circuit being connected with the N-stage operational amplifier and the flip-latch respectively to supply a working time sequence and a reset control signal for them, and each stage operational amplifier having the same structure. This circuit has high gain and improved comparison speed. | 2015-07-16 |
20150200634 | DEVICE FOR BALANCING THE RISE AND FALL SLEW-RATES OF AN OPERATIONAL AMPLIFIER - An amplifier includes a pair of transistors connected in a differential stage, and a bias current source connected to a common node of the differential stage. A slew-rate compensation circuit is configured to derive from the common node a dynamic compensation current during a phase in which the voltage of the common node varies. | 2015-07-16 |
20150200635 | OPERATIONAL TRANSCONDUCTANCE AMPLIFIER, RECONFIGURABLE FULLY DIFFERENTIAL VOLTAGE SENSING AMPLIFIER AND RECONFIGURABLE FULLY DIFFERENTIAL CAPACITIVE SENSING AMPLIFIER - An operational transconductance amplifier includes a cascode differential-pair amplifying circuit, a bias driving circuit, and a common mode feedback circuit. The cascode differential-pair amplifying circuit is configured for receiving a differential input voltage and for providing a differential output voltage. The bias driving circuit is configured for providing a first bias current to drive the cascode differential-pair amplifying circuit and for adjusting the transconductance of the transconductance amplifier. The bias driving circuit includes a first floating-gate transistor. The first floating-gate transistor is configured for adjusting the first bias current. The common mode feedback circuit is configured for adjusting a second bias current of the cascode differential-pair amplifying circuit according to the differential output voltage so that the differential output voltage is stabilized. A reconfigurable fully differential voltage sensing amplifier and a reconfigurable fully differential capacitive sensing amplifier are disclosed herein as well. | 2015-07-16 |
20150200636 | AMPLIFIER CIRCUIT, A/D CONVERTER, AND COMMUNICATION APPARATUS - An amplifier circuit according to one embodiment includes an input terminal, an output terminal, an amplifier, a first switch, and a first signal setter. An input side of the amplifier is connected to the input terminal and an output side is connected to the output terminal. A difference between a signal input from the input side and a predetermined reference signal is amplified with a predetermined gain. The first switch opens and closes between the output side of the amplifier and the output terminal. The first signal setter sets a signal of the output terminal to the predetermined signal when the first switch opens. | 2015-07-16 |
20150200637 | BIOSIGNAL AMPLIFYING CIRCUIT - A biosignal apparatus is described including an amplifier and a sampler. The amplifier is configured to alternate between an operating state and a low power state based on a periodically changing control signal. The sampler is configured to sample a signal output from the amplifier in response to the amplifier being in the operating state and maintain the sampled signal in response to the amplifier being in the low power state. | 2015-07-16 |
20150200638 | AUDIO OUTPUT CONTROL METHOD AND ELECTRONIC DEVICE SUPPORTING THE SAME - Disclosed is an audio output control method and an electronic device supporting the same. The audio output control method includes determining an output of an audio processing unit decoding an audio source signal, and controlling generating of a reference signal to be supplied to an audio output unit in response to an output of the audio processing unit. | 2015-07-16 |
20150200639 | METHODS AND APPARATUS FOR LAYERED WAVEFORM AMPLITUDE VIEW OF MULTIPLE AUDIO CHANNELS - A system receives a plurality of waveforms. The system renders a graphical representation of the plurality of waveforms. The graphical representation includes an individual graphical representation for each of the waveforms in the plurality of waveforms, and a combined representation of the plurality of waveforms. The combined representation combines at least two of the plurality of waveforms in a single representation. | 2015-07-16 |
20150200640 | AUDIO POWER AMPLIFICATION WITH REDUCED INPUT POWER SUPPLY CREST FACTOR - A power converter has an output that is coupled in parallel with an energy reservoir circuit and a power supply node of an audio power amplifier. The converter can set an upper limit on its input supply current that is variable in accordance with a control input. A controller is to produce a signal, coupled to the control input of the power converter, that is responsive to a measure of input supply voltage of the power converter and either output voltage of the power converter or output power of the amplifier. Other embodiments are also described and claimed. | 2015-07-16 |
20150200641 | METHOD FOR PROVIDING AUDIO AND ELECTRONIC DEVICE ADAPTED TO THE SAME - A method and an electronic device are provided for simultaneously outputting different audios with directionality. The method includes outputting a first audio, and when a request to output a second audio is detected, changing at least one attribute value of the first audio and the second audio and outputting the first audio and the second audio. | 2015-07-16 |
20150200642 | RF SIGNAL AUTOMATIC GAIN CONTROL METHOD - The automatic gain control (AGC) method contains the following steps: producing a feedback signal and transmitting the feedback signal to a signal processing unit to produce a working signal; transmitting the working signal to a first signal control unit to produce a first control voltage; transmitting the first control voltage to a second signal control unit to produce a second control voltage, which is a fixed voltage; and transmitting the second control voltage to an AGC unit where the fixed second control voltage is used as a reference value. As such, when a radio-frequency (RF) input signal varies due to channel loading variation, an RF output signal by the AGC unit can be maintained within a specified dB range. | 2015-07-16 |
20150200643 | CLIPPING PROTECTION IN FIXED-WIDTH AUDIO MIXING - An apparatus provides both clipping protection and signal level conservation while the system operates in the original width type. The apparatus includes a first shifting unit right shifting a first digital input signal to provide a first shifted signal; a second shifting unit right shifting a second digital input signal to provide a second shifted signal; a combiner combining the first shifted signal and the second shifted signal to provide a combined signal; a soft limiter soft limiting the combined signal by reducing some of the amplitudes of the combined signal to provide a soft limited signal; and a third shifting unit left shifting the soft limited signal to provide an output signal. | 2015-07-16 |
20150200644 | EMI suppression device and method for network transmission - The present invention discloses an EMI suppression device, comprising: a first transformer including a first circuit-end central tap to receive a first circuit signal from two first circuit-end signal taps, and a first cable-end central tap to receive a first cable signal from two first cable-end signal taps; a second transformer including a second circuit-end central tap to receive a second circuit signal from two second circuit-end signal taps, and a second cable-end central tap to receive a second cable signal from two second cable-end signal taps; a first circuit-end inductor coupled between the first circuit-end central tap and a system ground to reduce the common mode noise of the first circuit signal; and a second circuit-end inductor coupled between the second circuit-end central tap and the system ground to reduce the common mode noise of the second circuit signal. Said first and second circuit-end inductors operate separately. | 2015-07-16 |
20150200645 | SNAP-ON COAXIAL CABLE BALUN AND METHOD FOR TRAPPING RF CURRENT ON OUTSIDE SHIELD OF COAX AFTER INSTALLATION - Apparatus and method for a radially attachable RF trap attached from a side to a shielded RF cable. In some embodiments, the RF trap creates a high impedance on the outer shield of the RF cable at a frequency of RF signals carried on at least one inner conductor of the cable. In some embodiments, an RF-trap apparatus for blocking stray signals on a shielded RF cable that has a peripheral shield conductor and a inner conductor for carrying RF signals includes: a case; an LC circuit having a resonance frequency equal to RF signals carried on the inner conductor; projections that pierce and connect the LC circuit to the shield conductor; and an attachment device that holds the case to the cable with the LC circuit electrically connected to the shield conductor of the shielded RF cable. | 2015-07-16 |
20150200646 | Wireless Communication Device and Method of Adjusting Antenna Matching - A wireless communication device includes a diversity antenna operating in a receiving frequency band to receive a receiving signal in the reception frequency band, a tunable matching circuit for adjusting a matching of the diversity antenna according to a control signal, a detection circuit for detecting a wireless communication system corresponding to the receiving signal to generate a detection result, wherein the detection result indicates an antenna configuration and a transmission frequency band corresponding to the wireless communication system, and a radio-frequency processing circuit for determining whether to adjust the matching of the diversity antenna to weaken antenna performance of the diversity antenna in both or one of the transmission frequency band and the reception frequency band according to the antenna configuration so as to improve an isolation between the diversity antenna and a main antenna. | 2015-07-16 |
20150200647 | PIEZOELECTRIC VIBRATION COMPONENT - A piezoelectric vibration component that includes a sealed space formed between first and second package members, and a piezoelectric vibrator is bonded to the first package member with first and second conductive adhesive portions. In the piezoelectric vibrator, a first vibration electrode and a first extended electrode are formed on a first surface of a piezoelectric substrate, and a second vibration electrode and a second extended electrode are formed on a second surface of the piezoelectric substrate. At least the second extended electrode provided on the second principal surface has a higher bonding strength with respect to the conductive adhesive than that of the electrodes on the first principal surface. The electrode patterns on the first and second principal surfaces differ from each other so that the first surface and the second surface can be distinguished from each other. | 2015-07-16 |
20150200648 | OPERATIONAL TRANSCONDUCTANCE AMPLIFIER, OPERATIONAL TRANSCONDUCTANCE AMPLIFIER-CAPACITOR FILTER AND HIGH ORDER RECONFIGURABLE ANALOG FILTER - An operational transconductance amplifier includes a fully-differential amplifying circuit, a bias driving circuit, and a common mode feedback circuit. The fully-differential amplifying circuit is configured for receiving a differential input voltage and providing a differential output voltage. The fully-differential amplifying circuit includes a plurality of diffusor-differential-pair circuits. The bias driving circuit is configured for providing at least one first bias current to drive the fully-differential amplifying circuit and adjust the transconductance of the transconductance amplifier. The common mode feedback circuit is configured for stabilizing the differential output voltage. An operational transconductance amplifier-capacitor (OTA-C) filter and a high order filter are disclosed herein as well. | 2015-07-16 |
20150200649 | FREQUENCY MANAGEMENT USING SAMPLE RATE CONVERSION - In one embodiment, an apparatus includes a first receiver path with a first digitizer to digitize an incoming signal obtained from a radio frequency signal including at least a first desired channel into samples, the first digitizer to operate at a first sampling frequency, a first sample rate converter coupled to an output of the first digitizer to receive the samples at the first sampling frequency and to output the samples at a fixed sampling frequency, and a first digital processor to receive and process the samples at the fixed sampling frequency. The apparatus may further include a controller to receive a frequency change indication and to dynamically control the first sample rate converter to accommodate a change in the first sampling frequency from a first rate to a second rate. | 2015-07-16 |
20150200650 | Capacitively Coupled Input Buffer - A buffer circuit comprising a capacitor, the capacitor comprising a first terminal and a second terminal, an input signal being coupled to the first terminal; a first buffer stage coupled to the second terminal of the capacitor such that the input signal is capacitively coupled to the first buffer stage; and, a pulse generator coupled to control the first buffer stage, the pulse generator being configured to generate a control pulse corresponding to a hold time of the first buffer stage such that the buffer circuit detects a transition of the input signal during the hold time. | 2015-07-16 |
20150200651 | MASTER-SLAVE FLIP-FLOP CIRCUIT AND METHOD OF OPERATING THE MASTER-SLAVE FLIP-FLOP CIRCUIT - A master-slave flip-flop circuit with a master latch and slave latch has clock generating circuitry which generates a gated clock signal based on the clock signal and a gating control signal. When the gating control signal has a first value, then the gated clock signal has a value dependent on the clock signal, while when the gating control signal has a second value then the gated clock signal has a fixed value independent of the clock signal. At least one component of the master-slave flip-flop circuit is controlled by the gated clock signal so that dynamic switching power can be reduced. The gating control signal is dependent on the input signal or a signal within the master latch and is independent of a slave signal in the slave latch and the output signal of the flip-flop. | 2015-07-16 |
20150200652 | LOW POWER TOGGLE LATCH-BASED FLIP-FLOP INCLUDING INTEGRATED CLOCK GATING LOGIC - Inventive aspects include integrated clock gating logic that can generate an internal glitch-free clock signal. Inventive aspects further include a toggle latch that is coupled to the integrated clock gating logic. The toggle latch can receive the internal clock signal from the integrated clock gating logic. The toggle latch can toggle and latch a data value responsive to the internal clock signal. The integrated clock gating logic can include a latch to latch a clock gating logic signal responsive to a clock signal. The clock gating logic signal can cause the internal clock signal to be quiescent when the input data to the flip-flop remains constant, thereby conserving power consumption. | 2015-07-16 |
20150200653 | POWER-ON RESET CIRCUIT - A power-on reset circuit includes a first resistor having one end connected to a power source node; a first capacitor connected to another end of the first resistor; a second resistor having one end connected to the power source node; a second capacitor connected to another end of the second resistor; a first inverter having a power source terminal connected to the other end of the first resistor and an input terminal connected to the other end of the second resistor; and a second inverter having a power source terminal connected to the other end of the first resistor, an input terminal connected to an output terminal of the first inverter, and an output terminal electrically connected to a reset signal output terminal. | 2015-07-16 |
20150200654 | POWER SUPPLY IMPEDANCE OPTIMIZING APPARATUS - In a power supply impedance optimizing apparatus, first and second noise detecting circuits detect noises of first and second power supplies by magnetic field coupling between bonding wires of the first and second power supplies and bonding wires for first and second noise detection. A noise determining circuit determines a noise level using a frequency component in each of one or more frequency ranges as extracted from each of the noises of the first and second power supplies. The noise determining circuit controls ON/OFF state of the first switch connected between pads of the first and second power supplies and the second switch connected between pins of the first and second power supplies based on a determination result of the noise level. | 2015-07-16 |
20150200655 | DUTY CYCLE CORRECTION CIRCUIT AND OPERATION METHOD THEREOF - A duty cycle correction circuit includes a clock adjustment unit configured to adjust a duty ratio of an input clock signal in response to a duty control signal and generate an output clock signal, a tracking type setting unit configured to generate an tracking type selection signal for setting a first or second tracking type based on a duty locking state of the output clock signal, and a control signal generation unit configured to generate the duty control signal, into which the first or second tracking type is incorporated, in response to the tracking type selection signal and the output clock signal. | 2015-07-16 |
20150200656 | DUTY CYCLE CORRECTION CIRCUIT AND OPERATION METHOD THEREOF - A duty cycle correction circuit includes a clock adjustment unit configured to adjust a duty ratio of an input clock signal in response to a duty control signal and generate an output clock signal, a tracking type setting unit configured to generate an tracking type selection signal for setting a first or second tracking type based on a duty locking state of the output clock signal, and a control signal generation unit configured to generate the duty control signal, into which the first or second tracking type is incorporated, in response to the tracking type selection signal and the output clock signal. | 2015-07-16 |
20150200657 | Nonvolatile Latch Circuit And Logic Circuit, And Semiconductor Device Using The Same - To provide a novel nonvolatile latch circuit and a semiconductor device using the nonvolatile latch circuit, a nonvolatile latch circuit includes a latch portion having a loop structure where an output of a first element is electrically connected to an input of a second element, and an output of the second element is electrically connected to an input of the first element; and a data holding portion configured to hold data of the latch portion. In the data holding portion, a transistor using an oxide semiconductor as a semiconductor material for forming a channel formation region is used as a switching element. In addition, a capacitor electrically connected to a source electrode or a drain electrode of the transistor is included. | 2015-07-16 |
20150200658 | FULLY DIFFERENTIAL LEVEL CONVERSION CIRCUIT - A fully differential level conversion circuit includes a positive signal branch, a negative signal branch and a coupling branch. The negative signal branch has identical structural features with the positive signal branch, which includes a drive terminal and a load terminal, an external fully differential signal is inputted to the drive terminals of the positive signal branch and the negative signal branch correspondingly. The coupling branch includes a first group of active couplers which forms a dual structure with the drive terminal of the positive signal branch and a second group of active couplers which form another dual structure with the drive terminal of the negative signal branch, both of which are connected between the drive terminals and load terminals. The fully differential level conversion circuit realizes applications in the signal processing process which has low power consumption and high-speed, and improves duty cycle of the output signal. | 2015-07-16 |
20150200659 | TRIANGULAR WAVE GENERATING CIRCUIT TO PROVIDE CLOCK SYNCHRONIZATION - A triangular wave generating circuit incorporates a capacitor, first, second, third, and fourth constant current sources, first and second switching units, a high/low level limiter, a clock generator, and a phase detecting unit. The first and second constant current sources charge the capacitor and the third and fourth constant current sources discharge the capacitor. The phase detecting unit compares an externally supplied clock signal with an internal clock signal and generates first and second phase signals base on a phase difference between the externally supplied clock signal and the internal clock signal. The second switching unit comprises a third switch and a fourth switch. The third switch couples the second constant current source to the capacitor in response to the first phase signal. The fourth switch couples the fourth constant current source to the capacitor in response to the second phase signal. | 2015-07-16 |
20150200660 | INTEGRATED CIRCUIT AND TRANSMISSION AND RECEPTION APPARATUS - An integrated circuit includes a transistor, and an impedance matching circuit coupled with the transistor. The impedance matching circuit includes a signal line to transmit a high-frequency signal and a power supply line that is a short stub branched from the signal line and supplies current to the transistor. The power supply line includes a bent line and a shortcut line to shortcut the bent line. | 2015-07-16 |
20150200661 | DRIVING METHOD AND DRIVING CIRCUIT FOR POWER SWITCHING DEVICE - According to example embodiments, a method of driving a power switch device includes applying a first voltage to a gate electrode of the power switch device, and applying a drive voltage to the gate electrode of the power switch device after applying the first voltage to the gate electrode of the power switch device. The first voltage is higher than the drive voltage of the power switch device in a turn-on state. | 2015-07-16 |
20150200662 | Monolithically Integrated Cascode Switches - Disclosed inventions are directed to advanced high-voltage switches with improved performance characteristics, increased reliability, and better compatibility with conventional gate drivers. The inventions disclosed herein implement a hybrid switch, comprising a high-voltage normally-on SiC VJFET, controlled via a low-voltage Si MOSFET in a cascode (Baliga-pair) configuration. The SiC VJFET and Si MOSFET are integrated monolithically at a wafer level, with the Si MOSFET fabricated on the Si layer that is directly adjacent to a dielectric layer on top of the SiC VJFET. Methods of making and operating these switches are also provided. | 2015-07-16 |
20150200663 | SAMPLE AND HOLD SWITCH CIRCUIT - A sample and hold switch circuit includes a clock generation sub-circuit, a gate voltage bootstrap unit, a sampling Field Effect Transistor, a holding capacitor and a substrate selection sub-circuit which is connected with a signal input terminal, a signal output terminal and a substrate of the sampling Field Effect Transistor and arranged for selecting the signal input terminal or the signal output terminal to connect with the substrate of the sampling Field Effect Transistor according to the voltages of the analog signal inputted and the analog signal outputted. The sample and hold switch circuit reduces nonlinearity of the sampling Field Effect Transistor caused by its gate-source voltage changing with input signal, and eliminates bulk effect of the sampling Field Effect Transistor, thereby improving linearity of the sampling Field Effect Transistor, and extending dynamic range of the sample and hold switch circuit. | 2015-07-16 |
20150200664 | TOUCH SENSOR - Embodiments of the invention provide a touch sensor and a method of manufacturing the touch sensor. The touch sensor includes a base substrate, and an electrode pattern formed on the base substrate. The electrode pattern includes a first pattern layer formed on the base substrate, a second pattern layer formed on the first pattern layer, and a third pattern layer formed to enclose the second pattern layer. The third pattern layer is formed to cover a side and an exposed upper surface of the second pattern layer and is made of tin. | 2015-07-16 |
20150200665 | OPERATION DEVICE - An operation device includes a detecting portion that is configured to detect an operation by a detected object and includes a plurality of operational areas each having a different assigned function executable on a controlled device as an operational object; and a dividing portion to guide the operation of the detected object and to separate the plurality of operational areas along boundaries between the plurality of operational areas of the detecting portion. The dividing portion includes an operable area that allows an operation across adjacent ones of the operational areas by the detected object. | 2015-07-16 |
20150200666 | FOUR-STATE INPUT DETECTION CIRCUITRY - A circuit to detect states of a signal is provided. The circuit comprises an input node to receive an input signal. A state detection circuit detects a state of the input signal and generates a detection signal. The state corresponds to at least one of three states. Furthermore, the detection signal generated by the state detection circuit has a level based on the detected state of the input signal. A logic discriminator circuit generates first and second state signals based at least partly on the level of the detection signal. A clock detection circuit generates a clock signal based at least partly on a sequence of logic transitions of the first and second state signals. | 2015-07-16 |
20150200667 | COLLAPSIBLE GLUE LOGIC SYSTEMS AND METHODS - Provided are systems and methods for reducing power consumption in the interface and routing circuitry associated with various core modules of an integrated circuit or system. One system includes core modules, glue logic domains adapted to interface the plurality of core modules, and a power controller electrically coupled to the glue logic domains. Each glue logic domain includes a glue logic module implemented as a soft macro with metal traces extending beyond an extent of the glue logic module. The power controller decouples power from selected glue logic domains based on control signals and/or detected power down states of core modules and/or other glue logic domains. The power controller facilitates the power transitions using logic state retention, logic state clamping, ordered or scheduled transitioning, and/or other power transition systems and methods. | 2015-07-16 |
20150200668 | SEMICONDUCTOR DEVICE - The power consumption of a semiconductor device that can function as a latch circuit or the like is reduced. The semiconductor device includes a first circuit and a switch that controls conduction between an input terminal and the first circuit. The first circuit includes n second circuits (n is an integer of 2 or more) and a variable resistor. An output node of any of the n second circuits is electrically connected to an input node of the second circuit in a first stage through the variable resistor. The variable resistor can be, for example, a transistor whose channel is formed in an oxide semiconductor layer. A reduction in the number of elements or signals leads to a reduction of the power consumption of the semiconductor device. | 2015-07-16 |
20150200669 | CLOCK GATING CIRCUIT FOR REDUCING DYNAMIC POWER - A clock-gating circuit is disclosed that may reduce unnecessary power consumption associated with clock distribution networks. For some embodiments, the clock-gating circuit includes a latch control circuit, a storage latch, and a logic gate. The control circuit has inputs to receive an input clock signal, a clock enable signal, and a clock gating control signal, and has an output terminal to generate a latch enable signal. The latch has a data terminal responsive to the clock enable signal, a latch enable terminal responsive to the latch enable signal, and an output to generate the clock gating control signal. The logic gate has inputs to receive the input clock signal and the clock gating control signal, and has an output terminal to generate an output clock signal. The clock-gating circuit may reduce power consumption during an enabled state by maintaining the latch enable signal at a constant logic state, thereby reducing dynamic power consumption by preventing internal logic gates from dynamically switching logic states while the input clock signal is gated. | 2015-07-16 |
20150200670 | GATE DRIVER AND RELATED CIRCUIT BUFFER - A circuit buffer for outputting a voltage signal having a magnitude greater than a withstand voltage of any circuit element in the circuit buffer includes a first transistor and a second transistor. The first transistor includes a first terminal and a second terminal electrically connected to an input terminal and an output terminal of the circuit buffer respectively, a third terminal electrically connected to a first power supply terminal, and a fourth terminal electrically connected to the third terminal of the first transistor. The second transistor includes a first terminal and a second terminal electrically connected to the input terminal and the output terminal of the circuit buffer respectively, a third terminal electrically connected to a second power supply terminal, and a fourth terminal electrically connected to the third terminal of the second transistor. Voltages of the first and second power supply terminal are switched between two different levels, respectively. | 2015-07-16 |
20150200671 | IMPLEMENTATION OF RELATED CLOCKS - An integrated circuit (IC) that includes multiple clock domains is provided. Each clock domain operates at a user specified data rate, and the data rates of at least two of the clock domains are related by a common base clock. The specified data rate of each clock domain is controlled by a modulating signal. Each clock domain includes reconfigurable circuits that operate on the common base clock, and the modulating signal controls the data rate of the clock domain by modulating reconfiguration of the reconfigurable circuits. The reconfigurable circuits reconfigure when the modulating signal enables the reconfiguration. | 2015-07-16 |
20150200672 | PROGRAMMABLE LOGIC DEVICE AND SEMICONDUCTOR DEVICE - A programmable logic device that includes a storage device having smaller area and lower power consumption is provided. The programmable logic device includes a logic block including a storage device. The storage device includes a plurality of groups each including at least a first switch, a transistor that is turned on or off in accordance with a signal including configuration data input to a gate of the transistor through the first switch, and a second switch controlling the electrical connection between a first wiring and a second wiring together with the transistor when the second switch is turned on or off in accordance with the potential of the first wiring. In the logic block, the relationship between the logic level of a signal input and the logic level of a signal output is determined in accordance with the potential of the second wiring. | 2015-07-16 |
20150200673 | METHOD OF OUTPUTTING POSITIONING PULSE BY PLC - A method of outputting a positioning pulse by a programmable logic controller (PLC) is provided. The method includes setting up the desired cycle of a pulse to be output; determining a number of needed clocks based on a number of system clocks and a desired frequency according to the desired cycle; determining a total number of needed clocks based on the number of needed clocks and the desired frequency; determining a clock difference based on the number of system clocks and the total number of needed clocks; determining a first number of setup clocks corresponding to a first output pulse in a certain cycle; determining a second number of setup clocks corresponding to pulses except for the first output pulse; and outputting a pulse based on the first number of setup clocks and the second number of setup clocks. | 2015-07-16 |
20150200674 | TIMING ADJUSTMENT CIRCUIT, CLOCK GENERATION CIRCUIT, AND METHOD FOR TIMING ADJUSTMENT - A timing adjustment circuit includes a detection unit to generate a detection signal in response to a first clock having a duty cycle of 50% and a first frequency, a second clock having a duty cycle of 50% and a second frequency that is half the first frequency, and a third clock having a duty cycle of 50%, the second frequency, and a phase displacement of 90 degrees relative to the second clock, the detection signal indicating timing relationship between the first clock and the second and third clocks, a low-pass filter to receive the detection signal, and a variable-delay circuit to adjust relative timing relationship between the first clock and the second clock in response to an output of the low-pass filter such that a center point of a pulse of the first clock is aligned with a center point of a pulse of the second clock. | 2015-07-16 |
20150200675 | Initializing Components of an Integrated Circuit - Methods, systems, and computer program products for initializing one or more components of a system, the system comprising an integrated circuit that comprises at least one processor, are disclosed. A method includes initializing at least one component of the system, determining a temperature of the integrated circuit using a temperature sensing device embedded on the integrated circuit, comparing the determined temperature to a predetermined suitable temperature operating range of at least one additional component to yield a comparison result, and initializing the at least one additional component based on the comparison result. The at least one additional component may be initialized on the condition that the determined temperature of the integrated circuit is within the predetermined suitable temperature operating range of the at least one additional component. | 2015-07-16 |
20150200676 | PREDICTION BASED DIGITAL CONTROL FOR FRACTIONAL-N PLLS - Methods and systems for phase correction include determining a phase error direction and generating a prediction for the phase error based on a sigma-delta error. It is determined whether the prediction agrees with the determined phase error direction. If the prediction does not agree, a phase correction is adjusted in accordance with the predicted phase error. | 2015-07-16 |
20150200677 | REMOVING DETERMINISTIC PHASE ERRORS FROM FRACTIONAL-N PLLS - Methods and devices for phase adjustment include a phase detector that is configured to compare a reference clock and a feedback clock and to generate two output signals. A difference in time between pulse widths of the two output signals corresponds to a phase difference between the reference clock and the feedback clock. A programmable delay line is configured to delay an earlier output signal in accordance with a predicted deterministic phase error. An oscillator is configured to generate a feedback signal in accordance with the delayed output signal. A divider is configured to divide a frequency of the oscillator output by an integer N. The integer N is varied to achieve an average fractional divide ratio and the predicted deterministic phase error is based on the average divide ratio and an instantaneous divide ratio. | 2015-07-16 |
20150200678 | DELTA-SIGMA MODULATOR - Provided is a delta-sigma modulator including a summer summing an input signal and an analog signal, a first integrator integrating an output signal from the summer and outputting a first integration signal, a second integrator integrating the first integration signal and outputting a second integration signal, a comparator comparing the second integration signal and a reference signal and outputting a digital signal according to the comparison result, and a digital-to-analog converter converting the digital signal into an analog signal in response to a clock signal and outputting the converted analog signal, wherein the second integrator operates based on an Nth order (where N is natural number of 1 or greater) transfer function. | 2015-07-16 |
20150200679 | Digital Down Converter With Equalization - A digital down converter with equalization includes an analog to digital converter (ADC), a frequency divider, an FIR-decimator-I, an FIR-decimator-Q and a frequency corrector. In operation, after some preprocessing, the FIR-decimator-I performs signal transformation equivalent to a sequence of equalization, multiplication of the processed signal by a sine wave of a conversion frequency and low pass filtering, and the FIR-decimator-Q performs signal transformation equivalent to a sequence of equalization, multiplication of the processed signal by a sine wave of conversion frequency with a phase shift of 90° and low pas filtering. The transformed signals are applied to the frequency corrector, which provides a frequency shift of predetermined value with respect to a nominal carrier frequency of the applied analog input signal and generates an In-Phase output and a Quadrature output. | 2015-07-16 |
20150200680 | METHOD AND DEVICE FOR DIGITALIZING SCINTILLATION PULSE - A method for digitalizing scintillation pulses includes: defining n threshold voltages V_th, forming a voltage comparison unit by n low-voltage differential signaling receiving ports, outputting, by the voltage comparison unit, a state-flip and a threshold voltage corresponding to the state-flip when one scintillation pulse to be sampled exceeds any one of the thresholds; and sampling digitally a time when the state-flip in step (2) occurs by a time-to-digit converter and identifying the threshold voltage corresponding to the state-flip, to acquire the voltage and the time for the scintillation pulse. The method can be performed using a device for digitalizing scintillation pulses. | 2015-07-16 |
20150200681 | Segmented Digital-To-Analog Converter With Overlapping Segments - In one embodiment, a segmented digital-to-analog converter (DAC) has two configurations (i.e., sub-DACs) with overlapping operating ranges and a data mapper that maps the digital input signal into two different digital signals, one for each sub-DAC. The currents generated by the sub-DACs are combined and then used to generate the corresponding analog output signal. Because the sub-DACs have overlapping operating ranges, the DAC can be calibrated to account for process variations that result in the actual current ratio between the two sub-DACs being different from the ideal, designed current ratio. Calibration algorithms generate calibration constants that are applied by the data mapper when mapping the digital input signal into the two digital signals respectively applied to the two sub-DACs. In this way, high-precision DACs can be implemented without requiring expensive circuitry to handle undesirable current mismatch resulting from process variations. | 2015-07-16 |
20150200682 | ANALOG-TO-DIGITAL CONVERSION APPARATUS - An A/D conversion apparatus includes a signal processor, a quantizer, and a controller. The signal processor has circuit blocks connected in a loop to process an analog input signal. The quantizer generates a quantization value by quantizing an output of at least one of the circuit blocks including a final-stage circuit block. In each circuit block, one end of a first capacitor is connected through a switch to an input terminal of an operational amplifier, and one end of each of second and third capacitors is connected directly to the operational amplifier. The controller generates an A/D conversion result of the analog input signal according to the quantization value and changes connection conditions of the capacitors so that the signal processor and the quantizer function as a delta-sigma modulator or a cyclic A/D converter. | 2015-07-16 |
20150200683 | PARALLEL-SERIAL CONVERTER CIRCUIT - A parallel-serial converter circuit has a frequency divider configured to generate a frequency-divided signal by dividing a frequency of a reference clock signal by a dividing ratio depending on a logic of a speed control signal, a timing pulse generator configured to generate a timing pulse signal based on the frequency-divided signal, a load signal generator configured to generate a load signal based on the speed control signal and the timing pulse signal, a bit clock generator configured to generate a bit clock signal based on the speed control signal and the timing pulse signal, and a parallel-serial converter configured to newly load the parallel data in synchronization with the load signal and convert the loaded parallel data into serial data in synchronization with the bit clock signal. | 2015-07-16 |
20150200684 | METHOD AND SYSTEM FOR ESTIMATING PARAMETER OF DATA CHANNEL MODEL IN COMMUNICATION SYSTEM - A method and a system for estimating a parameter in a communication system are provided. The method includes estimating a parameter of a data channel model in a communication system, decoding a packet received through a determined noise channel to convert the packet into data indicating one of a success and failure of a reception of the packet, configuring a prototype channel having at least one unknown parameter, estimating the at least one unknown parameter using the data indicating the one of the success and the failure of the reception of the packet, and determining the size of a parity field of a forward error correction (FEC) symbol, using the estimated at least one unknown parameter. | 2015-07-16 |
20150200685 | RECORDING AND REPRODUCING DEVICE, ERROR CORRECTION METHOD, AND CONTROL DEVICE - A recording and reproducing device includes a plurality of data storing units, a control unit, a first error detection-and-correction unit, and a second error detection-and-correction unit. The control unit creates stripe data with a predetermined write capacity, creates a redundant group, associates a plurality of pieces of stripe data, and controls the writing of the associated data into each of the plurality of the data storing units. The first error detection-and-correction unit detects whether an error is present in each of the pieces of the stripe data, and corrects the stripe data. The second error detection-and-correction unit groups the second error correction code and the pieces of the stripe data, creates a plurality of error correction groups, detects whether an error is present in each of the pieces of the split stripe data in the same error correction group, and corrects the split stripe data. | 2015-07-16 |
20150200686 | ENCODING DEVICE, DECODING DEVICE, AND OPERATING METHOD THEREOF - An encoding device includes a first encoder that generates a message matrix including a plurality of message blocks and a parity block having parity information of the plurality of message blocks, and a second encoder that adds row parity information and column parity information to the message matrix. | 2015-07-16 |
20150200687 | CHANNEL CODING METHOD OF VARIABLE LENGTH INFORMATION USING BLOCK CODE - A method for channel-coding information bits using a code generation matrix including 32 rows and A columns corresponding to length of the information bits includes, channel-coding the information bits having “A” length using basis sequences having 32-bit length corresponding to columns of the code generation matrix, and outputting the channel-coded result as an output sequence. If “A” is higher than 10, the code generation matrix is generated when (A-10) additional basis sequences were added as column-directional sequences to a first or second matrix. The first matrix is a TFCI code generation matrix composed of 32 rows and 10 columns used for TFCI coding. The second matrix is made when at least one of an inter-row location or an inter-column location of the first matrix was changed. The additional basis sequences satisfy a value 10 of a minimum Hamming distance. | 2015-07-16 |
20150200688 | DYNAMIC LOG-LIKELIHOOD RATIO MAPPING FOR ERROR CORRECTING CODE DECODING - Apparatuses, systems, methods, and computer program products are disclosed for error correction. A soft read module is configured to obtain soft read information for a cell of a non-volatile memory medium. The soft read information may indicate a likelihood that a data value for the cell is correct. A reliability module is configured to associate the cell with a log-likelihood ratio (LLR) mapping from a plurality of LLR mappings based on one or more reliability characteristics for a set of cells that includes the cell. An LLR map module is configured to determine an LLR value based on the soft read information by using the LLR mapping. | 2015-07-16 |
20150200689 | METHOD AND APPARATUS FOR ENCODING AND DECODING IN ELECTRONIC DEVICE - A method and an apparatus for encoding and decoding in an electronic device are provided. In a decoding method, at least one parity symbol is received. A Cauchy matrix is generated using the at least one parity symbol. A Cauchy submatrix is configured from the Cauchy matrix based on the number of at least one lost data symbol and an inverse matrix of the Cauchy submatrix is calculated. At least one parity symbol corresponding to the at least one lost data symbol is updated. The at least one lost data symbol is recovered using the updated at least one parity symbol. | 2015-07-16 |
20150200690 | INTER CARRIER-AGGREGATION ISOLATION IN A RECEIVER - A device includes a first amplifier circuit coupled to a first transformer and a second transformer, the first transformer selectively coupled to a first shared power distribution network through a first switch, the second transformer selectively coupled to a second shared power distribution network through a second switch. | 2015-07-16 |
20150200691 | MOBILE WIRELESS DEVICE FOR A MOTOR VEHICLE, AND METHOD FOR OPERATING THE MOBILE WIRELESS DEVICE - A mobile radio apparatus for a motor vehicle has a first mobile radio module and a second mobile radio module. Furthermore, a first antenna and a second antenna are provided for transmitting mobile radio signals. To provide robust voice telephony for the motor vehicle that can be implemented with little circuit complexity, a switching device is connected to the antennas and to a respective signal connection of the mobile radio modules and that is designed to take a switching signal as a basis for changing over between a first switching state, in which the first signal connection is coupled to the first antenna and the second signal connection is coupled to the second antenna, and a second switching state, in which the first signal connection is coupled to the second antenna and the second signal connection is coupled to the first antenna. | 2015-07-16 |
20150200692 | SYSTEM FOR THE COEXISTENCE BETWEEN A PLURALITY OF WIRELESS COMMUNICATIONS MODULES SHARING SINGLE ANTENNA - A system for the coexistence between a plurality of wireless communication modules sharing a single antenna includes an antenna, first and second transceiving paths, and first and second wireless communications modules. The first wireless communications module is coupled to a first transceiving path and transmits or receives first wireless signals via the first transceiving path. The second wireless communications module is coupled to the second transceiving path and transmits and receives second wireless signals via the first and the second transceiving paths, wherein signal strengths of the second wireless signals passing through the second transceiving path are attenuated by a certain level, and the attenuated second wireless signals are added to the first wireless signals when passing through the first transceiving path, wherein one of the first and the second communications module is a LTE module and the other one is a WLAN module. | 2015-07-16 |
20150200693 | TRANSMITTER HAVING INTEGRATED DESIGN OF MULTIPLE WIRELESS COMMUNICATION MODULES - A transmitter includes a first wireless communication module, a second wireless communication module, a multiplexer, a digital-to-analog converter and a filter. The multiplexer selectively outputs a first digital signal derived from a digital output of the first wireless communication module or a second digital signal derived from a digital output of the second wireless communication module as a selected output. The digital-to-analog converter converts the selected output into an analog signal. The filter processes the analog signal and includes an adjustable resistive element. When the multiplexer selects the first digital signal as the selected output, the adjustable resistive element is adjusted to have a first resistance value such that the filter has a first bandwidth. When the multiplexer selects the second digital signal as the selected output, the adjustable resistive element is adjusted to have a second resistance value such that the filter has a second bandwidth. | 2015-07-16 |
20150200694 | Detecting Narrow Band Interference in Wireless Networks using Spectral Analysis - A method detects narrow band interference in wireless networks by first thresholding each block of samples to produce thresholded samples. The samples are normalized frequency magnitudes obtained from a spectrum of a wireless signal in a channel. Each block of the thresholded samples is summed to produce a thresholded value for each block. Then, thresholded values are autocorrelated to determine whether a bandwidth of the wireless signal is consistent with narrow band interference. | 2015-07-16 |
20150200695 | Method and Apparatus for Processing a Multiple-Carrier Signal Provided with Subcarriers Distributed in a Band - A method for processing a multiple carrier signal provided with subcarriers distributed in a band. The method includes calculating a subcarrier noise of an edge of the band, calculating a subcarrier noise of a center of the band, calculating a ratio of the subcarrier noise of the edge of the band to the subcarrier noise of the center of the band, determining whether the ratio is greater than a threshold, and acknowledging that the edge of the band suffers from interference when the ratio is greater than the threshold. | 2015-07-16 |
20150200696 | METHOD AND DEVICE FOR MAINTAINING THE PERFORMANCE QUALITY OF A COMMUNICATION SYSTEM IN THE PRESENCE OF NARROW BAND INTERFERENCE - A system that incorporates teachings of the subject disclosure may include, for example, a process for determining, by a base station comprising a processor, a mitigation strategy based on detection of a narrow band interferer according to an adaptive threshold. The narrow band interferer is detected in a wide frequency band of a received signal, and the adaptive threshold is determined by sampling at least some narrow band signal power levels in the wide frequency band. Information descriptive of the narrow band interferer is obtained, and interference caused by the narrow band interferer is reduced based on the information and according to the mitigation strategy. Other embodiments are disclosed. | 2015-07-16 |
20150200697 | INTERFERENCE CANCELATION USING COOPERATIVE SENSING - A first receiver of a victim communication device may detect a first signal from an aggressor transmitter that potentially may interfere with a second signal intended to be received at a second receiver of the victim communication device. It may be determined whether the first signal interferes with the second signal based, at least in part, on the characteristics of the first signal and the second receiver. If the first signal may interfere with the second signal, the second receiver may implement reconstruction and cancelation of the interference attributable to the first signal. | 2015-07-16 |
20150200698 | RF MODULE AND WIRELESS COMMUNICATION DEVICE - A radio frequency module of a wireless communication device is provided. The radio frequency module is coupled between an antenna and a micro-control unit and includes a radio frequency front-end, a radio frequency integrated circuit, a baseband low-pass filter and a comparator. The radio frequency front-end receives a radio frequency signal through the antenna. The radio frequency integrated circuit receives the radio frequency signal from the radio frequency front-end and converts the radio frequency signal into a baseband signal. The baseband low-pass filter receives the baseband signal from the radio frequency integrated circuit and filters the baseband signal. The comparator compares the filtered baseband signal with a first reference signal and outputs a comparison result signal to the micro-control unit. | 2015-07-16 |
20150200699 | PROTECTIVE CASE HAVING MODULAR COMPONENTS - A protective case for a mobile device such as a tablet computer is disclosed that includes modular components that can be mixed and matched by the user at the point of purchase to facilitate creation of a user customizable look. The case includes a shell that is configured to retain the tablet device and a front cover that is configured to protect and conceal the screen of the tablet when the case is in the closed position. When the assembled case is in the open position and the tablet is retained within the shell, the cover is configured to stand the shell up on edge. The shell and front cover can be reversibly attached to one another by the user, so that the user can select a shell of one color, material, design, or style and a front cover of another color, material, design or style. Retention tab and slot are employed to reversibly lock the front cover to the shell to form a seamless integrated multi use mode case. | 2015-07-16 |
20150200700 | TWO-WAY WIRELESS COMMUNICATION ENABLED INTRUSION DETECTOR ASSEMBLIES - A fixed magnetic contact wireless transceiver including a two-way transceiver element adapted to be operable for two-way wireless communication between a fixed magnetic contact wireless transceiver component and an intrusion alarm system, an antenna facilitating the two-way wireless communication between the fixed magnetic contact wireless transceiver component and the intrusion alarm system, and an antenna ground reference plane, opposite the antenna, wherein the antenna includes a substrate, a top surface of the substrate being coated with a gold plated copper substrate coating, the coating having a gap formed therein, and half via holes formed in a perimeter of the antenna, the half via holes being coated with gold plated copper half via hole coatings which form a continuum with the gold plated copper substrate coating. | 2015-07-16 |
20150200701 | ASSEMBLY COMPRISING TWO ANTENNAS CONTROLLABLE TO OUTPUT OR NOT OUTPUT SIGNALS - An assembly, a method of operating the assembly and antennas for use in the assembly, where two or more antennas ( | 2015-07-16 |