29th week of 2014 patent applcation highlights part 14 |
Patent application number | Title | Published |
20140197489 | Power MOSFETs and Methods for Forming the Same - Power Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) and methods of forming the same are provided. A power MOSFET may comprise a first drift region formed at a side of a gate electrode, and a second drift region beneath the gate electrode, adjacent to the first drift region, with a depth less than a depth of the first drift region so that the first drift region and the second drift region together form a stepwise shape. A sum of a depth of the second drift region, a depth of the gate dielectric, and a depth of the gate electrode may be of substantially a same value as a depth of the first drift region. The first drift region and the second drift region may be formed at the same time, using the gate electrode as a part of the implanting mask. | 2014-07-17 |
20140197490 | SEMICONDUCTOR DEVICE - A semiconductor device with improved characteristics is provided. The semiconductor device includes a LDMOS, a source plug electrically coupled to a source region of the LDMOS, a source wiring disposed over the source plug, a drain plug electrically coupled to a drain region of the LDMOS, and a drain wiring disposed over the drain plug. The structure of the source plug of the semiconductor device is devised. The semiconductor device is structured such that the drain plug is linearly disposed to extend in a direction Y, and the source plug includes a plurality of separated source plugs arranged at predetermined intervals in the direction Y. In this way, the separation of the source plug decreases an opposed area between the source plug and the drain plug, and can thus decrease the parasitic capacitance therebetween. | 2014-07-17 |
20140197491 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device and manufacturing method are disclosed which provide increased ESD resistance. By disposing a slit mask when forming a second p-type well layer, impurity concentration of the second p-type well layer is partially reduced. By forming a second n-type offset layer in the second p-type well layer having decreased impurity concentration, it is possible to increase thickness of the second n-type offset layer in this place compared with that heretofore known. By increasing thickness of the second n-type offset layer, a depletion layer does not reach an n-type drain layer at a low voltage when reverse bias is applied to the drain. It thus is possible to prevent thermal destruction caused by localized electrical field concentration. As a result, it is possible to increase ESD resistance. As it is sufficient to replace a photoresist mask, there is no increase in the number of processes. | 2014-07-17 |
20140197492 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD - Semiconductor devices and fabrication methods are provided. In an exemplary method, a semiconductor layer including a first opening can be provided. The first opening can be filled with a stress material. The stress material can then be etched to form a second opening having a width less than a width of the first opening to leave a stress material layer in the semiconductor layer and on each sidewall of the second opening. The semiconductor layer can be etched to form a fin structure on a sidewall surface of the stress material layer. A main gate structure can be formed on the sidewall surface of the fin structure. A back gate structure can be formed on the sidewall surface of the stress material layer. | 2014-07-17 |
20140197493 | DEFECT REDUCTION FOR FORMATION OF EPITAXIAL LAYER IN SOURCE AND DRAIN REGIONS - The embodiments of mechanisms for forming source/drain (S/D) regions of field effect transistors (FETs) described enable forming an epitaxially grown silicon-containing layer with reduced number of particles on surface of recesses. The described mechanisms also reduce the effect of the residual particles on the epitaxial growth. The mechanisms include controlled etch of a native oxide layer on the surfaces of recesses to reduce creation of particles, and pre-CDE etch to remove particles from surface. The mechanisms also include reduced etch/deposition ratio(s) of initial CDE unit cycle(s) of CDE process to reduce the effect of residual particles on the formation of the epitaxially grown silicon-containing layer. With the application of one or more of the mechanisms, the quality of the epitaxial layer is improved. | 2014-07-17 |
20140197494 | TRENCH SILICIDE AND GATE OPEN WITH LOCAL INTERCONNECT WITH REPLACEMENT GATE PROCESS - A semiconductor device fabrication process includes forming insulating mandrels over replacement metal gates on a semiconductor substrate with first gates having sources and drains and at least one second gate being isolated from the first gates. Mandrel spacers are formed around each insulating mandrel. The mandrels and mandrel spacers include the first insulating material. A second insulating layer of the second insulating material is formed over the transistor. One or more first trenches are formed to the sources and drains of the first gates by removing the second insulating material between the insulating mandrels. A second trench is formed to the second gate by removing portions of the first and second insulating materials above the second gate. The first trenches and the second trench are filled with conductive material to form first contacts to the sources and drains of the first gates and a second contact to the second gate. | 2014-07-17 |
20140197495 | SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME - A semiconductor device may include an n-MOS transistor, and a p-MOS transistor. The p-MOS transistor may include, but is not limited to, a gate insulating film and a gate electrode. The gate electrode may have an adjacent portion that is adjacent to the gate insulating film. The adjacent portion may include a polysilicon that contains an n-type dopant and a p-type dopant. | 2014-07-17 |
20140197496 | Semiconductor Structure with Suppressed STI Dishing Effect at Resistor Region - An integrated circuit includes a semiconductor substrate; a first shallow trench isolation (STI) feature of a first width and a second STI feature of a second width in a semiconductor substrate. The first width is less than the second width. The first STI feature has an etch-resistance less than that of the second STI feature. | 2014-07-17 |
20140197497 | NATIVE PMOS DEVICE WITH LOW THRESHOLD VOLTAGE AND HIGH DRIVE CURRENT AND METHOD OF FABRICATING THE SAME - A native p-type metal oxide semiconductor (PMOS) device that exhibits a low threshold voltage and a high drive current over a varying range of short channel lengths and a method for fabricating the same is discussed in the present disclosure. The source and drain regions of the native PMOS device, each include a strained region, a heavily doped raised region, and a lightly doped region. The gate region includes a stacked layer of a gate oxide having a high-k dielectric material, a metal, and a contact metal. The high drive current of the native PMOS device is primarily influenced by the increased carrier mobility due to the strained regions, the lower drain resistance due to the raised regions, and the higher gate capacitance due to the high-k gate oxide of the native PMOS device. | 2014-07-17 |
20140197498 | INTEGRATED CIRCUITS AND METHODS FOR FABRICATING INTEGRATED CIRCUITS WITH IMPROVED SILICIDE CONTACTS - Integrated circuits and methods for fabricating integrated circuits are provided herein. In an embodiment, a method for fabricating an integrated circuit includes forming over a semiconductor substrate a gate structure. The method further includes depositing a non-conformal spacer material around the gate structure. A protection mask is formed over the non-conformal spacer material. The method etches the non-conformal spacer material and protection mask to form a salicidation spacer. Further, a self-aligned silicide contact is formed adjacent the salicidation spacer. | 2014-07-17 |
20140197499 | Self Aligned Contact Formation - The present disclosure relates to methods of forming a self-aligned contact and related apparatus. In some embodiments, the method forms a plurality of gate lines interspersed between a plurality of dielectric lines, wherein the gate lines and the dielectric lines extend in a first direction over an active area. One or more of the plurality of gate lines are into a plurality of gate line sections aligned in the first direction. One or more of the plurality of dielectric lines are cut into a plurality of dielectric lines sections aligned in the first direction. A dummy isolation material is deposited between adjacent dielectric sections in the first direction and between adjacent gate line sections in the first direction. One or more self-aligned metal contacts are then formed by replacing a part of one or more of the plurality of dielectric lines over the active area with a contact metal. | 2014-07-17 |
20140197500 | CAPACITIVE SENSOR INTEGRATED ONTO SEMICONDUCTOR CIRCUIT - There is disclosed a capacitive sensor on a passivation layer of a semiconductor circuit such as an ASIC, and a method for manufacturing such sensor. The system and method may comprise: forming a bottom electrode layer and landing pad on a portion of the passivation layer located over active circuitry of the ASIC; forming a gas sensitive layer onto the bottom electrode layer and the landing pad; creating a via through the gas sensitive layer to expose a portion of the landing pad; forming a top electrode layer onto the gas sensitive layer, wherein the top electrode layer completely overlays a surface area of the bottom electrode layer, and wherein the forming process for the top electrode layer deposits a portion of the top electrode layer into the via hole, thereby forming an electrical connection between the top electrode layer and the landing pad. | 2014-07-17 |
20140197501 | MEMS Device with Polymer Layer, System of a MEMS Device with a Polymer Layer, Method of Making a MEMS Device with a Polymer Layer - A MEMS device, a method of making a MEMS device and a system of a MEMS device are shown. In one embodiment, a MEMS device includes a first polymer layer, a MEMS substrate disposed on the first polymer layer and a MEMS structure supported by the MEMS substrate. The MEMS device further includes a first opening disposed in the MEMS substrate and a second opening disposed in the first polymer layer. | 2014-07-17 |
20140197502 | Comb MEMS Device and Method of Making a Comb MEMS Device - A MEMS device and a method to manufacture a MEMS device are disclosed. An embodiment includes forming trenches in a first main surface of a substrate, forming conductive fingers by forming a conductive material in the trenches and forming an opening from a second main surface of the substrate thereby exposing the conductive fingers, the second main surface opposite the first main surface. | 2014-07-17 |
20140197503 | SENSOR PACKAGE - A sensor package is disclosed. One embodiment provides a sensor device having a carrier, a semiconductor sensor mounted on the carrier and an active surface. Contact elements are electrically connecting the carrier with the semiconductor sensor. A protective layer made of an inorganic material covers at least the active surface and the contact elements. | 2014-07-17 |
20140197504 | Mg Discontinuous Insertion Layer for Improving MTJ Shunt - A MTJ is disclosed with a discontinuous Mg or Mg alloy layer having a thickness from 1 to 3 Angstroms between a free layer and a capping layer in a bottom spin valve configuration. It is believed the discontinuous Mg layer serves to block conductive material in the capping layer from diffusing through the free layer and into the tunnel barrier layer thereby preventing the formation of conductive channels that function as electrical shunts within the insulation matrix of the tunnel barrier. As a result, the “low tail” percentage in a plot of magnetoresistive ratio vs Rp is minimized which means the number of high performance MTJ elements in a MTJ array is significantly increased, especially when a high temperature anneal is included in the MTJ fabrication process. The discontinuous layer is formed by a low power physical vapor deposition process. | 2014-07-17 |
20140197505 | SHIELDS FOR MAGNETIC MEMORY CHIP PACKAGES - Chip packages are described with soft-magnetic shields that are included inside or attached externally to the package containing a MRAM chip. In one group of embodiments a single shield with vias for bonding wires is affixed to the surface of the MRAM chip having the contact pads. The limitation of shield to chip distance due to bonding wire is eliminated by VIA holes according to the invention which achieves minimal spacing between the shield and chip. A second shield without vias can be positioned on the opposite side of the chip from the first shield. In one group of embodiments a hardened ferro-fluid shield can be the only shield or the structure can include a shield with or without vias. One group of embodiments includes an external shield with vias for solder access to the package contact pads affixed to the outer surface of the package. | 2014-07-17 |
20140197506 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device includes: an organic substrate; an integrated circuit and a chip part provided on the organic substrate; a molded section including a central portion and a peripheral portion, and forming, as a whole, a concave shape, the central portion sealing the integrated circuit and the chip part on the organic substrate, and the peripheral portion standing around the central portion; and a solid-state image pickup element provided on the central portion of the molded section, the solid-state image pickup element having a top edge that is lower in position in a thickness direction than a top edge of the peripheral portion of the molded section. | 2014-07-17 |
20140197507 | BURIED WAVEGUIDE PHOTODETECTOR - A method of forming an integrated photonic semiconductor structure having a photodetector and a CMOS device may include forming the CMOS device on a first silicon-on-insulator region, forming a silicon optical waveguide on a second silicon-on-insulator region, and forming a shallow trench isolation (STI) region surrounding the silicon optical waveguide such that the shallow trench isolation electrically isolating the first and second silicon-on-insulator region. Within a first region of the STI region, a first germanium material is deposited adjacent a first side wall of the semiconductor optical waveguide. Within a second region of the STI region, a second germanium material is deposited adjacent a second side wall of the semiconductor optical waveguide, whereby the second side wall opposes the first side wall. The first and second germanium material form an active region that evanescently receives propagating optical signals from the first and second side wall of the semiconductor optical waveguide. | 2014-07-17 |
20140197508 | IMAGE SENSOR AND METHOD FOR FABRICATING THE SAME - An image sensor comprises a substrate, a plurality of image sensing elements and a first inorganic optical layer, wherein the substrate has an active region; the image sensing elements are disposed in the active region; and the first inorganic optical layer covers the image sensing elements and has at least two adjacent edges for forming an angle greater than 90 degrees (90°). | 2014-07-17 |
20140197509 | PHOTOSENSITIVE IMAGING DEVICES AND ASSOCIATED METHODS - Backside illuminated photosensitive devices and associated methods are provided. In one aspect, for example, a backside-illuminated photosensitive imager device can include a semiconductor substrate having multiple doped regions forming a least one junction, a textured region coupled to the semiconductor substrate and positioned to interact with electromagnetic radiation, and a passivation region positioned between the textured region and the at least one junction. The passivation region is positioned to isolate the at least one junction from the textured region, and the semiconductor substrate and the textured region are positioned such that incoming electromagnetic radiation passes through the semiconductor substrate before contacting the textured region. Additionally, the device includes an electrical transfer element coupled to the semiconductor substrate to transfer an electrical signal from the at least one junction. | 2014-07-17 |
20140197510 | CONVERSION STRUCTURE, IMAGE SENSOR ASSEMBLY AND METHOD FOR FABRICATING CONVERSION STRUCTURE - An electromagnetic wave conversion structure consists of a substrate, a plurality of electromagnetic wave conversion units forming a two-dimensional array, a reflective film and a plurality of reflective layers. The substrate has a first surface and a second surface disposed opposite to the first surface. The second surface consists of a plurality of trenches formed in the body of the substrate. Each electromagnetic wave conversion units is disposed in each trench, is used to absorb first electromagnetic waves with a first wavelength and is used to emit second electromagnetic waves with a second wavelength. The first wavelength is shorter than the second wavelength. The reflective film covers the first surface of the substrate and is used to reflect the second electromagnetic wave. Each of the reflective layers is disposed on the sidewall of each trench of the corresponding electromagnetic wave conversion unit. | 2014-07-17 |
20140197511 | METHODS FOR FORMING BACKSIDE ILLUMINATED IMAGE SENSORS WITH FRONT SIDE METAL REDISTRIBUTION LAYERS - Methods for forming backside illuminated (BSI) image sensors having metal redistribution layers (RDL) and solder bumps for high performance connection to external circuitry are provided. In one embodiment, a BSI image sensor with RDL and solder bumps may be formed using a temporary carrier during manufacture that is removed prior to completion of the BSI image sensor. In another embodiment, a BSI image sensor with RDL and solder bumps may be formed using a permanent carrier during manufacture that partially remains in the completed BSI image sensor. A BSI image sensor may be formed before formation of a redistribution layer on the front side of the BSI image sensor. A redistribution layer may, alternatively, be formed on the front side of an image wafer before formation of BSI components such as microlenses and color filters on the back side of the image wafer. | 2014-07-17 |
20140197512 | SEMICONDUCTOR DEVICE - A semiconductor device includes a substrate with first and second lower electrodes, a semiconductor element supported on the substrate and including upper and lower electrodes, a conductive bonding material bonding the lower electrode of the element and the substrate to each other, a wire connecting the upper electrode of the element and the substrate to each other, and a sealing resin covering the semiconductor element and the wire. The substrate includes a barrier that encloses at least partially the conductive bonding material. | 2014-07-17 |
20140197513 | Image Sensor with Improved Dark Current Performance - Provided is a semiconductor image sensor device. The image sensor device includes a semiconductor substrate that includes an array region and a black level correction region. The array region contains a plurality of radiation-sensitive pixels. The black level correction region contains one or more reference pixels. The substrate has a front side and a back side. The image sensor device includes a first compressively-stressed layer formed on the back side of the substrate. The first compressively-stressed layer contains silicon nitride. The image sensor device includes a metal shield formed on the compressively-stressed layer. The metal shield is formed over at least a portion of the black level correction region. The image sensor device includes a second compressively-stressed layer formed on the metal shield and the first compressively-stressed layer. The second compressively-stressed layer contains silicon oxide. A sidewall of the metal shield is protected by the second compressively-stressed layer. | 2014-07-17 |
20140197514 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device that is equipped with a semiconductor substrate, a composite metal film, and a detection terminal is provided. The composite metal film is formed on a surface or a back face of the semiconductor substrate, and has a first metal film, and a second metal film that is joined to the first metal film and is different in Seebeck coefficient from the first metal film. The detection terminal can detect a potential difference between the first metal film and the second metal film. | 2014-07-17 |
20140197515 | HIGH VOLTAGE CIRCUIT LAYOUT STRUCTURE - A high voltage circuit layout structure has a P-type substrate; a first N-type tub, a second N-type tub, a third N-type tub, a first P-type tub with a first width and a second P-type tub with a second width formed on the P-type substrate; wherein the first P-type tub is formed between the first N-type tub and the second N-type tub; and the second P-type tub is formed between the second N-type tub and the third N-type tub. | 2014-07-17 |
20140197516 | INTEGRATION OF 3D STACKED IC DEVICE WITH PERIPHERAL CIRCUITS - An integrated circuit device includes a substrate including a first region and a second region. A pit is formed in the first region. A stack of active layers alternating with insulating layers is deposited in the pit. The stack includes a particular insulating layer. The particular insulating layer has a first thickness, where a sum of the first thickness, thickness of active layers, and thicknesses of other insulating layers is essentially equal to a depth of the pit. The first thickness is different than the thicknesses of the other insulating layers by an amount within a range of process variations for the depth of the pit, for the thicknesses of the active layers, and for the thicknesses of other insulating layers. The device includes a planarized surface over the first and second regions, where an uppermost one of the active layers has a top surface below the planarized surface. | 2014-07-17 |
20140197517 | TRIMMING CIRCUIT FOR AN INTEGRATED CIRCUIT AND RELATED INTEGRATED DEVICE - A trimming circuit is configured to carry out a trimming operation on a device portion of an integrated circuit device. The trimming circuit includes: shunt fuses wherein each shunt fuse is coupled in parallel to a trimming resistance, further resistances wherein each further resistance is coupled in parallel to a respective shunt fuse. The circuit is configured to allow the flow of the trimming current when the respective shunt fuse is burnt during the trimming operation. | 2014-07-17 |
20140197518 | STACKED STRUCTURE SEMICONDUCTOR DEVICE - A semiconductor device includes a capacitor formed in a semiconductor substrate of a first conductivity type. The capacitor includes: a heavily-doped layer of a second conductivity type placed over the substrate, a first insulating layer placed over the heavily-doped layer of the second conductivity type, and a first metal layer placed over the first insulating layer. The semiconductor device further includes comprises a second insulating layer deposited over the capacitor and at least one resistor formed over the second insulating layer. The resistor includes a layer of a resistive material region arranged between two regions of a second metal layer. | 2014-07-17 |
20140197519 | MIM CAPACITOR AND MIM CAPACITOR FABRICATION FOR SEMICONDUCTOR DEVICES - In a particular embodiment, a method of forming a metal-insulator-metal (MIM) capacitor includes removing, using a lithographic mask, a first portion of an optical planarization layer to expose a region in which the MIM capacitor is to be formed. A second portion of an insulating layer is formed on a first conductive layer that is formed on a plurality of trench surfaces within the region. The method further includes removing at least a third portion of the insulating layer according to a lift-off technique. | 2014-07-17 |
20140197520 | RESISTOR AND RESISTOR FABRICATION FOR SEMICONDUCTOR DEVICES - In a particular embodiment, a method includes removing a first portion of an optical planarization layer using a lithographic mask to expose a region of the optical planarization layer. A resistive layer is formed at least partially within the region. The method further includes removing at least a second portion of the optical planarization layer and at least a third portion of the resistive layer to form a resistor. | 2014-07-17 |
20140197521 | SEMICONDUCTOR DEVICE HAVING TWO-WAY CONDUCTION CHARACTERISTICS, AND ELECTROSTATIC DISCHARGE PROTECTION CIRCUIT INCORPORATING THE SAME - A semiconductor device includes an n-type first doped region for receiving an external voltage, an n-type second doped region and a p-type third doped regions all formed in a p-type substrate, and is configured to have a first threshold voltage for forward conduction between the first and second doped regions, and a second threshold voltage for forward conduction between the first and third doped regions. A current is drained by flowing through the first doped region, the substrate and the second doped region if the external voltage is greater than the first threshold voltage or by flowing through the third doped region, the substrate and the first doped region if the external voltage is less than the second threshold voltage. | 2014-07-17 |
20140197522 | HYBRID CONDUCTOR THROUGH-SILICON-VIA FOR POWER DISTRIBUTION AND SIGNAL TRANSMISSION - A method of providing signal, power and ground through a through-silicon-via (TSV), and an integrated circuit chip having a TSV that simultaneously provides signal, power and ground. In one embodiment, the method comprises forming a TSV through a semiconductor substrate, including forming a via in the substrate; and forming a multitude of conductive bars in the via. The multitude of conductive bars include at least one signal bar, at least one power bar, and at least one ground bar. The method further comprises connecting the at least one power bar to a power voltage source to apply power through the TSV; connecting the at least one ground bar to a ground voltage; and connecting the at least one signal bar to a source of an electronic signal to conduct the signal through the TSV and to form a hybrid power-ground-signal TSV in the substrate. | 2014-07-17 |
20140197523 | CHIP ARRANGEMENT AND A METHOD FOR FORMING A CHIP ARRANGEMENT - A chip arrangement is provided, the chip arrangement, including: a carrier; at least one chip including at least one contact pad disposed over the carrier; an encapsulation material at least partially surrounding the at least one chip and the carrier; and at least one low temperature co-fired ceramic sheet disposed over a side of the carrier. | 2014-07-17 |
20140197524 | DIE PACKAGE STRUCTURE - A die packaged structure includes a pad on the central region of the die. A packaged substrate with an opening disposed in the central region, and a connecting terminal is passed through the packaged substrate and disposed around the opening. An external connecting terminal is disposed on the four sides of the packaged substrate. A first metal wire is electrically connected the connecting terminal with the external connecting terminal, and the back of the packaged substrate is fixed on the die, such that the pad is exposed on the opening. A second metal wire is electrically connected the pad with the connecting terminal. A packaged body is encapsulated the packaged substrate, the die and the second metal wire, and the external connecting terminal is exposed. A conductive component is electrically connected with the external connecting terminal and is arranged on the four sides of the die packaged structure. | 2014-07-17 |
20140197525 | POWER MODULE - A power module configured to arrange a first electrode on a surface of which a first switching device is bonded, a second electrode on a surface of which a second switching device is bonded, and a third electrode by stacking the first electrode, the first switching device, the second electrode, the second switching device, and the third electrode in this order from the bottom in a stacking direction, characterized by first through third electrode pieces each connected to the first through third electrodes, first and second signal lines each connected to the first and second switching devices, wherein the first through third electrode pieces and the first and second signal lines are provided extending outward in the same plane as the second electrode. | 2014-07-17 |
20140197526 | SEMICONDUCTOR DEVICE ASSEMBLY WITH THROUGH-PACKAGE INTERCONNECT AND ASSOCIATED SYSTEMS, DEVICES, AND METHODS - Methods for making semiconductor devices are disclosed herein. A method configured in accordance with a particular embodiment includes forming a spacer material on an encapsulant such that the encapsulant separates the spacer material from an active surface of a semiconductor device and at least one interconnect projecting away from the active surface. The method further includes molding the encapsulant such that at least a portion of the interconnect extends through the encapsulant and into the spacer material. The interconnect can include a contact surface that is substantially co-planar with the active surface of the semiconductor device for providing an electrical connection with the semiconductor device. | 2014-07-17 |
20140197527 | CHIP ARRANGEMENT AND A METHOD FOR MANUFACTURING A CHIP ARRANGEMENT - A chip arrangement is provided, the chip arrangement, including a carrier; a first chip electrically connected to the carrier; a ceramic layer disposed over the carrier; and a second chip disposed over the ceramic layer; wherein the ceramic layer has a porosity in the range from about 3% to about 70%. | 2014-07-17 |
20140197528 | OPTICAL SEMICONDUCTOR APPARATUS - An optical semiconductor apparatus includes a lid body bonded to an upper surface of a frame body, the lid body having an opening at a position vertically overlapping with an optical semiconductor device. The lid body has a first portion which is positioned to surround the opening and has an upper surface to which a light-transmissive member is bonded, a second portion which is positioned to surround the first portion, and a third portion which is positioned to surround the second portion and has a lower surface to which the frame body is bonded. The upper surface of the first portion is positioned lower than an upper surface of the third portion. The second portion has a thin-walled portion positioned to surround the first portion, the thin-walled portion having a thickness thinner than that of the first portion as well as thinner than that of the third portion. | 2014-07-17 |
20140197529 | METHODS OF FABRICATING PACKAGE STACK STRUCTURE AND METHOD OF MOUNTING PACKAGE STACK STRUCTURE ON SYSTEM BOARD - A package stack structure includes a lower semiconductor chip on a lower package substrate having a plurality of lower via plug lands, a lower package having a lower molding compound surrounding a portion of a top surface of the lower package substrate and side surfaces of the lower semiconductor chip, an upper semiconductor chip on an upper package substrate having a plurality of upper via plug lands, an upper package having an upper molding compound covering the upper semiconductor chip, via plugs vertically penetrating the lower molding compound, the via plugs connecting the lower and upper via plug lands, respectively, and a fastening element and an air space between a top surface of the lower molding compound and a bottom surface of the upper package substrate. | 2014-07-17 |
20140197530 | SEMICONDUCTOR DEVICE WITH CHIP HAVING LOW-K-LAYERS - A semiconductor device is described having at least one semiconductor chip, the chip having an active area on a top side thereof, the active area formed at least in part of low-k material, said low-k material defining a low-k subarea of said active area; an embedding material, in which said at least one semiconductor chip is embedded, at least part of the embedding material forming a coplanar area with said active area; at least one contact area within the low-k subarea; a redistribution layer on the coplanar area, the redistribution layer connected to said contact areas; at least one first-level interconnect, located outside said low-k subarea, the first-level interconnect electrically connected to at least one of said contact areas via the redistribution layer. | 2014-07-17 |
20140197531 | COMPACT DEVICE PACKAGE - Various embodiments related to a compact device package are disclosed herein. In some arrangements, a flexible substrate can be coupled to a carrier having walls angled relative to one another. The substrate can be shaped to include two bends. First and second integrated device dies can be mounted on opposite sides of the substrate between the two bends in various arrangements. | 2014-07-17 |
20140197532 | Semiconductor Module and Method for Manufacturing Semiconductor Module - A semiconductor module includes a case including a receiving space that is formed by a frame portion and a pair of wall portions disposed to face each other with the frame portion therebetween. The wall portion includes a heat-dissipation portions and a support wall that supports the heat-dissipation portions at the frame portion, and the wall portion includes a heat-dissipation portion and a support wall that supports the heat-dissipation portion at the frame portion. The heat-dissipation portions provided at the wall portion are separately provided by being disposed to face a plurality of semiconductor device blocks respectively. A plurality of separate heat-dissipation portions is surrounded by the support wall, the support wall is deformed to recessed from the frame portion through the separate heat-dissipation portions inside the case such that a plurality of insulating sheets is closely joined to a plurality of lead frames and the plurality of heat-dissipation portions. | 2014-07-17 |
20140197533 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device is provided, the method including: mounting a first element on a wiring substrate, placing a first heat sink on the first element with a metal material interposed between the first heat sink and the first element, attaching the first heat sink to the first element via the metal material by heating and melting the metal material, and mounting a second element on the wiring substrate after the steps of attaching the first heat sink to the first element. | 2014-07-17 |
20140197534 | SUBSTRATE WITH BOND FINGERS - A flip chip mounting board includes a substrate having a top surface and a plurality of generally parallel, longitudinally extending, laterally spaced apart bond fingers are formed on the top surface. Each of the plurality of bond fingers has a first longitudinal end portion and a second longitudinal end portion. A first strip of laterally extending solder resist material overlies the first longitudinal end portions of the bond fingers. The first strip has an edge wall with a plurality of longitudinally projecting tooth portions separated by gaps with a longitudinally extending tooth portion being aligned with every other one of the bond fingers. Adjacent bond fingers have first end portions covered by different longitudinal lengths of solder resist material. | 2014-07-17 |
20140197535 | WAFER-LEVEL PACKAGING MECHANISMS - A semiconductor package includes a first semiconductor die surrounded by a molding compound. The semiconductor package further includes a first conductive pad on the first semiconductor die, wherein the first conductive pad is at a top metal level of the first semiconductor die. The semiconductor package further includes redistribution lines (RDLs) formed over the first conductive pad, wherein at least one RDL of the RDLs extends beyond the boundaries of the semiconductor die, and a portion of the at least one RDL contacts the first conductive pad, wherein a surface of the first conductive pad contacting the portion of the at least one RDL is at a different level than a surface of the molding compound under the at least one RDL extended beyond the boundaries of the first semiconductor die. | 2014-07-17 |
20140197536 | PACKAGE STRUCTURE AND METHOD FOR MANUFACTURING THEREOF - The invention provides an electronic device package and method for manufacturing thereof. The electronic device package includes a substrate, an electronic chip, a bonding pad, a first passivation layer, a conductive layer, a second passivation layer, and a solder ball. The conductive layer has a first side end and a second side end, and the solder ball is positioned on the first side end of the conductive layer. The second passivation layer contacts with both the upper surface and the sidewall of the second side end of the conductive layer, and the first passivation layer contacts with the lower surface of the second side end of the conductive layer, so as to completely encapsulate the second end of the conductive layer. The electronic device package accordingly prevents the moisture penetration and to enhance the reliability of the electronic device. | 2014-07-17 |
20140197537 | Void-Free Metallic Filled High Aspect Ratio Openings - One embodiment is a device which includes at least one filled via or trench wherein the at least one filled via or trench includes void-free filled metal or alloy, and the filled via or trench has an aspect ratio in a range from 9:1 to about 28:1. | 2014-07-17 |
20140197538 | COPPER ETCHING INTEGRATION SCHEME - The present disclosure is directed to an interconnect structure. The metal interconnect structure has a metal body disposed over a semiconductor substrate and a projection extending from the metal body. A barrier layer continuously extends over the projection from a first sidewall of metal body to an opposing second sidewall of the metal body. A layer of dielectric material is disposed over the semiconductor substrate at a position abutting the metal body and the projection. | 2014-07-17 |
20140197539 | Bonded System with Coated Copper Conductor - A semiconductor component includes a semiconductor die and a copper-containing electrical conductor. The semiconductor die has a semiconductor device region, an aluminum-containing metal layer on the semiconductor device region, and at least one additional metal layer on the aluminum-containing metal layer which is harder than the aluminum-containing metal layer. The copper-containing electrical conductor is bonded to the at least one additional metal layer of the semiconductor die via an electrically conductive coating of the copper-containing electrical conductor which is softer than the copper of the copper-containing electrical conductor. | 2014-07-17 |
20140197540 | Extended Redistribution Layers Bumped Wafer - A semiconductor device is manufactured by, first, providing a wafer, designated with a saw street guide, and having a bond pad formed on an active surface of the wafer. The wafer is taped with a dicing tape. The wafer is singulated along the saw street guide into a plurality of dies having a plurality of gaps between each of the plurality of dies. The dicing tape is stretched to expand the plurality of gaps to a predetermined distance. An organic material is deposited into each of the plurality of gaps. A top surface of the organic material is substantially coplanar with a top surface of a first die of the plurality of dies. A redistribution layer is patterned over a portion of the organic material. An under bump metallization (UBM) is deposited over the organic material in electrical communication, through the redistribution layer, with the bond pad. | 2014-07-17 |
20140197541 | MICROELECTRONIC ASSEMBLY HAVING A HEAT SPREADER FOR A PLURALITY OF DIE - A microelectronic assembly ( | 2014-07-17 |
20140197542 | SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING SEMICONDUCTOR DEVICES - Semiconductor devices are provided. A semiconductor device may include a substrate and a plurality of lines on the substrate. The semiconductor device may include a dielectric layer on the substrate and adjacent the plurality of lines. The semiconductor device may include a connection element in the dielectric layer. In some embodiments, the semiconductor device may include a plurality of contacts on the connection element, and a conductive interconnection on one of the plurality of contacts that are on the connection element and on a contact that is spaced apart from the connection element. | 2014-07-17 |
20140197543 | Enforcement of Semiconductor Structure Regularity for Localized Transistors and Interconnect - A global placement grating (GPG) is defined for a chip level to include a set of parallel and evenly spaced virtual lines. At least one virtual line of the GPG is positioned to intersect each contact that interfaces with the chip level. A number of subgratings are defined. Each subgrating is a set of equally spaced virtual lines of the GPG that supports a common layout shape run length thereon. The layout for the chip level is partitioned into subgrating regions. Each subgrating region has any one of the defined subgratings allocated thereto. Layout shapes placed within a given subgrating region in the chip level are placed in accordance with the subgrating allocated to the given subgrating region. Non-standard layout shape spacings at subgrating region boundaries can be mitigated by layout shape stretching, layout shape insertion, and/or subresolution shape insertion, or can be allowed to exist in the final layout. | 2014-07-17 |
20140197544 | SEMICONDUCTOR DEVICE COMPRISING METALLIZATION LAYERS OF REDUCED INTERLAYER CAPACITANCE BY REDUCING THE AMOUNT OF ETCH STOP MATERIALS - Upon forming a complex metallization system, the parasitic capacitance between metal lines of adjacent metallization layers may be reduced by providing a patterned etch stop material. In this manner, the patterning process for forming the via openings may be controlled in a highly reliable manner, while, on the other hand, the resulting overall dielectric constant of the metallization system may be reduced, thereby also significantly reducing the parasitic capacitance between stacked metal lines. | 2014-07-17 |
20140197545 | NON-CYLINDRICAL CONDUCTING SHAPES IN MULTILAYER LAMINATED SUBSTRATE CORES - Non-cylindrical conducting shapes are described in the context of multilayer laminated substrate cores. In one example a package substrate core includes a plurality of dielectric layers pressed together to form a multilayer core, a conductive bottom pattern on a bottom surface of the multilayer core, and a conductive top pattern on a top surface of the multilayer core. At least one elongated via extends through each layer of the multilayer core, each elongated via containing a conductor and each connected to a conductor of a via in an adjacent layer to electrically connect the top pattern and the bottom pattern through the conductors of the elongated vias. | 2014-07-17 |
20140197546 | PAD STRUCTURES AND WIRING STRUCTURES IN A VERTICAL TYPE SEMICONDUCTOR DEVICE - Step shape pad structure and wiring structure in vertical type semiconductor device are include a first conductive line having a first line shape and including first pad regions at an upper surface of an edge portion, and a second conductive line having s second line shape and being spaced apart from the first conductive line and provided on the first conductive line. An end portion of the first conductive line is extended to a first position. Second pad regions are included on an upper surface of an edge portion of the second conductive line. An end portion of the second conductive line is extended to the first position. The second conductive line includes a dent portion at a facing portion to the first pad regions in a vertical direction to expose the first pad regions. The pad structure may be used in a vertical type nonvolatile memory device. | 2014-07-17 |
20140197547 | PACKAGE ON PACKAGE STRUCTURES AND METHODS FOR FORMING THE SAME - A method of forming a semiconductor device package includes removing a portion of a first connector and a molding compound surrounding the first connector to form an opening, wherein the first connector is part of a first package, and removing the portion of the first connector comprises forming a surface on the first connector which is at an angle with respect to a top surface of the molding compound. The method further includes placing a second connector in the opening, wherein the second connector is part of a second package having a semiconductor die. The method further includes bonding the second connector to a remaining portion of the first connector. | 2014-07-17 |
20140197548 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH MOLDED GRID-ARRAY MECHANISM AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a lead-frame having a metal connector mounted thereon and having a peripheral mounting region; forming an insulation cover on the lead-frame and on the metal connector; connecting an integrated circuit die over the insulation cover; forming a top encapsulation on the integrated circuit die with the peripheral mounting region exposed from the top encapsulation; forming a routing layer, having a conductive land, from the lead-frame; and forming a bottom encapsulation partially encapsulating the routing layer and the insulation cover. | 2014-07-17 |
20140197549 | SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME - A semiconductor package includes a package substrate, a semiconductor chip, a die attach film, a molding member, and a dummy finger. A bond finger is arranged on an upper surface of the package substrate. The semiconductor chip is arranged on the upper surface of the package substrate, and electrically connected to the bond finger. The die attach film is interposed between the semiconductor chip and the package substrate such that the semiconductor chip is attached to the package substrate. The molding member is formed on the upper surface of the package substrate to cover the semiconductor chip. The dummy finger is formed between the upper surface of the package substrate and the molding member. Moisture in the void formed in the die attach film may be released through the discharge passageway. Thus, the package substrate is prevented from being swollen during a subsequent thermal process such as a reflow process. | 2014-07-17 |
20140197550 | SEMICONDUCTOR DEVICE - A semiconductor device includes a substrate having a first surface, a height adjuster mounted on the first surface of the substrate via a first adhesive layer, a semiconductor chip mounted on the height adjuster via a second adhesive layer, an electronic component mounted on the first surface of the substrate via a third adhesive layer, a bonding wire, and a sealing member. The length of the electronic component in a first direction corresponding to the thickness direction of the substrate is larger than the length of the semiconductor chip in the first direction, and the sum of the lengths of the height adjuster, the second adhesive layer, and the semiconductor chip in the first direction is larger than the length of the electronic component in the first direction. | 2014-07-17 |
20140197551 | Method for Fabricating a Semiconductor Chip Panel - The method comprises providing a carrier, providing a plurality of semiconductor chips, the semiconductor chips each comprising a first main face and a second main face opposite to the first main face and side faces connecting the first and second main faces, placing the semiconductor chips on the carrier with the second main faces facing the carrier, and applying an encapsulation material to the side faces of the semiconductor chips. | 2014-07-17 |
20140197552 | CHIP ARRANGEMENT, A METHOD FOR MANUFACTURING A CHIP ARRANGEMENT, INTEGRATED CIRCUITS AND A METHOD FOR MANUFACTURING AN INTEGRATED CIRCUIT - A chip arrangement is provided, the chip arrangement, including a carrier; at least one chip electrically connected to a carrier top side; an encapsulation material at least partially surrounding the at least one chip and the carrier top side, wherein the encapsulation material is formed on one or more lateral sides of the carrier; and a ceramic material disposed on a carrier bottom side, and on at least one side of the encapsulation material. | 2014-07-17 |
20140197553 | METHOD FOR MANUFACTURING A SUBSTRATE FOR A DISPLAY DEVICE - A method for manufacturing a substrate for a display device comprises forming a first pattern within an active region of the substrate and at the same time forming a first overlay pattern at corner regions of the active region; and forming a second pattern within the active region of the substrate and at the same time forming a second overlay pattern at corner regions of the active region, wherein the first overlay pattern includes gradations arranged in a predetermined direction, and the second overlay pattern includes gradations arranged in the predetermined direction to face the gradations of the first overlay pattern. | 2014-07-17 |
20140197554 | DEVICE FOR FOAMING MILK, BEVERAGE MAKER COMPRISING SAID DEVICE, AND METHOD FOR FOAMING MILK - The present invention relates to a device for frothing up a liquid, in particular cold and/or unheated milk, having a liquid supply line for supplying the liquid, an air supply line which opens into the liquid supply line for supplying air into the liquid, a discharge line which is configured downstream of the opening of the air supply line into the liquid supply line for discharging the mixture of liquid and air, a first conveying unit, in particular a pump, which is provided for conveying the liquid through the liquid supply line and/or the mixture through the discharge line and a mixing unit which is provided downstream of the opening in the discharge line, the mixing unit including at least one narrow place or being configured as narrow place of the discharge line. | 2014-07-17 |
20140197555 | METHOD AND APPARATUS FOR TREATMENT AND PURIFICATION OF LIQUID THROUGH AERATION - An aeration system for the treatment and purification of liquid is presented. The aeration system includes a decompression chamber extending a length between an inlet end and an outlet end and a motor connected to the decompression chamber. The system includes drive shaft connected to the motor and extending into a hollow interior of the decompression chamber wherein airflow into the hollow interior is restricted through at least one inlet port. An orifice plate is connected to the drive shaft, wherein the orifice plate includes a plurality of apertures. A rotor disk is connected to the drive shaft, wherein the rotor disk includes a plurality of deflecting blades. When the outlet end of the system is positioned in liquid and the driveshaft and rotor disk are rotated micro bubbles are formed in the liquid thereby treating and purifying the liquid. | 2014-07-17 |
20140197556 | SYSTEM AND METHOD FOR LIQUID DISTRIBUTION - A liquid flow distributor for positioning above one or more packing sections in a packed exchange tower includes a plurality of troughs. At least one trough in the plurality of troughs has along a side thereto a deflecting member The deflecting member is angulated to generally follow a shape of the at least one trough. A diffuser side of the deflecting member is positioned to deposit the liquid into a discharge region. A plurality of break bars are disposed on the diffuser side of the deflecting member. A deflector side of the deflecting member is positioned for deflecting ascending vapor away from the discharge region. | 2014-07-17 |
20140197557 | METHOD FOR PREPARING A POROUS NUCLEAR FUEL - A method for producing a porous fuel including uranium, optionally plutonium, and optionally at least one minor actinide, the method including: a) compacting a mixture including a first type of agglomerate including uranium oxide in a form of uranium dioxide UO | 2014-07-17 |
20140197558 | Method of Ring-Shaped Structure Placement in an Eye-Mountable Device - Example eye-mountable devices and methods for fabricating eye-mountable devices are described. A method may include applying a first amount of polymerizable material to a ring-shaped structure, where the ring-shaped structure comprises at least one sensor configured to detect an analyte. The method also may include positioning the ring-shaped structure with the first amount of polymerizable material applied thereto in a mold, where the mold is configured to form an eye-mountable device. Further, the method may include applying pressure on the ring-shaped structure in the mold while curing the first amount of polymerizable material. Still further, the method may include adding a second amount of polymerizable material to the mold with the ring-shaped structure therein, and curing the second amount of polymerizable material to form an over-molded polymer layer such that the ring-shaped structure is at least partially enclosed in the eye-mountable device. | 2014-07-17 |
20140197559 | MOLD, MOLD MANUFACTURING METHOD AND METHOD FOR MANUFACTURING ANTI-REFLECTION FILM USING THE MOLD - A mold of at least one embodiment of the present invention includes: a base; a conductive layer provided on the base; and an anodized film provided on the conductive layer, the anodized film having an inverted motheye structure in its surface, the inverted motheye structure having a plurality of recessed portions whose two-dimensional size viewed in a direction normal to the surface is not less than 10 nm and less than 500 nm, wherein the base, the conductive layer, and the anodized film are capable of transmitting ultraviolet light. | 2014-07-17 |
20140197560 | PRODUCTION OF CARBON-FIBER REINFORCED COKE - A method produces carbon fiber-reinforced coke. Carbon fiber-reinforced plastic (CFRP) materials derived from components and semi-finished products are continuously fed through a top side of the drum of a delayed coker as a partial flow or as a main flow, and the CFRP materials sink through the gas phase into the still liquid phase. The carbon fibers are released through carbonization of the resin matrix and incorporated therein during the coking process. The decomposition products of the resin matrix are supplied to a material recovery process. | 2014-07-17 |
20140197561 | DETECTION OF CHANGE IN ORIENTATION OF CENTRAL AXIS OF PLATEN ASSEMBLY - A molding system ( | 2014-07-17 |
20140197562 | COMPOSITE MATERIAL FOR MAKING ARTICLES OUT OF POLYURETHANE DOPED WITH POLYMERIC GEL AND THE PROCEDURE FOR MAKING IT - A standard polyurethane doped with a polymeric gel uniformly diffused in the body, where the polyurethane acquires the properties of the gel without any change to its structure in a durable stable manner. | 2014-07-17 |
20140197563 | CARBON DIOXIDE SEQUESTRATION IN CONCRETE ARTICLES - Concrete articles, including blocks, substantially planar products (such as pavers) and hollow products (such as hollow pipes), are formed in a mold while carbon dioxide is injected into the concrete in the mold, through perforations. | 2014-07-17 |
20140197564 | METHOD FOR PRODUCING FINE PARTICLES - Provided is a method for producing fine particles in which fine particles having a uniform particle size distribution can be simply obtained with a low environmental load. The present invention relates to a method for producing fine particles including the step of preparing minute pieces by cutting a resin film at equal intervals into a width of 0.05 to 500 μm. | 2014-07-17 |
20140197565 | CIRCUMFERENTIAL WALKER - An orthopedic device in the form of a circumferential walker includes a first member (posterior shell) and a second member (dorsal shell) corresponding to the first member. An outsole or plantar shell portion is attached to, or formed on or with the posterior shell. A hinge mechanism is provided between the posterior and dorsal shells to allow the dorsal shell to be swung away from the posterior shell in order to accommodate an anatomical limb therein. Inflatable bladders having perspiration wicking channels and/or openings are provided within a liner for insertion between the posterior and dorsal shells. Quick-connecting buckle and retaining assemblies can be provided to allow a user to quickly don and doff the orthopedic device. | 2014-07-17 |
20140197566 | TWIN SCREW EXTRUDER - An extruder is disclosed, and more particularly, a twin screw extruder for mixing, compounding, kneading and/or extruding of materials. The twin screw extruder includes a barrel assembly having a housing. The twin screw extruder further includes a first screw provided within the housing and comprising threads. The twin screw extruder further includes a second screw provided within the housing and comprising a threaded portion and a shaft portion devoid of threads. A drive system which drives the first screw and the second screw. | 2014-07-17 |
20140197567 | COMPACTING AND INJECTION MOLD FOR A FIBER PREFORM FOR FABRICATING A TURBINE ENGINE GUIDE VANE MADE OF COMPOSITE MATERIAL - A compacting and injection mold for a fiber preform is for use in fabricating a turbine engine guide vane out of composite material. The mold includes a shell forming a trough that is to receive the fiber preform and that is closed in leaktight manner by bottom and top covers, compacting blocks arranged inside the trough each having a surface pressing normally against a surface of the fiber preform that is to be compacted, and closure blocks arranged inside the trough. Each closure block has a surface pressing normally against a surface of a compacting block and does not have a surface in contact with the fiber preform. | 2014-07-17 |
20140197568 | MINERAL COMPOSITE PANEL AND ITS PRODUCTION PROCESS - The embodiments herein provide a prefabricated mineral composite panel and a method for producing the same for constructing the internal walls, the lateral walls and the corner walls in a building. The method comprising the steps of: preparing and assembling a cast, fixing a mesh in the cast, pouring a prefabricated mineral composite into the cast, smoothening and flattening a top surface of the cast, disassembling the cast to withdraw a semi-dried prefabricated mineral composite panel, placing the semi-dried prefabricated mineral composite panel in a drying room for drying the prefabricated mineral composite, removing the dried prefabricated mineral composite panel from the drying room and packaging the prefabricated mineral composite panel. | 2014-07-17 |
20140197569 | METHOD OF FABRICATING A HOLE IN A COMPOSITE PANEL - A method of forming a hole in a composite panel includes positioning a first fiber sheet on a layup table, where the layup table has a forming tool extending outward from a portion of the table, and the fiber sheet includes a plurality of fibers oriented along a first common direction. The method further includes extending the forming tool through the first fiber sheet such that a subset of the plurality of fibers are displaced about the forming tool: applying a resin to the sheet of fibers; pre-curing the resin to form a pre-preg part defining a hole about the forming tool; and removing the pre-preg part from the layup table. | 2014-07-17 |
20140197570 | INJECTION MOLDING METHOD AND INJECTION MOLDING MACHINE - After a first die and a second die are opened, a base film of a film is separated from the first die so as to tilt the surface of the film with respect to a parting face of the first die. | 2014-07-17 |
20140197571 | PREVENTION OF FRETTING CREVICE CORROSION OF MODULAR TAPER INTERFACES IN ORTHOPEDIC IMPLANTS - A thin high strength polymer based self-reinforced composite (SRC) made from a biocompatible and commonly used orthopedic implant material is interposed between the hard connections of the modular taper interface of an orthopedic implant. A thick film of this ultra high strength SRC with the fibers oriented to maximally resist the fretting motion and wear, can be interposed between the modular components to result in a relatively soft, non-conducting interposed layer that will prevent contact between hard interfaces and reduce or eliminate the oxide film abrasion associated with this mechanism. Alternatively, the SRC may be formed using surface control methods resist fretting, such as by using sticky-compliant surfaces and channels for fluid, among others. | 2014-07-17 |
20140197572 | METHOD FOR PRODUCING A TUBULAR HOLLOW BODY, AND TUBULAR HOLLOW BODY - The invention relates to a method for producing a tubular hollow body ( | 2014-07-17 |
20140197573 | CONCRETE FORMING SYSTEMS AND METHODS - Systems and methods for constructing concrete foundations are provided which allow for rapid and high-precision placement and alignment of anchor bolts across large distances. A frame system is constructed outside of an excavation and then suspended, using supports, over an excavation. The frame system can include a frame having one or more templates for anchor bolts, a form suspended from the frame, and a mat and cage assembly tied to the frame. The frame system can be aligned in proper position and the anchor bolts placed in the frame system before the concrete is placed. In this way, the anchor bolts can be cast in place as the footing is placed. | 2014-07-17 |
20140197574 | APPARATUS AND METHOD USABLE WITH AN INJECTION MOLDER FOR PRODUCING ARTICLES - An apparatus usable with an injection molder for producing articles includes a first mold support including a first mold, and a second mold support including a second mold and a first die. The first mold support is movable relative to the second mold support between a first position and a second position. In the first position, the first mold and the second mold being brought together to form an injection molded article include a body having at least one protrusion extending outwardly from the body and facing the second mold. In the second position, the first mold and the first die being brought together to subsequently form the article, the first die selectively subsequently forming an altered cross sectional region in at least a portion of the protrusion, forming an undercut in the altered cross sectional region or between the altered cross sectional region of the subsequently formed protrusion and the body. | 2014-07-17 |
20140197575 | DEVICE FOR INJECTING A FILLING MATERIAL IN THE FLUID PHASE INTO A CANAL SPACE - A method is for fabricating a device for injecting a filler material in the fluid phase into a root canal space, the device including an adapter nozzle, an auto-mixer connected to the adapter nozzle, an intra-oral injection nozzle positioned at the upper end of the auto-mixer. The method includes using a shape memory material to make the injection nozzle so as to be bendable according to a desired orientation. The method also includes arranging on the exterior surface of the injection nozzle, circular ribs defining a groove, and moulding the upper end of the auto-mixer in this groove so that the injection nozzle is lodged in position in the upper end while retaining a degree of freedom in rotation around its axis of symmetry, or one or multiple circular ribs parallel to each other. | 2014-07-17 |
20140197576 | DEVICE AND METHOD FOR THE PRODUCTION OF A THREE-DIMENSIONAL OBJECT - The device and the method serve for the production of a three-dimensional object from a solidifiable by a sequential discharge of drops onto an object carrier for the object to be produced, the device including discharge unit with an outlet orifice discharges drops along an axis (s) in a direction to the object carrier, and control means configured to control the motion of the object carrier and the object on the one hand and the outlet orifice on the other hand relative to each other in space, where due to the fact that means are provided for a mutual alignment of the object carrier or the object on the one hand and the outlet orifice on the other hand and that can be controlled by control means, with the axis (s) in a mutually aligned state intersecting a surface of the object carrier or the already produced object, such that a method and a device are provided for the production of a three-dimensional object with geometric overhangs and/or undercuts using solidifiable materials. | 2014-07-17 |
20140197577 | DURABLE EARTHENWARE ENGRAVING PROCESS - A method of forming a detailed image on a surface of an earthenware item is disclosed. The method comprises: (a) processing a digital image to produce an output image; (b) etching a burnable material to create peaks, valleys and indents corresponding to the output image to form a mold; (c) casting a flexible template against the mold to obtain a mirror image of the output image in the flexible template; (d) casting a surface of the earthenware in an unsintered state against the flexible template to record the output image by peaks and valleys in the surface of the earthenware item; (e) bisque firing the earthenware item in the unsintered state to render the output image permanent; and (f) applying stain to the surface of the bisque fired earthenware item and removing excess stain from of the surface of the earthenware item. | 2014-07-17 |
20140197578 | ELECTROPHOTOGRAPHIC ENDLESS BELT, METHOD FOR PRODUCING THE SAME, AND ELECTROPHOTOGRAPHIC APPARATUS - A high-quality electrophotographic endless belt and a method capable of efficiently producing the belt are provided. A method for producing an electrophotographic endless belt comprising a base layer including a thermoplastic resin composition and an inner-surface layer, which includes: (1) forming an energy curable film having a glass transition temperature on an inner surface of a test tube-shaped preform including a thermoplastic resin and then subjecting the preform to blow molding to obtain a blow-molded bottle; (2) irradiating the blow-molded bottle with energy rays to cure the film to form an inner-surface layer; and (3) cutting out an endless belt from the blow-molded bottle having the inner-surface layer obtained in (2). | 2014-07-17 |
20140197579 | POLYMER ADDITIVE LAYER MANUFACTURING - An additive layer manufacturing method for producing a shaped article, comprising providing a powdered thermoplastic polymer material ( | 2014-07-17 |
20140197580 | METHOD FOR PRODUCING A BIO-PET POLYMER - The invention relates to a method for producing a bio-PET polymer comprising the following steps: Step A) providing at least one diacid compound, comprising a terephtalate compound; Step B) providing at least one diol compound, comprising monoethylene glycol; wherein—at least one of the terephtalate compound and/or the monoethylene glycol is obtained from at least one bio-based material, and—at least one of the diacid compound and/or the diol compound further comprises at least one crystallization retarding compound; and Step C) copolymerizing a mixture of the diacid compound and the diol compound to obtain a bio-PET polymer comprising diacid units and diol units, comprising up to 7.5 mol % of unit(s) corresponding to the at least one crystallization retarding compound, based on the total number of moles of diacid units contained in the bio-PET. The invention also relates to a method for producing a bio-PET packaging element, comprising the following steps:—performing the method described above; and—Step D) converting the bio-PET into the bio-PET packaging element. | 2014-07-17 |
20140197581 | Apparatus for the heating of plastics material pre-forms with aeration screening capable of being dismantled - An apparatus ( | 2014-07-17 |
20140197582 | PRESSURE MAINTAINING DEVICE FOR CREATING COMPOSITE COMPONENTS BY INJECTING RESIN AND ASSOCIATED METHOD - A pressure maintaining device for a resin injecting system, including a first chamber that can be connected to a pressurizing device and is able to be connected to a vacuum generating device; a second chamber that can be connected to a resin injection network of the injection system by a resin injection pipe and a resin outlet pipe, the first chamber and the second chamber being arranged so that the one is unable to leak into the other; a flexible body able to transmit pressurizing of the first chamber to the second chamber so as to apply pressure to the injection network of the injection system; a perforated rigid plate able to limit the deformation of the flexible body when the vacuum is created in the first chamber. | 2014-07-17 |
20140197583 | CERAMIC COMPOSITION AND CERAMIC INJECTION-MOLDING PROCESS - A ceramic composition for an injection-molding process for producing a combustion chamber pressure sensor, in particular for producing an insulation punch of a combustion chamber pressure sensor, includes a ceramic component in a proportion of greater than or equal to 50% by weight and a glass component in a proportion of less than or equal to 50% by weight. The ceramic component includes aluminum oxide. The glass component includes silicon dioxide or a silicon dioxide precursor. The ceramic composition further includes an alkaline earth metal oxide or an alkaline earth metal oxide precursor. The ceramic composition allows production of an insulation punch having a particularly good insulation capability. A ceramic injection-molding process includes the ceramic composition. | 2014-07-17 |
20140197584 | TILTING CONVERTER - A tilting converter comprising a container ( | 2014-07-17 |
20140197585 | HYDRAULICALLY DAMPED DRIVE TRAIN MOUNTS - The invention relates to a hydraulically damped drive train mount ( | 2014-07-17 |
20140197586 | DAMPING DEVICE WITH ADJUSTABLE SPRING RATE - A spring and damping device for a wheel suspension in motor vehicles includes an upper region, a lower region, and a damping element arranged between the upper region and the lower region. The device further includes a coil spring element and a rubber spring element. The coil spring element and the rubber spring element are arranged one behind the other along a center axis of the damping element such that the coil spring element is positioned to exert a force on the rubber spring element. The device allows a spring rate to be adjusted based either on sensed conditions, or by driver input. The spring rate may be adjustable between discrete settings or continuously variable. | 2014-07-17 |
20140197587 | WORK HOLDER - A work holder which is adapted to hold a workpiece firmly in place for machining operations with respect to a machine tool. The workpiece is fashioned with a dovetail protuberance, which protuberance is designed to affix the workpiece to the work holder to the machining operations. Once the machining is completed, the dovetail protuberance may be removed in any convenient manner. Thus, the finished product may not then exhibit the former protuberance. | 2014-07-17 |
20140197588 | TOOL GUIDE SYSTEMS AND RELATED METHODS - Some embodiments include a system. The system includes a base member configured to be coupled a support structure, a multidirectional arm coupled to the base member, and a track coupled to the multidirectional arm. The track can be configured to receive a tool and can comprise a proximal end and a distal end opposite the proximal end. Other embodiments of related systems and methods are also disclosed. | 2014-07-17 |