29th week of 2013 patent applcation highlights part 25 |
Patent application number | Title | Published |
20130182423 | ADJUSTABLE PORTABLE LIGHT - A portable light includes: a cylindrical housing having a longitudinal axis and receiving a bezel and a lamp for projecting a light radially away from the longitudinal axis; and a cradle assembly including a clamp for receiving the cylindrical housing, wherein the clamp includes a plurality of features for engaging selected ones of corresponding features on the cylindrical housing to secure the cylindrical housing at a selected rotational position about its longitudinal axis with regard to the cradle assembly. | 2013-07-18 |
20130182424 | HANDHELD LIGHTING DEVICE - A handheld lighting device includes: a hand tool battery coupling unit, a cooling element, and an illuminating device which has an emission direction. The cooling element has at least one outer surface which is situated in the emission direction downstream from an outer surface of the illuminating device, which is transilluminated during operation. | 2013-07-18 |
20130182425 | LAMP AND LIGHTING APPARATUS - A lamp according to the present invention includes: a line portion which blocks a part of light proceeding from a light emitting unit in a direction perpendicular to a tube axis direction; and a raised portion which blocks the light proceeding from the light emitting unit in the direction perpendicular to the tube axis direction that is not blocked by the line portion. The raised portion has an end portion having a linear shape in the tube axis direction, the end portion being an end portion of a section of the raised portion that blocks light. | 2013-07-18 |
20130182426 | REPLACEABLE BRACKET LAMP TUBE AND LAMP HEAD COVER - A bracket lamp tube and a lamp head cover thereon are provided. The lamp head cover comprises a cover body ( | 2013-07-18 |
20130182427 | FLUORESCENT LAMP HOLDER ASSEMBLY - Fluorescent lamp holder assembly ( | 2013-07-18 |
20130182428 | Handrail with Orientable Illumination - A handrail assembly for lighting an adjacent area includes two stanchions for attachment to a surface, each stanchion including mounting structure; a bar for attachment to the stanchions, the bar having two ends and defining mounting structure at the ends; and a lighting element configured to be carried by the bar. The mounting structure of the stanchions and bars cooperate to provide two alternate mounting orientations of the bar within the stanchions. In a first of the orientations the lighting element is offset circumferentially in a first direction relative to a centerline of the stanchions lighting a first adjacent area on a first side of the stanchions. In a second of the orientations the lighting element is offset circumferentially in a second direction opposite the first direction relative to the centerline of the stanchions lighting a second adjacent area on a second side of the stanchions. | 2013-07-18 |
20130182429 | PROGRAMMABLE DE-FOGGER SYSTEM FOR A LIGHT PROJECTOR - A light projector for operation during a show that contains theatrical haze. The light projector may include a light source, a lens, a fan, and a housing having an inner chamber. The lens may have a first side and a second side. The first side of the lens may be contained within the inner chamber of the housing. The second side the lens may be outside of the inner chamber of the housing. The fan may be configured to be operated to generate air flow inside the inner chamber of the housing. A substantial portion of the air flow may be directed to impinge upon the first side of the lens to cause de-fogging of theatrical haze condensate on the first side of the lens. | 2013-07-18 |
20130182430 | Planar LED Lighting Apparatus - A planar LED lighting apparatus includes a housing and multiple LEDs. The housing includes a reflective body and a light output surface opposing the reflective body. The multiple LEDs are mounted on sidewalls of the housing, and light from the multiple LEDs is reflected by the reflective body to travel toward the light output surface. | 2013-07-18 |
20130182431 | Planar LED Lighting Apparatus - A planar LED lighting apparatus includes a housing and multiple LEDs. The housing includes a reflective face and a light output surface opposing the reflective face. The multiple LEDs are mounted on sidewalls of the housing, and the axial light of the multiple LEDs is incident on the reflective face. | 2013-07-18 |
20130182432 | ILLUMINATION DEVICE - An illumination device includes a main body unit, a light source module and a cover unit. The light source module is disposed in an upper space of the main body unit to be separated therefrom and includes a substrate and at least one light emitting device respectively disposed on both surfaces of the substrate. The cover unit is disposed on the main body unit to cover the light source module and allowing light emitted from the light source module to be emitted from a surface of the cover unit in a radial manner. | 2013-07-18 |
20130182433 | LIGHTING APPARATUS - A lighting apparatus includes a light source including a plurality of solid-state light-emitting elements, each of which emits light using a semiconductor; a shielding body that includes an opening that allows only a part of the light emitted from the light source to pass through; a lens that converts the light allowed to pass through the opening into spotlight; and a reflecting body that is provided between the lens and the shielding body and reflects the light that is traveling in a direction diverged from the lens, to reach the lens. | 2013-07-18 |
20130182434 | LIGHT EMITTING MODULE AND BACKLIGHT LIGHTING LAMP CHAIN COMPRISING THE SAME - A light emitting module may include: a PCB board; a light emitting assembly mounted on the PCB board; a lens and an encapsulating housing, the encapsulating housing encapsulating therein the PCB board, the light emitting assembly and part of the lens, and an exit surface of the lens being exposed out of the encapsulating housing, wherein the encapsulating housing is formed therein with a first concave region surrounding the exit surface and reducing light blocking, and at least a second concave region into the first concave region, wherein the second concave region is designed in such a way that water in the first concave region is drained via the second concave region. | 2013-07-18 |
20130182435 | LASER APPARATUS FOR GENERATING A LINE-SHAPED INTENSITY DISTRIBUTION IN A WORKING PLANE - An illumination apparatus produces a linear intensity distribution. The illumination apparatus contains laser light sources arranged in a number N of rows with in each case a number M of laser light sources which are arranged one next to the other, and emit laser light in a first propagation direction. A number of beam-deflection devices are arranged behind the laser light sources in the first propagation direction and deflect the laser light emitted by the laser light sources into a second propagation direction to a working plane. A beam-merging device is arranged behind the beam-deflection devices in the second propagation direction such that it merges the individual laser beam bundles of the laser light sources into the linear intensity distribution, with adjacent rows being arranged in a first direction perpendicular to first and second emission directions and also offset with respect to one another in the first propagation direction. | 2013-07-18 |
20130182436 | LAMP VENTILATION SYSTEM - A lighting module has a housing that houses an array of light-emitting elements and has multiple channels that each have an opening at the end of each channel. All of the openings of the channels are positioned along the same plane in some examples. The plane is opposite the surface of the housing that emits the light from the light-emitting elements. An intake fan is positioned in at least one of the channels so that it causes air to enter the housing through that channel's opening. An exhaust fan is positioned in another one of the channels so that it causes air to be forced out of the housing through the other channel's opening. The air flow through the intake channel and the exhaust channel help cool the lighting module during use. | 2013-07-18 |
20130182437 | ILLUMINATION DEVICE HAVING A HEAT SINK AND METHOD FOR DIRECTING A LIGHT BUNDLE EMITTED BY AN ILLUMINATION DEVICE - An illumination device may include a heat sink, on which at least one light source is fastened at least indirectly, wherein the heat sink is held movably in a holder in such a way that the heat sink moves with greater difficulty in an energized state of the light source than in a de-energized state of the light source. | 2013-07-18 |
20130182438 | LED LIGHTING FIXTURE - A light emitting diode (LED) populated circuit board is defined by a regular polygonal shaped circuit board. A channel is provided through the circuit board to form a first side diametrically opposed to a second side with a plurality of first and second legs extending from one side towards the other. A plurality of bridges are positioned along the channel to physically connect two portions of the circuit board together. LEDs are then electrically populated along the first side and first legs and along the second side and second legs. When the bridges are broken the two portions can be separated and then re-aligned along the ends of the legs to form a larger circuit board. | 2013-07-18 |
20130182439 | LED LIGHT STRING - A design of light string comprises a bulb socket, a pair of conductive wires, and LED electrically disposed onto the bulb socket. The LED is incorporated with a pair of legs which are alternatively in contact with the pair of conductive wires, and then are sandwiched between a pair of first and second casings which jointly configures the light bulb. This configuration simplifies the assembling of the conductive wires and LED such that no need of solder or glue or contacts. | 2013-07-18 |
20130182440 | ANGLED LIGHT BOX LIGHTING SYSTEM - A lighting system comprising a light box housing, a plurality of lighting units including a housing, a plurality of light emitting elements mounted on a PCB within the housing. The light emitting elements arranged on an angled surface such that the light emitting elements emit light in a sideways direction from the lighting units. The lighting units can also be interconnected in a daisy-chain configuration, such that the lighting units form a row of lighting units. The row of lighting units adapted to be mounted within the light box housing, wherein the light box housing comprises one or more rows of lighting units. | 2013-07-18 |
20130182441 | ADJUSTABLE BEAM ILLUMINATOR - An adjustable beam illuminator may provide a beam of light with an output cone angle that is adjustable (e.g., continuously adjustable) from small output angles (substantially collimated beam, “spot” mode) to larger output angles providing “flood” illumination. The illuminator may emit infrared light, for example. | 2013-07-18 |
20130182442 | Underwater Light Having a Sealed Polymer Housing and Method of Manufacture Therefor - An underwater light having a sealed polymer housing includes a rear housing component formed at least in part from a thermally conductive and electrically insulative material, an electronic assembly having at least one light-emitting element mounted thereto, the electronic assembly in thermal communication with the rear housing component, and a lens mounted to the rear housing component and forming a watertight seal therebetween, the lens and the rear housing component enclosing the electronic assembly. At least a portion of the rear housing component conducts heat away from the electronic assembly to cool the electronic assembly. | 2013-07-18 |
20130182443 | Device and Apparatus for Efficient Collection and Re-Direction of Emitted Radiation - An apparatus is described that includes a light source, a first reflector, a lens and a second reflector. The first reflector is positioned to reflect a first portion of light from the light source, wherein the first portion of light is radiated from the light source in a central forward solid angle as defined by an outer edge of the first reflector. The lens is disposed azimuthally horizontal to the light source for accepting a second portion of light from the light source emitted in a peripheral forward solid angle. The second reflector reflects the first portion of light after reflectance from the first reflector and the second portion of light after passing through the lens in a composite beam, wherein the first reflector and the lens are configured such that the first and second portions of light behave as though they were emitted from a point source at the focus of the second reflector. | 2013-07-18 |
20130182444 | LED HEAD AND PHOTON EXTRACTOR - The invention concerns a semiconductor based light source comprising a back part, a front side and at least one semiconductor chip having an emitting surface, at least one reflective optical element being arranged below said at least one semiconductor chip, a material with low refractive index being disposed on a side of said reflective optical element facing said front side, wherein said semiconductor based light source comprises on said front side a compound material with high refractive index having at least one diffractive optical element embedded therein, such as to direct light incident on said diffractive optical element towards preferred directions. | 2013-07-18 |
20130182445 | METHOD OF MANUFACTURING AN IMPROVED OPTICAL LAYER FOR A LIGHT EMITTING DEVICE WITH SURFACE NANO-MICRO TEXTURATION BASED ON COHERENT ELECTROMAGNETIC RADIATION SPECKLE LITHOGRAPHY - An object of the present invention is to provide a cheap, rapid, controlled, reproducible and polyvalent method for manufacturing a light emitting device with an internal source of light capable of achieving an enhancement in extraction efficiency. The invention proposes a method for manufacturing an optical layer for a light emitting device having an internal source of light and an optical layer separating the internal source of light and an external medium of light diffusion, wherein the method comprises the use of coherent electromagnetic radiation speckle lithography, such as laser speckle lithography, to make a nano/micro texturation on at least one surface of the optical layer. | 2013-07-18 |
20130182446 | CANDLES AND ACCESSORIES WITH REMOVABLE DECORATIONS - Removable and reusable sheets of light-filtering material that include a pattern are disclosed that can be used to decorate candles and other home accessories. Each sheet of light-filtering material can be cut to a desired shape and applied to an accessory. The light-filtering sheet includes transparent areas that allows the color of the accessory to be seen through the light-filtering sheet. The light-filtering material can filter light in many different ways, including by modifying the percent of light transmitted through the material, by modifying the percent of light reflected by the material, by modifying the color of light reflected or transmitted by the material, or by light refraction or light diffraction. | 2013-07-18 |
20130182447 | LED MOUNTING SEAT - An LED mounting seat includes a main body having a supporting surface that abuts against a light emitting portion of an LED, a connecting end that is connected to a circuit board, and a side surface that interconnects the supporting surface and the connecting end. The side surface is formed with a pair of lateral grooves. Each of the lateral grooves is defined by a groove-defining surface that has an abutting surface portion facing an opening of the corresponding one of the lateral grooves. The LED has two leads extending respectively through the lateral grooves and abutting respectively against the abutting surface portions of the groove-defining surfaces. | 2013-07-18 |
20130182448 | PROCEDURE AND STEERING MECHANISM TO CONTROL MAIN HEADLIGHTS WITH ADJUSTABLE VERTICAL CUT-OFF LINE TO REDUCE THE GLARE OF OBJECTS - A control device for vehicle headlights with adjustable light distributions and with an adjustable vertical cut-offline in at least one light distribution,
| 2013-07-18 |
20130182449 | ROTORCRAFT HAVING LIGHTING EQUIPMENT WITH A PLURALITY OF HEADLIGHTS OPERATED FOR LANDING, WINCHING, AND SEARCHING - A rotorcraft ( | 2013-07-18 |
20130182450 | SIGNALING LAMPS FOR MOTOR VEHICLE - An optical device is incorporated into an external part of a motor vehicle and comprises at least one sub-assembly including a light curtain or light curtain plus light guide and, on either side thereof, transparent plates each of which has at least one part being transparent and at least one other part being semi-transparent. At least one light source is connected to an electric source and emits rays of light that spread in a thickness of the light curtain or light curtain plus light guide. The sub-assembly and light source are incorporated into a housing, and the optical device collaborates with at least one lamp incorporated into a body-shell of the vehicle or LED on a suitable plate included in a sub-housing incorporated into the housing and emits rays of light through at least a portion of the light curtain or light curtain plus light guide that is transparent. | 2013-07-18 |
20130182451 | VEHICLE PLASTIC WINDOW - A vehicle plastic window includes a plastic structure. The outer part of the vehicle plastic window is formed by a transparent outer plastic portion. The inner part of the vehicle plastic window is formed by an opaque inner plastic portion. The inner plastic portion is formed integrally with the outer plastic portion from the inner side by the two-color molding. A lamp installing portion is formed integrally with a rear inner plastic portion from the inner side. The lamp installing portion is provided for attaching a lamp, which emits light to the outside, to the vehicle plastic window. The rear inner plastic portion has a transmission portion, which transmits light from the lamp. | 2013-07-18 |
20130182452 | LIGHT-EMITTING DEVICE, ILLUMINATION DEVICE, AND VEHICLE HEADLAMP - A headlamp ( | 2013-07-18 |
20130182453 | Vehicle Headlamp - A vehicle headlamp includes a transparent cover, a lamp body, and a illumination optical system which is accommodated in the lamp body and projects light to a predetermined illumination region in front of a vehicle via the transparent cover, wherein the illumination optical system includes a semiconductor light-emitting element in which an optical axis is configured to be directed toward the transparent cover, and a light beam guide tube which is provided between the semiconductor light-emitting element and the transparent cover and defines the illumination region by surrounding the optical axis. | 2013-07-18 |
20130182454 | EXTENDIBLE AND PIVOTABLE BICYCLE RACK - A bicycle rack for arrangement on the rear end of a motor vehicle in an extendible fashion is provided. The bicycle rack includes a carrying frame, a slide-in element that is displaceably arranged in the carrying frame, and a carrier element that is pivotably arranged on the side-in element. | 2013-07-18 |
20130182455 | DISPLAY DEVICE - Disclosed is a display device including a plurality of channels for forming a specific pattern, in which each of the channels includes: a light source module comprising one or more light sources for generating optical signals having different wavelengths; a driving module for controlling on/off or strength of the optical signal generated in the light source module; an optical waveguide for transferring the optical signal generated in the light source module to an outside without a loss of the optical signal; and a scattering pattern for scattering the optical signal transferred through the optical waveguide and displaying the scattered optical signal to the outside. | 2013-07-18 |
20130182456 | Edge type LED backlight unit - A LED backlight unit structure, especially a edge type LED backlight unit, which had a substrate and a one or plurality LED light source lay on the substrate, and a light guide plate | 2013-07-18 |
20130182457 | LIGHTING ASSEMBLY WITH STATIC AUTOSTEREOSCOPIC IMAGE OUTPUT - A lighting assembly includes a light guide in which light propagates by total internal reflection between opposed major surfaces. The light guide receives light generated by two light sources at opposed light input edges of the light guide. The light guide includes light extracting elements that respectively extract light to form a left eye image at a first region and a right eye image at a second region. The left eye and right eye images, when viewed by a viewer, form a static autostereoscopic image. | 2013-07-18 |
20130182458 | LIGHT-EMITTING DEVICE FOR EMITTING DIFFUSE LIGHT - A light-emitting device which has a plate-shaped light guide ( | 2013-07-18 |
20130182459 | LIGHTING DEVICE - A lighting device is provided and includes a light guide plate including a plurality of light incident surfaces and two light emitting surfaces, a plurality of edge frames, and at least one light source. Each of the edge frames includes a main body including an accommodating groove and an opening, first and second clamp members, and first and second fixing elements respectively located on first and second ends of the main body. The light emitting surfaces are clamped by the first and second clamp members of each edge frame. Each of the light incident surfaces is inserted in the main body of one of the edge frames through the opening and accommodated in the accommodating groove. The light source is located in the accommodating groove of one of the edge frames and adjacent to the corresponding light incident surface. | 2013-07-18 |
20130182460 | MAGNETITE-CONTAINING RESIN AND ELECTRONIC COMPONENT - This disclosure provides a magnetic material-containing resin to be used for coating and forming cores. A magnetite-containing resin of the present invention includes a magnetite having a residual magnetic flux density of less than 15 Am | 2013-07-18 |
20130182461 | SYSTEM AND METHOD FOR POWER TRANSFER CONTROL - The present invention employs system and method in for distinguishing between power capabilities of various external power sources and a system that can communicate the identified power capabilities to the secondary side of the wireless power transfer system. Once the secondary side of the wireless power transfer system receives the power capability information, it adjusts the current available for a payload in accordance with the information received on power source capabilities. | 2013-07-18 |
20130182462 | LINEAR SYNCHRONOUS RECTIFIER DRIVE CIRCUIT - A drive circuit arranged to drive a synchronous rectifier of a power converter includes a differential amplifier stage connected to the synchronous rectifier and arranged to supply a drive signal to the synchronous rectifier to turn the synchronous rectifier on and off and a high voltage blocking stage connected between the synchronous rectifier and the differential amplifier stage. The differential amplifier stage is arranged such that a voltage level of the drive signal depends on a load of the power converter. | 2013-07-18 |
20130182463 | VALLEY-DETECTION DEVICE FOR QUASI-RESONANCE SWITCHING AND METHOD USING THE SAME - A valley-detection device for quasi-resonance switching and a method using the same is disclosed, which uses first and second capacitors to connect with a comparator, and the comparator connects with an NMOSFET connecting to a transformer. When the NMOSFET is turned off, the energy stored in the transformer is discharged and a resonant signal across the source and the drain is generated, and a first constant current charges the first capacitor at a start time point of the resonant signal until a voltage of the resonant signal first reaches to a crossing voltage. Then, a second constant current charges the second capacitor when the voltage of the resonant signal equals to the crossing voltage while the voltage of the resonant signal varies from high to low. Finally, the comparator turns on the NMOSFET when a voltage of the second capacitor equals to a voltage of the first capacitor. | 2013-07-18 |
20130182464 | DC Converter With Low Starting Voltage - The present invention relates to an electronic circuit with which input voltages at an input of the circuit are converted into higher output voltages at an output of the circuit, whereby the voltage conversion already starts at low voltages at the input. According to the present invention, the DC converter circuit for the generation of an output voltage from an input voltage (V | 2013-07-18 |
20130182465 | WIND POWER CONVERTER STRUCTURE AND WIND POWER GENERATION SYSTEM INCLUDING THE SAME - A wind power converter structure and a wind power generation system including the converter structure are provided. The converter structure comprises a plurality of generator-side converters arranged in a nacelle located on a top part of the tower; a plurality of grid-side converters arranged on a bottom part of the tower or outside the tower, wherein a DC input side of the grid-side converter is coupled to a DC output side of the generator-side converter; at least one DC bus connected between the generator-side converter and the grid-side converter; and an isolation transformer of which a primary side is coupled to the AC output side of the grid-side converter, wherein a secondary side of the isolation transformer is coupled to a power grid. | 2013-07-18 |
20130182466 | EXCITATION CONTROL CIRCUIT AND ELECTRICALLY EXCITED WIND POWER SYSTEM HAVING THE SAME - The present invention provides an excitation control circuit and the electrically excited wind power system having the same. The excitation control circuit includes a plurality of full-power converters, each of which has a generator-side converter and a grid-side converter; a DC excitation module including a plurality of DC-DC converters; and a control module, controlling or switching any DC-DC converter working normally, and controlling excitation switch turning ON or turning OFF. | 2013-07-18 |
20130182467 | CONVERTER - A voltage source converter comprising three phase elements defining a star connection in which a first end of each phase element is connected to a common junction; at least two converter limbs, each converter limb including first and second DC terminals for connection in use to a DC network and an AC terminal connected in series with a second end of a phase element, each converter limb defining first and second limb portions, including a chain-link converter, each chain-link converter including chain-link modules; and a third DC terminal connected to the common junction of the star connection to define an auxiliary connection, wherein in use a current is injected into the auxiliary connection to modify a voltage of each chain-link module in each limb portion. | 2013-07-18 |
20130182468 | WIND POWER CONVERTER - A wind power converter comprises a multiple of phase power converters, each of which being adapted to convert power output from a corresponding phase of a wind generator to a corresponding phase of a grid; each of the phase power converters comprising: a full-wave rectifier, being adapted to rectify the power input through a first terminal and a second terminal from the corresponding phase of the wind generator; a capacitor being adapted to be charged by the power rectified by the full-wave rectifier; and a full-wave active inverter, being adapted to invert the power stored in the capacitor and output the inverted power to the corresponding phase of the grid through a third terminal and a fourth terminal; wherein: the first terminal or the second terminal is connected to a first virtual neutral; and the third terminal or the fourth terminal is connected to a second virtual neutral. | 2013-07-18 |
20130182469 | ELECTRO-MAGNETIC INTERFERENCE REDUCTION CIRCUIT FOR POWER CONVERTERS AND METHOD FOR THE SAME - The present invention provides a circuit of reducing electro-magnetic interference for a power converter. The circuit includes an oscillator, a current generation circuit, a feedback circuit and a ramping generator. The oscillator has a first terminal for receiving a first jittering current and a second terminal for feeding a second jittering current. The first jittering current and the second jittering current are correlated with a line signal obtained from an input of the power converter to vary a frequency of the oscillator. The first jittering current and the second jittering current are unequal. As the first jittering current is set greater than the second jittering current, the frequency of the switching signal increases whenever the line signal is increasing. As the first jittering current is set lower than the second jittering current, the frequency of the switching signal decreases whenever the line signal is increasing. | 2013-07-18 |
20130182470 | Power Module Package Having a Multi-Phase Inverter and Power Factor Correction - According to an exemplary implementation, a power module package includes a multi-phase inverter. The power module package also includes a multi-phase inverter driver configured to drive the multi-phase inverter. The power module package further includes a power factor correction (PFC) circuit where the PFC circuit is configured to regulate a bus voltage of the multi-phase inverter and a PFC driver configured to drive the PFC circuit. The multi-phase inverter, the multi-phase inverter driver, the PFC circuit, and the PFC driver are situated on a package substrate of the power module package. The multi-phase inverter driver and the PFC driver can be in a common driver integrated circuit (IC). | 2013-07-18 |
20130182471 | OVERVOLTAGE PROTECTION CIRCUIT FOR AT LEAST ONE BRANCH OF A HALF-BRIDGE, INVERTER, DC/DC VOLTAGE CONVERTER AND CIRCUIT ARRANGEMENT FOR OPERATING AN ELECTRICAL MACHINE - An overvoltage protection circuit is provided for at least one branch of a half-bridge which includes a controllable semiconductor switch element and a free-wheeling diode connected in series and situated on a common circuit substrate. The protection circuit includes a commutation branch connected in parallel with the half-bridge branch, the commutation branch including at least one commutation capacitor also situated on the circuit substrate. | 2013-07-18 |
20130182472 | POWER-SAVING VOLTAGE CONVERTER SYSTEM - A voltage converter system having a converter and a connector system may include a control circuit that enables or disables the converter in response to the connection status of the connector system. | 2013-07-18 |
20130182473 | AUTOMATIC VOLTAGE CONVERSION SYSTEM BASED ON A SINGLECHIP - The invention discloses an automatic voltage conversion system based on a singlechip, comprising a control unit, a power circuit unit, a transformer unit, a voltage sampling unit, an output protection unit and a voltage switching unit; wherein, the power circuit unit provides suitable working voltage for the whole circuit; the voltage sampling switching units are respectively connected to the control unit; the transformer unit is connected to the voltage switching unit; the output protection unit input is connected to the control unit, and output protection unit output is connected to the transformer unit; and the control unit, as a control system based on a singlechip, is used for controlling operation of both the voltage switching and output protection units after processing the signal gathered by the voltage sampling unit. The system can perform automatic voltage conversion, and high and low input voltage protection and provide transformer over temperature protection. | 2013-07-18 |
20130182474 | POWER CONVERSION DEVICE FOR SOLAR ENERGY GENERATING SYSTEM - A power conversion device includes a DC-DC converter, a DC-AC inverter and a relay. The DC-DC converter leads in a DC from an external solar panel and transforms the DC into a direct voltage. The DC-AC inverter transforms the direct voltage from the DC-DC converter into an alternating voltage and connecting to an external electric load via electric load output ends. The relay includes a coil connected to an external commercial power line via commercial power input ends, and conductive contacts actuated by the coil and serially-disposed between the commercial power input ends and the DC-AC inverter, and with the commercial power line electrifying the coils, the conduction control is formed therebetween, preventing the electric energy of the solar energy generation from inversely transmitting to the commercial power line when interrupting the commercial power service. | 2013-07-18 |
20130182475 | MULTI-PHASE INVERTER CONTROL DEVICE AND CURRENT CONTROL METHOD FOR THE SAME - The present invention provides a multi-phase inverter control device and a current control method for the same. The multi-phase inverter control device comprises a discrete circuit receiving CT IOCCS, CT IOCS and CT LIVS, and converting them into a plurality of DT signals; a multi-dimensional quantization circuit calculating according to an MDFQCC (Multi-Dimensional Feedback Quantization Current Control) algorithm to obtain DT IOVS for determining a plurality of switching signals; a driver circuit receiving the switching signals, and converting the switching signals into a plurality of switch driving signals; and an inverter circuit receiving the switch driving signals to output voltage across the load. The present invention decreases switching frequency, reduces switching loss and controls the inverter to output current efficiently. | 2013-07-18 |
20130182476 | ADAPTIVE SAMPLING CIRCUIT FOR DETECTING THE DEMAGNETIZED VOLTAGE OF THE TRANSFORMER - An adaptive sampling circuit of the power converter according to the present invention comprises a sample-and-hold unit and a signal-generation circuit. The sample-and-hold unit is coupled to a transformer to generate a feedback signal by sampling a demagnetized voltage of the transformer in response to a sample signal. The signal-generation circuit generates the sample signal in response to a magnetized voltage of the transformer, the demagnetized voltage of the transformer, a switching signal and a code. The sample signal is used for sampling the demagnetized voltage. The feedback signal is correlated to an output voltage of the power converter. The switching signal is generated in response to the feedback signal for switching the transformer and regulating the output of the power converter. The adaptive sampling circuit is used to precisely measure the demagnetized voltage of the transformer without the limitation of the transformer design. | 2013-07-18 |
20130182477 | Method for Stabilizing an Electric Grid - A method for grid support by means of an inverter is disclosed, wherein the grid is supported by feeding in compensation currents. The method includes measuring a prevailing grid state, and breaking down voltages measured for measuring the prevailing grid state into symmetrical components of the grid state including positive sequence system components and negative sequence system components. The method further includes determining symmetrical components of a compensation current including positive sequence system components and negative sequence system components of the compensation current as functions of deviations of the positive sequence system components and negative sequence system components of the grid state from reference values, and feeding-in a compensation current as the vector sum of the determined symmetrical components of the compensation current | 2013-07-18 |
20130182478 | REACTOR, CONVERTER, AND ELECTRIC POWER CONVERTER - A small reactor with high heat-release performance is provided. A reactor | 2013-07-18 |
20130182479 | VARIABLE VOLTAGE REFERENCE IN POWER RECTIFICATION - A power rectification system includes power electronics configured to rectify an alternating current (AC) waveform to produce a direct current (DC) output voltage, a control circuit configured to control the power electronics based upon an error value, and a voltage reference control portion configured to provide the error value based upon a variable voltage reference and the DC output voltage. The variable voltage reference varies between the DC output voltage and a fixed voltage reference. | 2013-07-18 |
20130182480 | AC POWER SUPPLY APPARATUS - In an AC power supply apparatus, first and second switching circuits connected in series to an input terminal to which a DC input power supply is connected include first and second rectification elements, respectively. A capacitor, an inductor, and a capacitive load are equivalently connected in series to the second switching circuit. The capacitor is charged after the first switching circuit is turned on before the second rectification element is turned off and the charged capacitor is caused to discharge after the second switching circuit is turned on before the second rectification element is turned off. The above operations are periodically repeated. The voltage of the capacitive load is reversed with current flowing during the charge and the discharge of the capacitor to adjust the on and off periods of the first and second switching circuits in order to supply desired AC voltage to the capacitive load. | 2013-07-18 |
20130182481 | Coupled Electron Shuttle Providing Electrical Rectification - A nanoscale electron shuttle with two elastically mounted conductors positioned within a gap between conductors produces asymmetrical electron conduction between the conductors when the conductors receive an AC signal to provide for rectification, detection and/or power harvesting. | 2013-07-18 |
20130182482 | CONTENT ADDRESSABLE MEMORY DEVICE - A semiconductor integrated circuit includes a plurality of output transistors each controlling the magnitude of an output voltage relative to the magnitude of a load current according to a control value indicated by an impedance control signal applied to a control terminal, a voltage monitor circuit outputting an output voltage monitor value indicating a voltage value of the output voltage, and a control circuit controlling the magnitude of the control value according to the magnitude of an error value between a reference voltage indicating a target value of the output voltage and the output voltage monitor value, and controls based on the control value whether any of such transistors be brought to a conducting state. The control circuit increases a change step of the control value relative to the error value during a predetermined period according to prenotification signals for notifying a change of the load current in advance. | 2013-07-18 |
20130182483 | Discrete Three-Dimensional Memory Comprising Off-Die Address/Data Translator - The present invention discloses a discrete three-dimensional memory (3D-M). Its 3D-M arrays are located on at least one 3D-array die, while its address-data translator (A/D-translator) is located on a separate peripheral-circuit die. The A/D-translator converts at least an address and/or data between logical space and physical space for the 3D-array die. A single A/D-translator die can support multiple 3D-array dies. | 2013-07-18 |
20130182484 | WORD LINE AND POWER CONDUCTOR WITHIN A METAL LAYER OF A MEMORY CELL - A memory cell | 2013-07-18 |
20130182485 | Data Storage and Stackable Configurations - A first memory device and second memory device have a same input/output layout configuration. To form a stack, the second memory device is secured to the first memory device. To facilitate connectivity, the second memory device is rotationally offset with respect to the first memory device in the stack to align outputs of the first memory device with corresponding inputs of the second memory device. The rotational offset of the second memory device with respect to the first memory device aligns one or more outputs of the first memory device with one or more respective inputs of the second memory device. Based on links between outputs and inputs from one memory device to another in the stack, the stack of memory devices can include paths facilitating one or more series connection configurations through the memory devices. | 2013-07-18 |
20130182486 | MEMORY CELLS HAVING A COMMON GATE TERMINAL - Arrays of memory cells having a common gate terminal and methods of operating and forming the same are described herein. As an example, an array of memory cells may include a group of memory cells each having a resistive storage element coupled to a select device. Each select device includes a first terminal, a second terminal, and a gate terminal, where the gate terminal is common to each memory cell of the group. | 2013-07-18 |
20130182487 | PROGRAMMABLE METALLIZATION CELL WITH TWO DIELECTRIC LAYERS - A programmable metallization device comprises a first electrode and a second electrode, and a first dielectric layer, a second dielectric layer, and an ion-supplying layer in series between the first and second electrodes. In operation, a conductive bridge is formed or destructed in the first dielectric layer to represent a data value. During read, a read bias is applied that is sufficient to cause formation of a transient bridge in the second dielectric layer, and make a conductive path through the cell if the bridge is present in the first dielectric layer. If the bridge is not present in the first dielectric layer during the read, then the conductive path is not formed. Upon removal of the read bias voltage any the conductive bridge formed in the second dielectric layer is destructed while the conductive bridge in the corresponding other first dielectric layer, if any, remains. | 2013-07-18 |
20130182488 | NON-VOLATILE SEMICONDUCTOR MEMORY AND DATA PROCESSING METHOD IN NON-VOLATILE SEMICONDUCTOR MEMORY - A non-volatile semiconductor memory according to an embodiment includes: a data storage unit including a memory cell array and a writing circuit; an encoder that directs the writing circuit to write write data to the memory cell array; a writing determining circuit that determines whether the writing of the write data to the memory cell array within a predetermined number of writing operations fails or succeeds, inverts the write data to generate new write data when the writing of the write data fails, and directs the writing circuit to write the new write data to the memory cell array; a switching circuit that inverts read data which is read from the memory cell to generate new read data when the writing determining circuit determines that the writing of the write data fails; and a decoder that decodes the read data into the information data. | 2013-07-18 |
20130182489 | REPLACEMENT OF A FAULTY MEMORY CELL WITH A SPARE CELL FOR A MEMORY CIRCUIT - A memory integrated circuit device is provided. The device includes a plurality of regular address inputs and at least one spare address input configured for a selected mode or an unselected mode. The device includes a plurality of control inputs, a plurality of data inputs, and a plurality of data outputs. The device has a plurality of memory arrays. Each of the memory arrays comprises a plurality of memory cells. Each of the plurality of memory cells is coupled to a data input/output. The device has a spare group of memory cells comprising a plurality of spare memory cells. Each of the plurality of spare memory cells is externally (or internally) addressable using the address match table and configured with the spare address input; whereupon the spare address input is coupled to the address match table to access the spare memory cells. | 2013-07-18 |
20130182490 | Static Random Access Memory Cell with Single-Sided Buffer and Asymmetric Construction - Balanced electrical performance in a static random access memory (SRAM) cell with an asymmetric context such as a buffer circuit. Each memory cell includes a circuit feature, such as a read buffer, that has larger transistor sizes and features than the other transistors within the cell, and in which the feature asymmetrical influences the smaller cell transistors. For best performance, pairs of cell transistors are to be electrically matched with one another. One or more of the cell transistors nearer to the asymmetric feature are constructed differently, for example with different channel width, channel length, or net channel dopant concentration, to compensate for the proximity effects of the asymmetric feature. | 2013-07-18 |
20130182491 | SYSTEM AND METHOD FOR MODIFYING ACTIVATION OF A SENSE AMPLIFIER - Systems, methods, and other embodiments associated with controlling a sense amplifier in a memory device are described. According to one embodiment, an apparatus includes a signal generator configured to generate a sense enable signal that activates a sense amplifier of a memory cell in a memory device. The apparatus includes a dummy memory cell connected to a current mirror circuit that is configured to detect a timing variation in the dummy memory cell from a predefined timing and to alter a timing of the sense enable signal based, at least in part, on the timing variation. The apparatus also includes a controller configured to modify the timing of the sense enable signal by selectively enabling one or more of a plurality of semiconductor gates in the current mirror circuit. The plurality of semiconductor gates are connected in parallel. | 2013-07-18 |
20130182492 | 10T SRAM CELL WITH NEAR DUAL PORT FUNCTIONALITY - An integrated circuit including an array of SRAM cells containing a write port with a write word line and two read buffers with read word lines. The write port includes passgate transistors connected to each data node of the SRAM cell. A process of operating the integrated circuit in which source nodes of read buffer driver transistors are biased during a read operation. A process of operating the integrated circuit in which source nodes of read buffer driver transistors are floated during a read operation. A process of operating the integrated circuit in which the write port and the read ports share data lines and the source nodes of read buffer driver transistors are floated during a write operation. | 2013-07-18 |
20130182493 | Integrated Circuit With Separate Supply Voltage For Memory That Is Different From Logic Circuit Supply Voltage - In one embodiment, an integrated circuit includes at least one logic circuit supplied by a first supply voltage and at least one memory circuit coupled to the logic circuit and supplied by a second supply voltage. The memory circuit is configured to be read and written responsive to the logic circuit even if the first supply voltage is less than the second supply voltage during use. In another embodiment, a method includes a logic circuit reading a memory cell, the logic circuit supplied by a first supply voltage; and the memory cell responding to the read using signals that are referenced to the first supply voltage, wherein the memory cell is supplied with a second supply voltage that is greater than the first supply voltage during use. | 2013-07-18 |
20130182494 | SKEWED SRAM CELL - A memory cell including a cross-coupled latch with corresponding storage nodes, and further including first and second write pass gate transistors and first and second read pass gate transistors. The write pass gate transistors are controlled by a write word line and the read pass transistors are controlled by a read word line. Each read and write pass gate transistor is coupled between a storage node and either a bit line or a complementary bit line. The write pass gate transistors are implemented at a first strength level and the read pass gate transistors are implemented at a second strength level which is less than the first strength level. In this manner, the read and write margins are independently configurable without negatively impacting each other. | 2013-07-18 |
20130182495 | Efficient Static Random-Access Memory Layout - A complementary metal-oxide-semiconductor (CMOS) static random access memory (SRAM) with no well contacts within the memory array. Modern sub-micron CMOS structures have been observed to have reduced vulnerability to latchup. Chip area is reduced by providing no well contacts within the array. Wells of either or both conductivity types may electrically float during operation of the memory. In other implementations, extensions of the array wells into peripheral circuitry may be provided, with well contacts provided in those extended portions. | 2013-07-18 |
20130182496 | SEMICONDUCTOR STORAGE DEVICE - A semiconductor storage device includes plural bit lines and plural word lines. The memory cell array has plural memory cells that are connected with the bit lines and word lines, and can store data. Plural sense amplifiers detect the data stored in the memory cells. Plural write drivers write data in the memory cells. A comparison buffer temporarily stores the write data to be written in the memory cells by the write driver. In a series of write sequences, the comparison buffer stores the read data from the memory cells selected as the write object and the write data to be written in the selected memory cells. After a series of write sequences, when the pre-charge command for resetting the voltage of the bit lines is received, the write execution command is executed so that the comparison buffer executes write in the selected memory cells. | 2013-07-18 |
20130182497 | SEMICONDUCTOR STORAGE DEVICE - A semiconductor storage device having tunnel magnetoresistive elements in memory cells. | 2013-07-18 |
20130182498 | MAGNETIC MEMORY DEVICE AND DATA WRITING METHOD FOR MAGNETIC MEMORY DEVICE - A magnetic memory device including a plurality of memory cells, each of which stores therein 2 | 2013-07-18 |
20130182499 | MRAM Cell and Method for Writing to the MRAM Cell using a Thermally Assisted Write Operation with a Reduced Field Current - The present disclosure concerns a method for writing to a MRAM cell comprising a magnetic tunnel junction formed from a storage layer having a storage magnetization; a reference layer having a reference magnetization; and a tunnel barrier layer included between the sense and storage layers; and a current line electrically connected to said magnetic tunnel junction; the method comprising: passing a heating current in the magnetic tunnel junction for heating the magnetic tunnel junction; passing a field current for switching the storage magnetization in a written direction in accordance with the polarity of the field current. The magnitude of the heating current is such that it acts as a spin polarized current and can adjust the storage magnetization; and the polarity of the heating current is such as to adjust the storage magnetization substantially towards said written direction. | 2013-07-18 |
20130182500 | LATCHING CIRCUIT - A non-volatile latch circuit includes a pair of cross-coupled inverters, a pair of resistance-based memory elements, and write circuitry configured to write data to the pair of resistance-based memory elements. The pair of resistance-based memory elements is isolated from the pair of cross-coupled inverters during a latching operation. A sensing circuit includes a first current path that includes a resistance-based memory element and an output of the sensing circuit. The sensing circuit includes a second current path to reduce current flow through the resistance-based memory element at a first operating point of the sensing circuit. | 2013-07-18 |
20130182501 | SEMICONDUCTOR STORAGE DEVICE AND ITS MANUFACTURING METHOD - A magnetoresistive element | 2013-07-18 |
20130182502 | Operating Methods of Nonvolatile Memory Devices - Disclosed are methods of operating a nonvolatile memory device which includes a substrate and a plurality of cell strings provided on the substrate, each cell string including a plurality of memory cells stacked in a direction perpendicular to the substrate. The methods may include applying a word line erase voltage to word lines connected to memory cells of the plurality of cell strings; floating ground selection lines connected to ground selection transistors of the plurality of cell strings and string selection lines connected to string selection transistors of the plurality of cell strings; applying a ground voltage to at least one lower dummy word line connected to at least one lower dummy memory cell between memory cells and a ground selection transistor in each of the plurality of cell strings; applying an erase voltage to the substrate; and floating the at least one lower dummy word line after applying of the erase voltage. | 2013-07-18 |
20130182503 | METHOD, MEMORY CONTROLLER AND SYSTEM FOR READING DATA STORED IN FLASH MEMORY - An exemplary method for reading data stored in a flash memory is disclosed. The flash memory comprises a plurality of memory cells and stores N bit(s) data in a memory cell of the memory cells by programming the memory cell to one voltage state of 2N voltage states. The method includes: controlling the flash memory to perform at least one read operation upon the memory cell to obtain at least one binary digit for representing a bit of the N bits data; generating a codeword for representing the bit of the N bits data according to the at least one binary digit, wherein the codeword is different from the at least one binary digit; providing the codeword to an error correction decoder for performing an error correction operation. | 2013-07-18 |
20130182504 | PAGE BUFFER CIRCUIT AND NONVOLATILE MEMORY DEVICE HAVING THE SAME - A page buffer circuit includes first and second bit lines coupled to a first sensing circuit and with a first space therebetween, and third and fourth bit lines coupled to a second sensing circuit and with the first space therebetween. The second bit line and the third bit line are adjacent to each other with a second space therebetween, and the second space is smaller than the first space. | 2013-07-18 |
20130182505 | FLASH PROGRAMMING TECHNOLOGY FOR IMPROVED MARGIN AND INHIBITING DISTURBANCE - A charge storage memory is configured in a NAND array, and includes NAND strings coupled to bit lines via string select switches and includes word lines. A controller is configured to produce a program bias pulse by biasing the bit lines and string select lines in a first condition; setting a word line coupled to a target cell to a first voltage level while the bit lines and string select lines are in the first condition; thereafter, biasing the bit lines and string select lines in a second condition; and setting the word line coupled to the target cell to a second voltage level higher than the first voltage level while the bit lines and string select lines are in the second condition. Program bias pulses produced in this manner can be used in a modulated incremental stepped pulse programming sequence. | 2013-07-18 |
20130182506 | PROGRAMMING ALGORITHM FOR IMPROVED FLASH MEMORY ENDURANCE AND RETENTION - A method for programming a flash cell using a series of programming pulses, the method comprising providing a plurality of first successive programming pulses, wherein each of the first successive programming pulse is incremented by a first incremental amount and providing a plurality of second successive programming pulses, wherein each of the second successive programming pulses is incremented by a second incremental amount and wherein the second increment amount is smaller than the first incremental amount. A system and machine-readable media are also provided. | 2013-07-18 |
20130182507 | MEMORY SYSTEM TEMPERATURE CALIBRATION - A nonvolatile memory system includes a memory controller chip with at least one temperature sensor that is individually calibrated, at a single temperature, after the nonvolatile memory system is assembled, so that the calibration data is stored outside the memory controller chip, in a nonvolatile memory chip, thus obviating the need for components to store calibration data in the memory controller chip. | 2013-07-18 |
20130182508 | SEMICONDUCTOR DEVICE FOR ACCELERATING ERASE VERIFICATION PROCESS AND METHOD THEREFOR - A semiconductor device and a method for accelerating erase verification process thereof are introduced, in which a correction unit of erase verification is connected between broken bit lines of the semiconductor device and a page buffer. Grounding switches in the correction unit of erase verification are allowed to connect the broken bit lines to ground during an erase verification process by means of a specific circuit arrangement with respect to the broken lines. Thereby, the earth voltage is received, and further, that the broken bit lines pass the erase verification is identified by the page buffer, further saving time consumed in repeated verifications in the conventional technology significantly. | 2013-07-18 |
20130182509 | NEW 1T1b AND 2T2b FLASH-BASED, DATA-ORIENTED EEPROM DESIGN - An one-transistor-one-bit (1T1b) Flash-based EEPROM cell is provided along with improved key operation schemes including applying a negative word line voltage and a reduced bit line voltage for perform erase operation, which drastically reduces the high voltage stress on each cell for enhancing the Program/Erase cycles while reducing cell size. An array made by the 1T1b Flash-based EEPROM cells can be operated with Half-page or Full-page divided programming and pre-charging period for each program cycle. Utilizing PGM buffer made of Vdd devices in the cell array further save silicon area. Additionally, a two-transistor-two-bit (2T2b) EEPROM cell derived from the 1T1b cell is disclosed with additional cell size reduction but with the operation of program and erase the same as that for the 1T1b cells with benefits of no process change but much enhanced storage density, superior Program/Erase endurance cycle, and capability for operating in high temperature environment. | 2013-07-18 |
20130182510 | MEMORY DEVICES AND PROGRAMMING METHODS - Memory devices and programming methods are disclosed. In an embodiment of one such method, a memory cell is programmed to at least a first threshold voltage. After programming the memory cell to at least the first threshold voltage, the memory cell is read, using a read voltage that is less than the first threshold voltage. After reading the memory cell, the memory cell is programmed to at least a second threshold voltage that is greater than the first threshold voltage. | 2013-07-18 |
20130182511 | DIGITAL MEMORY SYSTEM THAT DYNAMICALLY ADJUSTS REFERENCE VOLTAGE AS A FUNCTION OF TRAFFIC INTENSITY - A digital memory system includes a memory controller having a driver configured for generating a digital signal. A memory module has a receiver in communication with the driver. The driver is configured for selectively directing the digital signal to the receiver of the memory module. A voltage control module is configured for determining a traffic intensity at which the digital signal is directed to the receiver and dynamically adjusting the reference voltage as a function of the traffic intensity at which the digital signal is directed to the receiver. | 2013-07-18 |
20130182512 | MEMORY CIRCUITS HAVING A PLURALITY OF KEEPERS - A circuit including a memory circuit, the memory circuit includes a first plurality of memory arrays and a first plurality of keepers, each keeper of the first plurality of keepers is electrically coupled with a corresponding one of the first plurality of memory arrays. The memory circuit further includes a first current limiter electrically coupled with and shared by the first plurality of keepers. | 2013-07-18 |
20130182513 | MEMORY SYSTEM CAPABLE OF CALIBRATING OUTPUT VOLTAGE LEVEL OF SEMICONDUCTOR MEMORY DEVICE AND METHOD OF CALIBRATING OUTPUT VOLTAGE LEVEL OF SEMICONDUCTOR MEMORY DEVICE - Provided are a semiconductor memory device and a memory system including the same, which may calibrate a level of an output voltage in consideration of channel environment and a mismatch in on-die termination (ODT) resistance of a memory controller. The memory system includes a memory controller and a semiconductor memory device. The semiconductor memory device is configured to generate a reference voltage based on driving information of the memory controller, and calibrate an output voltage level based on a reference voltage when the semiconductor memory device is electrically connected to the memory controller. | 2013-07-18 |
20130182514 | Mimicking Multi-Voltage Domain Wordline Decoding Logic for a Memory Array - Systems and methods for adaptively mimicking wordline decoding logic for multi-voltage domain memory are disclosed. In one embodiment, the multi-voltage domain memory includes a memory array implemented in a high voltage domain and a multi-voltage domain control circuit. The multi-voltage domain control circuit includes multi-voltage domain decoding logic that generates a wordline for the memory array and a multi-voltage domain mimic logic that mimics the multi-voltage domain decoding logic to generate a dummy wordline. In one embodiment, the dummy wordline is utilized to trigger an ending edge (e.g., a falling edge) of the wordline once the wordline is asserted. In addition or alternatively, the dummy wordline is utilized to generate one or more control signals for the memory array such as, for example, a pre-charge control signal and/or a sense amplifier enable signal. | 2013-07-18 |
20130182515 | DUAL-VOLTAGE DOMAIN MEMORY BUFFERS, AND RELATED SYSTEMS AND METHODS - Dual-voltage domain memory buffers, and related systems and methods are disclosed. To reduce area needed for voltage level shifters for voltage level shifting, latch banks are provided in a voltage domain of memory buffer read circuitry, separate from the voltage domain of a write data input to the latch banks. A write data input voltage level shifter is disposed between the write data input and the latch banks to voltage level shift write data on the write data input to the voltage domain of the latch banks. In this manner, voltage level shifters are not required to voltage level shill the latch bank outputs, because the latch banks are in the voltage domain of the memory buffer read circuitry. In this manner, semiconductor area that would otherwise be needed for the voltage level shifters to voltage level shift latch bank outputs is not required. | 2013-07-18 |
20130182516 | SEMICONDUCTOR DEVICE HAVING COUNTER CIRCUIT - A semiconductor device is disclosed which comprises a clock generating circuit generating first and second divided clocks by dividing an input clock by first and second division number, respectively, and a counter circuit including a shift register having a plurality of stages that sequentially shifts an input signal and outputs an output signal delayed based on setting information. The counter circuit individually controls operation timings of the stages of the shift register by selectively supplying either of the first and second divided clocks to each stage of the shift register, and either of signals from the stages of the shift register is extracted and outputted as the output signal. | 2013-07-18 |
20130182517 | FAIL ADDRESS STORAGE CIRCUIT, REDUNDANCY CONTROL CIRCUIT, METHOD FOR STORING FAIL ADDRESS AND METHOD FOR CONTROLLING REDUNDANCY - A redundancy control circuit includes: a fail address storage unit configured to store a fail address; a shared storage unit configured to store data as to whether a value stored in the fail address storage unit corresponds to both of a first address and a second address; an address comparator configured to compare a value stored in the fail address storage unit with a first input address and a second input address, respectively; and a redundancy controller configured to control a redundancy operation in response to a value stored in the shared storage unit and comparison results of the address comparator. | 2013-07-18 |
20130182518 | MEMORY CELL OF SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR DRIVING THE SAME - A semiconductor memory device includes a first fuse having one end coupled with a first bit line and configured to be programmed with a data, a second fuse having one end coupled with a second bit line and configured to be programmed with the data; a program controller coupled with the other ends of the first fuse and the second fuse and configured to perform a program operation on at least one of the first fuse and the second fuse in response to a program voltage, and a read controller coupled with the other ends of the first fuse and the second fuse and configured to perform a read operation on the first fuse and the second fuse in response to a read voltage. | 2013-07-18 |
20130182519 | MEMORY DEVICE AND VOLTAGE INTERPRETING METHOD FOR READ BIT LINE - A memory device comprises a memory cell array, a first and a second pre-charging switch circuits, a selecting circuit, an auxiliary memory cell array, a dynamic voltage controller and a sense amplifier. The auxiliary memory cell array comprises an auxiliary read bit line and a plurality of memory cells arranged in a column and electrically connected to the auxiliary read bit line. The second pre-charging switch circuit determines whether or not to supply a reference voltage to each of the aforementioned memory cells according to a pre-charging control signal. The dynamic voltage controller determines whether or not to supply a voltage to the auxiliary read bit line according to the voltage level of the output signal of the selecting circuit. The sense amplifier compares the voltage levels of the output signal of the selecting circuit and the voltage on the auxiliary read bit line to output a sensing result accordingly. | 2013-07-18 |
20130182520 | MEMORY DEVICE BASED ON CONDUCTANCE SWITCHING IN POLYMER/ELECTROLYTE JUNCTIONS - A non-volatile memory device including at least a first electrode and a second electrode provided on a substrate, the first and second electrodes being separated from each other; an organic semiconductive polymer electrically connecting the first and second electrodes; an electrolyte in contact with the organic semiconductive polymer; and a third electrode that is not in contact with the first electrode, the second electrode, and the organic semiconductive polymer; wherein the organic semiconductive polymer has a first redox state in which it exhibits a first conductivity, and a second redox state in which it exhibits a second conductivity. | 2013-07-18 |
20130182521 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SAME - A semiconductor memory device is operated by forming channels in a cell string including a plurality of memory cells and coupled between a bit line and a source line, applying first and second erase voltages having different levels to the channels through the bit line and the source line, respectively, and applying a first word line voltage to at least one word line among word lines coupled to the plurality of memory cells. | 2013-07-18 |
20130182522 | MEMORY DEVICE, METHOD OF OPERATING THE SAME, AND APPARATUS INCLUDING THE SAME - A method of operating a memory device includes masking at least one bank among a plurality of banks in response to a mode register writing command; and performing a refresh operation on a plurality of rows in one of unmasked banks in response to a first per-bank refresh command. | 2013-07-18 |