30th week of 2009 patent applcation highlights part 11 |
Patent application number | Title | Published |
20090184290 | Precursor composition, method for manufacturing precursor composition, method for manufacturing ferroelectric film, piezoelectric element, semiconductor device, piezoelectric actuator, ink jet recording head, and ink jet printer - To provide precursor compositions for forming ferroelectric, methods for manufacturing precursor compositions, and methods for forming ferroelectric films using precursor compositions, which have excellent composition controllability in a liquid phase method, and in which metal compositions such as lead can be reused. A precursor composition pertains to a precursor composition including a precursor for forming a ferroelectric, wherein the ferroelectric is expressed by a general formula of AB | 2009-07-23 |
20090184291 | LIQUID CRYSTALLINE MEDIUM AND LIQUID CRYSTAL DISPLAY - A dielectrically positive liquid crystalline media comprising:
| 2009-07-23 |
20090184292 | POLYMER COMPOUND AND POLYMER LIGHT EMITTING DEVICE - A polymer compound having a conjugated polymer main chain and at least one side chain selected from the following (a), (b) and (c):
| 2009-07-23 |
20090184293 | PROCESS FOR REFORMING HYDROCARBONS - The invention relates to a process for the production of synthesis gas from a hydrocarbon feedstock, wherein the entire hydrocarbon feed is passed through a radiant furnace, heat exchanger reformer and autothermal reformer in a series arrangement, and in which effluent gas from the autothermal reformer is used as heat source for the reforming reactions occurring in the heat exchange reformer. | 2009-07-23 |
20090184294 | Novel macromolecular antioxidants comprising differing antioxidant moieties: structures, methods of making and using the same - Described are antioxidant macromolecules and methods of making and using same. | 2009-07-23 |
20090184295 | THERMOELECTRIC TRANSPORTATION MATERIAL CONTAINING NITROGEN - A nitrogen-containing thermoelectric material, which has an element composition represented by: | 2009-07-23 |
20090184296 | Method for Manufacturing LiMnPO4 - The main object of the invention is to obtain LiMnPO | 2009-07-23 |
20090184297 | COLOR FILTER INK SET, COLOR FILTER, IMAGE DISPLAY DEVICE, AND ELECTRONIC DEVICE - A color filter ink set is adapted to be used to manufacture a color filter by an inkjet method. The color filter ink set includes a plurality of inks with each of the inks including a colorant and a liquid medium that disperses and/or dissolves the colorant. The inks include a green ink having C. I. Pigment Green 58 and a substance represented by a prescribed chemical formula. A viscosity at 25° C. of the liquid medium of the green ink is lower than a viscosity at 25° C. of the liquid medium of the ink other than the green ink. A difference (η | 2009-07-23 |
20090184298 | PROCESS FOR REPROCESSING A SPENT NUCLEAR FUEL AND OF PREPARING A MIXED URANIUM-PLUTONIUM OXIDE - A process for reprocessing a spent nuclear fuel and for preparing a mixed uranium-plutonium oxide. The process: a) separates the uranium and plutonium from fission products, americium, and curium that are present in an aqueous nitric solution resulting from dissolution of the fuel in nitric acid, the separating including at least one operation of coextracting the uranium and plutonium from the solution by a solvent phase; b) partitions the coextracted uranium and plutonium to a first aqueous phase containing plutonium and uranium, and a second aqueous phase containing uranium but no plutonium; c) purifies the plutonium and uranium that are present in the first aqueous phase; and d) coconverts the plutonium and uranium to a mixed uranium/plutonium oxide. | 2009-07-23 |
20090184299 | ADJUSTABLE LIFTING AND STABILIZATION RESCUE STRUT SYSTEM - A lifting strut and stabilization system includes a lower outer tubular member in slidable engagement with an upper extendable inner tubular member, a mechanism for receiving and supporting a jack on the outer tubular member, a pin for optionally restraining the upper tubular member from further engagement into the lower tubular member, while allowing unrestrained extension of the upper tubular member from within the lower tubular member, and a removably attached jack having a bracket at its upper end incorporating a saddle or half-hole for engaging a strut lift pin located in a corresponding saddle, half-hole or flat bearing surface located on the upper end of the lower tubular member, the lift pin extending through the saddle holes in the upper tubular member, such that upon actuation of the jack, the upper jack bracket engages the lift pin and extends the upper tubular member from within the lower tubular member. | 2009-07-23 |
20090184300 | METAL FENCE POST PROTECTIVE CAP - A metal fence post protective cap made of a flexible plastic material to fit snuggly on top of a T shaped cross section and uniformly spaced studs extending from one surface. The cap is formed with channels to receive the T shaped cross section and the studs with all of the channels being closed at the top. The T shaped cross section receiving channels are completely open at the bottom of the cap but the bottom of the stud receiving channel is partially closed with a retainer portion which engages and outer portion of a stud to resist accidental removal of the cap from the post. The retainer portion merges with a small lead in opening acting as a guide to align studs with the stud receiving channel during installation of the cap on the post. | 2009-07-23 |
20090184301 | PALISADE FENCING - A palisade fence is described comprising support posts and rails extending between the posts, and pales mounted between the rails. The rails define V-shaped apertures for receiving the pales. The pales are additionally secured to the rails by bolts. | 2009-07-23 |
20090184302 | ADJUSTABLE RAILING POST BRACKET - A rail post bracket includes a base with longitudinal members extending up from the base creating a square or rectangular surround for insertion of a rail post support and a rail post. The rail post support is inserted first following which the rail posts can be inserted over the rail post support and removed from the bracket to avoid the need for securing the rail posts into place using grout or concrete. The bracket base is attachable to any solid surface using bolts placed through bolt holes located in the base. Attached to the bottom of the base are adjustable feet for leveling of the rail post bracket. An adjustable mechanism is attached to and partially inset in the front longitudinal member to assist in leveling the rail post. Together these features enable a rail to be leveled in every direction and can be adjusted over time if the mounting surface moves and settles, as well as enabling the easy removal and replacement of rail posts. | 2009-07-23 |
20090184303 | BALUSTRADING - A kit of parts for assembly into a balustrade ( | 2009-07-23 |
20090184304 | PHASE CHANGE MEMORY DEVICE HAVING PLUG-SHAPED PHASE CHANGE LAYERS AND METHOD FOR MANUFACTURING THE SAME - A phase change memory device having plug-shaped phase change layers and a process of manufacturing the same is provided. The device and process includes forming first electrodes on a substrate. An insulation layer is then formed to cover the first electrodes. Plug-shaped phase change layers are then formed in the insulation layer to contact the first electrodes. The plug-shaped phase change layers have a straight-line or an ‘L’ shape when viewed as a cross-section and a horseshoe or a semicircle shape when viewed from above. Finally, bit lines are formed on the insulation layer to contact the phase change layers and additionally serve as second electrodes. The device may further include heaters interposed between the first electrodes and the plug-shaped phase change layers. | 2009-07-23 |
20090184305 | Resistive memory devices and methods of manufacturing the same - A resistive memory device includes a first electrode and a first insulation layer arranged on the first electrode. A portion of the first electrode is exposed through a first hole in the first insulation layer. A first variable resistance layer contacts the exposed portion of the first electrode and extends on the first insulation layer around the first hole. A first switching device electrically connects to the first resistive switching layer. | 2009-07-23 |
20090184306 | PHASE CHANGE MEMORY CELL WITH FINFET AND METHOD THEREFOR - A phase change memory (PCM) cell includes a transistor, a PCM structure, and a heater. The transistor has a first current electrode and a second current electrode in a structure, and a channel region having a first portion along a first sidewall of the structure and having a second portion along a second sidewall of the structure. The second sidewall is opposite the first sidewall. The transistor has a control electrode that has a first portion adjacent to the first sidewall and a second portion adjacent to the second sidewall. The PCM structure exhibits first and second resistive values when in first and second phase states, respectively. The heater is on the structure and produces heat when current flows through the heater for changing the phase state of the phase change structure. | 2009-07-23 |
20090184307 | PHASE CHANGE MEMORY DEVICE AND METHOD OF FABRICATING THE SAME - A phase change memory device and a method of fabricating the same are provided. A phase change material layer of the phase change memory device is formed of germanium (Ge)-antimony (Sb)-Tellurium (Te)-based Ge | 2009-07-23 |
20090184308 | Forming an Intermediate Electrode Between an Ovonic Threshold Switch and a Chalcogenide Memory Element - An intermediate electrode between an ovonic threshold switch and a memory element may be formed in the same pore with the memory element. This may have many advantages including, in some embodiments, reducing leakage. | 2009-07-23 |
20090184309 | PHASE CHANGE MEMORY CELL WITH HEATER AND METHOD THEREFOR - A method for forming a phase change memory cell (PCM) includes forming a heater for the phase change memory and forming a phase change structrure electrically coupled to the heater. The forming a heater includes siliciding a material including silicon to form a silicide structure, wherein the heater includes at least a portion of the silicide structure. The phase change structure exhibits a first resistive value when in a first phase state and exhibits a second resistive value when in a second phase state. The silicide structure produces heat when current flows through the silicide structure for changing the phase state of the phase change structure. | 2009-07-23 |
20090184310 | MEMORY CELL WITH MEMORY ELEMENT CONTACTING AN INVERTED T-SHAPED BOTTOM ELECTRODE - Memory cells are described along with methods for manufacturing. A memory cell described herein includes a bottom electrode comprising a base portion and a pillar portion on the base portion, the pillar portion having a top surface and a width less than that of the base portion. A memory element is on the top surface of the pillar portion and comprises memory material having at least two solid phases. A top electrode is on the memory element. | 2009-07-23 |
20090184311 | Nanowire placement by electrodeposition - Electrodeposition is used to deposit nanowires in a controlled fashion with accurate placement and orientation. A substrate is provided with a mesa having electrically conductive sidewalls. The substrate is immersed in an electroplating solution having a dispersion of nanowires, and metal is electroplated onto the sidewalls of the mesa. During electrodeposition, nanowires are incorporated and partially embedded in the deposited metal film. The nanowires will tend to be parallel with the substrate. Additionally electrodes can be deposited to provide electrical contact with the free ends of the nanowires. In this way, electrical connections can be provided to nanowires in a controlled, reproducible manner. The deposited nanowires can be used in a multitude of devices. | 2009-07-23 |
20090184312 | BENZOFLUORENE COMPOUND AND USE THEREOF - A novel material having high hole-transporting ability and a high glass transition temperature and having long-lasting durability is obtained. | 2009-07-23 |
20090184313 | MATERIALS FOR ORGANIC ELECTROLUMINESCENT DEVICES - The present invention relates to organic electroluminescent devices, in particular blue-emitting devices, in which compounds of the formulae (1) to (4) are used as host material or dopant in the emitting layer and/or as hole-transport material and/or as electron-transport material. | 2009-07-23 |
20090184314 | THIN FILM TRANSISTOR, MATRIX SUBSTRATE, ELECTROPHORESIS DISPLAY DEVICE, AND ELECTRONIC APPARATUS - Provided is a thin film transistor including a substrate, a source electrode and a drain electrode disposed above the substrate so as to oppose each other, an organic semiconductor film disposed between the source electrode and the drain electrode to generate a channel region, and a gate electrode disposed opposite the organic semiconductor film via a gate insulating film. The gate electrode includes an aperture in the channel region. | 2009-07-23 |
20090184315 | THIN FILM TRANSISTOR ARRAY SUBSTRATE HAVING IMPROVED ELECTRICAL CHARACTERISTICS AND METHOD OF MANUFACTURING THE SAME - A thin film transistor array substrate, which can have high mobility of charge and can achieve uniform electrical characteristics for wide display devices, and a method of manufacturing the thin film transistor array substrate, are provided. The thin film transistor array substrate includes an oxide semiconductor layer having a channel and formed on an insulating substrate, a gate electrode overlapping the oxide semiconductor layer, a gate insulating film disposed between the oxide semiconductor layer and the gate electrode, and a passivation film formed on the oxide semiconductor layer and the gate electrode. At least one of the gate insulating film and the passivation film contains fluorine-containing silicon. | 2009-07-23 |
20090184316 | Method to extract gate to source/drain and overlap capacitances and test key structure therefor - A method to extract gate to source/drain and overlap capacitances is disclosed. A first capacitance of a first test key having a reference structure and a second capacitance of a second test key having a novel structure are measured. The second test key may comprise at least a gate formed on an insulation structure, at least a contact formed on the insulation structure aside, and a metal layer formed on the contact. Another embodiment of the second test key may comprise at least a gate formed on the semiconductor substrate, a contact formed aside, and a metal layer formed on the contact. Further another embodiment uses a test key comprising at least an elongated gate and an elongated doping region aside, and only one or a few contacts are formed on an end portion of the elongated doping region. | 2009-07-23 |
20090184317 | ARRAY OF MUTUALLY INSULATED GEIGER-MODE AVALANCHE PHOTODIODES, AND CORRESPONDING MANUFACTURING PROCESS - An embodiment of an array of Geiger-mode avalanche photodiodes, wherein each photodiode is formed by a body of semiconductor material, having a first conductivity type, housing a first cathode region, of the second conductivity type, and facing a surface of the body, an anode region, having the first conductivity type and a higher doping level than the body, extending inside the body, and facing the surface laterally to the first cathode region and at a distance therefrom, and an insulation region extending through the body and insulating an active area from the rest of the body, the active area housing the first cathode region and the anode region. The insulation region is formed by a mirror region of metal material, a channel-stopper region having the second conductivity type, surrounding the mirror region, and a coating region, of dielectric material, arranged between the mirror region and the channel-stopper region. | 2009-07-23 |
20090184318 | THIN FILM TRANSISTOR ARRAY PANEL, DISPLAY DEVICE INCLUDING THE SAME, AND METHOD THEREOF - A thin film transistor (“TFT”) array panel according to an exemplary embodiment of the present invention includes a substrate, a first storage electrode formed on the substrate, a first TFT formed on the substrate and separated from the first storage electrode, a first insulating layer formed on the first storage electrode and the first TFT and having a first opening disposed on the first storage electrode, a pixel electrode connected to the first TFT and overlapping the first storage electrode in the first opening, and a second insulating layer disposed between the first storage electrode and the pixel electrode in the first opening, wherein at least a portion of the boundary of the pixel electrode overlaps the first storage electrode and is disposed in the first opening. Accordingly, storage appropriate capacitance is ensured and a reduction of the aperture ratio may be decreased. | 2009-07-23 |
20090184319 | DISPLAY SUBSTRATE AND A METHOD OF MANUFACTURING THE DISPLAY SUBSTRATE - A method of manufacturing a display substrate is described. In the method, a gate line and a gate electrode are formed on a base substrate. A source metal layer is formed on the base substrate having the gate line and the gate electrode. A data line, a source electrode and a drain electrode are formed by etching the source metal layer by using an etching gas. An additive gas is provided to the base substrate having the drain electrode so that the additive gas reacts with an etching component of the etching gas to remove a by-product formed at an exposed portion of the data line, the source electrode and drain electrode. Thus, corrosion of the fine pattern due to an etching gas may be prevented and/or reduced. | 2009-07-23 |
20090184320 | Method of manufacturing an image TFT array for an indirect X-ray sensor and structure thereof - In the image TFT array structure, at least one first line, a lower electrode, a pad electrode, a common electrode and a first electrode connected with the first line are defined simultaneously by etching a first conductive layer. At least one second line intersecting the first line, an upper electrode corresponding to the lower electrode, a second electrode connected with the second line and a third electrode connected with the upper electrode are defined simultaneously by etching a second conductive layer applied to cover the substrate and above the first conductive layer. The lower electrode and the upper electrode of the storage capacitor have an approximately same large area. | 2009-07-23 |
20090184321 | MICROCRYSTALLINE SILICON THIN FILM TRANSISTOR AND METHOD FOR MANUFACTURING THE SAME - This invention provides a top-gate microcrystalline thin film transistor and a method for manufacturing the same. An inversion layer channel is formed in a top interface of a microcrystalline active layer, and being separated from an incubation layer in a bottom interface of the microcrystalline active layer. The inversion layer channel is formed in the crystallized layer of the top interface of the microcrystalline active layer. As such, the present microcrystalline thin film transistor has better electrical performance and reliability. | 2009-07-23 |
20090184322 | ELECTROCONDUCTIVE FILM-FORMING METHOD, A THIN FILM TRANSISTOR, A THIN FILM TRANSISTOR-PROVIDED PANEL AND A THIN FILM TRANSISTOR-PRODUCING METHOD - An electroconductive film having high adhesion and a low resistivity is formed. An electroconductive film composed mainly of copper and containing an addition metal such as Ti is formed by sputtering a target composed mainly of copper in a vacuum atmosphere into which a nitriding gas is introduced. Such an electroconductive film has high adhesion to a silicon layer and a substrate, and is hardly peeled from the substrate. Further, since the electroconductive film has a low resistivity and a low contact resistance to a transparent electroconductive film, the electric characteristics do not degrade even when it is used as an electrode film. The electroconductive film formed by the present invention is suitable particularly as a barrier film for an electrode of a TFT or a semiconductor element. | 2009-07-23 |
20090184323 | THIN FILM TRANSISTOR ARRAY PANEL AND METHOD FOR MANUFACTURING THE SAME - The present invention relates to a thin film transistor array panel and a method for manufacturing the same. A thin film transistor array panel according to the present invention includes a substrate, a light blocking member formed on the substrate and including a first furrow and a receiving portion, a gate line disposed on the first furrow, a semiconductor layer disposed on the gate line, a source electrode and a drain electrode formed on the semiconductor layer, and a pixel electrode connected to the drain electrode. The source electrode is an extension of the data line. | 2009-07-23 |
20090184324 | THIN FILM TRANSISTOR ARRAY PANEL AND METHOD FOR MANUFACTURING THE SAME - The present invention relates to a thin film transistor array panel and a manufacturing method thereof. The thin film transistor array panel according to the present invention includes a substrate, a light blocking member formed on the substrate, a gate line disposed on the light blocking member. The gate line and the light blocking member define a closed region A color filter is formed in the closed region and contacts the side surface of the gate line. A gate insulating layer is formed on the gate line and the color filter, a data line and a drain electrode are formed on the gate insulating layer, and a pixel electrode is connected to the drain electrode. | 2009-07-23 |
20090184325 | METHOD OF PLANARIZING SUBSTRATE, ARRAY SUBSTRATE AND METHOD OF MANUFACTURING ARRAY SUBSTRATE USING THE SAME - A method of planarizing a substrate. An organic layer is formed on a base substrate to cover a metal line formed on the base substrate. A portion of the organic layer is removed to form a pre-planarization layer exposing the metal layer, so that a surface of the base substrate having the metal line is planarized. The pre-planarization layer is cured to flow toward a side surface of the metal line to form a planarization layer making contact with the side surface of the metal line. Therefore, a stepped portion between the base substrate and the metal line can be minimized or substantially eliminated, thereby increasing the surface uniformity of a subsequent layer, thereby improving the reliability of the manufacturing process. | 2009-07-23 |
20090184326 | DISPLAY SUBSTRATE, METHOD FOR MANUFACTURING THE DISPLAY SUBSTRATE AND DISPLAY APPARATUS HAVING THE DISPLAY SUBSTRATE - A display substrate includes a base substrate, a gate line, a gate insulation layer, a data line, a thin-film transistor (TFT) and a pixel electrode. The gate line is extended in a first direction on the base substrate. The gate insulation layer is formed on the base substrate to cover the gate line. The data line is extended in a second direction and intersects the gate line at an intersecting portion. At the intersecting portion, the data line is separated from the gate line by an air gap. In another embodiment, the data line also includes at least one etching hole extending to the air gap. The TFT is electrically connected to the data and the gate lines. The pixel electrode is electrically connected to the TFT. | 2009-07-23 |
20090184327 | METHOD FOR PRODUCING SILICON CARBIDE SINGLE CRYSTAL - A method for the production of an SiC single crystal includes the steps of growing a first SiC single crystal in a first direction of growth on a first seed crystal formed of an SiC single crystal, disposing the first SiC single crystal grown on the first seed crystal in a direction parallel or oblique to the first direction of growth and cutting the disposed first SiC single crystal in a direction of a major axis in a cross section perpendicular to the first direction of growth to obtain a second seed crystal, using the second seed crystal to grow thereon in a second direction of growth a second SiC single crystal to a thickness greater than a length of the major axis in the cross section, disposing the second SiC single crystal grown on the second seed crystal in a direction parallel or oblique to the second direction of growth and cutting the disposed second SiC single crystal in a direction of a major axis in a cross section perpendicular to the second direction of growth to obtain a third seed crystal, using the third seed crystal to grow thereon a third SiC single crystal, and cutting the third SiC single crystal grown on the third seed crystal in such a manner as to expose a {0001} crystal face, thereby obtaining an SiC single crystal. The method enables the crystal to be enlarged efficiently without impairing crystallinity. | 2009-07-23 |
20090184328 | ELECTRICAL SWITCHING DEVICE AND METHOD OF EMBEDDING CATALYTIC MATERIAL IN A DIAMOND SUBSTRATE - An electrical switching device ( | 2009-07-23 |
20090184329 | Positive electrode for semiconductor light-emitting device - An object of the present invention is to provide a transparent positive electrode for use in a face-up-type chip which can emit intense light even using a low drive voltage. | 2009-07-23 |
20090184330 | LIGHT-EMITTING MODULE INCLUDING SUBSTRATE WITH SPACE FORMED AROUND RIM - A light-emitting module includes a light-emitting element, a substrate on which are mounted the light-emitting element and heat dissipater. The substrate and heat dissipater are connected together by one mounting member and a space is formed around the rim of the substrate. | 2009-07-23 |
20090184331 | PHOTODETECTION SEMICONDUCTOR DEVICE, PHOTODETECTOR, AND IMAGE DISPLAY DEVICE - Shields that transmit light to be detected and have conductivity are disposed on light receiving surfaces of photodiodes ( | 2009-07-23 |
20090184332 | Package structure module with high density electrical connections and method for packaging the same - A package structure module with high density electrical connections includes a drive IC structure, an LED array structure, and a plurality of conductive structures. The drive IC structure has a plurality of first open grooves formed on a lateral wall thereof. The LED array structure has a plurality of second open grooves formed on a lateral wall thereof to respectively face the first open grooves. Each conductive structure traverse the corresponding first open groove and the corresponding second open groove in order to electrically connect between the drive IC structure and the LED array structure. | 2009-07-23 |
20090184333 | LIGHT EMITTING DIODE DEVICE - An LED device includes a substrate, a plurality of LEDs, a first light pervious layer, a reflective plate, and a plurality of phosphor particles contained in the first light pervious layer. The LEDs are electrically mounted on the substrate and configured for emitting light of a first wavelength. The reflective plate is mounted on the substrate for directing the light of the first wavelength to transmit through the first light pervious layer. The phosphor particles are configured for converting the light of the first wavelength into light of a second wavelength. A distribution of the phosphor particles in the first light pervious layer gradually decreases from a center to a periphery thereof. | 2009-07-23 |
20090184334 | PHOTONIC CRYSTAL LIGHT EMITTING DEVICE AND MANUFACTURING METHOD OF THE SAME - There is provided a photonic crystal light emitting device including: a light emitting structure including first and second conductivity type semiconductor layers and an active layer interposed therebetween; a transparent electrode layer formed on the second conductivity type semiconductor layer, the transparent electrode layer having a plurality of holes arranged with a predetermined size and period so as to form a photonic band gap for light emitted from the active layer, whereby the transparent electrode layer includes a photonic crystal structure; and first and second electrode electrically connected to the first conductivity type semiconductor layer and the transparent electrode layer, respectively. The photonic crystal light emitting device has a transparent electrode layer formed of a photonic crystal structure defined by minute holes, thereby improved in light extraction efficiency. | 2009-07-23 |
20090184335 | OPTICAL SEMICONDUCTOR DEVICE - An optical semiconductor device includes: a package having a bottom portion and a sidewall portion; a semiconductor chip having an optical element formed on one surface thereof and having an opposite surface to the one surface fixed to the bottom portion of the package; a transparent member fixed to the semiconductor chip so as to cover the optical element; and a sealing resin filling a space between the package and the semiconductor chip. The sidewall portion has in an upper part thereof an overhang portion that projects toward inside of the package. The transparent member is exposed from a window portion formed by the overhang portion. | 2009-07-23 |
20090184336 | SEMICONDUCTOR LIGHT EMITTING DEVICE AND MANUFACTURING METHOD THEREFOR - A semiconductor light emitting device includes: a semiconductor layer; an insulating film on the semiconductor layer and having an opening; a multilayer adhesive layer on the insulating film; and a Pd electrode in contact with the semiconductor layer through the opening and in contact with the multilayer adhesive layer. The multilayer adhesive layer includes an Au layer at the top and an alloy of Au and Pd at the interface between the Au layer and the Pd electrode. | 2009-07-23 |
20090184337 | Light-Emitting Diode, Package Structure Thereof and Manufacturing Method for the Same - A light-emitting diode includes a sapphire substrate, an n-type semiconductor, a light-emitting layer, a p-type semiconductor layer, an anode and a conductive material. The n-type semiconductor layer is formed on the sapphire substrate and has a side surface, a center section and an edge around the center portion. The light-emitting layer is formed on the n-type semiconductor layer. The p-type semiconductor layer is formed on the light-emitting layer. The anode is formed on the p-type semiconductor layer. The conductive material is formed on the bottom surface of the sapphire substrate and is in contact with the n-type semiconductor layer. | 2009-07-23 |
20090184338 | SEMICONDUCTOR DEVICE - A semiconductor device having the present high withstand voltage power device IGBT has at a back surface a p collector layer with boron injected in an amount of approximately 3×10 | 2009-07-23 |
20090184339 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes: an insulating film provided on a back surface of a semiconductor substrate; a plurality of isolation regions provided to reach the insulating film from a main surface of the semiconductor substrate; at least a first semiconductor layer and a second semiconductor layer which are electrically insulated from each other by the isolation regions in the semiconductor substrate; a first voltage applied terminal electrically connected to a front surface of the first semiconductor layer; a second voltage applied terminal electrically connected to a front surface of the second semiconductor layer; a selector circuit receiving voltages from the first voltage applied terminal and the second voltage applied terminal, and supplying an output in accordance with a combination of the voltages; and a conductive layer provided so as to contact with the insulating film provided to the back side of the semiconductor substrate. | 2009-07-23 |
20090184340 | SEMICONDUCTOR DEVICE AND METHOD OF PRODUCING THE SAME - A semiconductor device is provided in which a semiconductor substrate can be prevented from being broken while elements can be prevented from being destroyed by a snap-back phenomenon. After an MOS gate structure is formed in a front surface of an FZ wafer, a rear surface of the FZ wafer is ground. Then, the ground surface is irradiated with protons and irradiated with two kinds of laser beams different in wavelength simultaneously to thereby form an N | 2009-07-23 |
20090184341 | Elimination of STI recess and facet growth in embedded silicon-germanium (eSiGe) module - A method (and semiconductor device) of fabricating a semiconductor device eliminates shallow trench isolation (STI) recess in embedded SiGe p-type field effect transistor (pFET) structures. This increases device performance by improving isolation and decreasing leakage current caused by SiGe facet growth and silicide encroachment at the STI. A mask is selectively formed over the STI and adjacent nFET regions to protect them during formation (e.g., reactive ion etching (RIE)) of the embedded source/drain (S/D) regions of the pFET. The mask also extends over the STI edge by a predetermined distance to cover a portion of the embedded S/D region disposed between the STI and gate structure. This helps protect or isolate the STI region during SiGe layer formation in the defined embedded S/D regions. | 2009-07-23 |
20090184342 | METHOD FOR ENHANCING GROWTH OF SEMI-POLAR (AL,IN,GA,B)N VIA METALORGANIC CHEMICAL VAPOR DEPOSITION - A method for growing a semi-polar nitride semiconductor thin film via metalorganic chemical vapor deposition (MOCVD) on a substrate, wherein a nitride nucleation or buffer layer is grown on the substrate prior to the growth of the semi-polar nitride semiconductor thin film. | 2009-07-23 |
20090184343 | ISOLATION STRUCTURE, NON-VOLATILE MEMORY HAVING THE SAME, AND METHOD OF FABRICATING THE SAME - A method of forming an isolation structure, comprising: (a) providing a base having a recess; (b) forming a stop layer on the base and in the recess; (c) forming a dielectric material on the stop layer so as to allow the rest of the recess to be filled with the dielectric material; (d) removing the dielectric material over the base by performing a chemical mechanical polishing (CMP) process until a part of the stop layer is exposed so as to form a dielectric layer in the recess; and (e) removing a part of the stop layer, wherein the another part of the stop layer and the dielectric layer filled in the recess constitute the isolation structure. | 2009-07-23 |
20090184344 | Solid-state image capturing element, method for manufacturing the solid-state image capturing element, and electronic information device - A solid-state image capturing element according to the present invention is provided, in which one or a plurality of light receiving sections for photoelectrically converting an incident light to generate a signal charge is provided on a surface of a semiconductor area or a surface of a semiconductor substrate and a peripheral circuit with a transistor is provided, where a reflection preventing film provided above the light receiving sections and a gate sidewall film of the transistor are formed with a common nitride film that is formed simultaneously. | 2009-07-23 |
20090184345 | CONTACTS FOR CMOS IMAGERS AND METHOD OF FORMATION - Low leakage contacts on leakage sensitive areas of a CMOS imager, such as a floating diffusion region or a photodiode, are disclosed. At least one low leakage polysilicon contact is provided over a leakage sensitive area of a CMOS imager. The polysilicon contact comprises a polysilicon region in direct contact with the area of interest (the leakage sensitive area) and a metal region located over the polysilicon region. The polysilicon contact provides an improved ohmic contact with less leakage into the substrate. The polysilicon contact may be provided with other conventional metal contacts, which are employed in areas of the CMOS imager that do not require low leakage. | 2009-07-23 |
20090184346 | Nonvolatile memory and three-state FETs using cladded quantum dot gate structure - The present invention discloses structures and method of fabricating cladded quantum dot gate nonvolatile memory and three-state field-effect transistor devices that can be scaled down to sub-22 nm dimensions and embedded along side with other functional circuits. Another innovation is the design of transport channel, which comprises an asymmetric coupled well structure comprising two or more wells. This structure enhances the retention time in nonvolatile memory by increasing the effective separation between channel charge and the quantum dots located in the floating gate. The cladded quantum dot gate FETs can be designed in Si, InGaAs—InP and other material systems. The 3-state FET devices form the basis of novel digital circuits using multiple valued logic and advanced analog circuits. One or more layers of SiO | 2009-07-23 |
20090184347 | COATING LIQUID FOR GATE INSULATING FILM, GATE INSULATING FILM AND ORGANIC TRANSISTOR - To provide a coating fluid for a gate insulating film, which can be baked at a low temperature of at most 180° C.; a gate insulating film having excellent solvent resistance and further having good characteristics in e.g. specific resistance or semiconductor mobility; and an organic transistor employing the gate insulating film. | 2009-07-23 |
20090184348 | Slim Spacer Implementation to Improve Drive Current - Slim spacers are implemented in transistor fabrication. More particularly, wide sidewall spacers are initially formed and used to guide dopants into source/drain regions in a semiconductor substrate. The wide sidewall spacers are then removed and slim sidewall spacers are formed alongside a gate stack of the transistor. The slim spacers facilitate transferring stress from an overlying pre metal dielectric (PMD) liner to a channel of the transistor, and also facilitate reducing a resistance in the transistor by allowing silicide regions to be formed closer to the channel. This mitigates yield loss by facilitating predictable or otherwise desirable behavior of the transistor. | 2009-07-23 |
20090184349 | 3D BACKSIDE ILLUMINATED IMAGE SENSOR WITH MULTIPLEXED PIXEL STRUCTURE - A three-dimensional pixel array, a method of manufacturing a pixel array and an imager including the three-dimensional pixel array. The three-dimensional array includes multiple groups of pixels, each group of pixels including a first layer and a second layer. The first layer includes multiple photosensitive elements, one per pixel in the group, at least one floating diffusion region connected to each photosensitive element in the group via at least one respective transfer gate per pixel and multiple transfer gate lines, at least two transfer gate lines connected to each respective transfer gate in each row of pixels. The second layer includes at least a rest transistor per group and a source follower transistor coupled to the shared floating diffusion in the first layer. | 2009-07-23 |
20090184350 | Non-volatile semiconductor memory device - A non-volatile semiconductor memory device having a memory cell in which operating potentials are few and the scale of the peripheral circuitry is reduced includes a select transistor having a source/drain on both sides of a channel of a semiconductor substrate and having a gate electrode disposed on the channel via a thick gate insulating film; an element isolation region formed on the semiconductor substrate in an area adjacent to the select transistor; an antifuse adjacent to the element isolation region, having a lower electrode formed on the semiconductor substrate and having an upper electrode disposed on the semiconductor substrate in an area between the element isolation region and lower electrode via a thin gate insulating film; and a connection contact electrically connecting the source and upper electrode and contacting the source and the upper electrode. | 2009-07-23 |
20090184351 | SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor substrate, an active region formed in the semiconductor substrate and extending in a first direction, the active region including a transistor sub-region and a capacitor sub-region, a first trench extending around the transistor sub-region, an isolation layer disposed in the first trench, a second trench extending around the capacitor sub-region, a first transistor including a first insulating layer disposed on the transistor sub-region, the first transistor including a first conductive layer disposed on the first insulating layer, and a first capacitor including a second insulating layer extending over the capacitor sub-region and a sidewall of the second trench, the first capacitor including a second conductive layer disposed on the second insulating layer, the active region having an end portion in the first direction opposite to the transistor sub-region and extending across the first capacitor. | 2009-07-23 |
20090184352 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - A semiconductor device includes: a semiconductor substrate; a lateral MOSFET formed in an upper portion of a first region of the semiconductor substrate; a vertical MOSFET formed in a second region of the semiconductor substrate; a backside electrode formed on a lower surface of the semiconductor substrate and connected to a lower region of source/drain regions of the vertical MOSFET; and a connecting member penetrating the semiconductor substrate and connecting one of source/drain regions of the lateral MOSFET to the backside electrode. | 2009-07-23 |
20090184353 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - To prevent two contacts that have different heights, share at least one interlayer insulating film and are disposed close to each other from being short-circuited to each other due to misalignment thereof, a semiconductor device according to the invention has a recess in an interlayer insulating film in which a first contact hiving a lower height, the recess being formed by the upper surface of the first contact, and a silicon nitride sidewall is formed in the recess to extend from the upper surface of the first contact and along the side surface of the recess. | 2009-07-23 |
20090184354 | SEMICONDUCTOR DEVICE COMPRISING CAPACITOR AND METHOD OF FABRICATING THE SAME - A semiconductor device, having a memory cell region and a peripheral circuit region, includes an insulating film, having an upper surface, formed on a major surface of a semiconductor substrate to extend from the memory cell region to the peripheral circuit region. A capacitor lower electrode assembly is formed in the memory cell region to upwardly extend to substantially the same height as the upper surface of the insulating film on the major surface of the semiconductor substrate. Additionally, the lower electrode assembly includes first and second lower electrodes that are adjacent through the insulating film. A capacitor upper electrode is formed on the capacitor lower electrode through a dielectric film, to extend onto the upper surface of the insulating film. The capacitor lower electrode includes a capacitor lower electrode part having a top surface and a bottom surface. A semiconductor device organized as just described, permits implementation having a high density of integration while ensuring the capacitor exhibits high reliability and a constant capacitance. | 2009-07-23 |
20090184355 | INTEGRATED CIRCUIT ARRANGEMENT WITH CAPACITOR AND FABRICATION METHOD - An integrated circuit arrangement contains an insulating region, which is part of a planar insulating layer, and a capacitor which contains: near and far electrode regions near and remote from the insulating region and a dielectric region. The capacitor and an active component are on the same side of the insulating layer, and the near electrode region and an active region of the component are planar and parallel to the insulating layer. The near electrode region is monocrystalline and contains multiple webs. | 2009-07-23 |
20090184356 | DEEP TRENCH CAPACITOR IN A SOI SUBSTRATE HAVING A LATERALLY PROTRUDING BURIED STRAP - A deep trench is formed to a depth midway into a buried insulator layer of a semiconductor-on-insulator (SOI) substrate. A top semiconductor layer is laterally recessed by an isotropic etch that is selective to the buried insulator layer. The deep trench is then etched below a bottom surface of the buried insulator layer. Ion implantation is performed at an angle into the deep trench to dope the sidewalls of the deep trench beneath the buried insulator layer, while the laterally recessed sidewalls of the top semiconductor layer are not implanted with dopant ions. A node dielectric and trench fill materials are deposited into the deep trench. A buried strap has an upper buried strap sidewall that is offset from a lower buried strap sidewall and a deep trench sidewall. | 2009-07-23 |
20090184357 | SOI BASED INTEGRATED CIRCUIT AND METHOD FOR MANUFACTURING - A SOI based integrated circuit and method for manufacturing a SOI based integrated circuit is disclosed. One embodiment provides an integrated circuit having a silicon-on-insulator carrier including a substrate, a buried insulating layer on the substrate and a semiconductor layer on the buried insulating layer. A trench extends at least through the semiconductor layer and into the buried insulating layer. A conductive region is formed in the buried insulating layer, wherein the conductive region partly surrounds the trench and is configured to interconnect the semiconductor layer and the substrate. | 2009-07-23 |
20090184358 | METHOD FOR FABRICATING A SEMICONDUCTOR DEVICE AND THE SEMICONDUCTOR DEVICE MADE THEREOF - A method for fabricating a semiconductor device and the device made thereof are disclosed. In one aspect, the method includes providing a substrate comprising a semiconductor material. The method further includes patterning at least one fin in the substrate, the fin comprising a top surface, at least one sidewall surface, and at least one corner. A supersaturation of point defects is created in the at least one fin. The at least one fin is annealed and then cooled down such that semiconductor atoms of the semiconductor material migrate via the point defects. | 2009-07-23 |
20090184359 | Split-gate non-volatile memory devices having nitride tunneling layers - A memory device having a cell stack and a select gate formed adjacent to the cell stack. The cell stack includes a first trap-free-nitride layer formed on a channel region of a substrate, a second nitride layer formed on the first nitride layer, an oxide layer formed on the second nitride layer, a control gate formed on the high-K oxide layer, and a poly spacer as the select gate formed adjacent to the control gate. | 2009-07-23 |
20090184360 | Non-volatile memory device and method of fabricating the same - Provided are a non-volatile memory device that may expand to a stacked structure and may be more easily highly integrated and an economical method of fabricating the non-volatile memory device. The non-volatile memory device may include at least one semiconductor column. At least one first control gate electrode may be arranged on a first side of the at least one semiconductor column. At least one second control gate electrode may be arranged on a second side of the at least one semiconductor column. A first charge storage layer may be between the at least one first control gate electrode and the at least one semiconductor column. A second charge storage layer may be between the at least one second control gate electrode and the at least one semiconductor column. | 2009-07-23 |
20090184361 | LATERAL CHARGE STORAGE REGION FORMATION FOR SEMICONDUCTOR WORDLINE - Devices and methods for forming charge storage regions are disclosed. In one embodiment, a semiconductor device comprises a semiconductor layer having a trench, charge storage layers formed at both side surfaces of the trench, a wordline buried in the trench in contact with the charge storage layers, and source-drain regions formed in the semiconductor layer at both sides of the trench. | 2009-07-23 |
20090184362 | Flash memory cell string - The present invention relates to a flash memory cell string. The flash memory cell string includes a plurality of cell devices and switching devices connected to ends of the cell devices. Each of the cell devices includes a semiconductor substrate, and a transmissive insulating layer, a charge storage node, a control insulating layer and a control electrode sequentially formed on the semiconductor substrate. In the flash memory cell string, a buried insulating layer is provided on the semiconductor substrate between the cell device and an adjacent cell device, thus enabling an inversion layer, which performs the functions of source/drain, to be easily formed. | 2009-07-23 |
20090184363 | SILICON ON INSULATOR DEVICE AND METHOD FOR FABRICATING THE SAME - An SOI device includes an SOI substrate having a structure in which a first buried oxide layer and a silicon layer are stacked in turn over a semiconductor substrate. A gate is formed over the silicon layer of the SOI substrate. A second buried oxide layer is formed at both sides of the gate in a lower portion of the silicon layer so that a lower end portion of the second buried oxide layer is in contact with the first buried oxide layer. A junction region is then formed in the portion of the silicon layer above the second buried oxide layer so that the lower end portion of the junction region is in contact with the second buried oxide layer. | 2009-07-23 |
20090184364 | NON-VOLATILE SEMICONDUCTOR STORAGE DEVICE AND METHOD OF MANUFACTURING THE SAME - A non-volatile semiconductor storage device includes device regions and device isolation regions that are formed on a semiconductor substrate, with a first direction defined as their longitudinal direction. The non-volatile semiconductor storage device also includes memory cells having a cell transistor formed on the device regions and a selection transistor to select the cell transistor. Each of gate electrode wires provides a common connection between a plurality of memory cells arranged in a line in a second direction, and is arranged to extend in the second direction. Each of the gate electrode wires has a first width on the device regions and a second width larger than the first width on the device isolation regions. | 2009-07-23 |
20090184365 | SEMICONDUCTOR MEMORY DEVICE USING SILICON NITRIDE FILM AS CHARGE STORAGE LAYER OF STORAGE TRANSISTOR AND MANUFACTURING METHOD THEREOF - A semiconductor memory device includes a tunnel insulating film, charge storage layer, block insulating film and control gate electrode stacked and formed on the surface of a semiconductor substrate. The charge storage layer is formed of an insulating film containing nitrogen. A dopant that reduces the trap density of charges moved in and out of an internal portion of the charge storage layer via the tunnel insulating film is doped into a region of the charge storage layer on the interface side with the tunnel insulating film or a dopant is doped into the above region with higher concentration in comparison with that of another region. | 2009-07-23 |
20090184366 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor memory device has a substrate having a semiconductor layer, an n-type semiconductor region formed beneath a main surface of the semiconductor layer, a plurality of cell gates being aligned at a space from each other and including a gate insulating film formed on the main surface of the semiconductor layer, a charge storage layer formed on the gate insulating film, a charge block layer formed on the charge storage layer and a control gate electrode formed on the charge block layer, an insulating film between cells formed on the main surface of the semiconductor layer between the cell gates, and a carbon accumulation region formed in the insulating film between the cells and has a maximum concentration of a carbon element in a region within 2 nm from an interface between the semiconductor layer and the insulating film between the cells. | 2009-07-23 |
20090184367 | SEMICONDUCTOR DEVICE MANUFACTURING METHOD, AND SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device in which the formation of buried wiring is facilitated includes: forming columnar patterns, which are arranged in a two-dimensional array, and bridge patterns, which connect the columnar patterns in a column direction, on a main surface of a silicon substrate; injecting an impurity in a surface portion of each of the columnar patterns and bridge patterns and in surface portions of the silicon substrate, thereby forming impurity injection layers; forming a side wall on sides of the columnar patterns and bridge patterns; removing the impurity injection layer, which has been formed in the silicon substrate, with the exception of the impurity injection layer covered by the bottom portions of the side walls; removing the side walls by etch-back; and thermally oxidizing the surface portion of the bridge patterns and then etching away the same. Buried wiring extending in the column direction of the columnar patterns is formed within the silicon substrate. | 2009-07-23 |
20090184368 | IC CHIP - An IC chip, including a switch LDMOS device and an analog LDMOS device, is configured on a substrate having a first conductive type. Components of the two LDMOS devices respectively include two gate conductive layers configured on two first active regions of the substrate. A common source contact region having a second conductive type is configured in a second active region, which is configured between the two first active regions. An isolation structure is included for isolating the second active region and the first active regions. The isolation structure between the first active regions and the second active region has a length “A” extending along a longitudinal direction of a channel under each gate conductive layer, and each gate conductive layer on each first active region has a length “L” extending along the longitudinal direction of the channel, the two LDMOS devices have different A/L values. | 2009-07-23 |
20090184369 | FINFET DEVICES AND METHODS FOR MANUFACTURING THE SAME - Disclosed herein is a tunneling fin field effect transistor comprising a fin disposed on a box layer disposed in a wafer; the wafer comprising a silicon substrate and a buried oxide layer. The fin comprises a silicide body that comprises a first silicide region and a second silicide region and forms a short between N and P doped regions. The silicide body is disposed on a surface of the buried oxide layer. A tunneling device disposed between the first silicide region and the second silicide region; the tunneling device comprising a first P-N junction. A gate electrode is further disposed around the fin; the gate electrode comprising a second P-N junction, and a third silicide region; the third silicide region forming a short between N and P doped regions in the gate electrode. | 2009-07-23 |
20090184370 | LATERAL SOI SEMICONDUCTOR DEVICES AND MANUFACTURING METHOD THEREOF | 2009-07-23 |
20090184371 | SEMICONDUCTOR DEVICE WITH AN SOI STRUCTURE - A first element includes a first diffused layer which is formed in the element forming film so as to reach an insulating film, a second diffused layer which is formed in the element forming film so as not to reach the insulating film, and a first body region formed between the first and the second diffused layers. A second element, which is formed on the element forming film so as to be adjacent to the first element, includes the second diffused layer, a third diffused layer which is formed in the element forming film so as to reach the insulating film, and a second body region formed between the second and the third diffused layers. A connection part connects the body region of the first element and the body region of the second element to each other electrically. | 2009-07-23 |
20090184372 | SOI SEMICONDUCTOR COMPONENTS AND METHODS FOR THEIR FABRICATION - SOI semiconductor components and methods for their fabrication are provided wherein the SOI semiconductor components include an MOS transistor in the supporting semiconductor substrate. In accordance with one embodiment the component comprises a semiconductor on insulator (SOI) substrate having a first semiconductor layer, a layer of insulator on the first semiconductor layer, and a second semiconductor layer overlying the layer of insulator. The component includes source and drain regions of a first conductivity type and first doping concentration in the first semiconductor layer. A channel region of a second conductivity type is defined between the source and drain regions. A gate insulator and gate electrode overlie the channel region. A drift region of the first conductivity type is located between the channel region and the drain region, the drift region having a second doping concentration less than the first doping concentration of the first conductivity determining dopant. | 2009-07-23 |
20090184373 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE - A semiconductor device is provided which has a semiconductor substrate. An active cell area having at least one active cell is formed in the semiconductor substrate, wherein at least sections of the active cell area are surrounded by an edge termination region. An integrated gate runner structure is arranged at least partially in the edge termination region and has at least one low electrical resistance portion and at least one high electrical resistance portion which are electrically connected in series with each other. | 2009-07-23 |
20090184374 | ANISOTROPIC STRESS GENERATION BY STRESS-GENERATING LINERS HAVING A SUBLITHOGRAPHIC WIDTH - A protruding structure having a linear edge is formed on a substrate. The protruding structure may be a gate line of a field effect transistor. A stress-generating liner is deposited on the substrate. A non-photosensitive self-assembling block copolymer layer containing at least two immiscible polymeric block components is deposited on the stress-generating liner, and is annealed to allow phase separation of immiscible components. The polymeric resist is developed to remove at least one of the at least two polymeric block components, which formed a pattern of nested lines due to the linear edge of the protruding structure. Linear nanoscale stripes are formed in the polymeric resist which is self-aligning and self-assembled. The stress-generating layer is patterned into linear stress-generating stripes having a sublithographic width. The linear stress-generating stripes provide a predominantly uniaxial stress along their lengthwise direction, providing an anisotropic stress to an underlying semiconductor device. | 2009-07-23 |
20090184375 | METHOD FOR FORMING STRAINED CHANNEL PMOS DEVICES AND INTEGRATED CIRCUITS THEREFROM - An integrated circuit (IC) includes a plurality of compressively strained PMOS transistors. The IC includes a substrate having a semiconductor surface. A gate stack is formed in or on the semiconductor surface and includes a gate electrode on a gate dielectric, wherein a channel region is located in the semiconductor surface below the gate dielectric. A source and a drain region is opposing sides of the gate stack. At least one compressive strain inducing region including at least one specie selected from Ge, Sn and Pb is located in at least a portion of the source and drain regions of the PMOS transistors, wherein the strain inducing region provides ≦10 | 2009-07-23 |
20090184376 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A dual work function semiconductor device and method for fabricating the same are disclosed. In one aspect, a device includes a first and second transistor on a first and second substrate region. The first and second transistors include a first gate stack having a first work function and a second gate stack having a second work function respectively. The first and second gate stack each include a host dielectric, a gate electrode comprising a metal layer, and a second dielectric capping layer therebetween. The second gate stack further has a first dielectric capping layer between the host dielectric and metal layer. The metal layer is selected to determine the first work function. The first dielectric capping layer is selected to determine the second work function. | 2009-07-23 |
20090184377 | Semiconductor devices and fabrication methods thereof - Semiconductor devices and methods of fabricating semiconductor devices are disclosed. A disclosed semiconductor device includes a silicon substrate, a source region and a drain region. A gate electrode is formed on the silicon substrate. Also, a metal silicide layer is formed on each of the gate electrode, the source region, and the drain region. The metal silicide layer has a thickness uniformity of about 1˜20%. A disclosed fabrication method includes forming a metal layer on a silicon substrate having a gate electrode, a source region, and a drain region; performing a plasma treatment on the metal layer; forming a protective layer on the metal layer; and heat treating the silicon substrate on which the protective layer is formed to thereby form a metal silicide layer. A gas that includes nitrogen is used as a plasma gas during the plasma treatment. | 2009-07-23 |
20090184378 | STRUCTURE AND METHOD TO FABRICATE MOSFET WITH SHORT GATE - A method of producing a semiconducting device is provided that in one embodiment includes providing a semiconducting device including a gate structure atop a substrate, the gate structure including a dual gate conductor including an upper gate conductor and a lower gate conductor, wherein at least the lower gate conductor includes a silicon containing material; removing the upper gate conductor selective to the lower gate conductor; depositing a metal on at least the lower gate conductor; and producing a silicide from the metal and the lower gate conductor. In another embodiment, the inventive method includes a metal as the lower gate conductor. | 2009-07-23 |
20090184379 | SEMICONDUCTOR DEVICE HAVING DUMMY GATE PATTERN - A semiconductor device includes a diffusion layer formed on a semiconductor substrate, a gate pattern arranged over the diffusion layer, and a dummy gate pattern arranged adjacently to the gate pattern with a constant gap over the diffusion layer. The gate pattern functions as a gate electrode of a MOS transistor while the dummy gate pattern does not function as the gate electrode. The dummy gate pattern is disconnected at a predetermined position in a gate width direction over the diffusion layer. By this stricture, the semiconductor is capable of achieving both an improvement in dimensional accuracy and a high-speed circuit operation. | 2009-07-23 |
20090184380 | Metal oxide semiconductor (MOS) transistors with increased break down voltages and methods of making the same - A transistor comprises a substrate of a first conductivity type, a drain region and a source region of a second conductivity type, a gate, a gate oxide layer, an adjustment implant region of the first conductivity type and a planar junction. The drain region and the source region are disposed in the substrate. The gate is placed over the substrate between the source region and the drain region. The gate is separated from the substrate by the gate oxide layer. The adjustment implant region is disposed under the gate oxide layer and in the substrate. A second doping concentration of the adjustment implant region is higher than a first doping concentration of the substrate. The adjustment implant region and the drain region in a predetermined shape form the planar junction with a surface curvature pointing towards the drain region to relax electrical field intensity at a location of the planar junction. | 2009-07-23 |
20090184381 | SEMICONDUCTOR SENSOR AND METHOD FOR MANUFACTRUING THE SAME - A semiconductor sensor includes: a semiconductor substrate; a plurality of piezoelectric thin films layered on the semiconductor substrate, the plurality of piezoelectric thin films including at least a pair of the piezoelectric thin films layered above and below; a pair of electrodes that are formed at an interface of at least the pair of the piezoelectric thin films layered above and below and excite surface acoustic waves; a thin film directly under a lowest-layer piezoelectric film of the piezoelectric thin films; a metal thin film that is formed at an interface of the lowest-layer piezoelectric thin film and the thin film, and facilitate a growth of a ridge-and-valley portion on a surface of an uppermost-layer piezoelectric thin film of the piezoelectric thin films; and a sensitive film for molecular adsorption formed on at least the ridge-and-valley portion on the uppermost-layer piezoelectric thin film. | 2009-07-23 |
20090184382 | METHOD TO REDUCE DISLOCATION DENSITY IN SILICON - A crystalline material structure is provided. The crystalline material structure includes a semiconductor structure being annealed at temperatures above the brittle-to-ductile transition temperature of the semiconductor structure, and cooled in an approximately linear time-temperature profile down to approximately its respective transition temperature T | 2009-07-23 |
20090184383 | PHOTODETECTOR - A semiconductor photodetector is disclosed which can have a high responsivity, high saturation power, and high bandwidth. The photodetector comprises a waveguide structure comprising: an active waveguide comprising an absorber for converting photons conveying an optical signal into charge carriers conveying a corresponding electrical signal; a carrier collection layer for transporting the charge carriers conveying the electrical signal; and a secondary waveguide immediately adjacent to the carrier collection layer, for receiving the photons to be detected, and which is evanescently coupled to the active waveguide. The secondary passive waveguide layer in the photodetector epitaxial structure enables the use of fast carrier transport material to generate high intrinsic bandwidth and travelling wave techniques associated with a scheme of evanescent coupling to increase the responsivity, saturated output power and bandwidth. This enables a detector with an ultra-thin absorption layer implying a high intrinsic bandwidth for the device. This can be combined with a travelling wave technique to overcome the limitation on the bandwidth due to the depletion capacitance, resulting in a high bandwidth, high responsivity, high power photodetector. | 2009-07-23 |
20090184384 | ARRAY OF MUTUALLY ISOLATED, GEIGER-MODE, AVALANCHE PHOTODIODES AND MANUFACTURING METHOD THEREOF - An embodiment of array of Geiger-mode avalanche photodiodes, wherein each photodiode is formed by a body of semiconductor material, having a first conductivity type and housing an anode region, of a second conductivity type, facing a top surface of the body, a cathode-contact region, having the first conductivity type and a higher doping level than the body, facing a bottom surface of the body, an insulation region extending through the body and insulating an active area from the rest of the body, the active area housing the anode region and the cathode-contact region. The insulation region is formed by a first mirror region of polycrystalline silicon, a second mirror region of metal material, and a channel-stopper region of dielectric material, surrounding the first and second mirror regions. | 2009-07-23 |
20090184385 | OPTICAL SEMICONDUCTOR PACKAGE WITH COMPRESSIBLE ADJUSTMENT MEANS - An optical semiconductor package includes a support with a passage to receive a ring holding a lens situated facing an optical sensor. The support has, in the passage, at least one local release recess and the ring is equipped peripherally with a locally projecting, elastically deformable element. The local release recess and the elastically deformable element are such that, when the ring occupies an angular mounting position, the locally projecting elastically deformable element is engaged in the local recess of the support and, when the ring is pivoted from the aforementioned angular mounting position, the locally projecting elastically deformable element is moved out of the recess of the support and is compressed against the wall of the passage in order to secure the ring relative to the support. | 2009-07-23 |
20090184386 | SOLID-STATE IMAGE PICKUP DEVICE AND FABRICATION METHOD THEREFOR - Disclosed herein is a solid-state image pickup device, including, a light receiving pixel section, a black level reference pixel section, a multi-layer wiring line section, a first light blocking film, a second light blocking film, a third light blocking film, and a fourth light blocking layer. | 2009-07-23 |
20090184387 | SENSOR, SOLID-STATE IMAGING DEVICE, AND IMAGING APPARATUS AND METHOD OF MANUFACTURING THE SAME - A sensor is provided. The sensor includes semiconductor layer; a photodiode, an impurity-doped polycrystalline silicon layer; and a gate electrode. The photodiode is formed in the semiconductor layer. The impurity-doped polycrystalline silicon layer is formed above the semiconductor layer. The gate electrode applies a gate voltage to the polycrystalline silicon layer. A wiring layer is provided on a first surface of the semiconductor layer and light is incident on a second surface thereof. | 2009-07-23 |
20090184388 | Photodiode, ultraviolet sensor having the photodiode, and method of producing the photodiode - A photodiode includes a silicon semiconductor layer; a P-type high concentration diffusion layer with a P-type impurity diffused therein at a high concentration; an N-type high concentration diffusion layer with an N-type impurity diffused therein at a high concentration; and a low concentration diffusion layer with one of the P-type impurity and the N-type impurity diffused therein at a low concentration. The P-type high concentration diffusion layer and the N-type high concentration diffusion layer are formed in the silicon semiconductor layer, and are arranged to face each other with the low concentration diffusion layer in between. The photodiode further includes an interlayer insulation film formed on the silicon semiconductor layer, so that a covalent bond between silicon and hydrogen is formed in an atom row of the low concentration layer adjacent to an interface thereof with respect to the interlayer insulation film. The silicon semiconductor layer where the low concentration layer is formed may have a thickness between 3 nm and 36 nm. | 2009-07-23 |
20090184389 | Nonvolatile Nanotube Diodes and Nonvolatile Nanotube Blocks and Systems Using Same and Methods of Making Same - A non-volatile nanotube switch and memory arrays constructed from these switches are disclosed. A non-volatile nanotube switch includes a conductive terminal and a nanoscopic element stack having a plurality of nanoscopic elements arranged in direct electrical contact, a first comprising a nanotube fabric and a second comprising a carbon material, a portion of the nanoscopic element stack in electrical contact with the conductive terminal. Control circuitry is provided in electrical communication with and for applying electrical stimulus to the conductive terminal and to at least a portion of the nanoscopic element stack. At least one of the nanoscopic elements is capable of switching among a plurality of electronic states in response to a corresponding electrical stimuli applied by the control circuitry to the conductive terminal and the portion of the nanoscopic element stack. For each electronic state, the nanoscopic element stack provides an electrical pathway of corresponding resistance. | 2009-07-23 |