30th week of 2014 patent applcation highlights part 15 |
Patent application number | Title | Published |
20140203281 | DISPLAY DEVICE HAVING REPAIR AND DETECT STRUCTURE - A display device having repair and detect structure includes a substrate, a pixel array, a first shorting bar and a first repair line. The pixel array disposed on the substrate includes a plurality of data lines and a plurality of gate lines. The first shorting bar disposed on the substrate is connected to the gate lines for testing the gate lines, and the first shorting bar includes a first shorting segment. The first repair line is disposed on the substrate for repairing at least one of the data lines. The first shorting segment of the first shorting bar is electrically connected to the first repair line. Furthermore, another repair and detect structure of a display device is disclosed, wherein the first shorting bar includes a first shorting segment, the first repair line includes a first repair segment, and the first shorting segment overlaps with the first repair segment. | 2014-07-24 |
20140203282 | Semiconductor Test Structures - A method performed using a resistive device, where the resistive device includes a substrate with an active region separated from a gate electrode by a dielectric and electrical contacts along a longest dimension of the gate electrode, the method comprising, performing one or more processes to form the resistive device, measuring a resistance between the electrical contacts, and correlating the measured resistance with a variation in one or more of the processes. | 2014-07-24 |
20140203283 | FLAT PANEL DETECTOR AND MANUFACTURING METHOD THEREOF, CAMERA DEVICE - A flat panel detector comprises a photoelectric conversion layer and a pixel detecting element disposed under the photoelectric conversion layer. The pixel detecting element comprises: a pixel electrode for receiving charges, a storage capacitor for storing the received charges, and a thin film transistor for controlling outputting of the stored charges. The storage capacitor comprises a first electrode and a second electrode. The first electrode comprises an upper electrode and a bottom electrode that are disposed opposite to each other and electrically connected. A second electrode is sandwiched between the upper electrode and the bottom electrode. It is insulated between the upper electrode and the second electrode and between the second electrode and the bottom electrode. | 2014-07-24 |
20140203284 | Semiconductor Device and Method for Manufacturing the Same - A semiconductor device includes a pixel electrode and a transistor which includes a first gate electrode, a first insulating layer over the first gate electrode, a semiconductor layer over the first insulating layer, a second insulating layer over the semiconductor layer, and a second gate electrode. The pixel electrode and the second gate electrode are provided over the second insulating layer. The first gate electrode has a region overlapping with the semiconductor layer with the first insulating layer provided therebetween. The second gate electrode has a region overlapping with the semiconductor layer with the second insulating layer provided therebetween. A first region is at least part of a region where the second gate electrode overlaps with the semiconductor layer. A second region is at least part of a region where the pixel electrode is provided. The second insulating layer is thinner in the first region than in the second region. | 2014-07-24 |
20140203285 | ELECTROOPTIC DEVICE SUBSTRATE, ELECTROOPTIC DEVICE, AND ELECTRONIC APPARATUS - An electrooptic device substrate includes a scan line that is provided on an element substrate, a foundation insulating layer, a semiconductor layer provided on the foundation insulating layer, a gate insulating layer, recesses that are provided at both sides of the semiconductor layer so as to penetrate through the foundation insulating layer and the gate insulating layer, a gate electrode that is provided on the gate insulating layer and is electrically connected to the scan line in the recesses, an insulating interlayer that covers the gate insulating layer, the gate electrode, and the recesses, and a data line that is provided on the insulating interlayer so as to overlap with the scan line, the semiconductor layer, the gate electrode, and the recesses. The recesses include first recesses that overlap with the scan line and second recesses that extend to outer sides of the scan line. | 2014-07-24 |
20140203286 | Electro-Optical Device and Electronic Device - An object of the present invention is to provide an EL display device, which has a high operating performance and reliability. A third passivation film | 2014-07-24 |
20140203287 | NITRIDE LIGHT-EMITTING DEVICE WITH CURRENT-BLOCKING MECHANISM AND METHOD FOR FABRICATING THE SAME - A nitride light emitting device comprises a current blocking Schottky junction zone formed below the p-electrode and above the active region so that current injection from the p-electrode to the area of the active region that is vertically shaded by the p-electrode is blocked by the Schottky junction zone. A method for fabricating the same is also provided. | 2014-07-24 |
20140203288 | COMPOUND SEMICONDUCTOR DEVICE HAVING GALLIUM NITRIDE GATE STRUCTURES - The present disclosure provides a semiconductor structure. The semiconductor structure includes a buffer layer on a substrate, an graded aluminum gallium nitride (AlGaN) layer disposed on the buffer layer, a gallium nitride (GaN) layer disposed on the graded AlGaN layer, a second AlGaN layer disposed on the GaN layer and a gate stack disposed on the second AlGaN layer. The gate stack includes one or more of a III-V compound p-doped layer, a III-V compound n-doped layer, an aluminum nitride (AlN) layer between the III-V compound p-doped and n-doped layers, and a metal layer formed over the p-doped, AlN, and n-doped layers. A dielectric layer can also underlie the metal layer. | 2014-07-24 |
20140203289 | High Electron Mobility Transistors - The present disclosure relates to a donor layer of bi-layer AlGaN and associated method of fabrication within a high electron mobility transistor (HEMT) configured to provide low-resistance ohmic source and drain contacts to reduce power consumption, while maintaining a high-mobility of a two-dimensional electron gas (2DEG) within a channel of the HEMT. The donor layer of bi-layer AlGaN comprises a mobility-enhancing layer of Al | 2014-07-24 |
20140203290 | Wire-Last Integration Method and Structure for III-V Nanowire Devices - In one aspect, a method of fabricating a nanowire FET device includes the following steps. A layer of III-V semiconductor material is formed on an SOI layer of an SOI wafer. Fins are etched into the III-V material and SOI layer. One or more dummy gates are formed over a portion of the fins that serves as a channel region of the device. A gap filler material is deposited onto the wafer. The dummy gates are removed selective to the gap filler material, forming trenches in the gap filler material. The SOI layer is removed from portions of the fins within the trenches thereby forming suspended nanowire channels in the channel regions of the device. The trenches are filled with at least one gate material to form one or more replacement gates surrounding the nanowire channels in a gate-all-around configuration. | 2014-07-24 |
20140203291 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes: an FET chip; pads provided on an upper surface of the FET chip; bumps provided on at least one of the pads; leads having first portions that are connected to the FET chip by the bumps and extend along the upper surface of the FET chip, and second portions that contact surfaces of the first portions along the upper surface of the FET chip and extend along a side surface of the FET chip, the first and second portions being formed by press or cutting; and a seal layer that seals the FET chip and the leads and a surface from which the second portions of the leads are exposed, the surface of the seal layer being on a lower surface side of the FET chip. | 2014-07-24 |
20140203292 | SEMICONDUCTOR LIGHT EMITTING DEVICE - A semiconductor light emitting device includes a light-transmissive substrate, a light-transmissive buffer layer disposed on the light-transmissive substrate, and a light emitting structure. The light-transmissive buffer layer includes a first layer and a second layer having different refractive indices and disposed alternately at least once. The light emitting structure includes a first conductivity-type semiconductor layer, an active layer, and a second conductivity-type semiconductor layer sequentially disposed on the buffer layer. | 2014-07-24 |
20140203293 | NITRIDE SEMICONDUCTOR LIGHT EMITTING DEVICE - A nitride semiconductor light emitting device includes a substrate, a multi-layer structure, a light-transmitting concave-convex structure and a light emitting structure. The multi-layer structure has layers of a first layer and a second layer such that the first and second layers have different refractive indexes and are alternately stacked. The concave-convex structure is disposed in an upper surface of the multi-layer structure and includes a light-transmitting material. The light emitting structure is disposed on the multi-layer structure and includes a first conductive semiconductor layer, an active layer, and a second conductive semiconductor layer. | 2014-07-24 |
20140203294 | Gallium Nitride Devices - Semiconductor structures comprising a III-nitride (e.g., gallium nitride) material region and methods associated with such structures are provided. In some embodiments, the structures include an electrically conductive material (e.g., gold) separated from certain other region(s) of the structure (e.g., a silicon substrate) by a barrier material in order to limit, or prevent, undesirable reactions between the electrically conductive material and the other component(s) which can impair device performance. In certain embodiments, the electrically conductive material may be formed in a via. For example, the via can extend from a topside of the device to a backside so that the electrically conductive material connects a topside contact to a backside contact. The structures described herein may form the basis of a number of semiconductor devices including transistors (e.g., FET), Schottky diodes, light-emitting diodes and laser diodes, amongst others. | 2014-07-24 |
20140203295 | INTEGRATED POWER DEVICE WITH III-NITRIDE HALF BRIDGES - A semiconductor device that includes a plurality of isolated half-bridges formed in a common semiconductor die. | 2014-07-24 |
20140203296 | SEMICONDUCTOR LIGHT EMITTING DEVICE AND METHOD FOR MANUFACTURING SAME - According to an embodiment, a semiconductor light emitting device includes a light emitting body including a semiconductor light emitting layer, a support substrate supporting the light emitting body, and a bonding layer provided between the light emitting body and the support substrate, the bonding layer bonding the light emitting body and the support substrate together. The device also includes a first barrier metal layer provided between the light emitting body and the bonding layer, and an electrode provided between the light emitting body and the first barrier metal layer. The first barrier layer includes a first layer made of nickel and a second layer made of a metal having a smaller linear expansion coefficient than nickel, and the first layer and the second layer are alternately disposed in a multiple-layer structure. The electrode is electrically connected to the light emitting body. | 2014-07-24 |
20140203297 | Method of Manufacturing Substrates Having Improved Carrier Lifetimes - This invention relates to a method for depositing silicon carbide material onto a substrate such that the resulting substrate has a carrier lifetime of 0.5-1000 microseconds, the method comprising a. introducing a gas mixture comprising a chlorosilane gas, a carbon-containing gas, and hydrogen gas into a reaction chamber containing a substrate; and b. heating the substrate to a temperature of greater than 1000° C. but less than 2000° C.; with the proviso that the pressure within the reaction chamber is maintained in the range of 0.1 to 760 torr. This invention also relates to a method for depositing silicon carbide material onto a substrate such that the resulting substrate has a carrier lifetime of 0.5-1000 microseconds, the method comprising a. introducing a gas mixture comprising a non-chlorinated silicon-containing gas, hydrogen chloride, a carbon-containing gas, and hydrogen gas into a reaction chamber containing a substrate; and b. heating the substrate to a temperature of greater than 1000° C. but less than 2000° C.; with the proviso that the pressure within the reaction chamber is maintained in the range of 0.1 to 760 torr. | 2014-07-24 |
20140203298 | STRAINED SILICON CARBIDE CHANNEL FOR ELECTRON MOBILITY OF NMOS - A semiconductor is formed on a (110) silicon (Si) substrate, with improved electron mobility. Embodiments include semiconductor devices having a silicon carbide (SiC) portion in the nFET channel region. An embodiment includes forming an nFET channel region and a pFET channel region in a Si substrate, such as a (110) Si substrate, and forming a silicon carbide (SiC) portion on the nFET channel region. The SiC portion may be formed by ion implantation of C followed by a recrystallization anneal or by epitaxial growth of SiC in a recess formed in the substrate. The use of SiC in the nFET channel region improves electron mobility without introducing topographical differences between NMOS and PMOS transistors. | 2014-07-24 |
20140203299 | SEMICONDUCTOR DEVICE - The semiconductor device of the present invention includes a first conductivity type semiconductor layer made of a wide bandgap semiconductor and a Schottky electrode formed to come into contact with a surface of the semiconductor layer, and has a threshold voltage V | 2014-07-24 |
20140203300 | SiC SEMICONDUCTOR ELEMENT AND MANUFACTURING METHOD THEREOF - Provided are a technology that simply forms a particular crystal surface such as a {03-38} surface having high carrier mobility in trench sidewalls and a SiC semiconductor element where most of the trench sidewalls appropriate for a channel member are formed from {03-38} surfaces. A trench structure formed in a (0001) surface or an off-oriented surface of a (0001) surface with an offset angle 8° or lower of SiC is provided. The channel member is in the trench structure. At least 90% of the area of the channel member is a {03-38} surface or a surface that a {03-38} surface offset by an angle from −8° to 8° in the <1-100> direction. Specifically, the trench sidewalls are finished to {03-38} surfaces by applying a thermal etching to a trench with (0001) surfaces of SiC. Thermal etching is conducted in a chlorine atmosphere above 800° C. with nitrogen gas as the carrier. | 2014-07-24 |
20140203301 | DISPLAY DEVICE - A display device includes a substrate and pixels arranged on the substrate in a matrix form. The substrate includes a display area in which the pixels are arranged and a non-display area disposed adjacent to a side of the display area. Each pixel includes a cover layer that extends in a row direction that includes a sidewall portion connected to the substrate and a cover portion spaced apart from the substrate and connected to the sidewall portion to define a tunnel-shaped cavity on the substrate. A width of the sidewall portion between adjacent pixels is less than a width of the sidewall portion disposed at an outermost position, and the cover layer seals one side of the tunnel-shaped cavity in the pixels arranged in a first row and a last row. | 2014-07-24 |
20140203302 | PIXEL STRUCTURE OF DISPLAY PANEL - A pixel structure of a display panel includes a gate line, a first data line, a second data line, a first active switching device, a second active switching device, a first pixel electrode and a second pixel electrode. The first pixel electrode is electrically connected to the first active switching device. The first pixel electrode includes a first main electrode disposed adjacent to one side of the first data line, and a second main electrode disposed adjacent to one side of the second data line. The second pixel electrode is electrically connected to the second active switching device. The second pixel electrode is disposed between the first main electrode and the second main electrode of the first pixel electrode. | 2014-07-24 |
20140203303 | Light-Emitting Diode Display Substrate, Method For Manufacturing Same, And Display Device - A light-emitting diode (LED) display substrate, a method for manufacturing the same, and a display device are provided and involve the display field. The method for manufacturing the LED display substrate comprises: forming a transparent conductive anode ( | 2014-07-24 |
20140203304 | LIGHT-EMITTING DEVICE PACKAGE STRIP AND METHOD FOR MANUFACTURING THE SAME - Provided is a light-emitting device package strip that includes a lead frame strip, a plurality of resin molding products that are injection-molded in the lead frame strip, and runner and gate members that are formed between adjacent resin molding products and on end sides of a line of adjacent resin molding products, each runner and gate member having a smaller thickness than a thickness of the resin molding products to facilitate cutting thereof. | 2014-07-24 |
20140203305 | LIGHT EMITTING DEVICE AND ITS METHOD OF MANUFACTURE - The light emitting device is provided with a substrate, semiconductor light emitting elements mounted on the substrate, a mold frame that surrounds the periphery of the light emitting elements on the substrate, and resin layers that fill the inside of the mold frame. The mold frame includes a first mold frame, and a second mold frame formed on top of the first mold frame. The resin layers include a first resin layer that embeds the light emitting elements in resin and is formed with a height approximately equal to the height of the top of the first mold frame, and a second resin layer on top of the first resin layer that is formed with a height approximately equal to the height of the top of the second mold frame. At least one of the resin layers (which are the first resin layer and the second resin layer) includes wavelength-shifting material to change the wavelength of light emitted from the semiconductor light emitting elements. | 2014-07-24 |
20140203306 | SEMICONDUCTOR LIGHT-EMITTING DEVICE - A semiconductor light-emitting device can include a wavelength converting layer including a surrounding portion, which covers at least one semiconductor light-emitting chip in order to emit various colored lights including white light. The semiconductor light-emitting device can include a substrate, a frame located on the substrate, the chip mounted on the substrate, a transparent material layer located on the wavelength converting layer so as to reduce from the wavelength converting layer toward a light-emitting surface thereof, and a reflective material layer disposed at least between the frame and both side surfaces of the wavelength converting layer and the transparent material layer. The semiconductor light-emitting device can be configured to improve light-emitting efficiency and a color variation by using the surrounding portion and an inclined side surface of transparent material layer, and therefore can emit various colored lights including white light having a high light-emitting efficiency from a small light-emitting surface. | 2014-07-24 |
20140203307 | DISPLAY PANEL AND SYSTEM FOR DISPLAYING IMAGES UTILIZING THE SAME - An embodiment of the invention provides a display panel, which includes a substrate having a pixel region and a peripheral region, a control element overlying the pixel region of the substrate, a conducting layer overlying the substrate in the peripheral region, a first insulating layer overlying the conducting layer in the peripheral region, wherein a ratio between an area of the first insulating layer and an area of the conducting layer in the peripheral region is between about 0.27 and 0.99, a lower electrode layer overlying the first insulating layer, and a second insulating layer overlying the lower electrode layer. | 2014-07-24 |
20140203308 | LIGHT-EMITTING DIES INCORPORATING WAVELENGTH-CONVERSION MATERIALS AND RELATED METHODS - In accordance with certain embodiments, semiconductor dies are embedded within polymeric binder to form, e.g., light-emitting dies and/or composite wafers containing multiple light-emitting dies embedded in a single volume of binder. | 2014-07-24 |
20140203309 | ELECTROLUMINESCENCE DISPLAY DEVICE - Disclosed is an electroluminescence device having a substrate, a thin film transistor over the substrate, an insulating film over the thin film transistor, an electroluminescence element over the insulating film, a passivation film over the electroluminescence element, and a counter substrate over the passivation film. The electroluminescence element is configured to emit light through the counter substrate, and a space between the substrate and the counter substrate is filled with a filler. The electroluminescence device is featured by the tapered side surface of a gate electrode of the thin film transistor. | 2014-07-24 |
20140203310 | DISPLAY PANEL AND DISPLAY UNIT - A display panel includes: a mounting substrate including light-emitting elements that are mounted for each pixel on a wiring substrate, in which the light-emitting elements have different luminescence wavelengths from each other; and a counter substrate provided in opposition to a surface, of the mounting substrate, on which the pixels are disposed, and including a light-shielding layer and a light diffusion layer. The light-shielding layer is provided on a surface, of a light transmissive substrate, that faces the pixels and has apertures at respective positions that face the light-emitting elements. The light diffusion layer blocks up the apertures, is provided on a surface, of the light-shielding layer, that faces the pixels, is at least in contact with end edges of the respective apertures, and forms a gap together with the light-emitting elements between the light diffusion layer and the light-emitting elements. | 2014-07-24 |
20140203311 | PHOTON EXTRACTION FROM NITRIDE ULTRAVIOLET LIGHT-EMITTING DEVICES - In various embodiments, a rigid lens is attached to a light-emitting semiconductor die via a layer of encapsulant having a thickness insufficient to prevent propagation of thermal expansion mismatch-induced strain between the rigid lens and the semiconductor die. | 2014-07-24 |
20140203312 | MIXED LIGHT LED STRUCTURE - Disclosed is a mixed light LED structure which is a solid-state phosphor plate manufactured by mixing phosphor and resin, and the solid-state phosphor plate is installed in a carrier and covered onto the top of a light emitting chip, and a specific ratio relation between the area of the solid-state phosphor plate and the area of the light emitting chip area or a specific ratio relation between the area of the solid-state phosphor plate and the area a light emitting hole are used. and also the relation of limiting the distance between the solid-state phosphor plate and the light emitting chip is satisfied, so as to achieve a better mixed light effect and a longer service life of the mixed light LED structure. | 2014-07-24 |
20140203313 | SEMICONDUCTOR LIGHT EMITTING DEVICE - According to one embodiment, a semiconductor light emitting device includes: a mounting substrate; a semiconductor light emitting element; a first resin; and a second resin. The semiconductor light emitting element includes: a semiconductor layer including a light emitting layer; a p-side electrode; a p-side interconnection unit; an n-side electrode; and an n-side interconnection unit. The first resin covers a periphery of the semiconductor light emitting element on the substrate and contains a phosphorescent substance capable of being excited by emission light of the light emitting layer. The second resin is provided on the first resin layer and the semiconductor light emitting element and contains a fluorescent body capable of being excited by emission light of the light emitting layer to emit light of a different peak wavelength from emission light of the light emitting layer. | 2014-07-24 |
20140203314 | SEMICONDUCTOR LIGHT EMITTING DEVICE - According to one embodiment, a semiconductor light emitting device includes: a semiconductor layer; a p-side electrode; an n-side electrode; and a fluorescent body layer. The p-side electrode is provided on a second surface side of the semiconductor layer. The n-side electrode is provided on the second surface side of the semiconductor layer. The fluorescent body layer is provided on a first surface side of the semiconductor layer and contains a plurality of fluorescent bodies configured to be excited by emission light of the light emitting layer and emit light of a different wavelength from the emission light and a bonding material integrating the plurality of fluorescent bodies and configured to transmit the emission light. An average spacing between adjacent ones of the fluorescent bodies is narrower than a peak wavelength of emission light of the light emitting layer. | 2014-07-24 |
20140203315 | LED LENS AND LED PACKAGE USING THE SAME - A light emitting diode (LED) lens comprises a light incident surface on a bottom surface of the LED lens facing a light source. A light exit surface, having a size greater than the bottom surface, is defined by a top surface of the LED lens. A planar portion, emitting light incident through the light incident surface, is in a central region of the light exit surface. At least one protrusion portion, protruding to be stepped with respect to the planar portion, is in a region of the light exit surface except for the central region. A reflective surface, defined by lateral surfaces of the LED lens between the top surface of the LED lens and the bottom surface thereof, guides the light incident through the light incident surface, and contacts a lower portion of the light exit surface corresponding to a boundary between the protrusion and the planar portions. | 2014-07-24 |
20140203316 | YELLOW PHOSPHOR LAYER CONTAINING COLORED BEADS FOR ADJUSTING ITS PERCEIVED OFF-STATE COLOR - LED dies, emitting blue light, are provided on a first support substrate to form a light emitting layer. A mixture of a transparent binder, yellow phosphor powder, magenta-colored glass beads, and cyan-colored glass beads is printed over the light emitting surface. The mixture forms a wavelength conversion layer when cured. The beads are sized so that the tops of the beads protrude completely through the conversion layer. When the LED dies are on, the combination of the yellow phosphor light and the blue LED light creates white light. When the LEDs are off, white ambient light, such as sunlight, causes the conversion layer to appear to be a mixture of yellow light, magenta light, and cyan light. The percentage of the magenta and cyan beads in the mixture is selected to create a desired off-state color, such as a neutral color, of the conversion layer for aesthetic purposes. | 2014-07-24 |
20140203317 | SEMICONDUCTOR LIGHT EMITTING DEVICE AND LIGHT EMITTING APPARATUS - There is provided a semiconductor light emitting device including a substrate having light transmission properties and including a first surface and a second surface opposed to the first surface, a light emitting structure including a first conductivity type semiconductor layer, an active layer, and a second conductivity type semiconductor layer sequentially disposed on the first surface of the substrate, a first electrode and a second electrode connected to the first conductivity type semiconductor layer and the second conductivity type semiconductor layer, respectively, and a window layer disposed on the second surface of the substrate, the window layer being formed of a light transmissive material which is different from a material of the substrate and including inclined side surfaces. | 2014-07-24 |
20140203318 | LIGHT EMITTING ELEMENT AND LIGHT EMITTING ELEMENT PACKAGE - A light emitting element includes: a sapphire substrate having a front surface and a rear surface opposite the front surface; a first conductive type semiconductor layer stacked on the front surface of the sapphire substrate; a light emitting layer stacked on the first conductive type semiconductor layer; a second conductive type semiconductor layer stacked on the light emitting layer; a reflective layer which contains Ag and is disposed on the rear surface of the sapphire substrate, the reflective layer reflecting light from the sapphire substrate toward the front surface of the sapphire substrate; and an adhesive layer which is interposed between the sapphire substrate and the reflective layer and is made of ITO, the adhesive layer being adhered to the reflective layer. | 2014-07-24 |
20140203319 | Article Including a Light Emitting Gadolinium-Containing Material and a Process of Forming the Same - An article, such as a light emitting device, can include a first material and a second material, wherein the first material is capable of emitting first radiation having a first emission maximum at a first wavelength, and the second material is capable of emitting second radiation in response to capturing the first radiation. The second material can have a second emission maximum at a second wavelength within the visible light spectrum. In an embodiment, the second material can be different from the first material. In another embodiment, a difference between the first wavelength and the second wavelength can be at least approximately 70 nm. Additionally, the second material can include a luminescent material having a formula of Gd | 2014-07-24 |
20140203320 | COMPOSITE HIGH REFLECTIVITY LAYER - A high efficiency light emitting diode with a composite high reflectivity layer integral to said LED to improve emission efficiency. One embodiment of a light emitting diode (LED) chip comprises an LED and a composite high reflectivity layer integral to the LED to reflect light emitted from the active region. The composite layer comprises a first layer, and alternating plurality of second and third layers on the first layer, and a reflective layer on the topmost of said plurality of second and third layers. The second and third layers have a different index of refraction, and the first layer is at least three times thicker than the thickest of the second and third layers. For composite layers internal to the LED chip, conductive vias can be included through the composite layer to allow an electrical signal to pass through the composite layer to the LED. | 2014-07-24 |
20140203321 | LIGHT EMITTING DIODE PACKAGE HAVING HEAT DISSIPATING SLUGS - A light emitting diode package having heat dissipating slugs is provided. The light emitting diode package comprises first and second heat dissipating slugs formed of a conductive material and spaced apart from each other; a package main body coupled to the first and second heat dissipating slugs to support the first and second heat dissipating slugs; and a light emitting diode die electrically connected to the first and second heat dissipating slugs, wherein the respective first and second heat dissipating slugs are exposed to the outside through lower and side surfaces of the package main body. As such, the first and second heat dissipating slugs can be used as external leads. | 2014-07-24 |
20140203322 | Transparent Conductive Structure, Device comprising the same, and the Manufacturing Method thereof - An optical electrical device comprises a base and a transparent conductive structure on the base is disclosed. The base further comprises a light-emitting device and the transparent conductive structure comprises a transparent conductive oxide layer and a passivation layer on the transparent conductive oxide layer. The material of the transparent conductive oxide layer comprises transparent conductive metal oxide, such as ZnO. Furthermore, the transparent conductive metal oxide also comprises impurities, such as a carrier e.g. gallium. | 2014-07-24 |
20140203323 | PRIMER COMPOSITION AND OPTICAL SEMICONDUCTOR APPARATUS USING SAME - The invention provides a primer composition which adheres a substrate mounting an optical semiconductor device and a cured material of an addition reaction curing silicone composition that encapsulates the optical semiconductor device, includes (A) silazane compound or polysilazane compounds that has one or more silazane bonds in the molecule, (B) acrylic resin containing either one or both of acrylate ester and methacrylate ester that contains one or more SiH groups in the molecule, and (C) solvent. There can be provided a primer composition in which the adhesion between a substrate mounting an optical semiconductor device and a cured material of an addition reaction curing silicone composition that encapsulates the optical semiconductor device can be improved, the corrosion of a metal electrode on the substrate can be prevented, and the heat resistance and flexibility of a primer can be improved. | 2014-07-24 |
20140203324 | A STRIP-SHAPED GATE-MODULATED TUNNELING FIELD EFFECT TRANSISTOR AND A PREPARATION METHOD THEREOF - The present invention discloses a strip-shaped gate-modulated tunneling field effect transistor and a preparation method thereof, belonging to a field of field effect transistor logic device and the circuit in CMOS ultra large scale integrated circuit (ULSI). The tunneling field effect transistor includes a control gate, a gate dielectric layer, a semiconductor substrate, a highly-doped source region and a highly-doped drain region, where the highly-doped source region and the highly-doped drain region lie on both sides of the control gate, respectively, the control gate has a strip-shaped structure with a gate length greater than a gate width, and at one side thereof is connected to the highly-doped drain region and at the other side thereof extends laterally into the highly-doped source region; a region located below the control gate is a channel region; and the gate width of the control gate is less than twice width of a source depletion layer. The device modulates the source-side tunneling junction by using the strip-shaped gate structure, achieves the effect equivalent to that the source junction has a steep doping concentration gradient, and improves the TFET device performance; and the preparation method thereof is simple. | 2014-07-24 |
20140203325 | INTEGRATION OF GERMANIUM PHOTO DETECTOR IN CMOS PROCESSING - A method and device are provided for forming an integrated Ge or Ge/Si photo detector in the CMOS process by non-selective epitaxial growth of the Ge or Ge/Si. Embodiments include forming an N-well in a Si substrate; forming a transistor or resistor in the Si substrate; forming an ILD over the Si substrate and the transistor or resistor; forming a Si-based dielectric layer on the ILD; forming a poly-Si or a-Si layer on the Si-based dielectric layer; forming a trench in the poly-Si or a-Si layer, the Si-based dielectric layer, the ILD, and the N-well; forming Ge or Ge/Si in the trench; and removing the Ge or Ge/Si, the poly-Si or a-Si layer, and the Si-based dielectric layer down to an upper surface of the ILD. Further aspects include forming an in-situ doped Si cap epilayer or an ex-situ doped poly-Si or a-Si cap layer on the Ge or Ge/Si. | 2014-07-24 |
20140203326 | METHODS OF FORMING HETERO-LAYERS WITH REDUCED SURFACE ROUGHNESS AND BULK DEFECT DENSITY ON NON-NATIVE SURFACES AND THE STRUCTURES FORMED THEREBY - Methods of forming hetero-layers with reduced surface roughness and bulk defect density on non-native surfaces and the devices formed thereby are described. In one embodiment, the method includes providing a substrate having a top surface with a lattice constant and depositing a first layer on the top surface of the substrate. The first layer has a top surface with a lattice constant that is different from the first lattice constant of the top surface of the substrate. The first layer is annealed and polished to form a polished surface. A second layer is then deposited above the polished surface. | 2014-07-24 |
20140203327 | DEEP GATE-ALL-AROUND SEMICONDUCTOR DEVICE HAVING GERMANIUM OR GROUP III-V ACTIVE LAYER - Deep gate-all-around semiconductor devices having germanium or group III-V active layers are described. For example, a non-planar semiconductor device includes a hetero-structure disposed above a substrate. The hetero-structure includes a hetero-junction between an upper layer and a lower layer of differing composition. An active layer is disposed above the hetero-structure and has a composition different from the upper and lower layers of the hetero-structure. A gate electrode stack is disposed on and completely surrounds a channel region of the active layer, and is disposed in a trench in the upper layer and at least partially in the lower layer of the hetero-structure. Source and drain regions are disposed in the active layer and in the upper layer, but not in the lower layer, on either side of the gate electrode stack. | 2014-07-24 |
20140203328 | METHOD AND SYSTEM FOR A GALLIUM NITRIDE VERTICAL JFET WITH SELF-ALIGNED GATE METALLIZATION - A semiconductor device includes a III-nitride substrate and a first III-nitride epitaxial layer coupled to the III-nitride substrate and comprising a drift region, a channel region, and an extension region. The channel region is separated from the III-nitride substrate by the drift region. The channel region is characterized by a first width. The extension region is separated from the drift region by the channel region. The extension region is characterized by a second width less than the first width. The semiconductor device also includes a second III-nitride epitaxial layer coupled to a top surface of the extension region, a III-nitride gate structure coupled to a sidewall of the channel region and laterally self-aligned with respect to the extension region, and a gate metal structure in electrical contact with the III-nitride gate structure and laterally self-aligned with respect to the extension region. | 2014-07-24 |
20140203329 | NITRIDE ELECTRONIC DEVICE AND METHOD FOR FABRICATING NITRIDE ELECTRONIC DEVICE - Provided is a nitride electronic device having a structure that allows the reduction of leakage by preventing the carrier concentration from increasing in a channel layer. An inclined surface and a primary surface of a semiconductor stack extend along first and second reference planes R | 2014-07-24 |
20140203330 | SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit includes: a main-interconnect to which supply voltage or reference voltage is applied; a plurality of sub-interconnects; a plurality of circuit cells configured to be connected to the plurality of sub-interconnects; a power supply switch cell configured to control, in accordance with an input control signal, connection and disconnection between the main-interconnect and the sub-interconnect to which a predetermined one of the circuit cells is connected, of the plurality of sub-interconnects; and an auxiliary interconnect configured to connect the plurality of sub-interconnects to each other. | 2014-07-24 |
20140203331 | SOLID STATE IMAGING DEVICE AND IMAGING APPARATUS - A solid-state imaging device has, in a semiconductor substrate, plural PDs arranged two-dimensionally and signal reading circuits which are formed as MOS transistors and read out signals corresponding to charges generated in the respective PDs. Microlenses for focusing light beams are formed over the respective PDs. An interlayer insulating film in which interconnections are buried is formed as an insulating layer between the semiconductor substrate and the microlenses. Closed-wall-shaped structures are formed in the interlayer insulating film so as to surround parts of focusing optical paths of the microlenses, respectively. The structures are made of a nonconductive material that is different in refractive index from a material of what is formed around them. | 2014-07-24 |
20140203332 | SELF-ALIGNED BIOSENSORS WITH ENHANCED SENSITIVITY - Non-planar semiconductor FET based sensors are provided that have an enhanced sensing area to volume ratio which results in faster response times than existing planar FET based sensors. The FET based sensors of the present disclosure include a V-shaped gate dielectric portion located in a V-shaped opening formed in a semiconductor substrate. In some embodiments, the FET based sensors of the present disclosure also include a self-aligned source region and a self-aligned drain region located in the semiconductor substrate and on opposing sides of the V-shaped opening. In other embodiments, the FET based sensors include a self-aligned source region and a self-aligned drain region located in the semiconductor substrate and on opposing sides of a gate dielectric material portion that is present on an uppermost surface of the semiconductor substrate. | 2014-07-24 |
20140203333 | SEMICONDUCTOR DEVICE HAVING MODIFIED PROFILE METAL GATE - In one embodiment, a method includes providing a semiconductor substrate having a trench disposed thereon and forming a plurality of layers in the trench. The plurality of layers formed in the trench is etched thereby providing at least one etched layer having a top surface that lies below a top surface of the trench. In a further embodiment, this may provide for a substantially v-shaped opening or entry to the trench for the formation of further layers. Further, a device having a modified profile metal gate for example having at least one layer of the metal. | 2014-07-24 |
20140203334 | METHOD FOR FABRICATING A FINFET DEVICE INCLUDING A STEM REGION OF A FIN ELEMENT - A method includes providing a substrate having a fin extending from a first (e.g., top) surface of the substrate. The fin has first region (a stem region) and a second region (an active region) each having a different composition. The first region of the fin is modified to decrease a width of semiconductor material for example by etching and/or oxidizing the first region of the fin. The method then continues to provide a gate structure on the second region of the fin. FinFET devices having stem regions with decreased widths of semiconductor material are also provided. | 2014-07-24 |
20140203335 | Semiconductor Devices and Methods for Fabricating the Same - A semiconductor device includes an insulating film on a substrate and including a trench, a gate insulating film in the trench, a DIT (Density of Interface Trap) improvement film on the gate insulating film to improve a DIT of the substrate, and a first conductivity type work function adjustment film on the DIT improvement film. Related methods of forming semiconductor devices are also disclosed. | 2014-07-24 |
20140203336 | ADHESION LAYER AND MULTIPHASE ULTRA-LOW k DIELECTRIC MATERIAL - A dielectric material incorporating a graded carbon adhesion layer whereby the content of C increases with layer thickness and a multiphase ultra low k dielectric comprising a porous SiCOH dielectric material having a k less than 2.7 and a modulus of elasticity greater than 7 GPa is described. A semiconductor integrated circuit incorporating the above dielectric material in interconnect wiring is described and a semiconductor integrated circuit incorporating the above multiphase ultra low k dielectric in a gate stack spacer of a FET is described. | 2014-07-24 |
20140203337 | METHOD OF FORMING GATE DIELECTRIC LAYER AND METHOD OF FABRICATING SEMICONDUCTOR DEVICE - A method for fabricating a semiconductor device includes ion-implanting germanium into a monocrystalline silicon-containing substrate; forming a gate oxide layer over a surface of the monocrystalline silicon-containing substrate and forming, under the gate oxide layer, a germanium-rich region in which the germanium is concentrated, by performing a plasma oxidation process; and crystallizing the germanium-rich region by performing an annealing process. | 2014-07-24 |
20140203338 | FinFET Device with Epitaxial Structure - A FinFET device includes a substrate, a fin, and isolation regions on either side of the fin. The device also includes sidewall spacers above the isolation regions and formed along the fin structure. A recessing trench is formed by the sidewall spacers and the fin, and an epitaxially-grown semiconductor material is formed in and above the recessing trench, forming an epitaxial structure. | 2014-07-24 |
20140203339 | SEMICONDUCTOR DEVICE COMPRISING SELF-ALIGNED CONTACT ELEMENTS AND A REPLACEMENT GATE ELECTRODE STRUCTURE - A semiconductor device includes a high-k metal gate electrode structure that is positioned above an active region, has a top surface that is positioned at a gate height level, and includes a high-k dielectric material and an electrode metal. Raised drain and source regions are positioned laterally adjacent to the high-k metal gate electrode structure and connect to the active region, and a top surface of each of the raised drain and source regions is positioned at a contact height level that is below the gate height level. An etch stop layer is positioned above the top surface of the raised drain and source regions and a contact element connects to one of the raised drain and source regions, the contact element extending through the etch stop layer and a dielectric material positioned above the high-k metal gate electrode structure and the raised drain and source regions. | 2014-07-24 |
20140203340 | PHOTODIODE AND PRODUCTION METHOD - The photodiode has a p-type doped region ( | 2014-07-24 |
20140203341 | ELECTRIC FIELD ASSISTED PERPENDICULAR STT-MRAM - A perpendicular STT-MRAM comprises apparatus, a method of operating and a method of manufacturing a spin-torque magnetoresistive memory and a plurality of magnetoresistive memory element having a recording layer which has an interface interaction with an underneath dielectric functional layer. The energy switch barrier of the recording layer is reduced under an electric field applying along a perpendicular direction of the functional with a proper voltage on a digital line from a control circuitry; accordingly, the perpendicular magnetization of the recording layer is readily reversible in a low spin-transfer switching current. | 2014-07-24 |
20140203342 | FERROELECTRIC RANDOM ACCESS MEMORY WITH OPTIMIZED HARDMASK - Device structures, fabrication methods, and design structures for a capacitor of a memory cell of ferroelectric random access memory device. The capacitor may include a first electrode comprised of a first conductor, a ferroelectric layer on the first electrode, a second electrode on the ferroelectric layer, and a cap layer on an upper surface of the second electrode. The second electrode may be comprised of a second conductor, and the cap layer may have a composition that is free of titanium. The second electrode may be formed by etching a layer of a material formed on a layer of the second conductor to define a hardmask and then modifying the remaining portion of that material in the hardmask to have a comparatively less etch rate, when exposed to a chlorine-based reactive ion etch chemistry, than when initially formed. | 2014-07-24 |
20140203343 | Non-volatile Memory Cell Having A Floating Gate And A Coupling Gate With Improved Coupling Ratio Therebetween - A non-volatile memory cell having a split gate, wherein the floating gate and the coupling/control gate have complimentary non-planar shapes. The shape may be a step shape. An array of such cells and a method of manufacturing the cells are also disclosed. | 2014-07-24 |
20140203344 | 3D MEMORY - Three-dimensional memory cells and methods of making and using the memory cells are discussed generally herein. In one or more embodiments, a three-dimensional vertical memory can include a memory stack. Such a memory stack can include memory cells and a dielectric between adjacent memory cells, each memory cell including a control gate and a charge storage structure. The memory cell can further include a barrier material between the charge storage structure and the control gate, the charge storage structure and the barrier material having a substantially equal dimension. | 2014-07-24 |
20140203345 | NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE - A non-volatile semiconductor memory device is proposed whereby voltage can be more flexibly set in accumulating electric charges into a selected memory cell transistor in comparison with a conventional device. In a non-volatile semiconductor memory device ( | 2014-07-24 |
20140203346 | VERTICAL TYPE SEMICONDUCTOR DEVICES INCLUDING A METAL GATE AND METHODS OF FORMING THE SAME - Vertical type semiconductor devices including a metal gate and methods of forming the vertical type semiconductor devices are provided. The vertical type semiconductor devices may include a channel pattern. The vertical type semiconductor devices may also include first and second gate patterns sequentially stacked on a sidewall of the channel pattern. The first and second gate pattern may include first and second metal elements, respectively and the second gate pattern may have a resistance lower than a resistance of the first gate pattern. | 2014-07-24 |
20140203347 | METHOD OF MAKING A NON-VOLATILE MEMORY (NVM) CELL STRUCTURE - A non-volatile memory device includes a substrate and a charge storage layer. The charge storage layer comprises a bottom layer of oxide, a layer of discrete charge storage elements on the bottom layer of oxide, and a top layer of oxide on the charge storage elements. A control gate is on the top layer of oxide. A surface of the top layer of oxide facing a surface of the control gate is substantially planar. | 2014-07-24 |
20140203348 | SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING THE SAME - Provided is a semiconductor device, which includes a gate electrode crossing over a semiconductor fin disposed on a substrate, a gate dielectric layer disposed between the gate electrode and the semiconductor fin, a channel region having a three dimensional structure defined in the semiconductor fin under the gate electrode, impurity regions disposed in the semiconductor fin at both sides of the gate electrode and spaced apart from the gate electrode, a first interlayer dielectric layer covering an entire surface of the substrate, except for the gate electrode, first contact plugs passing through the first interlayer dielectric layer and contacting the impurity regions, and a second interlayer dielectric layer covering the gate electrode and partially filling a space between the gate electrode and the impurity regions to define an air gap between the gate electrode and the impurity regions. | 2014-07-24 |
20140203349 | METHOD OF PRODUCING A HIGH-VOLTAGE-RESISTANT SEMICONDUCTOR COMPONENT HAVING VERTICALLY CONDUCTIVE SEMICONDUCTOR BODY AREAS AND A TRENCH STRUCTURE - A high-voltage-resistant semiconductor component ( | 2014-07-24 |
20140203350 | Vertical Tunneling Field-Effect Transistor Cell and Fabricating the Same - A tunneling field-effect transistor (TFET) device is disclosed. A frustoconical protrusion structure is disposed over the substrate and protrudes out of the plane of substrate. A drain region is disposed over the substrate adjacent to the frustoconical protrusion structure and extends to a bottom portion of the frustoconical protrusion structure as a raised drain region. A gate stack is disposed over the substrate. The gate stack has a planar portion, which is parallel to the surface of substrate and a gating surface, which wraps around a middle portion of the frustoconical protrusion structure, including overlapping with the raised drain region. An isolation dielectric layer is disposed between the planar portion of the gate stack and the drain region. A source region is disposed as a top portion of the frustoconical protrusion structure, including overlapping with a top portion of the gating surface of the gate stack. | 2014-07-24 |
20140203351 | Vertical Tunneling Field-Effect Transistor Cell and Fabricating the Same - A tunneling field-effect transistor (TFET) device is disclosed. A frustoconical protrusion structure is disposed over a substrate and protruding out of the plane of substrate. A source region is disposed as a top portion of the frustoconical protrusion structure. A sidewall spacer is disposed along sidewall of the source region. A source contact with a critical dimension (CD), which is substantially larger than a width of the source region, is formed on the source region and the sidewall spacer together. | 2014-07-24 |
20140203352 | Vertical Tunneling Field-Effect Transistor Cell and Fabricating the Same - A tunneling field-effect transistor (TFET) device is disclosed. A protrusion structure is disposed over the substrate and protrudes out of the plane of substrate. Isolation features are formed on the substrate. A drain region is disposed over the substrate adjacent to the protrusion structure and extends to a bottom portion of the protrusion structure as a raised drain region. A drain contact is disposed over the drain region and overlap with the isolation feature. | 2014-07-24 |
20140203353 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device includes a first step of forming a fin-shaped semiconductor layer, a first insulating film around the fin-shaped semiconductor layer, and a pillar-shaped semiconductor layer on the fin-shaped semiconductor layer. A second step forms a gate insulating film around the pillar-shaped semiconductor layer, a gate electrode around the gate insulating film, and a gate line. A third step forms a first first-conductivity-type diffusion layer in an upper portion of the pillar-shaped semiconductor layer and a second first-conductivity-type diffusion layer in a lower portion of the pillar-shaped semiconductor layer and an upper portion of the fin-shaped semiconductor layer. A fourth step includes depositing, planarizing, and etching-back a first interlayer insulating film to expose an upper portion of the pillar-shaped semiconductor layer, depositing a first metal, and etching the metal to form a first sidewall around the upper portion of the pillar-shaped semiconductor layer. | 2014-07-24 |
20140203354 | SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor layer of a first conductivity type and a semiconductor layer of a second conductivity type formed thereon. The semiconductor device also includes a body layer extending a first predetermined distance into the semiconductor layer of the second conductivity type and a pair of trenches extending a second predetermined distance into the semiconductor layer of the second conductivity type. Each of the pair of trenches consists essentially of a dielectric material disposed therein and a concentration of doping impurities present in the semiconductor layer of the second conductivity type and a distance between the pair of trenches define an electrical characteristic of the semiconductor device. The semiconductor device further includes a control gate coupled to the semiconductor layer of the second conductivity type and a source region coupled to the semiconductor layer of the second conductivity type. | 2014-07-24 |
20140203355 | FIELD EFFECT TRANSISTOR AND SCHOTTKY DIODE STRUCTURES - In accordance with an embodiment a structure can include a monolithically integrated trench field-effect transistor (FET) and Schottky diode. The structure can include a first gate trench extending into a semiconductor region, a second gate trench extending into the semiconductor region, and a source region flanking a side of the first gate trench. The source region can have a substantially triangular shape, and a contact opening extending into the semiconductor region between the first gate trench and the second gate trench. The structure can include a conductor layer disposed in the contact opening to electrically contact the source region along at least a portion of a slanted sidewall of the source region, and the semiconductor region along a bottom portion of the contact opening. The conductor layer can form a Schottky contact with the semiconductor region. | 2014-07-24 |
20140203356 | SEMICONDUCTOR DEVICE INCLUDING VERTICAL SEMICONDUCTOR ELEMENT - A semiconductor device including a vertical semiconductor element has a trench gate structure and a dummy gate structure. The trench gate structure includes a first trench that penetrates a first impurity region and a base region to reach a first conductivity-type region in a super junction structure. The dummy gate structure includes a second trench that penetrates the base region reach the super junction structure and is formed to be deeper than the first trench. | 2014-07-24 |
20140203357 | Semiconductor Device and Method of Manufacturing the Same - According to a method of manufacturing a semiconductor device, hard mask lines are formed in parallel in a substrate and the substrate between the hard mask lines is etched to form grooves. A portion of the hard mask line and a portion of the substrate between the grooves are etched. A top surface of the etched portion of the substrate between the grooves is higher than a bottom surface of the groove. A conductive layer is formed to fill the grooves. The conductive layer is etched to form conductive patterns in the grooves, respectively. | 2014-07-24 |
20140203358 | SEMICONDUCTOR DEVICE WITH ENHANCED 3D RESURF - A device includes a semiconductor substrate, source and drain regions in the semiconductor substrate and spaced from one another along a first lateral dimension, and a drift region in the semiconductor substrate and through which charge carriers drift during operation upon application of a bias voltage between the source and drain regions. The drift region has a notched dopant profile in a second lateral dimension along an interface between the drift region and the drain region. | 2014-07-24 |
20140203359 | BUTTED SOI JUNCTION ISOLATION STRUCTURES AND DEVICES AND METHOD OF FABRICATION - A structure, a FET, a method of making the structure and of making the FET. The structure including: a silicon layer on a buried oxide (BOX) layer of a silicon-on-insulator substrate; a trench in the silicon layer extending from a top surface of the silicon layer into the silicon layer, the trench not extending to the BOX layer, a doped region in the silicon layer between and abutting the BOX layer and a bottom of the trench, the first doped region doped to a first dopant concentration; a first epitaxial layer, doped to a second dopant concentration, in a bottom of the trench; a second epitaxial layer, doped to a third dopant concentration, on the first epitaxial layer in the trench; and wherein the third dopant concentration is greater than the first and second dopant concentrations and the first dopant concentration is greater than the second dopant concentration. | 2014-07-24 |
20140203360 | REDUCING CONTACT RESISTANCE BY DIRECT SELF-ASSEMBLING - As stated above, methods of forming a source/drain contact for a transistor are disclosed. In one embodiment, a transistor is formed on a semiconductor-on-insulator (SOI) substrate, which includes a semiconductor-on-insulator (SOI) layer, a buried insulator layer and a silicon substrate. This forming can include forming a gate and a source/drain region. A hardmask can then be formed over the transistor and a self-assembling (DSA) polymer can be directed to cover a portion of the source/drain region. A set of trenches can be formed through the hardmask and into the source/drain region using the DSA polymer as a mask. Then the polymer and the hardmask can be stripped, leaving the trenched source/drain region. | 2014-07-24 |
20140203361 | EXTREMELY THIN SEMICONDUCTOR-ON-INSULATOR FIELD-EFFECT TRANSISTOR WITH AN EPITAXIAL SOURCE AND DRAIN HAVING A LOW EXTERNAL RESISTANCE - An aspect of this invention is a method for fabricating an extremely thin semiconductor-on-insulator (ETSOI) field-effect transistor (FET) having an epitaxial source and drain. The method includes providing an ETSOI substrate; forming at least one isolation structure on the ETSOI substrate; forming a gate on the ETSOI substrate; forming a spacer-on the ETSOI substrate; and using an epitaxial growth process to provide a raised source/drain structure having a non-uniform concentration of carbon along a vertical axis. | 2014-07-24 |
20140203362 | SEMICONDUCTOR DEVICES INCLUDING GATES AND DUMMY GATES OF DIFFERENT MATERIALS - Semiconductor devices are provided. The semiconductor devices may include an active pattern and a insulation layer. The semiconductor devices may include a gate that is on the active pattern and that includes a first material, and a dummy gate that is on the insulation layer and that includes a second material different from the first material. | 2014-07-24 |
20140203363 | Extremely Thin Semiconductor-On-Insulator Field-Effect Transistor With An Epitaxial Source And Drain Having A Low External Resistance - An aspect of this invention is a method for fabricating an extremely thin semiconductor-on-insulator (ETSOI) field-effect transistor (FET) having an epitaxial source and drain. The method includes providing an ETSOI substrate; forming at least one isolation structure on the ETSOI substrate; forming a gate on the ETSOI substrate; forming a spacer on the ETSOI substrate; and using an epitaxial growth process to provide a raised source/drain structure having a non-uniform concentration of carbon along a vertical axis. | 2014-07-24 |
20140203364 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - A semiconductor device having an n channel MISFET formed on an SOI substrate including a support substrate, an insulating layer formed on the support substrate and a silicon layer formed on the insulating layer has the following structure. An impurity region for threshold adjustment is provided in the support substrate of a gate electrode so that the silicon layer contains carbon. The threshold value can be adjusted by the semiconductor region for threshold adjustment in this manner. Further, by providing the silicon layer containing carbon, even when the impurity of the semiconductor region for threshold adjustment is diffused to the silicon layer across the insulating layer, the impurity is inactivated by the carbon implanted into the silicon layer. As a result, the fluctuation of the transistor characteristics, for example, the fluctuation of the threshold voltage of the MISFET can be reduced. | 2014-07-24 |
20140203365 | SEMICONDUCTOR DEVICE - There is disclosed a semiconductor device. The device comprises: a silicon layer; a tapered insulating layer formed on the silicon layer; and a plurality of Bipolar CMOS DMOS device layers formed above the tapered insulating layer. The taper of the tapered insulating layer is in the lower surface of the tapered insulating layer. The tapered insulating layer has a substantially planar upper surface and is at least partially recessed in the silicon layer. | 2014-07-24 |
20140203366 | Semiconductor Devices and Methods of Manufacture Thereof - Semiconductor devices and methods of manufacture thereof are disclosed. A complimentary metal oxide semiconductor (CMOS) device includes a PMOS transistor having at least two first gate electrodes comprising a first parameter, and an NMOS transistor having at least two second gate electrodes comprising a second parameter, wherein the second parameter is different than the first parameter. The first parameter and the second parameter may comprise the thickness or the dopant profile of the gate electrode materials of the PMOS and NMOS transistors. The first and second parameter of the at least two first gate electrodes and the at least two second gate electrodes establish the work function of the PMOS and NMOS transistors, respectively. | 2014-07-24 |
20140203367 | Transistor Structure for Electrostatic Discharge Protection - The present invention discloses a transistor structure for electrostatic discharge protection. The structure includes a substrate, a doped well, a first doped region, a second doped region and a third doped region. The doped well is disposed in the substrate and has a first conductive type. The first doped region is disposed in the substrate, encompassed by the doped well and has the first conductive type. The second doped region is disposed in the substrate, encompassed by the doped well and has a second conductive type. The third doped region is disposed in the substrate, encompassed by the doped well and has the second conductive type. A gap is disposed between the first doped region and the second doped region. | 2014-07-24 |
20140203368 | ELECTROSTATIC DISCHARGE PROTECTION DEVICE - The invention provides an electrostatic discharge (ESD) protection device. The ESD protection device includes a semiconductor substrate having an active region. A first well region having a first conductive type is formed in the active region. A first doped region having the first conductive type is formed in the first well region. A first metal contact is disposed on the first doped region. A second metal contact is disposed on the active region, connecting to the first well region. The first metal contact and a second metal contact are separated by a poly pattern or an insulating layer pattern disposed on the first well region. | 2014-07-24 |
20140203369 | FIN FIELD-EFFECT TRANSISTORS AND FABRICATION METHOD THEREOF - A method is provided for fabricating a fin field-effect transistor. The method includes providing a semiconductor substrate, and forming a plurality of fins with hard mask layers and an isolation structure. The process also includes forming a first dummy gate layer on the fins and the isolation structure, and polishing the first dummy gate layer until the hard mask layer is exposed. Further, the method includes removing the hard mask layer to expose a top surface of the fins, and forming a second dummy gate material layer on the first dummy gate material layer. Further, the method also includes etching the second dummy gate layer and the first dummy gate layer to form a dummy gate on each of the fins. | 2014-07-24 |
20140203370 | Semiconductor Device and Fabricating Method Thereof - A semiconductor device is provided. The semiconductor device includes a first fin on a substrate, a first gate electrode formed on the substrate to intersect the first fin, a first elevated source/drain on the first fin on both sides of the first gate electrode, and a first metal alloy layer on an upper surface and sidewall of the first elevated source/drain. | 2014-07-24 |
20140203371 | FINFET DEVICE FORMATION - A method includes patterning a fin on a semiconductor substrate, depositing a local trench isolation (LTI) layer on the semiconductor substrate, patterning a gate stack over a channel region of the fin and over a portion of the LTI layer, depositing a first capping layer over exposed portions of the LTI layer, performing an etching process to remove oxide material from exposed portions of the fin, and epitaxially growing a semiconductor material from exposed portions of the fin to define active regions. | 2014-07-24 |
20140203372 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF - A semiconductor device includes an inter-layer dielectric (ILD) layer over a substrate; and a first gate feature in the ILD layer, the first gate feature comprising a first gate material and having a first resistance, wherein the first gate material comprises a first conductive material. The semiconductor device further includes a second gate feature in the ILD layer, the second gate feature comprising a second gate material and having a second resistance higher than the first resistance, wherein the second material comprises at least 50% by volume silicon oxide. | 2014-07-24 |
20140203373 | DEVICE AND METHODS FOR HIGH-K AND METAL GATE STACKS - A semiconductor device having five gate stacks on different regions of a substrate and methods of making the same are described. The device includes a semiconductor substrate and isolation features to separate the different regions on the substrate. The different regions include a p-type field-effect transistor (pFET) core region, an input/output pFET (pFET IO) region, an n-type field-effect transistor (nFET) core region, an input/output nFET (nFET IO) region, and a high-resistor region. | 2014-07-24 |
20140203374 | N/P Boundary Effect Reduction for Metal Gate Transistors - The present disclosure provides a method of fabricating a semiconductor device. The method includes forming a plurality of dummy gates over a substrate. The dummy gates extend along a first axis. The method includes forming a masking layer over the dummy gates. The masking layer defines an elongate opening extending along a second axis different from the first axis. The opening exposes first portions of the dummy gates and protects second portions of the dummy gates. A tip portion of the opening has a width greater than a width of a non-tip portion of the opening. The masking layer is formed using an optical proximity correction (OPC) process. The method includes replacing the first portions of the dummy gates with a plurality of first metal gates. The method includes replacing the second portions of the dummy gates with a plurality of second metal gates different from the first metal gates. | 2014-07-24 |
20140203375 | Reduced Substrate Coupling for Inductors in Semiconductor Devices - The present disclosure provides reduced substrate coupling for inductors in semiconductor devices. A method of fabricating a semiconductor device having reduced substrate coupling includes providing a substrate having a first region and a second region. The method also includes forming a first gate structure over the first region and a second gate structure over the second region, wherein the first and second gate structures each include a dummy gate. The method next includes forming an inter layer dielectric (ILD) over the substrate and forming a photoresist (PR) layer over the second gate structure. Then, the method includes removing the dummy gate from the first gate structure, thereby forming a trench and forming a metal gate in the trench so that a transistor may be formed in the first region, which includes a metal gate, and an inductor component may be formed over the second region, which does not include a metal gate. | 2014-07-24 |
20140203376 | FINFET INTEGRATED CIRCUITS WITH UNIFORM FIN HEIGHT AND METHODS FOR FABRICATING THE SAME - Methods for fabricating FinFET integrated circuits with uniform fin height and ICs fabricated from such methods are provided. A method includes etching a substrate using an etch mask to form fins. A first oxide is formed between the fins. A first etch stop is deposited on the first oxide. A second oxide is formed on the first etch stop. A second etch stop is deposited on the second oxide. A third oxide is deposited overlying the second etch stop. An STI extends from at least a surface of the substrate to at least a surface of the second etch stop overlying the fins to form a first active region and a second active region. The first etch stop overlying the fins is removed. The third oxide is removed to expose the second etch stop. A gate stack is formed overlying a portion of each of the fins. | 2014-07-24 |
20140203377 | SEMICONDUCTOR DEVICES - Semiconductor devices include a first gate pattern provided on the first active region, a second gate pattern over the first active region, a third gate pattern over the second active region, and a fourth gate pattern over the second active region. The second gate pattern is parallel to the first gate pattern in a first direction. The third gate pattern has an asymmetric shape to the first gate pattern with respect to the first direction, and the fourth gate pattern is parallel to the third gate pattern in the first direction, and has an asymmetric shape to the second gate pattern with respect to the first direction. MOS transistors having good properties may be provided in a narrow horizontal area. The MOS transistors may be used in highly stacked semiconductor devices. | 2014-07-24 |
20140203378 | Adaptive Fin Design for FinFETs - A method of designing a standard cell includes determining a minimum fin pitch of semiconductor fins in the standard cell, wherein the semiconductor fins are portions of FinFETs; and determining a minimum metal pitch of metal lines in a bottom metal layer over the standard cell, wherein the minimum metal pitch is greater than the minimum fin pitch. The standard cell is placed in an integrated circuit and implemented on a semiconductor wafer. | 2014-07-24 |
20140203379 | INTEGRATION OF LAMINATE MEMS IN BBUL CORELESS PACKAGE - An apparatus including a die including a first side and an opposite second side including a device side with contact points and lateral sidewalls defining a thickness of the die; a build-up carrier coupled to the second side of the die, the build-up carrier including a plurality of alternating layers of conductive material and insulating material, wherein at least one of the layers of conductive material is coupled to one of the contact points of the die; and at least one device within the build-up carrier disposed in an area void of a layer of patterned conductive material. A method and an apparatus including a computing device including a package including a microprocessor are also disclosed. | 2014-07-24 |
20140203380 | CHIP PACKAGE COMPRISING A MICROPHONE STRUCTURE AND A METHOD OF MANUFACTURING THE SAME - In various embodiments, a method for manufacturing a chip package is provided. The method includes arranging a chip over a substrate, the chip including a microphone structure and an opening to the microphone structure; and encapsulating the chip with encapsulation material such that the opening is kept at least partially free from the encapsulation material. | 2014-07-24 |