30th week of 2012 patent applcation highlights part 15 |
Patent application number | Title | Published |
20120187390 | ORGANIC ELECTROLUMINESCENCE ELEMENT, DISPLAY DEVICE USING ORGANIC ELECTROLUMINESCENCE ELEMENT, AND METHOD OF MANUFACTURING ORGANIC ELECTROLUMINESCENCE ELEMENT - One embodiment of the present invention is an organic electroluminescence element including: a substrate; a first electrode that is formed on the substrate; a luminescent medium layer that includes at least an organic luminescent layer and one or more functional layers other than the organic luminescent layer formed on the first electrode; and a second electrode that faces the first electrode with the luminescent medium layer interposed therebetween, wherein at least one functional layer formed between the first electrode and the organic luminescent layer includes first and second metal compounds and the functional layer is a functional layer in which a gradient is obtained at least partially in a film thickness direction for a ratio of the first metal compound to the second metal compound. | 2012-07-26 |
20120187391 | AROMATIC AMINE DERIVATIVE, ORGANIC DEVICE MATERIAL AND HOLE-INJECTION/TRANSPORT MATERIAL AND ORGANIC ELECTROLUMINESCENT ELEMENT MATERIAL EACH COMPRISING THE DERIVATIVE, AND ORGANIC ELECTROLUMINESCENT ELEMENT - An aromatic amine derivative represented by the following formula (1), wherein L is a linking group, Z is a group represented by the following formula (2) and A | 2012-07-26 |
20120187392 | IMIDAZOPYRIDINE DERIVATIVES AND ORGANIC ELECTROLUMINESCENT ELEMENTS CONTAINING SAME - An imidazopyridine derivative shown by the following formula (1). | 2012-07-26 |
20120187393 | THIN FILM TRANSISTOR, ACTIVE MATRIX SUBSTRATE, AND MANUFACTURING METHOD THEREOF - A thin film transistor includes a gate electrode, a semiconductor layer, and a source electrode and a drain electrode placed on the semiconductor layer and electrically connected with the semiconductor layer. The semiconductor layer includes a light-transmitting semiconductor film and an ohmic conductive film placed on the light-transmitting semiconductor film and having a lower light transmittance than the light-transmitting semiconductor film. The ohmic conductive film is formed not to protrude from the light-transmitting semiconductor film. The ohmic conductive film is formed in separate parts with a channel part between the source electrode and the drain electrode interposed therebetween. The source electrode and the drain electrode are connected to the light-transmitting semiconductor film through the ohmic conductive film. | 2012-07-26 |
20120187394 | Display Device, Light-Emitting Device, Lighting Device, and Electronic Appliance - A light energy reuse type display device, light-emitting device, and lighting device with low power consumption, which efficiently convert light emitted from a light source (including light emission from a light-emitting element) into electric power, are provided. A photoelectric conversion element interposed between a pair of substrates functions as a color filter (a colored layer); thus, light emitted from a light source (including light emission from a light-emitting element) is efficiently converted into electric power, and a light energy reuse type display device, light-emitting device, and lighting device with low power consumption can be provided. | 2012-07-26 |
20120187395 | OXIDE SEMICONDUCTOR ELEMENT AND SEMICONDUCTOR DEVICE - A semiconductor element having high mobility, which includes an oxide semiconductor layer having crystallinity, is provided. The oxide semiconductor layer includes a stacked-layer structure of a first oxide semiconductor film and a second oxide semiconductor film having a wider band gap than the first oxide semiconductor film, which is in contact with the first oxide semiconductor film. Thus, a channel region is formed in part of the first oxide semiconductor film (that is, in an oxide semiconductor film having a smaller band gap) which is in the vicinity of an interface with the second oxide semiconductor film. Further, dangling bonds in the first oxide semiconductor film and the second oxide semiconductor film are bonded to each other at the interface therebetween. Accordingly, a decrease in mobility resulting from an electron trap or the like due to dangling bonds can be reduced in the channel region. | 2012-07-26 |
20120187396 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A base insulating film is formed over a substrate. A first oxide semiconductor film is formed over the base insulating film, and then first heat treatment is performed to form a second oxide semiconductor film. Then, selective etching is performed to form a third oxide semiconductor film. An insulating film is formed over the first insulating film and the third oxide semiconductor film. A surface of the insulating film is polished to expose a surface of the third oxide semiconductor film, so that a sidewall insulating film is formed in contact with at least a side surface of the third oxide semiconductor film. Then, a source electrode and a drain electrode are formed over the sidewall insulating film and the third oxide semiconductor film. A gate insulating film and a gate electrode are formed. | 2012-07-26 |
20120187397 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device which includes an oxide semiconductor and has favorable electrical characteristics is provided. In the semiconductor device, an oxide semiconductor film and an insulating film are formed over a substrate. Side surfaces of the oxide semiconductor film are in contact with the insulating film. The oxide semiconductor film includes a channel formation region and regions containing a dopant between which the channel formation region is sandwiched. A gate insulating film is formed on and in contact with the oxide semiconductor film. A gate electrode with sidewall insulating films is formed over the gate insulating film. A source electrode and a drain electrode are formed in contact with the oxide semiconductor film and the insulating film. | 2012-07-26 |
20120187398 | LIGHT EMITTING DEVICE - Embodiments are about light emitting devices having high bonding force between the support member and the light emitting structure and reliability. The light emitting device in an embodiment may include a support member, a light emitting structure disposed on the support member, wherein the light emitting structure including a first semiconductor layer, a second semiconductor layer, and an active layer between the first and second semiconductor layers, an electrode bonding layer disposed between the support member and the light emitting structure, and a third semiconductor layer disposed between the support member and the electrode bonding layer, wherein the third semiconductor including at least one of elements included in at least one of the first and second layers. | 2012-07-26 |
20120187399 | SUBSTRATE FOR FLEXIBLE DEVICE, THIN FILM TRANSISTOR SUBSTRATE FOR FLEXIBLE DEVICE, FLEXIBLE DEVICE, SUBSTRATE FOR THIN FILM ELEMENT, THIN FILM ELEMENT, THIN FILM TRANSISTOR, METHOD FOR MANUFACTURING SUBSTRATE FOR THIN FILM ELEMENT, METHOD FOR MANUFACTURING THIN FILM ELEMENT, AND METHOD FOR MANUFACTURING THIN FILM TRANSISTOR - Disclosed is a substrate for a flexible device which, when a TFT is produced on a flexible substrate in which a metal layer and a polyimide layer are laminated, can suppress deterioration of the electrical performance of the TFT due to the surface irregularities of the metal foil surface and can suppress detachment or cracks of the TFT. Also disclosed is a substrate for a thin film element which has excellent surface smoothness and is capable of suppressing deterioration of the characteristics of thin film elements. Also disclosed are methods for manufacturing substrates for thin film elements. | 2012-07-26 |
20120187400 | TEST STRUCTURE FOR DETECTION OF GAP IN CONDUCTIVE LAYER OF MULTILAYER GATE STACK - A semiconductor structure including a test structure for detection of a gap in a conductive layer of the semiconductor structure includes a semiconductor substrate; the test structure, the test structure being located on the semiconductor substrate, the test structure comprising a multilayer gate stack, wherein the multilayer gate stack includes a single conductive layer region including: a gate dielectric located on the semiconductor substrate; the conductive layer located on the gate dielectric; and an undoped amorphous silicon layer located on the conductive layer; and wherein the test structure is configured to detect the presence of the gap in the conductive layer. | 2012-07-26 |
20120187401 | DEVICE ALLOWING SUPPRESSION OF STRESS ON CHIP - A device includes: a first substrate including a plurality of first electrodes; a plurality of chips each including a plurality of through electrodes, the chips being stacked with each other such that the through electrodes of a lower one of the chips are connected respectively the through electrodes of an upper one of the chips to provide a chip stacked body; and a second substrate cooperating the first substrate to sandwich the chip stacked body between the first and second substrates, the second substrate including a plurality of second electrodes on a first surface that is opposite to a second surface facing the chip stacked body, each of the second electrodes being electrically connected to an associated one of the through electrodes of an uppermost one of the chips of the chip stacked body. | 2012-07-26 |
20120187402 | SEMICONDUCTOR DEVICE AND STACKED SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor chip having first and second surfaces. A first through electrode extends through the semiconductor chip. A first surface electrode is positioned on the first surface of the semiconductor chip and coupled to a first end of the first through electrode. A second surface electrode is positioned on the second surface of the semiconductor chip. The second surface electrode is coupled to a second end of the first through electrode. A second through electrode extends through the semiconductor chip and has third and fourth ends. A third surface electrode is positioned on the second surface of the semiconductor chip and is coupled to the fourth end of the second through electrode. The semiconductor device is free of a surface electrode on the first surface of the semiconductor chip and is coupled to the third end of the second through electrode. | 2012-07-26 |
20120187403 | TEST DEVICE AND A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - A test device includes a semiconductor substrate having a first test region and a second test region defined thereon, wherein a layout of the first test region includes first active regions separated from each other by isolation regions in the semiconductor substrate, second active regions formed between the first active regions, first gate lines formed on the semiconductor substrate, wherein each of the first gate lines has a first end adjacent to one of the first active regions and a second end adjacent to an end of one of the second active regions, respectively, first shared contacts each formed over a respective one of the second ends of the first gate lines and an upper part of one of the first active regions, and first nodes formed on the first shared contacts to be electrically connected to the first shared contacts, respectively. | 2012-07-26 |
20120187404 | DISPLAY DEVICE AND METHOD OF FABRICATING THE SAME - Provided is a display device that includes: a gate line disposed on a substrate, the gate line including a protruding gate electrode; a data line extending across the gate line, the data line having first and second segments spaced apart from each other; a semiconductor pattern overlapping with the gate electrode; a drain electrode that contacts a drain region of the semiconductor pattern and connects the first and second segments; a source electrode that contacts a source region of the semiconductor pattern; and a storage electrode overlapping with the data line. | 2012-07-26 |
20120187405 | THIN FILM TRANSISTOR ARRAY SUBSTRATE, MANUFACTURING METHOD THEREOF, AND LIQUID CRYSTAL DISPLAY DEVICE - A TFT array substrate includes a plurality of pixels arranged in a matrix, in which the pixel includes a thin film transistor, a pixel electrode conductively connected to a drain electrode, and a common electrode that is formed opposite the pixel electrode with an insulation film interposed therebetween. In the TFT array substrate, when one of the pixels is focused, the pixel electrode is divided into a plurality of divided pixel electrodes and includes a plurality of branch conductive parts that conductively connect each of the drain electrode and the plurality of divided pixel electrodes, and in plane view, the common electrode is not formed in at least a part of a formation region of the plurality of branch conductive parts. | 2012-07-26 |
20120187406 | THIN FILM TRANSISTOR SUBSTRATE AND DISPLAY APPARATUS USING THE SAME AND MANUFACTURING METHOD THEREOF - A thin film transistor substrate, a display apparatus using the same and a manufacturing method thereof are provided. The display apparatus includes a thin film transistor substrate, a top substrate and a display medium layer. The thin film transistor substrate includes a composite plate and several thin film transistors. The composite plate includes a core material structure and two insulation structures. The core material structure includes a metal layer. The two insulation structures are respectively disposed at two sides of the core material structure so as to sandwich the core material structure therebetween. The thin film transistors are disposed on the composite plate. The display medium layer is disposed between the thin film transistor substrate and the top substrate. | 2012-07-26 |
20120187407 | THIN FILM TRANSISTOR AND MANUFACTURING METHOD THEREOF - Disclosed are a thin film transistor and a method of manufacturing the thin film transistor. An electrode layer of the thin film transistor includes a seed layer formed of a transparent conductive material doped with indium gallium zinc oxide (IGZO) and a main layer formed of a transparent conductive material. The thin film transistor includes a substrate, a gate electrode on the substrate, a gate insulation film on the substrate to cover the gate electrode, a semiconductor layer disposed on the gate insulation film in a region corresponding to the gate electrode, an electrode layer having a double layer structure and disposed on the gate insulation film in a manner such that a topside portion of the semiconductor layer is exposed through the electrode layer, and a passivation layer on the gate insulation film to cover the semiconductor layer and the electrode layer. | 2012-07-26 |
20120187408 | MICROCRYSTALLINE SEMICONDUCTOR FILM, METHOD FOR MANUFACTURING THE SAME, AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - An embodiment of the present invention is a microcrystalline semiconductor film having a thickness of more than or equal to 70 nm and less than or equal to 100 nm and including a crystal grain partly projecting from a surface of the microcrystalline semiconductor film. The crystal grain has an orientation plane and includes a crystallite having a size of 13 nm or more. Further, the film density of the microcrystalline semiconductor film is higher than or equal to 2.25 g/cm | 2012-07-26 |
20120187409 | Hybrid Silicon Wafer - A hybrid silicon wafer which is a silicon wafer having a structure wherein monocrystalline silicon is embedded in polycrystalline silicon that is prepared by the unidirectional solidification/melting method. The longitudinal plane of crystal grains of the polycrystalline portion prepared by the unidirectional solidification/melting method is used as the wafer plane, and the monocrystalline silicon is embedded so that the longitudinal direction of the crystal grains of the polycrystalline portion forms an angle of 120° to 150° relative to the cleaved surface of the monocrystalline silicon. Thus provided is a hybrid silicon wafer comprising the functions of both a polycrystalline silicon wafer and a monocrystalline wafer. | 2012-07-26 |
20120187410 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A conventional DRAM needs to be refreshed at an interval of several tens of milliseconds to hold data, which results in large power consumption. In addition, a transistor therein is frequently turned on and off; thus, deterioration of the transistor is also a problem. These problems become significant as the memory capacity increases and transistor miniaturization advances. A transistor is provided which includes an oxide semiconductor and has a trench structure including a trench for a gate electrode and a trench for element isolation. Even when the distance between a source electrode and a drain electrode is decreased, the occurrence of a short-channel effect can be suppressed by setting the depth of the trench for the gate electrode as appropriate. | 2012-07-26 |
20120187411 | Semiconductor Device and Method for Manufacturing the Same - An object of the present invention is to prevent the deterioration of a TFT (thin film transistor). The deterioration of the TFT by a BT test is prevented by forming a silicon oxide nitride film between the semiconductor layer of the TFT and a substrate, wherein the silicon oxide nitride film ranges from 0.3 to 1.6 in a ratio of the concentration of N to the concentration of Si. | 2012-07-26 |
20120187412 | Gallium-Nitride-on-Handle Substrate Materials and Devices and Method of Manufacture - A gallium and nitrogen containing substrate structure includes a handle substrate member having a first surface and a second surface and a transferred thickness of gallium and nitrogen material. The structure has a gallium and nitrogen containing active region grown overlying the transferred thickness and a recessed region formed within a portion of the handle substrate member. The substrate structure has a conductive material formed within the recessed region configured to transfer thermal energy from at least the transferred thickness of gallium and nitrogen material. | 2012-07-26 |
20120187413 | NITRIDE SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - According to one embodiment, a nitride semiconductor device includes a first semiconductor, a second semiconductor layer, a third semiconductor layer, a fourth semiconductor layer, a first electrode, a second electrode and a third electrode. The first, second and fourth semiconductor layers include a nitride semiconductor. The second semiconductor layer is provided on the first semiconductor layer, has a band gap not less than that of the first semiconductor layer. The third semiconductor layer is provided on the second semiconductor layer. The third semiconductor layer is GaN. The fourth semiconductor layer is provided on the third semiconductor layer to have an interspace on a part of the third semiconductor layer, has a band gap not less than that of the second semiconductor layer. The first electrode is provided on a portion of the third semiconductor layer. The fourth semiconductor layer is not provided on the portion. | 2012-07-26 |
20120187414 | SEMICONDUCTOR LIGHT-EMITTING DEVICE AND PROCESS FOR PRODUCTION THEREOF - One aspect of the present invention provides a semiconductor light-emitting device improved in luminance, and also provides a process for production thereof. The process comprises a procedure of forming a relief structure on the light-extraction surface of the device by use of a self-assembled film. In that procedure, the light-extraction surface is partly covered with a protective film so as to protect an area for an electrode to be formed therein. The electrode is then finally formed there after the procedure. The process thus reduces the area incapable, due to thickness of the electrode, of being provided with the relief structure. Between the electrode and the light-extraction surface, a contact layer is formed so as to establish ohmic contact between them. | 2012-07-26 |
20120187415 | METHOD FOR CONDUCTIVITY CONTROL OF (Al,In,Ga,B)N - A method of controlled p-type conductivity in (Al,In,Ga,B)N semiconductor crystals. Examples include {10 | 2012-07-26 |
20120187416 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor substrate having a collector layer in which the carrier concentration is maximized at a carrier concentration peak position that is 1 μm or more from a surface of the semiconductor substrate. The semiconductor device further includes a collector electrode formed in contact with a surface of the collector layer. | 2012-07-26 |
20120187417 | SEMICONDUCTOR DEVICE - A conventional DRAM needs to be refreshed at an interval of several tens of milliseconds to hold data, which results in large power consumption. In addition, a transistor therein is frequently turned on and off; thus, deterioration of the transistor is also a problem. These problems become significant as the memory capacity increases and transistor miniaturization advances. Another problem is that an increase in memory capacity leads to an increase in the area, despite an attempt at integration through advancement of transistor miniaturization. A transistor is provided which includes an oxide semiconductor and has a trench structure including a trench for a gate electrode and a trench for element isolation. In addition, a plurality of memory elements each including the transistor having a trench structure and including an oxide semiconductor is stacked in a semiconductor device, whereby the circuit area of the semiconductor device can be reduced. | 2012-07-26 |
20120187418 | SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME - The present application provides a semiconductor structure and a method for manufacturing the same. The semiconductor structure comprises a semiconductor substrate, a semiconductor fin located on the semiconductor substrate, and an etch stop layer located between the semiconductor substrate and the semiconductor fin, wherein a lateral sidewall of the semiconductor fin is substantially on the Si { | 2012-07-26 |
20120187419 | Production Method for a Unipolar Semiconductor Component and Semiconductor Device - The invention relates to a production method for a unipolar semiconductor component having a drift layer ( | 2012-07-26 |
20120187420 | STRUCTURE AND METHOD TO MAKE REPLACEMENT METAL GATE AND CONTACT METAL - An electrical device is provided that in one embodiment includes a p-type semiconductor device having a first gate structure that includes a gate dielectric that is present on the semiconductor substrate, a p-type work function metal layer, a metal layer composed of titanium and aluminum, and a metal fill composed of aluminum. An n-type semiconductor device is also present on the semiconductor substrate that includes a second gate structure that includes a gate dielectric, a metal layer composed of titanium and aluminum, and a metal fill composed of aluminum. An interlevel dielectric is present over the semiconductor substrate. The interlevel dielectric includes interconnects to the source and drain regions of the p-type and n-type semiconductor devices. The interconnects are composed of a metal layer composed of titanium and aluminum, and a metal fill composed of aluminum. The present disclosure also provides a method of forming the aforementioned structure. | 2012-07-26 |
20120187421 | VERTICAL JUNCTION FIELD EFFECT TRANSISTORS AND DIODES HAVING GRADED DOPED REGIONS AND METHODS OF MAKING - Semiconductor devices and methods of making the devices are described. The devices can be junction field-effect transistors (JFETs) or diodes such as junction barrier Schottky (JBS) diodes or PiN diodes. The devices have graded p-type semiconductor layers and/or regions formed by epitaxial growth. The methods do not require ion implantation. The devices can be made from a wide-bandgap semiconductor material such as silicon carbide (SiC) and can be used in high temperature and high power applications. | 2012-07-26 |
20120187422 | SEMICONDUCTOR SUBSTRATE, METHOD FOR PRODUCING SEMICONDUCTOR SUBSTRATE, SUBSTRATE FOR SEMICONDUCTOR GROWTH, METHOD FOR PRODUCING SUBSTRATE FOR SEMICONDUCTOR GROWTH, SEMICONDUCTOR ELEMENT, LIGHT-EMITTING ELEMENT, DISPLAY PANEL, ELECTRONIC ELEMENT, SOLAR CELL ELEMENT, AND ELECTRONIC DEVICE - A semiconductor substrate that includes a semiconductor layer that exhibits high crystallinity includes a graphite layer formed of a heterocyclic polymer obtained by condensing an aromatic tetracarboxylic acid and an aromatic tetramine, and a semiconductor layer that is grown on the surface of the graphite layer, or includes a substrate that includes a graphite layer formed of a heterocyclic polymer obtained by condensing an aromatic tetracarboxylic acid and an aromatic tetramine on its surface, a buffer layer that is grown on the surface of the graphite layer, and a semiconductor layer that is grown on the surface of the buffer layer. | 2012-07-26 |
20120187423 | LIGHT EMITTING DIODE DEVICE - A manufacturing method of an LED device includes the following steps. First, a substrate and at least one LED disposed on the substrate are provided. Next, a porous material layer having a plurality of pores is formed on a surface of the LED. Finally, a plurality of nanocrystals are formed in the pores to construct a phosphor layer on the surface of the LED. | 2012-07-26 |
20120187424 | LIGHT EMITTING DIODE - Exemplary embodiments of the present invention relate to light emitting diodes including a plurality of light emitting cells on a substrate to be suitable for AC driving. The light emitting diode includes a substrate and a plurality of light emitting cell formed on the substrate. Each light emitting cell includes a first region at a boundary of the light emitting cell and a second region opposite to the first region. A first electrode pad is formed in the first region of the light emitting cell. A second electrode pad having a linear shape is disposed to face the first electrode pad while regionally defining a peripheral region together with the boundary of the second region. A wire connects the first electrode pad to the second electrode pad between two adjacent light emitting cells. | 2012-07-26 |
20120187425 | ORGANIC EL DISPLAY AND ELECTRONIC APPARATUS - Disclosed herein is an organic EL display device in which pixels each including an organic EL element formed by interposing an organic layer between an anode electrode and a cathode electrode are arranged in a matrix, the organic EL display device including: a common layer configured to be included in the organic EL element and be formed in the organic layer in common to the pixels; and a metal interconnect configured to surround periphery of the anode electrode and be electrically connected to the organic layer, wherein potential of the metal interconnect is set to a potential lower than potential of the anode electrode in a non-light-emission state of the organic EL element. | 2012-07-26 |
20120187426 | LIGHT SOURCE UNIT AND DEVICE USING SAME - Provided is a light source unit in which locating components are mounted on a substrate together with LEDs forming a light emitting portion, and with this, the light source unit can be more easily replaced, and the number of components can be reduced. | 2012-07-26 |
20120187427 | LAMINATING ENCAPSULANT FILM CONTAINING PHOSPHOR OVER LEDS - A process is described for wavelength conversion of LED light using phosphors. LED dies are tested for correlated color temperature (CCT), and binned according to their color emission. The LEDs in each_bin are mounted on a single submount to form an array of LEDs. Various thin sheets of a flexible encapsulant (e.g., silicone) infused with one or more phosphors are preformed, where each sheet has different color conversion properties. An appropriate sheet is placed over an array of LED mounted on a submount, and the LEDs are energized. The resulting light is measured for CCT. If the CCT is acceptable, the phosphor sheet is permanently laminated onto the LEDs and submount. By selecting a different phosphor sheet for each bin of LEDs, the resulting CCT is very uniform across all bins. | 2012-07-26 |
20120187428 | METHOD FOR THE PRODUCTION OF WHITE LEDS AND WHITE LED LIGHT SOURCE - For the production of a white LED having a predetermined color temperature, a blue LED ( | 2012-07-26 |
20120187429 | LED LIGHT SOURCE AND METHOD OF MANUFACTURING THE SAME - After the LEDs | 2012-07-26 |
20120187430 | Packaging Photon Building Blocks Having Only Top Side Connections in a Molded Interconnect Structure - Standardized photon building blocks are packaged in molded interconnect structures to form a variety of LED array products. No electrical conductors pass between the top and bottom surfaces of the substrate upon which LED dies are mounted. Microdots of highly reflective material are jetted onto the top surface. Landing pads on the top surface of the substrate are attached to contact pads disposed on the underside of a lip of the interconnect structure. In a solder reflow process, the photon building blocks self-align within the interconnect structure. Conductors in the interconnect structure are electrically coupled to the LED dies in the photon building blocks through the contact pads and landing pads. Compression molding is used to form lenses over the LED dies and leaves a flash layer of silicone covering the landing pads. The flash layer laterally above the landing pads is removed by blasting particles at the flash layer. | 2012-07-26 |
20120187431 | LIGHT EMITTING DIODES WITH LOW JUNCTION TEMPERATURE AND SOLID STATE BACKLIGHT COMPONENTS INCLUDING LIGHT EMITTING DIODES WITH LOW JUNCTION TEMPERATURE - A light emitting diode chip a support layer having a first face and a second face opposite the first face, a diode region on the first face of the support layer, and a bond pad on the second face of the support layer. The bond pad includes a gold-tin structure having a weight percentage of tin of | 2012-07-26 |
20120187432 | LED Platform with Membrane - An LED package comprises:
| 2012-07-26 |
20120187433 | STRUCTURE OF LIGHT SOURCE MODULE AND MANUFACTURING METHOD THEREOF - A circuit substrate and at least one light-emitting diode (LED) chip are adhered to a heatsink substrate in sequence, and then a packaging material is formed on the LED chip. The circuit substrate has at least one through hole, and the LED chip is buried in the through hole on the circuit substrate so that the LED chip is in direct contact with the heatsink substrate, so as to reduce the thermal resistance between the LED chip and the heatsink substrate, thus effectively dissipating the heat energy of the LED chip through the heatsink substrate. | 2012-07-26 |
20120187434 | Surface-Mount LED with Optical Lens - The present invention discloses a surface-mount LED with optical lens, comprising a surface-mount LED with a flat plane on the top thereof and an optical lens packaged on said flat plane. The present invention decreases the light emitting angle and increase the luminosity of the LED through the light convergence effect by the optical lens; the present invention also can effectively enhance the usage of the side light rays through the light reflection effect of the cylinder, no extra reflection cup is required; under the condition of the same luminance being provided, less LEDs are used according to the present invention, thereby saving energy and reducing cost. | 2012-07-26 |
20120187435 | METHOD FOR MANUFACTURING A STRUCTURE WITH A TEXTURED SURFACE AS A MOUNTING FOR AN ORGANIC LIGHT-EMITTING DIODE DEVICE, AND OLED STRUCTURE WITH A TEXTURED SURFACE - A production method and a structure having a textured surface forming the support for an organic-light-emitting-diode device, which structure is provided on a transparent substrate made of mineral glass on which is optionally deposited an interface film made of mineral glass, the profile of the texture of the surface comprising protrusions and troughs which are defined by an FT or a roughness parameter Rdq such that the protrusions are not too pointed and such that an increase in the extraction efficiency is ensured. The method especially consists in depositing on the glass substrate a coating film and in ensuring a contraction of the assembly by heating and cooling. | 2012-07-26 |
20120187436 | LIGHT EMITTING DIODE DEVICE AND MANUFACTURING METHOD THEREOF - A light emitting diode (LED) device includes a substrate, a supporting member, an electrode layer, an LED chip and an encapsulant. The substrate has a first surface and a second surface. The substrate defines a hole extending through the first surface and the second surface. The supporting member is attached to the second surface of the substrate and covers the hole. The supporting member and the substrate cooperatively define a cavity. The electrode layer is arranged on the first surface of the substrate and an inner surface of the cavity. The encapsulant is arranged on the electrode layer and covers the LED chip. | 2012-07-26 |
20120187437 | LIGHT-EMITTING DEVICE PACKAGE AND METHOD OF MANUFACTURING THE LIGHT-EMITTING DEVICE PACKAGE - A light-emitting device package having improved connection reliability of a bonding wire, heat dissipation properties, and light quality due to post-molding and a method of manufacturing the light-emitting device package. The light-emitting device package includes, for example, a wiring substrate having an opening; a light-emitting device that is disposed on the wiring substrate and covers the opening; a bonding wire electrically connecting a bottom surface of the wiring substrate to a bottom surface of the light-emitting device via the opening; a molding member that surrounds a side surface of the light-emitting device and not a top surface of the light-emitting device, which is an emission surface, is formed on a portion of a top surface of the wiring substrate, and is formed in the opening of the wiring substrate to cover the bonding wire; and a solder resist and a bump formed on the bottom surface of the wiring substrate. | 2012-07-26 |
20120187438 | LIGHT EMITTING DEVICE AND FABRICATING METHOD THEREOF - Disclosed is a light emitting device including a support substrate, a transistor unit disposed at one side of the upper surface of the support substrate, a light emitting device unit disposed at the other side of the upper surface of the support substrate, and an insulating layer disposed between the transistor unit and the light emitting device unit and between the support substrate and the transistor unit and isolating the transistor unit from the light emitting device unit. | 2012-07-26 |
20120187439 | SOLAR CELL ASSEMBLY AND ALSO SOLAR CELL ARRANGEMENT - The invention relates to a light-absorbing or light-emitting solar cell assembly and also a solar cell arrangement which is constructed from 2 to 10,000 of the solar cell assemblies according to the invention. | 2012-07-26 |
20120187440 | LUMINOUS DEVICES, PACKAGES AND SYSTEMS CONTAINING THE SAME, AND FABRICATING METHODS THEREOF - The present invention is directed to a vertical-type luminous device and high through-put methods of manufacturing the luminous device. These luminous devices can be utilized in a variety of luminous packages, which can be placed in luminous systems. The luminous devices are designed to maximize light emitting efficiency and/or thermal dissipation. Other improvements include an embedded zener diode to protect against harmful reverse bias voltages. | 2012-07-26 |
20120187441 | LED LIGHTING ARRANGEMENT INCLUDING LIGHT EMITTING PHOSPHOR - A method of manufacturing an LED lighting arrangement, comprises: receiving an optical component having a diffusing material that is light diffusive and at least one photoluminescent material that is excitable by light of a first wavelength range and which emits light of a second wavelength range; receiving an LED assembly that is operable to generate the light of the first wavelength range and mounting the optical component to the LED assembly to form the LED lighting arrangement. The optical component having the diffusing and photoluminescent materials is mass produced separately from the LED assembly and can be selected such that light generated by the optical component combined with the light generated by the LED assembly corresponds to light of a selected color. Also disclosed are LED lighting arrangements, components for LED lighting arrangements and methods of fabricating an optical component. | 2012-07-26 |
20120187442 | LIGHT EMITTING ELEMENT AND METHOD FOR MANUFACTURING LIGHT EMITTING ELEMENT - A light emitting element includes an optical semiconductor layer ( | 2012-07-26 |
20120187443 | LIGHT EMITTING CHIP AND METHOD FOR MANUFACTURING THE SAME - A light emitting chip includes a substrate, a buffer layer formed on the substrate and including a number of horizontally grown nitride nanostructures, a cap layer grows from a top of the nitride nanostructures, and a light emitting structure formed on the cap layer. The light emitting structure sequentially comprises a first semiconductor layer connected to the cap layer, a light emitting layer, and a second semiconductor layer. | 2012-07-26 |
20120187444 | TEMPLATE, METHOD FOR MANUFACTURING THE TEMPLATE AND METHOD FOR MANUFACTURING VERTICAL TYPE NITRIDE-BASED SEMICONDUCTOR LIGHT EMITTING DEVICE USING THE TEMPLATE - Disclosed herein is a method for manufacturing a template. The method includes growing a first nitride layer on a substrate; etching a top surface of the first nitride layer by supplying a chloride-based etching gas thereto; forming a plurality of first voids by growing a second nitride layer on the top surface of the first nitride layer; etching a top surface of the second nitride layer by supplying the etching gas thereto; and forming a plurality of second voids by growing a third nitride layer on the top surface of the second nitride layer. A method for manufacturing a nitride-based semiconductor light emitting device using the template is also disclosed. As a result, stress between lattices and dislocation defects are reduced by a plurality of voids formed in a nitride buffer layer, thereby improving quality of nitride layers grown in a template. In the case where a light emitting device is manufactured using the template, it is possible to improve workability of the manufacturing process and to enhance luminous efficacy of the light emitting device. | 2012-07-26 |
20120187445 | TEMPLATE, METHOD FOR MANUFACTURING THE TEMPLATE, AND METHOD FOR MANUFACTURING VERTICAL TYPE NITRIDE-BASED SEMICONDUCTOR LIGHT EMITTING DEVICE USING THE TEMPLATE - Disclosed is a method for manufacturing a template. The method includes growing a first nitride layer containing a Group-III material on a substrate; forming a plurality of etch barriers having different etching characteristics from the first nitride layer on the first nitride layer; forming a pillar-shaped nano structure by etching the first nitride layer in a pattern of the etch barriers using a chloride-based gas; and forming the nitride buffer layer having a plurality of voids formed therein by growing a second nitride layer on top of the nano structure. A method for manufacturing a nitride-based semiconductor light emitting device using the template is also disclosed. | 2012-07-26 |
20120187446 | SEMICONDUCTOR LIGHT EMITTING DEVICE AND METHOD FOR MANUFACTURING THE SAME - According to one embodiment, a semiconductor light emitting device includes first and second conductive layers, a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type, and a light emitting part. The second semiconductor layer is provided between the first conductive layer and the first semiconductor layer. The light emitting part is provided between the first and second semiconductor layers. The second conductive layer is in contact with the second semiconductor layer and the first conductive layer between the second semiconductor layer and the first conductive layer. The first and second conductive layers are transmittable to light emitted from the light emitting part. The first conductive layer includes a polycrystal having a first average grain diameter. The second conductive layer includes a polycrystal having a second average grain diameter of 150 nanometers or less and smaller than the first average grain diameter. | 2012-07-26 |
20120187447 | Part having a First and a Second Substrate and Method for the Production Thereof - A unit is provided which comprises a first substrate ( | 2012-07-26 |
20120187448 | GLASS, GLASS COVERING MATERIAL FOR LIGHT-EMITTING DEVICE, AND LIGHT-EMITTING DEVICE - Glass is provided which is capable of covering at a covering treatment temperature of at most 400° C. and which has a low thermal expansion coefficient and excellent weather resistance. Glass comprising, as represented by mol % based on oxides, from 29% to 33% of P | 2012-07-26 |
20120187449 | SEMICONDUCTOR WAFER, SEMICONDUCTOR BAR, METHOD OF MANUFACTURING SEMICONDUCTOR WAFER, METHOD OF MANUFACTURING SEMICONDUCTOR BAR, AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor wafer has a plurality of optical semiconductor devices (namely, semiconductor lasers) which are formed from epitaxially grown layers and arranged across the surface of the semiconductor wafer. The InGaAs epitaxial layer of the semiconductor wafer has an opening (or groove) which continuously extends along and between the plurality of optical semiconductor devices, and which exposes the layer underlying the InGaAs epitaxial layer to at least the layer overlying the InGaAs epitaxial layer. The semiconductor wafer may be scribed along this opening to form a vertically extending crack therein. | 2012-07-26 |
20120187450 | STI SILICON NITRIDE CAP FOR FLAT FEOL TOPOLOGY - Transistor devices are formed with a nitride cap over STI regions during FEOL processing. Embodiments include forming a pad oxide layer on a substrate, forming an STI region in the substrate so that the top surface is level with the top surface of the pad oxide, forming a nitride cap on the STI region and on a portion of the pad oxide layer on each side of the STI region, implanting a dopant into the substrate, deglazing the nitride cap and pad oxide layer, removing the nitride cap, and removing the pad oxide layer. Embodiments include forming a silicon germanium channel (c-SiGe) in the substrate prior to deglazing the pad oxide layer. The nitride cap protects the STI regions and immediately adjacent area during processes that tend to degrade the STI oxide, thereby providing a substantially divot free substrate and an STI region with a zero step height for the subsequently deposited high-k dielectric and metal electrode. | 2012-07-26 |
20120187451 | SEMICONDUCTOR ELEMENT - According to one embodiment, the semiconductor element includes a semi-insulating substrate which has a first first-conductivity-type layer. The semiconductor element includes a first semiconductor layer. The first semiconductor layer contains non-doped Al | 2012-07-26 |
20120187452 | SEMICONDUCTOR ELEMENT - According to one embodiment, the semiconductor element includes a first semiconductor layer. The first semiconductor layer contains Al | 2012-07-26 |
20120187453 | INSULATING LAYERS ON DIFFERENT SEMICONDUCTOR MATERIALS - A semiconductor structure is provided that includes a substrate having disposed thereon a silicon layer and a silicon germanium layer. An insulator is disposed between the silicon layer and the silicon germanium layer. An optional silicon nitride film is disposed conformally on the silicon layer and the silicon germanium layer, and a SiO | 2012-07-26 |
20120187454 | NITRIDE SUBSTRATES, THIN FILMS, HETEROSTRUCTURES AND DEVICES FOR ENHANCED PERFORMANCE, AND METHODS OF MAKING THE SAME - The present invention provides nitride semiconductors having a moderate density of basal plane stacking faults and a reduced density of threading dislocations, various products based on, incorporating or comprising the nitride semiconductors, including without limitation substrates, template films, templates, heterostructures with or without integrated substrates, and devices, and methods for fabrication of templates and substrates comprising the nitride semiconductors. | 2012-07-26 |
20120187455 | PHOTOSENSOR AND DISPLAY DEVICE - The sensitivity of a photosensor is improved without decreasing read-out efficiency. The photosensor includes: a photodiode (D | 2012-07-26 |
20120187456 | MAGNETIC RANDOM ACCESS MEMORY AND MANUFACTURING METHOD THEREOF - According to one embodiment, there is disclosed a magnetic random access memory comprising: a semiconductor substrate; a selective transistor formed at the surface region of the semiconductor substrate and having a gate electrode, a gate insulating film, a source and a drain; and a magnetoresistive element formed on the drain including a magnetic storage layer in which a magnetization direction is variable, a magnetic reference layer in which a magnetization direction is fixed, and a nonmagnetic layer sandwiched between the magnetic storage layer and the magnetic reference layer. | 2012-07-26 |
20120187457 | SEMICONDUCTOR DEVICE - A semiconductor device such as an ID chip of the present invention includes an integrated circuit using a semiconductor element formed by using a thin semiconductor film, and an antenna connected to the integrated circuit. It is preferable that the antenna is formed integrally with the integrated circuit, since the mechanical strength of an ID chip can be enhanced. Note that the antenna used in the present invention also includes a conducting wire that is wound round circularly or spirally and fine particles of a soft magnetic material are arranged between the conducting wires. Specifically, an insulating layer in which fine particles of a soft magnetic material are arranged between the conducting wires. Specifically, an insulating layer in which fine particles of a soft magnetic material are included is arranged between the conducting wires. | 2012-07-26 |
20120187458 | Asymmetric High-Voltage JFET and Manufacturing Process - A high voltage JFET has a deep well of a first type of conductivity made in a semiconductor substrate, a further well of an opposite second type of conductivity arranged in the deep well, a shallow well of a first type of conductivity arranged in the further well, a first contact region for source and a second contact region for drain arranged in the further well, a third contact region for gate arranged between the first contact region and the second contact region in the shallow well, a first distance between the first contact region and the third contact region being smaller than a second distance between the second contact region and the third contact region, and an electrical connection between the first contact region and the second contact region via at least one channel region present between the deep well and the shallow well in the further well. | 2012-07-26 |
20120187459 | SEMICONDUCTOR DEVICE INCLUDING AN EPITAXY REGION - A method is described which includes providing a substrate and forming a first spacer material layer abutting a gate structure on the substrate. A second spacer material layer is formed adjacent and abutting the gate structure and overlying the first spacer material layer. The first spacer material layer and the second spacer material layer are then etched concurrently to form first and second spacers, respectively. An epitaxy region is formed (e.g., grown) on the substrate which includes an interface with each of the first and second spacers. The second spacer may be subsequently removed and the first spacer remain on the device decreases the aspect ratio for an ILD gap fill. An example composition of the first spacer is SiCN. | 2012-07-26 |
20120187460 | METHOD FOR FORMING METAL SEMICONDUCTOR ALLOYS IN CONTACT HOLES AND TRENCHES - A method of forming a semiconductor device is provided that includes forming a first metal semiconductor alloy on a semiconductor containing surface, forming a dielectric layer over the first metal semiconductor alloy, forming an opening in the dielectric layer to provide an exposed surface the first metal semiconductor alloy, and forming a second metal semiconductor alloy on the exposed surface of the first metal semiconductor alloy. In another embodiment, the method includes forming a gate structure on a channel region of a semiconductor substrate, forming a dielectric layer over at least a source region and a drain region, forming an opening in the dielectric layer to provide an exposed surface the semiconductor substrate, forming a first metal semiconductor alloy on the exposed surface of the semiconductor substrate, and forming a second metal semiconductor alloy on the first metal semiconductor alloy. | 2012-07-26 |
20120187461 | SEMICONDUCTOR COMPONENT WITH A WINDOW OPENING AS AN INTERFACE FOR AMBIENT COUPLING - A window opening in a semiconductor component is produced on the basis of a gate structure which serves as an efficient etch resist layer in order to reliably etch an insulation layer stack without exposing the photosensitive semiconductor area. The polysilicon in the gate structure is then removed on the basis of an established gate etching process, with the gate insulation layer preserving the integrity of the photosensitive semiconductor material. | 2012-07-26 |
20120187462 | HIGH OPTICAL EFFICIENCY CMOS IMAGE SENSOR - High optical efficiency CMOS image sensors capable of sustaining pixel sizes less than 1.2 microns are provided. Due to high photodiode fill factors and efficient optical isolation, microlenses are unnecessary. Each sensor includes plural imaging pixels having a photodiode structure on a semiconductor substrate adjacent a light-incident upper surface of the image sensor. An optical isolation grid surrounds each photodiode structure and defines the pixel boundary. The optical isolation grid extends to a depth of at least the thickness of the photodiode structure and prevents incident light from penetrating through the incident pixel to an adjacent pixel. A positive diffusion plug vertically extends through a portion of the photodiode structure. A negative diffusion plug vertically extends into the semiconductor substrate for transferring charge generated in the photodiode to a charge collecting region within the semiconductor substrate. Pixel circuitry positioned beneath the photodiode controls charge transfer to image readout circuitry. | 2012-07-26 |
20120187463 | CMOS IMAGE SENSORS INCLUDING BACKSIDE ILLUMINATION STRUCTURE AND METHOD OF MANUFACTURING IMAGE SENSOR - An image sensor having a backside illumination structure can include a photo diode unit in a first wafer, where the photo diode unit includes photo diodes and transfer gate transistors coupled to respective ones of the photo diodes. A wiring line unit can be included on a second wafer that is bonded to the photo diode unit, where the wiring line unit includes wiring lines and transistors configured to process signals provided by the photo diode unit and configured to control the photo diode unit. A supporting substrate is bonded to the wiring line unit and a filter unit is located under the first wafer. | 2012-07-26 |
20120187464 | ELECTROMAGNETIC WAVE DETECTING ELEMENT - The present invention is to provide an electromagnetic wave detecting element that can prevent a decrease in light utilization efficiency at sensor portions. The sensor portions are provided so as to correspond to respective intersection portions of scan lines and signal lines, and have semiconductor layer that generate charges due to electromagnetic waves being irradiated, and at whose electromagnetic wave irradiation surface sides upper electrodes are formed, and at whose electromagnetic wave non-irradiation surface sides lower electrodes are formed. Bias voltage is supplied to the respective upper electrodes via respective contact holes by a common electrode line that is formed further toward an electromagnetic wave downstream side than the semiconductor layer. | 2012-07-26 |
20120187465 | ENHANCED CAPACITANCE TRENCH CAPACITOR - An integrated circuit including a trench capacitor has a semiconductor region in which a material composition varies in a quantity of at least one component therein such that the quantity alternates with depth a plurality of times between at least two different values. For example, a concentration of a dopant or a weight percentage of a second semiconductor material, such as germanium, in a semiconductor alloy can alternate between with depth a plurality of times between higher and lower values. The trench capacitor has an undulating capacitor dielectric layer, wherein the undulations of the capacitor dielectric layer are at least partly determined by the undulating interior surface of the trench. Such trench capacitor can provide enhanced capacitance, and can be incorporated in a memory cell such as a dynamic random access memory (“DRAM”) cell, for example. | 2012-07-26 |
20120187466 | NON-VOLATILE SEMICONDUCTOR STORAGE DEVICE - At least some of the memory transistors included in a first memory string are commonly connected to first conductive layers that are connected to at least some of the memory transistors included in a second memory string connected to the same third and fourth conductive layers as the first memory string. At least one of either the memory transistors or the back-gate transistor in the first memory string and at least one of either the memory transistors or the back-gate transistor in the second memory string are connected to the independent first or fifth conductive layers, respectively. | 2012-07-26 |
20120187467 | FLOATING GATES AND METHODS OF FORMATION - The present invention generally relates to a floating gate structure and method of forming the same. The floating gate structure has an upper portion which is wider than a middle portion of the floating gate structure. The upper portion may have a flared, rounded or bulbous shape instead of being pointed or having sharp corners. The reduction in pointed or sharp features of the upper portion reduces the electric field intensity near the upper portion, which decreases current leakage through the interpoly dielectric. The method includes forming a nitride cap on the upper surface of the floating gate structure to assist in shaping the floating gate. The floating gate is then formed using multiple selective oxidation and etching processes. | 2012-07-26 |
20120187468 | METAL CONTROL GATE FORMATION IN NON-VOLATILE STORAGE - Methods for fabricating control gates in non-volatile storage are disclosed. When forming stacks for floating gate memory cells and transistor control gates, a sacrificial material may be formed at the top of the stacks. After insulation is formed between the stacks, the sacrificial material may be removed to reveal openings. In some embodiments, cutouts are then formed in regions in which control gates of transistors are to be formed. Metal is then formed in the openings, which may include the cutout regions. Therefore, floating gate memory cells having at least partially metal control gates and transistors having at least partially metal control gates may be formed in the same process. A barrier layer may be formed prior to depositing the metal in order to prevent silicidation of polysilicon in the control gates. | 2012-07-26 |
20120187469 | METHOD OF MANUFACTURING SEMICONDUCTOR STORAGE DEVICE AND SEMICONDUCTOR STORAGE DEVICE - According to one embodiment, there is provided a method of manufacturing a semiconductor storage device. In the method, any one of Ge, Sn, C, and N is introduced as impurity to a surface of a semiconductor substrate. In the method, the semiconductor substrate is thermally oxidized so that a tunnel insulating film is formed on the surface of the semiconductor substrate to which the impurity is introduced. In the method, a gate having a charge accumulation layer is formed on the tunnel insulating film. In the method, impurity diffusion regions are formed in the semiconductor substrate in a self-aligned manner using the gate. | 2012-07-26 |
20120187470 | GATE STRUCTURES - A method of forming a gate structure includes forming a tunnel insulation layer pattern on a substrate, forming a floating gate on the tunnel insulation layer pattern, forming a dielectric layer pattern on the floating gate, the dielectric layer pattern including a first oxide layer pattern, a nitride layer pattern on the first oxide layer pattern, and a second oxide layer pattern on the nitride layer pattern, the second oxide layer pattern being formed by performing an anisotropic plasma oxidation process on the nitride layer, such that a first portion of the second oxide layer pattern on a top surface of the floating gate has a larger thickness than a second portion of the second oxide layer pattern on a sidewall of the floating gate, and forming a control gate on the second oxide layer. | 2012-07-26 |
20120187471 | METHODS OF MANUFACTURING A SEMICONDUCTOR DEVICE AND A SEMICONDUCTOR MEMORY DEVICE THEREBY - A method of manufacturing a semiconductor device comprises forming memory cells on a memory cell region, alternately forming a sacrificial layer and an insulating interlayer on a connection region for providing wirings configured to electrically connect the memory cells, forming an etching mask pattern including etching mask pattern elements on a top sacrificial layer, forming blocking sidewalls on either sidewalls of each of the etching mask pattern element, forming a first photoresist pattern selectively exposing a first blocking sidewall furthermost from the memory cell region and covering the other blocking sidewalls, etching the exposed top sacrificial layer and an insulating interlayer to expose a second sacrificial layer, forming a second photoresist pattern by laterally removing the first photoresist pattern to the extent that a second blocking sidewall is exposed, and etching the exposed top and second sacrificial layers and the insulating interlayers to form a staircase shaped side edge portion. | 2012-07-26 |
20120187472 | TRENCH POLY ESD FORMATION FOR TRENCH MOS AND SGT - A semiconductor device and its method of fabrication are described. A trench formed in a semiconductor substrate is partially filling said trench with a semiconductor material that lines a bottom and sides of the trench, leaving a gap in a middle of the trench running lengthwise along the trench. A first portion of the semiconductor material located below the gap is doped with dopants of a first conductivity type. The gap is filled with a dielectric material. Second portions of the semiconductor material located on the sides of the trench on both sides of the dielectric material are doped with dopants of a second conductivity type. The doping forms a P—N—P or N—P—N structure running lengthwise along the trench with differently doped regions located side by side across a width of the trench. | 2012-07-26 |
20120187473 | Edge Termination With Improved Breakdown Voltage - A MOSFET switch which has a low surface electric field at an edge termination area, and also has increased breakdown voltage. The MOSFET switch has a new edge termination structure employing an N-P-N sandwich structure. The MOSFET switch also has a polysilicon field plate configuration operative to enhance any spreading of any depletion layer located at an edge of a main PN junction of the N-P-N sandwich structure. | 2012-07-26 |
20120187474 | Trench Power MOSFET With Reduced On-Resistance - A semiconductor device includes a drift region, a well region extending above the drift region, an active trench including sidewalls and a bottom, the active trench extending through the well region and into the drift region and having at least portions of its sidewalls and bottom lined with dielectric material. The device further includes a shield disposed within the active trench and separated from the sidewalls of the active trench by the dielectric material, a gate disposed within the active trench above the first shield and separated therefrom by inter-electrode dielectric material, and source regions formed in the well region adjacent the active trench. The gate is separated from the sidewalls of the active trench by the dielectric material. The shield and the gate are made of materials having different work functions. | 2012-07-26 |
20120187475 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A conventional DRAM needs to be refreshed at an interval of several tens of milliseconds to hold data, which results in large power consumption. In addition, a transistor therein is frequently turned on and off; thus, deterioration of the transistor is also a problem. These problems become significant as the memory capacity increases and transistor miniaturization advances. A transistor is provided which includes a wide-gap semiconductor and has a trench structure including a trench for a gate electrode and a trench for element isolation. Even when the distance between a source electrode and a drain electrode is decreased, the occurrence of a short-channel effect can be suppressed by setting the depth of the trench for the gate electrode as appropriate. | 2012-07-26 |
20120187476 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - Trench portions ( | 2012-07-26 |
20120187477 | SUPER-JUNCTION TRENCH MOSFET WITH MULTIPLE TRENCHED SOURCE-BODY CONTACTS - A super-junction trench MOSFET with split gate electrodes is disclosed for high voltage device by applying multiple trenched source-body contacts with narrow CDs in unit cell. Furthermore, source regions are only formed along channel regions near the gate trenches, not between adjacent trenched source-body contacts for UIS (Unclamped Inductance Switching) current enhancement | 2012-07-26 |
20120187478 | SEMICONDUCTOR DEVICE - Provided is a semiconductor device capable of suppressing deterioration in characteristics even when an Avalanche phenomenon occurs in the semiconductor device. The semiconductor device includes a first conductive type drift region; a second conductive type body region disposed on a front surface side of the drift region; a gate trench penetrating the body region and extending to the drift region; a gate electrode disposed within the gate trench; an insulator disposed between the gate electrode and a wall surface of the gate trench; and a second conductive type diffusion region surrounding a bottom portion of the gate trench. An impurity concentration and dimension of the diffusion region are adjusted such that a breakdown is to occur at a p-n junction between the diffusion region and the drift region when an Avalanche phenomenon is occurring. | 2012-07-26 |
20120187479 | PROCESS FOR MANUFACTURING A POWER SEMICONDUCTOR DEVICE HAVING CHARGE-BALANCE COLUMNAR STRUCTURES ON A NON-PLANAR SURFACE, AND CORRESPONDING POWER SEMICONDUCTOR DEVICE - An embodiment of a process for manufacturing a power semiconductor device envisages the steps of: providing a body of semiconductor material having a top surface and having a first conductivity; forming columnar regions having a second type of conductivity within the body of semiconductor material, and surface extensions of the columnar regions above the top surface; and forming doped regions having the second type of conductivity, in the proximity of the top surface and in contact with the columnar regions. The doped regions are formed at least partially within the surface extensions of the columnar regions; the surface extensions and the doped regions have a non-planar surface pattern, in particular with a substantially V-shaped groove. | 2012-07-26 |
20120187480 | PROCESS FOR MANUFACTURING A POWER SEMICONDUCTOR DEVICE HAVING CHARGE-BALANCE COLUMNAR STRUCTURES ON A NON-PLANAR SURFACE, AND CORRESPONDING POWER SEMICONDUCTOR DEVICE - An embodiment of a process for manufacturing a power semiconductor device envisages the steps of: providing a body of semiconductor material having a top surface and having a first conductivity; forming columnar regions having a second type of conductivity within the body of semiconductor material, and surface extensions of the columnar regions above the top surface; and forming doped regions having the second type of conductivity, in the proximity of the top surface and in contact with the columnar regions. The doped regions are formed at least partially within the surface extensions of the columnar regions; the surface extensions and the doped regions have a non-planar surface pattern, in particular with a substantially V-shaped groove. | 2012-07-26 |
20120187481 | Vertical Trench LDMOS Transistor - A vertical trench LDMOS transistor includes a semiconductor layer of a first conductivity type; a first trench formed in the semiconductor layer and filled with a trench dielectric and a trench gate is formed in the first trench; a body region of a second conductivity type formed in the semiconductor layer adjacent the first trench; a source region formed in the body region and adjacent the first trench; a planar gate insulated from the semiconductor layer by a second gate dielectric layer and overlying the body region; and a drain drift region formed in the semiconductor layer. The planar gate forms a lateral channel in the body region between the source region and the drain drift region, and the trench gate in the first trench forms a vertical channel in the body region along the sidewall of the first trench between the source region and the semiconductor layer. | 2012-07-26 |
20120187482 | FABRICATION OF CMOS TRANSISTORS HAVING DIFFERENTIALLY STRESSED SPACERS - CMOS transistors are formed incorporating a gate electrode having tensely stressed spacers on the gate sidewalls of an n channel field effect transistor and having compressively stressed spacers on the gate sidewalls of a p channel field effect transistor to provide differentially stressed channels in respective transistors to increase carrier mobility in the respective channels. | 2012-07-26 |
20120187483 | Double diffused metal oxide semiconductor device and manufacturing method thereof - The present invention discloses a double diffused metal oxide semiconductor (DMOS) device and a manufacturing method thereof. The DMOS device includes: an isolation structure for defining device regions; a gate with a ring-shaped structure; a drain located outside the ring; and a lightly doped drain, a source, and a body electrode located inside the ring. To increase the sub-threshold voltage at the corners of the gate, the corners are located completely on the isolation structure, or the lightly doped drain is apart from the corners by a predetermined distance. | 2012-07-26 |
20120187484 | LATERAL DOUBLE DIFFUSED METAL OXIDE SEMICONDUCTOR DEVICE - A lateral double diffused metal oxide semiconductor (LDMOS) device includes a first buried layer having a second conduction type formed in an epitaxial layer having a first conduction type, a first high-voltage well having the second conduction type formed above one region of the first buried layer, a first drain diffusion region having the first conduction type formed above another region of the first buried layer, a second drain diffusion region having the second conduction type formed in a partial region of the first drain diffusion region, the second drain diffusion region including a gate pattern and a drain region, and a first body having the first conduction type including a source region and having a surface in contact with the second drain diffusion region. | 2012-07-26 |
20120187485 | SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING THE SAME - According to an embodiment of the invention, a semiconductor device includes a substrate, a second conductive type source region formed in the substrate, a second conductive type drain region formed in the substrate, a first conductive type channel region formed in the substrate, a second conductive type drift region formed between the first conductive type channel region and the second conductive type drain region, an insulator film buried on a surface of the second conductive type drift region, and a gate electrode including an opening between the first conductive type channel region and the insulator film and covering a surface of the substrate from the first conductive type channel region to part of the insulator film via a gate insulator. The second conductive type drift region includes a second portion of the second conductive type drift region formed in the substrate below the opening. | 2012-07-26 |
20120187486 | NON-UNIFORM CHANNEL JUNCTION-LESS TRANSISTOR - The present disclosure discloses a method of forming a semiconductor layer on a substrate. The method includes patterning the semiconductor layer into a fin structure. The method includes forming a gate dielectric layer and a gate electrode layer over the fin structure. The method includes patterning the gate dielectric layer and the gate electrode layer to form a gate structure in a manner so that the gate structure wraps around a portion of the fin structure. The method includes performing a plurality of implantation processes to form source/drain regions in the fin structure. The plurality of implantation processes are carried out in a manner so that a doping profile across the fin structure is non-uniform, and a first region of the portion of the fin structure that is wrapped around by the gate structure has a lower doping concentration level than other regions of the fin structure. | 2012-07-26 |
20120187487 | GE-ON-INSULATOR STRUCTURE AND METHOD FOR FORMING THE SAME - A method for forming a Ge-on-insulator structure is provided, comprising steps of: forming a Ge layer ( | 2012-07-26 |
20120187488 | FIELD EFFECT DEVICE PROVIDED WITH A THINNED COUNTER-ELECTRODE AND METHOD FOR FABRICATING - A field effect device comprises a substrate of semiconductor on insulator type successively provided with a support substrate, an electrically insulating layer and a semiconductor material film. First and second source/drain electrodes are formed in the semiconductor material layer. A conduction channel is formed in the semiconductor material layer and separates the first and second source/drain electrodes. A counter-electrode is formed in the support substrate and faces the first and second source/drain electrodes and the conduction channel. The counter-electrode is formed by a doped area of the support substrate having a first doping impurity concentration which decreases from an interface between the electrically insulating layer and the support substrate. | 2012-07-26 |
20120187489 | FIELD EFFECT DEVICE PROVIDED WITH A LOCALIZED DOPANT DIFFUSION BARRIER AREA AND FABRICATION METHOD - The field effect device comprises a sacrificial gate electrode having side walls covered by lateral spacers formed on a semiconductor material film. The source/drain electrodes are formed in the semiconductor material film and are arranged on each side of the gate electrode. A diffusion barrier element is implanted through the void left by the sacrificial gate so as to form a modified diffusion area underneath the lateral spacers. The modified diffusion area is an area where the mobility of the doping impurities is reduced compared with the source/drain electrodes. | 2012-07-26 |