30th week of 2022 patent applcation highlights part 57 |
Patent application number | Title | Published |
20220238357 | Die Bonding Apparatus and Manufacturing Method for Semiconductor Device - A die bonding apparatus includes a push-up unit, a head having a collet that sucks a die, and a control device. The control device is configured to suck a dicing tape using a dome plate; land the collet onto the die using the head; suck the die using the collet; lift plural blocks from the dome plate; stop the outermost block disposed on the outermost side among the plural blocks from lifting at a height where the die is peeled off from the dicing tape; and lift blocks other than the outermost block among the plural blocks higher than the outermost block to a predefined height. | 2022-07-28 |
20220238358 | CHIP-TRANSFERRING MODULE, AND DEVICE AND METHOD FOR TRANSFERRING AND BONDING CHIPS - A chip-transferring module, and a device and a method for transferring and bonding chips are provided. The chip-transferring module includes a mounting main body, a light-transmitting member, a first gas guiding structure and a second gas guiding structure. The mounting main body has a first accommodating space and a second accommodating space. The light-transmitting member is disposed in the first accommodating space. The first gas guiding structure is disposed in the mounting main body and has a plurality of suction openings exposed out of the mounting main body. The second gas guiding structure is disposed in the mounting main body and has at least one intake opening communicating with the second accommodating space. | 2022-07-28 |
20220238359 | CONTROLLING METHOD AND SUBSTRATE TRANSPORT MODULE - A controlling method according to an aspect of the present disclosure includes a first chamber provided with a fan, a second chamber to which a replacement gas is sent from the first chamber by the fan and which includes a transporter configured to transport a substrate, a circulation line configured to communicate the first chamber and the second chamber with each other and circulate the replacement gas, and a valve provided in the circulation line. The method includes replacing an inside of the first chamber and an inside of the second chamber with the replacement gas by turning off the fan and closing the valve, and circulating the replacement gas through the circulation line by turning on the fan and opening the valve. The replacing includes controlling the fan to be turned on and the valve to be opened for a predetermined period of time. | 2022-07-28 |
20220238360 | RF IMMUNE SENSOR PROBE FOR MONITORING A TEMPERATURE OF AN ELECTROSTATIC CHUCK OF A SUBSTRATE PROCESSING SYSTEM - A sensor probe includes an elongated body defining an inner cavity having an inner diameter. A printed circuit board is configured to be fitted within the inner cavity. A first temperature-sensing integrated circuit mounted at a first end of the printed circuit board. A cap is mounted to a first end of the elongated body adjacent to the first temperature-sensing integrated circuit. A housing is configured to receive a second end of the elongated body, wherein the housing is configured to be mounted to a baseplate of a substrate support. | 2022-07-28 |
20220238361 | SEMICONDUCTOR PROCESS SYSTEM AND METHOD - A system includes a first mask, a second mask and a mask container. The first mask includes a first identification code and a second identification code. The second mask includes a third identification code and a fourth identification code. The mask container is configured to store the first mask and the second mask. The first identification code is different from the third identification code. In response to a pattern, for performing a photolithography process, on the first mask, that is different from a pattern on the second mask, the second identification code is different from the fourth identification code. In response to the pattern on the first mask being the same as the pattern on the second mask, the second identification code is the same as the fourth identification code. | 2022-07-28 |
20220238362 | RETICLE POD WITH QUICK-RELEASE SUPPORT MECHANISM - The present invention provides a reticle pod comprising a lower cover and a support mechanism. The lower cover includes a carrying surface and a plurality of securing seats distributed on the carrying surface. The support mechanism includes a supporting portion extending upward for supporting a reticle or a reticle carrier, and a securing portion opposite the supporting portion, wherein the securing portion is detachably connected with a corresponding securing seat, so that the support mechanism can be selectively installed on the lower cover. | 2022-07-28 |
20220238363 | Graphite Plate - Disclosed is a graphite plate to solve a problem of poor performance uniformity of an epitaxial wafer obtained during carrying on epitaxial growth of material using the graphite plate. A graphite plate includes: a graphite plate body, includes a carrying recess and a recess located on one side of the carrying recess away from a central point of the graphite plate body; and a stopper, which is embedded in the recess in a matching manner, and the stopper protrudes from the bottom surface of the carrying recess to form a limiting structure. | 2022-07-28 |
20220238364 | ALIGNMENT HOLDER AND TESTING APPARATUS - An alignment holder for holding a composite specimen includes a holder body and a positioning mechanism. The holder body is configured to clamp a first side of the composite specimen therein. The positioning mechanism is movably engaged with the holder body. The positioning mechanism is configured to lean against a second side of the composite specimen and move relatively to the holder body for adjusting a clamping position of the composite specimen clamped by the holder body. | 2022-07-28 |
20220238365 | System For Isolating Electrodes At Cryogenic Temperatures - An insulating system to reduce or eliminate the possibility of arcing while the pressure within a chamber is being varied is disclosed. The system is operable at cryogenic temperatures, such that the insulating system is able to accommodate dimensional changes due to thermal contraction. The insulating system, which includes a housing having one or more bores, is disposed between the two components which are to be electrically connected. An electrical contact, which may be spring loaded, passes through the bore and is used to electrically connect the two components. The ends of the electrical contact are surrounded by an insulating extender which extends from the housing. In one embodiment, a spring-loaded piston is used as the insulating extender. This insulating extender compensates for changes in dimension due to thermal contraction and covers the portion of the electrical contact that extends beyond the outer surface of the housing. | 2022-07-28 |
20220238366 | MATERIAL FOR POSITIONAL ERROR COMPENSATION IN ASSEMBLY OF DISCRETE COMPONENTS - An assembly includes a substrate; a coating including a Bingham fluid disposed on a surface of the substrate; and a discrete component partially embedded in or disposed on the coating including the Bingham fluid. A method includes irradiating a dynamic release structure disposed on a carrier, in which a discrete component is adhered to the dynamic release structure, the irradiating causing the discrete component to be released from the carrier; and receiving the released discrete component into or onto a coating disposed on a surface of a substrate, the coating comprising a Bingham fluid. | 2022-07-28 |
20220238367 | 3D SEMICONDUCTOR DEVICES AND STRUCTURES WITH LOGIC GATES - A 3D semiconductor device including: a first level including a first single-crystal layer, a plurality of first transistors, a first metal layer (includes interconnection of first transistors), and a second metal layer, where first transistors' interconnection includes forming logic gates; a plurality of second transistors disposed atop, at least in part, of logic gates; a plurality of third transistors disposed atop, at least in part, of the second transistors; a third metal layer disposed above, at least in part, the third transistors; a global grid to distribute power and overlaying, at least in part, the third metal layer; a local grid to distribute power to the logic gates, the local grid is disposed below, at least in part, the second transistors, where the second transistors are aligned to the first transistors with less than 40 nm misalignment, where at least one of the second transistors includes a metal gate. | 2022-07-28 |
20220238368 | TRANSFER COMPONENT AND MANUFACTURING METHOD THEREOF, AND TRANSFER HEAD - A transfer component and a manufacturing method thereof, and a transfer head are provided in the disclosure. The method includes the following. An elastic adhesive layer is disposed on a surface of a substrate. A reticle with a hollow area is disposed on the elastic adhesive layer. The elastic adhesive layer is etched through the hollow area of the reticle. | 2022-07-28 |
20220238369 | TELESCOPING LINEAR EXTENSION ROBOT - A telescoping linear extension robot includes a base configured to support the telescoping linear extension robot, a first driven platform, drivingly coupled to the base, a second driven platform, drivingly coupled to the first driven platform, and a floating intermediate platform. The intermediate platform is configured to increase the extendable range of the driven extensions by facilitating additional extension using force generated by the driven platforms of the robot. This, in turn, allows for long-reach robot solutions with reduced physical footprint, complexity and cost. | 2022-07-28 |
20220238370 | Semiconductor Device with Gate Cut Structure and Method of Forming the Same - Semiconductor devices and methods of forming the same are provided. A method according to the present disclosure includes providing a workpiece including a frontside and a backside. The workpiece includes a substrate, a first plurality of channel members over a first portion of the substrate, a second plurality of channel members over a second portion of the substrate, an isolation feature sandwiched between the first and second portions of the substrate. The method also includes forming a joint gate structure to wrap around each of the first and second pluralities of channel members, forming a pilot opening in the isolation feature, extending the pilot opening through the join gate structure to form a gate cut opening that separates the joint gate structure into a first gate structure and a second gate structure, and depositing a dielectric material into the gate cut opening to form a gate cut feature. | 2022-07-28 |
20220238371 | SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THEREOF - A method includes: doping a region through a first surface of a semiconductor substrate; forming a plurality of doped structures within the semiconductor substrate, wherein each of the plurality of doped structures extends along a vertical direction and is in contact with the doped region; forming a plurality of transistors over the first surface, wherein each of the transistors comprises one or more source/drain structures electrically coupled to the doped region through a corresponding one of the doped structures; forming a plurality of interconnect structures over the first surface, wherein each of the interconnect structures is electrically coupled to at least one of the transistors; and testing electrical connections between the interconnect structures and the transistors based on detecting signals present on the doped region through a second surface of the semiconductor substrate, the second surface opposite to the first surface. | 2022-07-28 |
20220238372 | METHOD FOR FORMING BARRIER LAYER IN SEMICONDUCTOR STRUCTURE - A method for forming a barrier layer in a semiconductor structure is disclosed. A substrate having a dielectric layer is provided. The dielectric layer is exposed to a precursor having a first metal, and a first ammonia treatment is performed. A first purge operation is performed, a second ammonia treatment is performed after the first purge operation, and a second purge operation is performed after the second ammonia treatment to form the barrier layer on the dielectric layer. | 2022-07-28 |
20220238373 | GATE CONTACT STRUCTURE - Semiconductor structures and methods of forming the same are provided. In one embodiment, a semiconductor structure includes an active region over a substrate, a gate structure disposed over the active region, and a gate contact that includes a lower portion disposed over the gate structure and an upper portion disposed over the lower portion. | 2022-07-28 |
20220238374 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE AND SUBSTRATE PROCESSING APPARATUS - A method for manufacturing a semiconductor device is provided. In the method, a silicon-containing gas is supplied to a substrate having a recess in a surface thereof at a predetermined film deposition temperature, thereby depositing a first silicon film in the recess. Chlorine and hydrogen are supplied to the substrate while maintaining the predetermined film deposition temperature, thereby etching the first silicon film deposited in the recess to expand an opening width of the first silicon film. The silicon-containing gas is supplied to the substrate while maintaining the predetermined film deposition temperature, thereby further depositing a second silicon film on the first silicon film in the recess. | 2022-07-28 |
20220238375 | Self Aligned Contact Scheme - A method includes using a second hard mask layer over a gate stack to protect the gate electrode during etching a self-aligned contact. The second hard mask is formed over a first hard mask layer, where the first hard mask layer has a lower etch selectivity than the second hard mask layer. | 2022-07-28 |
20220238376 | GRATING REPLICATION USING HELMETS AND TOPOGRAPHICALLY-SELECTIVE DEPOSITION - Embodiments include an interconnect structure and methods of forming such an interconnect structure. In an embodiment, the interconnect structure comprises a first interlayer dielectric (ILD) and a first interconnect layer with a plurality of first conductive traces partially embedded in the first ILD. In an embodiment, an etch stop layer is formed over surfaces of the first ILD and sidewall surfaces of the first conductive traces. In an embodiment, the interconnect structure further comprises a second interconnect layer that includes a plurality of second conductive traces. In an embodiment, a via between the first interconnect layer and the second interconnect layer may be self-aligned with the first interconnect layer. | 2022-07-28 |
20220238377 | CHIP MANUFACTURING METHOD - A chip manufacturing method includes a modified layer forming step of forming a modified layer and a crack by applying, along planned dividing lines, a first laser beam having a wavelength transmitted through a substrate of a wafer including the substrate and a laminate in a state in which the back surface side of the substrate is exposed and a condensing point of the first laser beam is positioned within the substrate from the back surface side of the substrate, a grinding step of thinning the wafer to a predetermined thickness by grinding the back surface side of the substrate exposed in the modified layer forming step, and a laser-processed groove forming step of forming a laser-processed groove in the laminate by applying, along the planned dividing lines, a second laser beam having a wavelength absorbed by the substrate, from the front surface side of the wafer. | 2022-07-28 |
20220238378 | CHIP SINGULATION METHOD - A chip singulation method includes, in stated order: forming a surface supporting layer on an upper surface of a wafer; thinning the wafer from the undersurface to reduce the thickness to at most 30 μm; removing the surface supporting layer from the upper surface; forming a first metal layer and subsequently a second metal layer on the undersurface of the wafer; applying a dicing tape onto an undersurface of the second metal layer; applying, onto the upper surface of the wafer, a process of increasing hydrophilicity of a surface of the wafer; forming a water-soluble protective layer on the surface of the wafer; cutting the wafer, the first metal layer, and the second metal layer by irradiating a predetermined region of the upper surface of the wafer with a laser beam; and removing the water-soluble protective layer from the surface of the wafer using wash water. | 2022-07-28 |
20220238379 | WAFER DIVIDING METHOD AND DIVIDING APPARATUS - A wafer dividing method includes forming modified layers which will be starting points of division, integrally attaching an annular frame and the wafer together through a dicing tape, directing the wafer downward and expanding the dicing tape to divide, into individual device chips, the wafer along the modified layers formed along the streets, counting particles scattered at the time of division of the wafer by a particle counter disposed in a dust collection path set directly below the wafer, and determining, on the basis of the number of the particles, whether or not the modified layers have been properly formed, at the time of carrying out the dividing step. | 2022-07-28 |
20220238380 | LOCALIZED STRESS REGIONS FOR THREE-DIMENSION CHIPLET FORMATION - Aspects of the present disclosure provide a method for forming a chiplet onto a semiconductor structure. The method can include providing a first semiconductor structure having a first circuit and a first wiring structure formed on a first side thereof, and attaching the first side to a carrier substrate. The method can further include forming a composite of a first stress film and a second stress film on a second side of the first semiconductor structure, and separating the carrier substrate from the first semiconductor structure. The method can further include cutting the composite of the first stress film and the second stress film and the first semiconductor structure to define at least one chiplet, and bonding the at least one chiplet to a second semiconductor structure that has a second circuit and a second wiring structure such that the second wiring structure is connected to the first wiring structure. | 2022-07-28 |
20220238381 | SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME - A semiconductor structure includes a first metal gate structure and a second metal gate structure. The first metal gate structure includes a first high-k gate dielectric layer, a first work function metal layer over the first high-k gate dielectric layer, and a first intervening layer between the first high-k gate dielectric layer and the first work function metal layer. The second metal gate structure includes a second high-k gate dielectric layer and a second work function metal layer over the second high-k gate dielectric layer. The first work function metal layer and the second work function metal layer include a same material. A thickness of the first work function metal layer is less than a thickness of the second work function metal layer. | 2022-07-28 |
20220238382 | SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME - A semiconductor structure includes a first metal gate structure and a second metal gate structure. The first metal gate structure includes a first high-k gate dielectric layer, a first work function metal layer over the first high-k gate dielectric layer, and an N-containing barrier layer between the first high-k gate dielectric layer and the first work function metal layer. The second metal gate structure includes a second high-k gate dielectric layer and a second work function metal layer over the second high-k gate dielectric layer. The first high-k gate dielectric layer and the second high-k gate dielectric layer include a same metal material. The first high-k gate dielectric layer has a first metal concentration, the second high-k gate dielectric layer has a second metal concentration, and the first metal concentration is less than the second metal concentration. | 2022-07-28 |
20220238383 | NON-PLANAR I/O AND LOGIC SEMICONDUCTOR DEVICES HAVING DIFFERENT WORKFUNCTION ON COMMON SUBSTRATE - Non-planar I/O and logic semiconductor devices having different workfunctions on common substrates and methods of fabricating non-planar I/O and logic semiconductor devices having different workfunctions on common substrates are described. For example, a semiconductor structure includes a first semiconductor device disposed above a substrate. The first semiconductor device has a conductivity type and includes a gate electrode having a first workfunction. The semiconductor structure also includes a second semiconductor device disposed above the substrate. The second semiconductor device has the conductivity type and includes a gate electrode having a second, different, workfunction. | 2022-07-28 |
20220238384 | Nanosheet Thickness - According to one example, a semiconductor device includes a first region comprising a plurality of nanosheets vertically stacked above a substrate, a second region comprising a fin protruding from the substrate, a first gate structure wrapping around each of the nanosheets, and a second gate structure disposed over the top surface and sidewalls of the fin. A top surface of a topmost nanosheet of the plurality of nanosheets is vertically offset from a top surface of the fin. | 2022-07-28 |
20220238385 | MULTI-GATE DEVICES AND METHOD OF FABRICATING THE SAME - Provided is a semiconductor device including a semiconductor substrate, a plurality of semiconductor nanosheets, a plurality of source/drain (S/D) features and a gate stack. The semiconductor substrate includes a first fin and a second fin. The first fin has a first width less than a second width of the second fin, and a top surface of the first fin is lower than a top surface of the second fin. The plurality of semiconductor nanosheets are disposed on the first fin and the second fin. The plurality of source/drain (S/D) features are located on the first fin and the second fin and abutting the plurality of semiconductor nanosheets. The gate stack wraps each of the plurality of semiconductor nanosheets. | 2022-07-28 |
20220238386 | METHODS, APPARATUS, AND MANUFACTURING SYSTEM FOR SELF-ALIGNED PATTERNING OF A VERTICAL TRANSISTOR - A method, apparatus, and manufacturing system are disclosed herein for a vertical field effect transistor patterned in a self-aligned process. A plurality of fins is formed. A gate structure is formed on at least a first side and a second side of a lower portion of each fin. A spacer is formed on at least a first side and a second side of an upper portion of each fin. At least one layer is formed above the substrate and between the fins. An opening is formed in the at least one layer between the fins by an etching process. The spacer protects the gate structure during the etching process. | 2022-07-28 |
20220238387 | Gate Profile Control Through Sidewall Protection During Etching - A method includes depositing a dummy gate dielectric layer over a semiconductor region, depositing a dummy gate electrode layer, and performing a first etching process. An upper portion of the dummy gate electrode layer is etched to form an upper portion of a dummy gate electrode. The method further includes forming a protection layer on sidewalls of the upper portion of the dummy gate electrode, and performing a second etching process. A lower portion of the dummy gate electrode layer is etched to form a lower portion of the dummy gate electrode. A third etching process is then performed to etch the lower portion of the dummy gate electrode using the protection layer as an etching mask. The dummy gate electrode is tapered by the third etching process. The protection layer is removed, and the dummy gate electrode is replaced with a replacement gate electrode. | 2022-07-28 |
20220238388 | METHOD OF PRODUCING A GATE CUT IN A SEMICONDUCTOR COMPONENT - A method of producing a gate cut in a semiconductor component is provided. In one aspect, an array of nano-sized semiconductor fins is processed on a semiconductor substrate. Rails may be buried in the substrate and in a layer of dielectric material that isolates neighboring fins from each other. The rails may extend in the direction of the fins and each rail may be situated between two adjacent fins. The rails may be buried power rails for enabling the formation of a power delivery network at the back of an integrated circuit chip. At the front side of the substrate, one or more gate structures are produced. The gate structures extend transversally, or perpendicularly, with respect to the fins and the rails. A gate cut is produced by forming an opening from the back side of the substrate, and removing a portion of the gate structure at the bottom of the opening, thereby creating a gate cut that is aligned to the sidewalls of the rail. In another aspect, a semiconductor component, such as an integrated circuit, includes a gate cut that is aligned to the sidewalls of a buried contact rail. | 2022-07-28 |
20220238389 | SAMPLE WELL FABRICATION TECHNIQUES AND STRUCTURES FOR INTEGRATED SENSOR DEVICES - Methods of forming an integrated device, and in particular forming one or more sample wells in an integrated device, are described. The methods may involve forming a metal stack over a cladding layer, forming an aperture in the metal stack, forming first spacer material within the aperture, and forming a sample well by removing some of the cladding layer to extend a depth of the aperture into the cladding layer. In the resulting sample well, at least one portion of the first spacer material is in contact with at least one layer of the metal stack. | 2022-07-28 |
20220238390 | MANUFACTURING PROCESS WITH ATOMIC LEVEL INSPECTION - Costs may be avoided and yields improved by applying scanning probe microscopy to substrates in the midst of an integrated circuit fabrication process sequence. Scanning probe microscopy may be used to provide conductance data. Conductance data may relate to device characteristics that are normally not available until the conclusion of device manufacturing. The substrates may be selectively treated to ameliorate a condition revealed by the data. Some substrates may be selectively discarded based on the data to avoid the expense of further processing. A process maintenance operation may be selectively carried out based on the data. | 2022-07-28 |
20220238391 | DEVICE AND SYSTEM FOR TESTING FLATNESS - The present disclosure relates to a device and a system for testing flatness. The device for testing flatness includes a base, a testing platform, and a ranging sensor. The testing platform is assembled on the base. The testing platform includes a supporting structure. The supporting structure is disposed on the side of the testing platform away from the base and is used to support a to-be-tested board. The structure matches the structure of the to-be-tested board. The ranging sensor is disposed on the side of the testing platform away from the base. After the to-be-tested board is placed on the testing platform, the ranging sensor is used to test distances between a number N of to-be-tested positions on the to-be-tested board and the ranging sensor, to obtain N pieces of distance information, and the N pieces of distance information are used to determine the flatness of the to-be-tested board, where N is an integer greater than 2. According to the embodiments of the present disclosure, the flatness of the glass substrate can be tested to improve the manufacturing process to reduce the flatness of the glass substrate, and avoid the problem that the glass substrate is easily broken when entering the subsequent process equipment and the process equipment is down. | 2022-07-28 |
20220238392 | Method for detecting optimal production conditions of wafers - The invention relates to a method for detecting optimal production conditions of wafers, the method includes the following steps: a wafer is provided, a plurality of regions are defined on the wafer, the plurality of regions at least includes a first region and a second region, a first photolithography step is performed to expose the first region of the plurality of regions, a first ion implantation step is then performed, ions are doped in the first region, the first region has a first ion doping concentration. Next, a second photolithography step is performed to expose the second region, a second ion implantation step is performed and ions are doped in the second region, the second region has a second ion doping concentration. Afterwards, the electrical characteristics of the first region and the second region are respectively detected. | 2022-07-28 |
20220238393 | METHOD FOR OBTAINING PARAMETERS OF SEMICONDUCTOR STRUCTURE, METHOD FOR OBTAINING DETECTION STANDARD AND DETECTION METHOD - Embodiments of the present disclosure provide a method for obtaining parameters of a semiconductor structure, a method for obtaining a detection standard and a detection method. The method for obtaining parameters of a semiconductor structure includes: obtaining a semiconductor structure, the semiconductor structure including a substrate and a capacitor support structure on the substrate, the capacitor support structure having a plurality of capacitor holes therein, the capacitor holes penetrating the capacitor support structure in a thickness direction of the capacitor support structure; removing some height of the capacitor support structure; obtaining a test pattern, the test pattern being a pattern exposed at a top of the remaining capacitor support structure; and in the test pattern, obtaining a spacing between the capacitor holes at predetermined positions on the basis of a predetermined direction. | 2022-07-28 |
20220238394 | TEMPERATURE CONTROL METHOD, TEMPERATURE CONTROL DEVICE, AND OPTICAL HEATING DEVICE - A method includes a step (A) of causing the light source part to repeatedly switch between a light-on state and a substantially light-off state, a step (B) of measuring the temperature of the substrate to be treated by observing infrared light radiated from the substrate to be treated while the light source part is kept in the substantially light-off state in the step (A), and a step (C) of determining either of a level of electricity supplied to the light source part in a next round of the light-on state and a time for which the light source part is kept in the next round of the light-on state based on the temperature of the substrate to be treated measured in the step (B) and a predetermined target temperature. | 2022-07-28 |
20220238395 | SECURE INSPECTION AND MARKING OF SEMICONDUCTOR WAFERS FOR TRUSTED MANUFACTURING THEREOF - A method for securing and verifying semiconductor wafers during fabrication includes receiving a semiconductor wafer after a layer of features has been patterned thereon. At least one security mark is formed at one or more locations embedded within a backside of the semiconductor wafer by implanting an inert species at the one or more locations. At a subsequent point in fabrication and/or after fabrication of the semiconductor wafer has completed the backside of the wafer is inspected for detection of the at least one security mark. If the at least one security mark is not detected at an expected location within the backside of the semiconductor wafer a determination is made that the semiconductor wafer has been compromised. | 2022-07-28 |
20220238396 | LASER REPAIR METHOD AND LASER REPAIR DEVICE - A laser repair method includes a repair process of performing repair work by setting a laser radiation range for a defect part in a multi-layer film substrate and irradiating the defect part with a laser beam under set laser working conditions. In the repair process, spectrum data of the defect part is acquired, and the laser working conditions of the laser beam, with which the defect part is to be irradiated, are set using a neural network after learning on the basis of the spectrum data, and the neural network has undergone machine learning using, as learning data, measurement data including multi-layer film structure data, spectrum data of each multi-layer film structure, and laser working experimental data of each multi-layer film structure. | 2022-07-28 |
20220238397 | SEMICONDUCTOR STRUCTURE INCLUDING INTERCONNECTION TO PROBE PAD WITH PROBE MARK - Provided is a semiconductor structure including an interconnect structure, disposed over a substrate; a pad structure, disposed over and electrically connected to the interconnect structure, wherein the pad structure comprises a metal pad and a dielectric cap on the metal pad, and the pad structure has a probe mark recessed from a top surface of the dielectric cap into a top surface of the metal pad; a protective layer, conformally covering the top surface of the dielectric cap and the probe mark; and a bonding structure, disposed over the protective layer, wherein the bonding structure comprises: a bonding dielectric layer at least comprising a first bonding dielectric material and a second bonding dielectric material on the first bonding dielectric material; and a first bonding metal layer disposed in the bonding dielectric layer and penetrating through the protective layer and the dielectric cap to contact the metal pad. | 2022-07-28 |
20220238398 | Methods of Forming Semiconductor Device Packages - In an embodiment, a method includes: stacking a plurality of first dies to form a device stack; revealing testing pads of a topmost die of the device stack; testing the device stack using the testing pads of the topmost die; and after testing the device stack, forming bonding pads in the topmost die, the bonding pads being different from the testing pads. | 2022-07-28 |
20220238399 | CIRCUIT FOR DETECTING CRACK DAMAGE OF A DIE, METHOD FOR DETECTING CRACK, AND MEMORY - A circuit and method for detecting crack damage of a die are provided. The circuit comprises: a test circuit located within a seal ring of the die for outputting a pulse detection signal; a crack detection loop arranged outside a guard ring of an internal processing circuit of the die, having an input end connected to an output end of the test circuit and an output end connected to an output pin of the die; and a relay driving unit arranged between the input end and output end for increasing a capability of transmission of the pulse detection signal, wherein the seal ring surrounds the whole die; in a test mode, the test circuit outputs the pulse detection signal to the crack detection loop, and a test machine determines whether the die is damaged by a crack by reading a signal on the output pin of the die. | 2022-07-28 |
20220238400 | INSULATING COMPONENT, SEMICONDUCTOR PACKAGE, AND SEMICONDUCTOR APPARATUS - An insulating component includes an insulating substrate, a metal layer, a bond, and a lead terminal. The plate-like insulating substrate has a groove continuous from its upper to side surfaces. The metal layer includes a first metal layer on the upper surface of the insulating substrate and a second metal layer on an inner surface of the groove continuous with the first metal layer. The bond is on an upper surface of the metal layer. The lead terminal is on an upper surface of the first metal layer with the bond in between, and overlaps the grooves. The bond includes a first bond fixing the lead terminal to the first metal layer and a second bond on an upper surface of the second metal layer continuous with the first bond. The groove includes an inner wall having a ridge. The second bond is between the ridge and the lead terminal. | 2022-07-28 |
20220238401 | Seamless Interconnect Thresholds using Dielectric Fluid Channels - A method may include forming a cavity within a plastic structure with a channel positioned at a perimeter of the cavity, inserting the electronic component into the cavity, dispensing a dielectric fluid into the channel at the perimeter of the cavity, curing the dielectric fluid in situ to secure the electronic component within the cavity with a cured dielectric and printing interconnects for the electronic component. | 2022-07-28 |
20220238402 | STACKED DIE CAVITY PACKAGE - An apparatus is provided which comprises: a plurality of dielectric layers forming a substrate, a plurality of first conductive contacts on a first surface of the substrate, a cavity in the first surface of the substrate defining a second surface parallel to the first surface, a plurality of second conductive contacts on the second surface of the substrate, one or more integrated circuit die(s) coupled with the second conductive contacts, and mold material at least partially covering the one or more integrated circuit die(s) and the first conductive contacts. Other embodiments are also disclosed and claimed. | 2022-07-28 |
20220238403 | UNDERFILL INJECTION FOR ELECTRONIC DEVICES - A device for applying underfill material into a space between a substrate and a semiconductor chip is provided. The device includes a frame housing configured to cover at least an outer edge area of the semiconductor chip that is bonded to the substrate. The device also includes a sealant attached to the frame housing and configured to contact the outer edge area of the semiconductor chip. The device also includes an outlet made on the frame housing for evacuating the space; and an inlet made on the frame housing for injecting the underfill material to the space. | 2022-07-28 |
20220238404 | Package with Tilted Interface Between Device Die and Encapsulating Material - A method includes forming a polymer layer covering a metal via in a wafer, grooving the wafer to form a trench, wherein the trench extends from a top surface of the polymer layer into the wafer, and performing a die-saw on the wafer to separate the wafer into a plurality of device dies. A kerf passes through the trench. One of the device dies is placed over a carrier. An encapsulating material is dispensed over and around the device die. The method further includes pressing and curing the encapsulating material. After the encapsulating material is cured, a sidewall of the polymer layer is tilted. A planarization is performed on the encapsulating material until the polymer layer and the metal via are exposed. A redistribution line is formed over and electrically coupled to the metal via. | 2022-07-28 |
20220238405 | SEMICONDUCTOR DEVICE AND CORRESPONDING MANUFACTURING METHOD - An antenna-in-package semiconductor device includes a semiconductor chip coupled to a planar substrate. An encapsulation body encapsulates the semiconductor chip. The encapsulation body includes a through cavity extending to the planar substrate. A rectilinear wire antenna is mounted within the through cavity and extends, for instance from the planar substrate, along an axis that is transverse to a surface of the planar substrate to which the semiconductor chip is coupled. The rectilinear wire antenna is electrically coupled to the semiconductor chip. An insulating material fills the cavity to encapsulated the rectilinear wire antenna. | 2022-07-28 |
20220238406 | PACKAGE STRUCTURE AND METHOD OF MANUFACTURING THE SAME - A package structure and a method of manufacturing the same are provided. The package structure includes a die, an encapsulant, a first redistribution line (RDL) structure, a second RDL structure, a conductive terminal, and a through via. The encapsulant laterally encapsulates the die. The first redistribution line (RDL) structure on a first side of the die and the encapsulant, wherein the first RDL structure comprises a dielectric layer and a redistribution layer in the dielectric layer. The second RDL structure is located on a second side of the die and the encapsulant. The conductive terminal is connected to the redistribution layer. The through via extends through the encapsulant and the redistribution layer to contact the conductive terminal and the second RDL structure. | 2022-07-28 |
20220238407 | THREE-DIMENSIONAL INTEGRATED CIRCUIT STRUCTURES AND METHODS OF FORMING THE SAME - Three-dimensional integrated circuit (3DIC) structures and methods of forming the same are provided. A 3DIC structure includes a semiconductor package, a first package substrate, a molded underfill layer and a thermal interface material. The semiconductor package is disposed over and electrically connected to the first package substrate through a plurality of first bumps. The semiconductor package includes at least one semiconductor die and an encapsulation layer aside the semiconductor die. The molded underfill layer surrounds the plurality of first bumps and a sidewall of the semiconductor package, and has a substantially planar top surface. The CTE of the molded underfill layer is different from the CTE of the encapsulation layer of the semiconductor package. The thermal interface material is disposed over the semiconductor package. | 2022-07-28 |
20220238408 | SEMICONDUCTOR DEVICE - A semiconductor device including a substrate, a semiconductor package, a plurality of pillars and a lid is provided. The semiconductor package is disposed on the substrate and includes at least one semiconductor die. The plurality of pillars are disposed on the semiconductor package. The lid is disposed on the substrate and covers the semiconductor package and the plurality of pillars. The lid includes an inflow channel and an outflow channel to allow a coolant to flow into and out of a space between the substrate, the semiconductor package, the plurality of pillars and the lid. An inner surface of the lid, which faces and overlaps the plurality of pillars along a stacking direction of the semiconductor package and the lid, is a flat surface. | 2022-07-28 |
20220238409 | SEMICONDUCTOR STRUCTURE HAVING A THERMAL SHUNT BELOW A METALLIZATION LAYER AND INTEGRATION SCHEMES - A semiconductor structure is provided. The semiconductor structure comprises a heat generating device arranged over a substrate. An interlayer dielectric (ILD) material may be arranged over the heat generating device and the substrate. A metallization layer may be arranged over the interlayer dielectric material. A thermal shunt structure may be arranged proximal the heat generating device, whereby an upper portion of the thermal shunt structure may be arranged in the interlayer dielectric material and may be lower than the metallization layer, and a lower portion of the thermal shunt structure may be arranged in the substrate. | 2022-07-28 |
20220238410 | THERMALS FOR PACKAGES WITH INDUCTORS - An apparatus is provided which comprises: one or more pads comprising metal on a first substrate surface, the one or more pads to couple with contacts of an integrated circuit die, one or more substrate layers comprising dielectric material, one or more conductive contacts on a second substrate surface, opposite the first substrate surface, the one or more conductive contacts to couple with contacts of a printed circuit board, one or more inductors on the one or more substrate layers, the one or more inductors coupled with the one or more conductive contacts and the one or more pads, and highly thermally conductive material between the second substrate surface and a printed circuit board surface, the highly thermally conductive material contacting the one or more inductors. Other embodiments are also disclosed and claimed. | 2022-07-28 |
20220238411 | PACKAGE WITH A HIGHLY CONDUCTIVE LAYER DEPOSITED ON DIE USING THROUGHPUT ADDITIVE DEPOSITION PRIOR TO TIM1 DISPENSE - A device package and a method of forming a device package are described. The device package has dies disposed on a substrate, and one or more layers with a high thermal conductivity, referred to as the highly-conductive (HC) intermediate layers, disposed on the dies on the substrate. The device package further includes a lid with legs on an outer periphery of the lid, a top surface, and a bottom surface. The legs of the lid are attached to the substrate with a sealant. The bottom surface of the lid is disposed over the one or more HC intermediate layers and the one or more dies on the substrate. The device package may also include thermal interface materials (TIMs) disposed on the HC intermediate layers. The TIMs may be disposed between the bottom surface of the lid and one or more top surfaces of the HC intermediate layers. | 2022-07-28 |
20220238412 | ELASTIC THERMAL CONNECTION STRUCTURE - A thermal connection structure includes a foam layer having a light porous, semi-grid flexible material. A thermal conducting medium is injected within closed cells and foam voids of the foam layer. A heat dissipating layer couples the thermal conducting medium comprising a planar unsaturated ring that has thermal conductivity that couples a heat sink. | 2022-07-28 |
20220238413 | DOUBLE SIDED COOLING MODULE WITH POWER TRANSISTOR SUBMODULES - A double sided cooling module that includes a leadframe with a top Direct Copper Bonded (DCB) substrate and two or more power transistor submodules. Each one of the power transistor submodules includes a bottom DCB substrate, a spaced-apart row of first wires attached to a top metal layer of the bottom DCB substrate proximate to the first side of the top metal layer, a semiconductor die having a bottom side load path contact attached to a top surface of a die pad portion of the top metal layer, a top side control contact electrically coupled via at least one bond wire to a top surface of a control pad portion of the top metal layer, and an electrically conductive and thermally conductive spacer that is attached to the top side load path contact and to a bottom metal layer of the top DCB substrate. At least one of the first wires is attached to the control pad portion of the top metal layer and to a bottom metal layer of the top DCB substrate. Other ones of the first wires are attached to the die pad portion of the top metal layer and to the bottom metal layer of the top DCB substrate. | 2022-07-28 |
20220238414 | THERMAL CONDUCTIVE STRUCTURE AND ELECTRONIC DEVICE - A thermal conductive structure and an electronic device are provided. The thermal conductive structure includes a thermal conductive metal layer and a structural layer. The structural layer is disposed on the thermal conductive metal layer. The structural layer is a stacked structure formed by a graphene layer and a ceramic material layer, or the structural layer is a graphene-mixed ceramic material layer. The thermal conductive structure can quickly conduct the heat energy generated by the heat source to the outside, thereby improving the heat dissipation performance of the electronic device. | 2022-07-28 |
20220238415 | THERMOELECTRIC COOLING PEDESTAL FOR SUBSTRATE PROCESSING SYSTEMS - A temperature-controlled pedestal includes a pedestal, a temperature sensor to sense N temperature in N zones, and N temperature control devices arranged in the N zones, respectively. A voltage source selectively supplies power to the N temperature control devices. A controller is configured to cause the voltage source to control a temperature in the N zones by a) determining a hottest one of the N zones based on the N temperatures; b) if the hottest one of the N zones is not already cooling, increasing cooling to the hottest one of the N zones using one of the N temperature control devices; c) decreasing cooling to the N zones when a temperature of the N zones is less than a first temperature setpoint; and d) repeating a) to c) until all of the N zones have a temperate less than or equal to the first temperature setpoint. | 2022-07-28 |
20220238416 | DISTRIBUTING HEATSINK LOAD ACROSS A PROCESSOR MODULE WITH SEPARABLE INPUT/OUTPUT (I/O) CONNECTORS - A heatsink for distributing heatsink load across a processor module with separable input/output (I/O) connectors, comprising: a thermal conductor; and one or more pistons aligned with one or more separable interconnects of the processor module. | 2022-07-28 |
20220238417 | Integrated Assemblies and Methods of Forming Integrated Assemblies - Some embodiments include a method of forming an integrated assembly. Semiconductor material is patterned into a configuration which includes a set of first upwardly-projecting structures spaced from one another by first gaps, and a second upwardly-projecting structure spaced from the set by a second gap. The second gap is larger than the first gaps. Conductive material is formed along the first and second upwardly-projecting structures and within the first and second gaps. First and second segments of protective material are formed over regions of the conductive material within the second gap, and then an etch is utilized to pattern the conductive material into first conductive structures within the first gaps and into second conductive structures within the second gap. Some embodiments include integrated assemblies. | 2022-07-28 |
20220238418 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - The present invention provides a small and thin semiconductor device. The semiconductor device flip-chip bonds a semiconductor chip | 2022-07-28 |
20220238419 | INTEGRATED CIRCUIT LEAD FRAME AND SEMICONDUCTOR DEVICE THEREOF - An integrated circuit lead frame and a semiconductor device thereof are provided. The integrated circuit lead frame includes a die pad and a plurality of leads. The die pad is provided to attach a die. The plurality of leads are provided for connection to the die through wire bonding. The leads include a pair of a first lead and a second lead. The first lead includes a first body and a first extension portion connected to the first body. The second lead includes a second body and a second extension portion connected to the second body. The first extension portion and the second extension portion extend in directions toward each other. | 2022-07-28 |
20220238420 | ELECTRONIC DEVICE, METHOD FOR MANUFACTURING ELECTRONIC DEVICE, AND LEAD FRAME - An electronic device includes an electronic component provided with a first electrode pad, a die pad including an obverse surface facing in a first direction with the electronic component mounted on the obverse surface, a first lead, a second lead, and a first connection member electrically connecting the first electrode pad and the first lead to each other. The first lead and the second lead are disposed, as viewed in the first direction, on a same side of the die pad in a second direction perpendicular to the first direction. The first lead includes a first pad portion and a first extended portion. The first connection member is bonded to the first pad portion. The first extended portion extends from the first pad portion up to a position located between the die pad and the second lead as viewed in the first direction. | 2022-07-28 |
20220238421 | MOLDED PACKAGING FOR WIDE BAND GAP SEMICONDUCTOR DEVICES - A semiconductor device package may include a leadframe having a first portion with first extended portions and a second portion with second extended portions. Mold material may encapsulate a portion of the leadframe and a portion of a semiconductor die mounted to the leadframe. A first set of contacts of the semiconductor die may be connected to a first surface of the first extended portions, while a second set of contacts may be connected to a first surface of the second extended portions. A mold-locking cavity having the mold material included therein may be disposed in contact with a second surface of the first extended portions opposed to the first surface of the first extended portions, a second surface of the second extended portions opposed to the first surface of the second extended portions, the first portion of the leadframe, and the second portion of the leadframe. | 2022-07-28 |
20220238422 | Semiconductor Package with Barrier to Contain Thermal Interface Material - A semiconductor package includes a semiconductor die, an encapsulant body of electrically insulating material that encapsulates the semiconductor die, a thermal conduction plate comprising an outer surface that is exposed from the encapsulant body, a region of thermal interface material interposed between the thermal conduction plate and the semiconductor die, the region of thermal interface material being a liquid or semi-liquid, and a barrier that is configured to prevent the thermal interface material of the region from flowing laterally across the barrier | 2022-07-28 |
20220238423 | SEMICONDUCTOR DEVICE - Provided is a semiconductor device applicable to both types of packages regardless of whether or not double bonding of a lead frame pad is allowed. The semiconductor device includes: an operational amplifier; a feedback resistor; a reference voltage generation circuit; an output transistor; a first pad which is connected to an output terminal of the output transistor, and is to be selectively connected to a lead frame pad by a bonding wire; a second pad to be selectively connected to the lead frame pad by a bonding wire; and a connection switching element provided between the first pad and the second pad. In a case in which the second pad is connected to the lead frame pad by the bonding wire, the connection switching element interrupts connection between the first pad and the second pad. | 2022-07-28 |
20220238424 | SEMICONDUCTOR PACKAGE WITH ISOLATED HEAT SPREADER - A semiconductor package includes a metallic pad and leads, a semiconductor die attached to the metallic pad, the semiconductor die including an active side with bond pads opposite the metallic pad, a wire bond extending from a respective bond pad of the semiconductor die to a respective lead of the leads, a heat spreader over the active side of the semiconductor die with a gap separating the active side of the semiconductor die from the heat spreader, an electrically insulating material within the gap and in contact with the active side of the semiconductor die and the heat spreader; and mold compound covering the semiconductor die and the wire bond, and partially covering the metallic pad and the heat spreader, with the metallic pad exposed on a first outer surface of the semiconductor package and with the heat spreader exposed on a second outer surface of the semiconductor package. | 2022-07-28 |
20220238425 | SEMICONDUCTOR PACKAGE STRUCTURE - A semiconductor package structure includes a chip, a first conductive pillar, a dielectric layer, a first patterned conductive layer and a second patterned conductive layer. The chip has a first side with a first metal electrode pad and a second side with a second metal electrode pad. The first conductive pillar is disposed adjacent to the chip. The dielectric layer covers the chip and the first conductive pillar and exposes the first and second metal electrode pads of the chip and the first and second ends of the first conductive pillar. The first patterned conductive layer is disposed on a second surface of the dielectric layer and electrically connected between the second metal electrode pad and the second end of the first conductive pillar. The second patterned conductive layer is disposed on a first surface of the dielectric. | 2022-07-28 |
20220238426 | PACKAGED ELECTRONIC DEVICES HAVING DIELECTRIC SUBSTRATES WITH THERMALLY CONDUCTIVE ADHESIVE LAYERS - A packaged electronic device comprises a power semiconductor die that comprises a first terminal and a second terminal, a lead frame comprising a lower side and an upper side that comprises a die pad region, a first lead and a second lead, wherein the first lead is integral with the lead frame and electrically connected to the first terminal of the power semiconductor die through the lead frame, a dielectric substrate, and a thermally conductive adhesion layer on an upper side of the dielectric substrate. The power semiconductor die is on the die pad region of the lead frame and the lead frame is on an upper side of the thermally conductive adhesion layer | 2022-07-28 |
20220238427 | TRENCH GATE TRANSISTORS WITH LOW-RESISTANCE SHIELD AND GATE INTERCONNECTS - In a general aspect, a transistor can include a trench disposed in a semiconductor region and a gate electrode disposed in an upper portion of the trench. The gate electrode can include a first and second gate electrode segments. The transistor can also include a shield electrode having a first shield electrode portion disposed in a lower portion of the trench, and a second shield electrode portion orthogonally extending from the first shield electrode portion in the lower portion of the trench to the upper portion of the trench. The first shield electrode portion can be disposed below the first and second gate electrode segments, and the second shield electrode portion can being disposed between the first and second gate electrode segments. The transistor can also include a patterned buried conductor layer. The first and second gate electrode segments can be electrically coupled via the patterned buried conductor layer. | 2022-07-28 |
20220238428 | SEMICONDUCTOR STRUCTURE - A semiconductor structure includes: a pad structure disposed above a substrate; and a capacitor structure which is disposed between the substrate and the pad structure, is arranged to be opposite to the pad structure, and includes at least two capacitor units connected in parallel and spaced apart from each other, each of the capacitor units includes at least one capacitor device. | 2022-07-28 |
20220238429 | SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THEREOF - A semiconductor device includes an active region over a substrate extending along a first lateral direction. The semiconductor device includes a number of first conductive structures operatively coupled to the active region. The first conductive structures extend along a second lateral direction. The semiconductor device includes a number of second conductive structures disposed above the plurality of first conductive structures. The second conductive structures extend along the first lateral direction. The semiconductor device includes a first capacitor having a first electrode and a second electrode. The first electrode includes one of the first conductive structures and the active region, and the second electrode includes a first one of the second conductive structures. Each of the active region and the first conductive structures is electrically coupled to a power rail structure configured to carry a supply voltage. | 2022-07-28 |
20220238430 | CAPACITOR STRUCTURE, SEMICONDUCTOR STRUCTURE, AND METHOD FOR MANUFACTURING THEREOF - A capacitor structure is provided. The capacitor structure includes a substrate, a middle-of-line (MEOL) structure, and a metallization structure. The substrate has a first surface and a second surface opposite to the first surface. The MEOL structure is over the first surface of the substrate. The MEOL structure includes a capacitor, and the capacitor includes a bottom plate and a top plate over the bottom metal plate. The metallization structure is over the MEOL structure. The substrate further includes a plurality of first through vias extending from the second surface of the substrate to the bottom metal plate. The semiconductor structure including the capacitor structure and the method for manufacturing the semiconductor structure are also provided. | 2022-07-28 |
20220238431 | METHODS OF FORMING MICROELECTRONIC DEVICES, AND RELATED MICROELECTRONIC DEVICES, MEMORY DEVICES, AND ELECTRONIC SYSTEMS - A method of forming a microelectronic device comprises forming a stack structure comprising vertically alternating insulating structures and conductive structures arranged in tiers. Each of the tiers individually comprises one of the insulating structures and one of the conductive structures. A sacrificial material is formed over the stack structure and pillar structures are formed to extend vertically through the stack structure and the sacrificial material. The method comprises forming conductive plug structures within upper portions of the pillar structures, forming slots extending vertically through the stack structure and the sacrificial material, at least partially removing the sacrificial material to form openings horizontally interposed between the conductive plug structures, and forming a low-K dielectric material within the openings. Microelectronic devices, memory devices, and electronic systems are also described. | 2022-07-28 |
20220238432 | SEMICONDUCTOR DEVICE - A semiconductor device includes a first insulating layer on a semiconductor substrate. A first conductive film is on the first insulating layer. A first stacked structure is on the first conductive film and includes first electrode films and second insulating layers alternately stacked. A conductive member is along an outer edge of the first stacked structure around the first stacked structure and electrically connected to the semiconductor substrate. A second stacked structure is provided at least partially around the conductive member and includes the second insulating layers and third insulating layers alternately stacked on the first conductive film. The first conductive film includes a body part below the first stacked structure, a periphery part provided at a periphery of the body part away from the body part, and a slit part in the first conductive film between the conductive member and the second stacked structure in the periphery part. | 2022-07-28 |
20220238433 | SEMICONDUCTOR DEVICES - A semiconductor device includes a second insulating layer disposed on a substrate and that includes a first trench that extends in a first direction, a first via disposed in the first hole, a first interconnection layer disposed in the first trench on the first via and that has an upwardly upper region, and a third insulating layer disposed on the second insulating layer and that includes a second hole and a second trench connected to the second hole. The first trench has inclined side surfaces such that a width of the first trench increases in a direction toward the substrate, the second hole has inclined side surfaces such that a width of the second hole decreases in the direction toward the substrate, and a lower portion of the second hole is wider than an upper surface of the first interconnection layer. | 2022-07-28 |
20220238434 | PROTECTION LINER ON INTERCONNECT WIRE TO ENLARGE PROCESSING WINDOW FOR OVERLYING INTERCONNECT VIA - In some embodiments, the present disclosure relates to an integrated chip that includes a lower dielectric arranged over a substrate. An interconnect wire is arranged over the dielectric layer, and a first interconnect dielectric layer is arranged outer sidewalls of the interconnect wire. A protection liner that includes graphene is arranged directly on the outer sidewalls of the interconnect wire and on a top surface of the interconnect wire. The integrated chip further includes a first etch stop layer arranged directly on upper surfaces of the first interconnect dielectric layer, and a second interconnect dielectric layer arranged over the first interconnect dielectric layer and the interconnect wire. Further, an interconnect via extends through the second interconnect dielectric layer, is arranged directly over the protection liner, and is electrically coupled to the interconnect wire. | 2022-07-28 |
20220238435 | MULTILAYER-TYPE ON-CHIP INDUCTOR STRUCTURE - A multilayer-type on-chip inductor with a conductive structure includes an insulating redistribution layer disposed on an inter-metal dielectric layer, a first spiral trace layer disposed in the insulating redistribution layer, and a second spiral trace layer disposed in the inter-metal dielectric layer and correspondingly formed below the first spiral trace layer. | 2022-07-28 |
20220238436 | MULTILAYER-TYPE ON-CHIP INDUCTOR STRUCTURE - A multilayer-type on-chip inductor with a conductive structure includes an insulating redistribution layer disposed on an inter-metal dielectric (IMD) layer, and first and second winding portions symmetrically arranged in the IMD layer and the insulating redistribution layer with respect to a symmetrical axis. The first and second winding portions each includes at least first and second semi-circular stacking layers arranged from the inside to the outside and in concentricity. The first and second semi-circular stacking layers each has a first trace layer in the insulating redistribution layer and a second trace layer in the IMD layer and correspondingly formed below the first trace layer. A first slit opening passes through the second trace layer and extends in the extending direction of the length of the second trace layer. | 2022-07-28 |
20220238437 | SEMICONDUCTOR STRUCTURE AND PREPARATION METHOD THEREOF - A preparation method of the semiconductor structure includes: providing a substrate including a core device region and an anti-fuse device region; forming a first dielectric layer covering the core device region and the anti-fuse device region; forming a second dielectric layer covering the first dielectric layer and having a dielectric constant larger than a dielectric constant of the first dielectric layer; removing the second dielectric layer on the anti-fuse device region; and forming a conductive layer covering the first dielectric layer on the anti-fuse device region and the second dielectric layer on the core device region. | 2022-07-28 |
20220238438 | METALLIZATION LAYER AND FABRICATION METHOD - A second metal structure such as a metal plug is formed over a first metal structure, such as a metal line, by causing metal material from the first metal structure to migrate into an opening in a dielectric layer over the first metal structure. The metal material, which may be copper, is of a type that undergoes a reduction in density as it oxidizes. Migration is induced using gases that alternately oxidize and reduce the metal material. Over many cycles, the metal material migrates into the opening. In some embodiments, the migrated metal material partially fills the opening. In some embodiments, the migrated metal material completely fills the opening. | 2022-07-28 |
20220238439 | SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING THE SAME - A semiconductor device includes a transistor on a substrate, a first metal layer that is on the transistor and includes a lower wire electrically connected to the transistor, and a second metal layer on the first metal layer. The second metal layer includes an upper wire that is electrically connected to the lower wire and includes a via structure in a via hole and a line structure in a line trench. The via structure includes a via portion that is in the via hole and is coupled to the lower wire, and a barrier portion that vertically extends from the via portion to cover an inner surface of the line trench. The barrier portion is between the line structure and an insulating layer of the second metal layer. The barrier portion is thicker at its lower level than at its upper level. | 2022-07-28 |
20220238440 | BARE-DIE SMART BRIDGE CONNECTED WITH COPPER PILLARS FOR SYSTEM-IN-PACKAGE APPARATUS - A system-in-package apparatus includes a semiconductive bridge that uses bare-die pillars to couple with a semiconductive device such as a processor die. The apparatus achieves a thin form factor. | 2022-07-28 |
20220238441 | Semiconductor device and method of manufacturing a semiconductor device - In one example, a semiconductor device comprises a redistribution layer (RDL) substrate having a top surface and a bottom surface, wherein the RDL substrate comprises a filler-free dielectric material, an electronic device on the top surface of the RDL substrate, an electrical interconnect on the bottom surface of the RDL substrate and electrically coupled to the electronic device, a first protective material contacting a side surface of the electronic device and the top surface of the RDL substrate, and a second protective material contacting a side surface of the electrical interconnect and the bottom surface of the RDL substrate. Other examples and related methods are also disclosed herein. | 2022-07-28 |
20220238442 | SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THEREOF - A semiconductor device includes a first active region, disposed on a first side of a substrate, that extends along a first lateral direction. The semiconductor device includes a second active region, disposed on the first side, that extends along the first lateral direction. The first active region has a first conduction type and the second active region has a second conduction type opposite to the first conduction type. The semiconductor device includes a first interconnect structure, formed on a second side of the substrate opposite to the first side, that includes: a first portion extending along the first lateral direction and vertically disposed below the first active region; and a second portion extending along a second lateral direction. The first latera direction is perpendicular to the first lateral direction. | 2022-07-28 |
20220238443 | SEMICONDUCTOR DEVICE, AND ASSOCIATED METHOD AND SYSTEM - A semiconductor device, including: a transistor layer, a dielectric layer, a conductive strip and a power grid structure. The transistor layer includes a first active region configured to be a source/drain terminal of a first transistor and a second active region configured to be a source/drain terminal of a second transistor. The bottom surface of the dielectric layer is in direct contact with top surfaces of the source/drain terminals of the first and second transistors. The conductive strip is included in the dielectric layer and extends from the first active region toward the second active region for signal connection. The power grid structure is arranged to direct a power source to the transistor layer from a bottom of the transistor layer. | 2022-07-28 |
20220238444 | MICROELECTRONIC DEVICES INCLUDING STAIRCASE STRUCTURES, AND RELATED MEMORY DEVICES AND ELECTRONIC SYSTEMS - A microelectronic device includes a stack structure, a staircase structure, conductive pad structures, and conductive contact structures. The stack structure includes vertically alternating conductive structures and insulating structures arranged in tiers. Each of the tiers individually includes one of the conductive structures and one of the insulating structures. The staircase structure has steps made up of edges of at least some of the tiers of the stack structure. The conductive pad structures are on the steps of the staircase structure and include beta phase tungsten. The conductive contact structures are on the conductive pad structures. Memory devices, electronic systems, and methods of forming microelectronic devices are also described. | 2022-07-28 |
20220238445 | FULLY MOLDED BRIDGE INTERPOSER AND METHOD OF MAKING THE SAME - A semiconductor device may comprise a bridge die comprising copper studs. Copper posts may be disposed in a periphery of the bridge die. An encapsulant may be disposed on five sides of the bridge die, on sides of the copper studs, and on sides of the copper posts that leave ends of the copper studs and opposing first and second ends of the copper posts exposed from the encapsulant. A frontside build-up interconnect structure may be formed over the copper studs of the bridge die and coupled to second ends of the copper posts opposite the first ends of the copper posts. The frontside build-up interconnect structure comprising first pads at a first pitch within a footprint of the bridge die and second pads at a second pitch outside a footprint of the bridge die. The first pitch may be at least 1.5 times less than the second pitch. | 2022-07-28 |
20220238446 | SEMICONDUCTOR PACKAGE STRUCTURE AND METHOD FOR FORMING THE SAME - A semiconductor package structure includes a first semiconductor die and a second semiconductor die neighboring the first semiconductor die. The first semiconductor die includes a first edge, a second edge opposite the first edge, and a first metal layer exposed from the second edge. The second semiconductor includes a third edge neighboring the second edge of the first semiconductor die, a fourth edge opposite the third edge, and a second metal layer exposed from the third edge. The first metal layer of the first semiconductor die is electrically connected to the second metal layer of the second semiconductor die. | 2022-07-28 |
20220238447 | SEMICONDUCTOR DEVICE - According to one embodiment, a semiconductor device includes at least a package substrate, an external electrode, a mounting substrate, and a mounting electrode. A signal connection point of the external electrode is provided at an end portion in a longitudinal direction of the external electrode. A signal connection point of the mounting electrode is provided at an end portion of the mounting electrode. The end portion of the mounting electrode is opposite to the signal connection point of the external electrode facing to the mounting electrode in the longitudinal direction. | 2022-07-28 |
20220238448 | CHIP MODULE WITH ROBUST IN-PACKAGE INTERCONNECTS - Disclosed are chip module structures, each having a robust in-package interconnect for reliable performance. Some of the chip module structures achieve interconnect robustness through the use of vias in a spiral step pattern within the interconnect itself. Some chip module structures achieve interconnect robustness through the use of an interconnect stabilizer (referred to herein as a stabilization structure, fence or cage)), which includes vias in a repeating step pattern encircling the in-package interconnect, which is electrically isolated from back side solder balls, front side collapse chip connections (referred to herein as C4 connections), and the interconnect itself, and which is optionally connected to ground. Some chip module structures achieve interconnect robustness through the use of a combination of both vias in a spiral step pattern within the interconnect itself and an interconnect stabilizer. | 2022-07-28 |
20220238449 | HYBRID INTEGRATED CIRCUIT PACKAGE - Disclosed herein are multi-layer substrates for integrated circuit packages and methods of making the same. The multi-layer substrate may comprise a plurality of lower layers, at least one core layer, a plurality of upper layers, and a side surface. A first connection and a second connection may extend through or on an uppermost layer of the plurality of upper layers. A trace may be embedded in or on one of the plurality of upper layers, the trace electrically connected to the first connection and the second connection. A first mounting pad and a second mounting pad may be positioned on the side surface and/or the uppermost layer of the plurality of upper layers and a blocking capacitor may be electrically connected to the first mounting pad and the second mounting pad with the second mounting pad electrically connected to the second connection. | 2022-07-28 |
20220238450 | METHODS OF FABRICATING LEADLESS POWER AMPLIFIER PACKAGES INCLUDING TOPSIDE TERMINATIONS - Leadless power amplifier (PA) packages and methods for fabricating leadless PA packages having topside terminations are disclosed. In embodiments, the method includes providing electrically-conductive pillar supports and a base flange. At least a first radio frequency (RF) power die is attached to a die mount surface of the base flange and electrically interconnected with the pillar supports. Pillar contacts are further provided, with the pillar contacts electrically coupled to the pillar supports and projecting therefrom in a package height direction. The first RF power die is enclosed in a package body, which at least partially defines a package topside surface opposite a lower surface of the base flange. Topside input/out terminals are formed, which are accessible from the package topside surface and which are electrically interconnected with the first RF power die through the pillar contacts and the pillar supports. | 2022-07-28 |
20220238451 | COBALT BASED INTERCONNECTS AND METHODS OF FABRICATION THEREOF - An embodiment includes a metal interconnect structure, comprising: a dielectric layer disposed on a substrate; an opening in the dielectric layer, wherein the opening has sidewalls and exposes a conductive region of at least one of the substrate and an interconnect line; an adhesive layer, comprising manganese, disposed over the conductive region and on the sidewalls; and a fill material, comprising cobalt, within the opening and on a surface of the adhesion layer. Other embodiments are described herein. | 2022-07-28 |
20220238452 | METHOD FOR PREPARING SEMICONDUCTOR DEVICE STRUCTURE WITH CONDUCTIVE PLUGS OF DIFFERENT ASPECT RATIOS AND MANGANESE-CONTAINING LINLING LAYER - The present disclosure provides a method for preparing a semiconductor device structure. The method includes preparing a substrate having a pattern-dense region and a pattern-loose region; forming a first conductive layer disposed over the substrate; forming a first dielectric layer disposed over the first conductive layer; etching the first dielectric layer to form a first opening and a second opening exposing the first conductive layer; forming a first lining layer and a first conductive plug in the first opening and a second conductive plug in the second opening, wherein the first lining layer comprises manganese (Mn), the first conductive plug comprises copper (Cu), and the first conductive plug and the second plug are surrounded by the first lining layer; and forming a second conductive layer over the first dielectric layer, the first lining layer and the first conductive layer, wherein the second conductive layer comprises copper (Cu). | 2022-07-28 |
20220238453 | THREE-DIMENSIONAL MEMORY DEVICE INCLUDING MOLYBDENUM CARBIDE OR CARBONITRIDE LINERS AND METHODS OF FORMING THE SAME - A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers, and memory stack structures vertically extending through the alternating stack. Each of the memory stack structures includes a respective vertical semiconductor channel and a respective vertical stack of memory elements located at levels of the electrically conductive layers. Each of the electrically conductive layers includes a respective conductive liner comprising molybdenum carbide or carbonitride, and a respective molybdenum metal fill material portion. | 2022-07-28 |
20220238454 | SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF - A semiconductor structure includes a multi-level interconnect structure, a passivation layer, a barrier layer, and a pad layer. The passivation layer is above the multi-level interconnect structure. The barrier layer lines an inner sidewall of the passivation layer, a top surface of the passivation layer and a top surface of a conductive line of the multi-level interconnect structure. The barrier layer includes a first layer, a second layer, a third layer, and a fourth layer. The first layer is in a nano-crystalline phase. The second layer is above the first layer and in an amorphous phase. The third layer is above the second layer and in a polycrystalline phase. The fourth layer is above the third layer and in a nano-crystalline phase. The pad layer is above the barrier layer. | 2022-07-28 |
20220238455 | MODULE - A module includes a substrate having a first surface, a first component and a second component that are mounted on the first surface, a first conductive material mounted between the first component and the second component, a first sealing resin provided on the first surface to cover the first component, the second component, and the first conductive material, and a first shield film that covers the first sealing resin, in which the first sealing resin has a recess to expose at least a part of the first conductive material, the first shield film extends along an inner surface of the recess and is, thereby, electrically connected to the first conductive material, the first shield film is provided with an opening in the recess, a metal bump is disposed inside the recess, and the metal bump is electrically connected to the first conductive material through the opening. | 2022-07-28 |
20220238456 | PACKAGE STRUCTURE AND METHOD OF FABRICATING THE SAME - A package structure includes a redistribution structure, a first semiconductor die, a first passive component, a second semiconductor die, a first insulating encapsulant, a second insulating encapsulant, a second passive component and a global shielding structure. The redistribution structure includes dielectric layers and conductive layers alternately stacked. The first semiconductor die, the first passive component and the second semiconductor die are disposed on a first surface of the redistribution structure. The first insulating encapsulant is encapsulating the first semiconductor die and the first passive component. The second insulating encapsulant is encapsulating the second semiconductor die, wherein the second insulating encapsulant is separated from the first insulating encapsulant. The second passive component is disposed on a second surface of the redistribution structure. The global shielding structure is surrounding the first insulating encapsulant, the second insulating encapsulant, and covering sidewalls of the redistribution structure. | 2022-07-28 |