30th week of 2010 patent applcation highlights part 28 |
Patent application number | Title | Published |
20100188838 | ILLUMINATING APPARATUS - A peak of the radiation directivity of light emitted by each of LEDs is directed to a reflecting surface, and the light emitted by the LEDs is indirectly incident on an outer lens after reflection by the reflecting surface. Thus, problems, such as a local increase in brightness of a light emitting surface over areas corresponding to light emitting portions of the LEDs, are prevented. In addition, most of the light emitted by the LEDs is indirectly incident on the outer lens via the reflecting surface, so that dispersion of blue light and yellow light, which constitute the white light, by the outer lens is prevented. Thus, illumination light highly uniform in amount and color can be provided. | 2010-07-29 |
20100188839 | LIGHT EMITTING DIODE LIGHTING SYSTEM - A lighting system for generating an illumination product comprises an excitation source, blue/UV LED, operable to generate excitation radiation and a remotely located phosphor, photo luminescent material. Excitation radiation is guided from the excitation source to the phosphor by a waveguiding medium, the waveguiding medium being configured such that the distance the radiation travels from the excitation source to the phosphor layer is at least one centimeter in length. The UV/blue excitation source provides excitation radiation to the phosphor(s), causing the phosphor(s) to photo luminesce, and it may also provide a component of the final illumination product. The configuration of the waveguide allows a greater flexibility in lighting system configurations, such as hanging lighting fixtures, desk lighting fixtures, floor standing lighting fixtures, desk lamps, track lighting, spot lighting, accent lighting, lighting panels, inspection lamps and endoscopes. | 2010-07-29 |
20100188840 | BACKLIGHT ASSEMBLY AND DISPLAY DEVICE HAVING THE SAME - A backlight assembly includes a first substrate, a first electrode disposed on the first substrate, a second substrate disposed opposite to the first substrate, and a connector. The connector is disposed on the second substrate and includes a second electrode connected to the first electrode, and an elastic member which applies a force to the second electrode. The connector increases a contact force between the first electrode and the second electrode by applying the force to the second electrode. | 2010-07-29 |
20100188841 | LOUPE AND LIGHTING ASSEMBLY FOR CAMERA SENSOR DUST DETECTION - A loupe and lighting assembly for enhancing detection of dust particles on the optical sensor of a digital camera. The assembly is made of a cylindroid hollow-centered main frame body, into which is fixed a loupe lens. A battery housing is joined to the body in order to supply electrical power to a LED array. The LED array is made from a plurality of LED diodes mounted peripherally and around the inside of the cylindroid body, being tilted at an acute angle from the axis orthogonal to the plane of the cylindroid body so that all diodes axially converge toward a single focal point, at a certain distance from the main frame body. The dust particles scattered upon the sensor become clearly visible to an observer looking through the assembly when the dust particles location coincide with the LED common focal point. | 2010-07-29 |
20100188842 | Illumination Device for Paved Floor - An illumination device for illuminating a paved floor comprising a container, which comprises a box creating a cavity therein and a first frame, integrally connected to the upper rim of the box; an illumination set comprising at least one light source (e.g. LED), where the illumination set is installed inside the container, where at least one light source enables illumination of the illumination device; a cover, which is adapted to be seated within the first frame, where the cover enables light from the illumination set to be transferred therethrough; a second frame, enabling to hold the cover between the first and the second frame; and at least two fastening means enabling to fasten the second frame to the first frame to hold the cover therebetween. The illumination device may be configured to be installed in the paved floor as one of the floor's tiles. | 2010-07-29 |
20100188843 | EL POWER UNIT - A safety vest is sized to be worn by a human, wherein the vest has a front and back and left and right sides each having a shoulder portion. An EL strip is provided on each side of the vest extending from the bottom of the vest upwards toward the shoulder portion. A power source is supported by the vest and connected to the EL lamp strips to supply electrical energy to the strips so that they emit EL light, wherein the EL light emitted by the EL strip is a safety yellow color, and wherein other portions of the vest are a safety orange color. Further safety articles of clothing and devices are also described, including a power pack unit. | 2010-07-29 |
20100188844 | MOBILE ILLUMINATING DEVICE COMPRISING A TUBULAR HOUSING - A mobile illuminating device includes a generally cylindrical housing including: illuminating elements in the form of light-emitting diodes (LED) fixed on a support plate, electrical/electronic control and/or connectors between the illuminating elements and a battery. An axially extending section of the housing forms an interior space divided into a plurality of receptacles occupying respective circumferentially adjacent portions of the axial section. A first of the receptacles contains the diodes and a second of the receptacles contains batteries. | 2010-07-29 |
20100188845 | Lighting Apparatus and Connector Plate - Lighting apparatus and structures are described that are adapted for installation in housings. The housings can be pre-existing ones, such as those installed for high-intensity discharge (HID) or other types of lighting. The lighting apparatus can include a light unit (e.g., luminaire) with desired type of light source(s), for example, an array of LEDs. The apparatus can include structures that are adapted for use with the housings such that installation of a light unit requires a minimum of user effort and time. Such lighting apparatus, and related installation methods, can accordingly provide for high-efficiency lighting. Related assembly and installation techniques are also described. | 2010-07-29 |
20100188846 | ILLUMINATING DEVICE - An illuminating device is provided which is capable of being used for a variety of illuminating applications by combining panel cases housing surface light emitting bodies and of realizing light modulation control in a state in which each panel case is being combined. To one end of a long panel case | 2010-07-29 |
20100188847 | Lamp holder - A lamp holder is made by extrusion of aluminum. The lamp holder includes at least one recess for receiving an illuminator. The recess is defined by a mounting face, a first reflective face and a second reflective face. The mounting face is at 18 to 25 degrees from a horizontal plane. The first reflective face is at 120 to 130 degrees from a lower edge of the mounting face. The second reflective face is at 110 to 120 degrees from an upper edge of the mounting face. | 2010-07-29 |
20100188848 | ELECTRO-THERMAL SEPARATION LIGHT EMITTING DIODE LIGHT ENGINE MODULE - An electro-thermal separation light emitting diode light engine module includes a heat dissipater, an illuminating module and a printed circuit board. The illuminating module is provided on the heat dissipater and is provided with at least one contact end. The printed circuit board is transfixed with at least one hole for accepting the illuminating module and is provided with a circuit for electrically connecting the contact end. Therefore, the illuminating module can be cooled directly through the heat dissipater and can be connected electrically by the circuit of the printed circuit board, achieving the practical progressiveness by providing a better heat dissipation effect and reducing cost. | 2010-07-29 |
20100188849 | LED LIGHTING FIXTURE - The invention provides an LED lighting fixture capable of adjusting light distribution very conveniently. The LED lighting fixture of the invention includes LED light sources and radiator, the radiator is provided with mounting surface arrays and the LED light sources are mounted on the mounting surface arrays. The LED light sources are mounted on the mounting surface arrays, thus realizing secondary distribution of the LED light source and being capable of adjusting light distribution very conveniently as required; separate design of the radiator and the support frame facilitates realization of diversified appearances; and integrated heat radiation design fulfills heat radiation requirements. The LED lighting fixture can be a good substitute for the conventional lighting fixtures, has the advantages of being environment-friendly, efficient, energy-saving, safe and reliable, and can be widely applied to highways, urban roads, industrial parks, schools, squares, tunnels, etc. | 2010-07-29 |
20100188850 | LIGHT FIXTURE AND ASSOCIATED LED BOARD AND MONOLITHIC OPTIC - An embodiment of the invention is directed to a light fixture useful for area lighting. The light fixture includes a housing having a base and a top, and a light emitting diode (LED) light emission module disposed within the housing. The light emission module includes a centrally disposed aperture that receives a centrally disposed power lead for powering the light emission module. | 2010-07-29 |
20100188851 | Lighting Retrofit - A lighting fixture retrofit comprised of a reflector, light bulb receptacles, receptacle covers and a device for attachment to pre existing light fixtures. | 2010-07-29 |
20100188852 | ILLUMINATION DEVICE WITH SEMICONDUCTOR LIGHT-EMITTING ELEMENTS - An illumination device includes a base board, an insulator, a conductor, a plurality of semiconductor light-emitting elements and a light-transmissive sealing member. The base board includes a surface and projection portions. The projection portion is formed to become gradually thicker from its end toward the surface of the base board. The insulator is formed on the surface. The conductor is formed on the insulator. The semiconductor light-emitting elements are mounted on the projection portions. The semiconductor light-emitting elements are electrically connected to the conductor via connection members. The sealing member covers the insulator, the projection portions, the semiconductor light-emitting elements and the connection members. | 2010-07-29 |
20100188853 | LIGHT EMITTER - A light emitter is disclosed herein. An embodiment of the light emitter comprises a substrate having a substrate surface; a light emitting diode located on the substrate surface; an encapsulant located on the substrate surface and encapsulating the light emitting diode; and a reflector cup attached to the substrate, the reflector cup having a reflector cup first side and a reflector cup second side with a hole extending between the reflector cup first side and the reflector cup second side, wherein the reflector cup first side is attached to the substrate surface so that the hole in the reflector cup first side encompasses the light emitting diode. | 2010-07-29 |
20100188854 | LIGHT EMITTING DEVICE - A light-emitting device for gently projecting light is disclosed. The light-emitting device includes a light emitter having a first electrode and a second electrode disposed on the light emitter for emitting light, an encapsulation for encapsulating the light emitter, part of the first electrode, and part of the second electrode with a concave lens disposed on one side of the encapsulation, a reflective material attached to the convex reflector, and a concave reflective substrate disposed beneath the encapsulation to manipulate light and meet specific illumination needs. | 2010-07-29 |
20100188855 | HIGH-PRESSURE DISCHARGE LAMP, LAMP UNIT USING THE SAME, AND PROJECTION-TYPE IMAGE DISPLAY DEVICE USING THE LAMP UNIT - A short arc high-pressure discharge lamp has an arc tube | 2010-07-29 |
20100188856 | Multiple Reflective Lenses and Lens Systems - A variety of lenses, lens assemblies, imaging devices, applications for such lenses, assemblies and devices, and related methods of operation and manufacturing are disclosed. At least some embodiments of the invention relate to a lens that includes first and second inward-facing surfaces that are each at least partly reflective. The lens further includes a first aperture that is positioned around at least a portion of an outer periphery of one of the first and second inward-facing surfaces, and a second aperture existing proximate a central region of the lens. The light proceeding within the lens between the first and second inward-facing surfaces is reflected at least twice on at least one of the first and second inward-facing surfaces as it travels between the first aperture and the second aperture. | 2010-07-29 |
20100188857 | OPTICAL LENS STRUCTURE - An optical lens structure is disclosed. The optical lens structure is suitable to cover a light emitting source, wherein the light emitting source is suitable to provide an illumination light. The optical lens structure includes a trench structure and two optical light-emitting surfaces. The two optical light-emitting surfaces are located at both sides opposite to each other of the trench structure and physically connect the trench structure. The illumination light from the light emitting source is transmitted from the optical light-emitting surfaces to a direction far away from the light emitting source. | 2010-07-29 |
20100188858 | LIGHT REDIRECTING FILMS AND FILM SYSTEMS - Light redirecting film comprises a thin optically transparent substrate having a pattern of individual optical elements of well defined shape on or in at least one surface that are quite small relative to the length and width of the surface. At least some of the optical elements have at least one flat surface and at least one curved surface and may intersect each other to a greater extent on the curved surface than on the flat surface to increase the relative percentage of flat surface area to curved surface area of the intersecting optical elements. | 2010-07-29 |
20100188859 | REFLECTING ASSEMBLY OF A SIMULATED FIREPLACE - The invention presents a reflecting assembly of a simulated fireplace which comprises a shaft and a reflecting strip arranged with a plurality of reflectors, wherein a plurality of through openings being configured on the reflecting strip along the length direction, and the shaft extending inside the through openings sequentially. With the above solutions, the reflecting assembly according to the present invention has an advantage in that the shaft could be a simple round rod without any openings on it. After the shaft goes through the through openings sequentially, each of the reflectors is simply twisted towards a certain direction so as to form the reflecting assembly. The present invention has the advantages over the prior art in that the fabrication is easier, and in that the reflecting strip could be replaced as required since it's detachable from the shaft. | 2010-07-29 |
20100188860 | LOTUS BLOSSOM HEAT DISSIPATING DEVICE - The present invention relates to a lotus blossom heat dissipating device, wherein a heat dissipating device is structured from a circuit substrate and at least one heat dissipating plate, one side of which is connected to the back of the circuit substrate. The heat dissipating plate conducts away the heat produced by light-emitting elements, and a stacking method is used to additionally assemble a plurality of the heat dissipating plates. The circuit substrate is mounted with at least one light-emitting element, from which extend electric conducting electrical elements. The circuit substrate has a plurality of holes, the heat dissipating plates having coinciding holes corresponding to the plurality of holes, with the electrical elements penetrating the aforementioned holes. Accordingly, heat produced from the activated light-emitting elements is quickly conducted away through the heat dissipating plates, thereby providing a simple structure, and achieving the objective of saving on costs. | 2010-07-29 |
20100188861 | Light-Emitting Member and its Forming Mold - A forming mold of a light-emitting member according to the present invention at least comprises: a frame, an upper mold and a lower mold, and the frame is provided with carriers, pins and supporting portions. The upper and lower molds match with each other to provide a forming space for the base of the light-emitting member. The forming space contains the carriers and a part of the supporting portions. One or more projections are disposed at the position where the brinks of the upper and lower molds contact the supporting portions. After injection molding, the burrs formed by a plastic material along the supporting portions can be concealed in the recesses that are formed corresponding to each of the projections, thereby reducing the influence of the burrs on the external size of the base. | 2010-07-29 |
20100188862 | MAGNETICALLY MOUNTED LIGHT FOR USE IN INSPECTING STEEL BELTED TIRES - The invention includes a light assembly which is configured to magnetically mount on a steel belted tire and a method of inspecting the inside of the tire using the light assembly. | 2010-07-29 |
20100188863 | HOLDER FOR REMOVABLY ATTACHING A TOOL TO AN OBJECT AND METHOD THEREOF | 2010-07-29 |
20100188864 | Method and Apparatus for Vehicle With Adaptive Lighting System - In one embodiment, an adaptive external vehicle lighting system includes a vehicle communication network, a memory including program instructions for generating a model of a vehicle and the environment outside of the vehicle, identifying an object of interest based upon the generated model, analyzing rendering criteria associated with the identified object of interest, and rendering object of interest data based upon the analysis, a processor operably connected to the vehicle communication network and to the memory for executing the program instructions, and at least one rendering system operably connected to the processor through the vehicle communication network for rendering the object of interest data using an associated external lighting system of the vehicle. | 2010-07-29 |
20100188865 | LIGHT SOURCE MODULE AND VEHICULAR LAMP - A light source module includes a substrate made with a recess portion formed on one face and an unformed portion not having the recess portion formed therein; a light emitting diode disposed on the recess portion of the substrate; a pair of power supply members disposed on the unformed portion of the substrate; and a connecting portion formed on the substrate and connecting the light emitting diode and the pair of power supply members. A part of an end edge of the recess portion conforms to a part of a side edge of the substrate. | 2010-07-29 |
20100188866 | Vehicle room light apparatus - The present invention provides a vehicle room light apparatus which is small in size and achieves high heat dissipation. The vehicle room light apparatus includes a light source; a switch; and a case including a front surface as a designed surface and a back surface. The back surface having a first region on which the light source and the switch are arranged in line, a second region which has a space extending along the first region and an opening continuing to the space, a partition wall which separates the first and the second regions. | 2010-07-29 |
20100188867 | LIGHT EMITTING DIODE LIGHTING SYSTEM - A lighting system for generating an illumination product comprises an excitation source, blue/UV LED, operable to generate excitation radiation and a remotely located phosphor, photo luminescent material. Excitation radiation is guided from the excitation source to the phosphor by a waveguiding medium, the waveguiding medium being configured such that the distance the radiation travels from the excitation source to the phosphor layer is at least one centimeter in length. The UV/blue excitation source provides excitation radiation to the phosphor(s), causing the phosphor(s) to photo luminesce, and it may also provide a component of the final illumination product. The configuration of the waveguide allows a greater flexibility in lighting system configurations, such as hanging lighting fixtures, desk lighting fixtures, floor standing lighting fixtures, desk lamps, track lighting, spot lighting, accent lighting, lighting panels, inspection lamps and endoscopes. | 2010-07-29 |
20100188868 | Three-layer light guiding structure - A three-layer light guiding structure includes a light-guiding layer having a light-output face with a plurality of patterned points imprinted thereon; a middle light-transmittable layer being located at a bottom of the light-guiding layer opposite to the light-output face; and a reflecting layer being located at a bottom of the middle light-transmittable layer opposite to the light-guiding layer. The three-layer light guiding structure is formed through the coextrusion molding process, so that the light-guiding layer, the middle light-transmittable layer and the reflecting layer are integrally formed and bonded to one another after the molding. | 2010-07-29 |
20100188869 | POWER SYSTEM HAVING AC AND DC POWER SOURCES - A power system ( | 2010-07-29 |
20100188870 | CHARGE MODE CONTROL - An apparatus and a method for converting power from a power input to an DC output voltage or current, which apparatus has a serial resonance converter, where a first feedback circuit is connected from the output terminal to an error amplifier, where the apparatus further has a second feedback circuit with at least one first resistor that is connected to a coil and to ground, which second feed back circuit connects the line between the first resistor and the coil and towards an inverting integrator, the output of which is connected through a second capacitor to a second input at a control circuit. As a result, the oscillating frequency is under influence of a signal that depends on the voltage generated in the resistor connected in serial to the coil or transformer. | 2010-07-29 |
20100188871 | SYNCHRONOUS RECTIFIER NETWORK UNIT CIRCUIT AND METHOD - A synchronous rectifier network unit and synchronous rectifying method. The synchronous rectifier network unit includes a first body diode to which a first current flows at a first time when the first current flows to a first coil, and a first transistor which is turned on after the first body diode is conducted, and to which the first current flows, and it rectifies the first current by differently controlling the turn-off time of the first transistor according to the first current. | 2010-07-29 |
20100188872 | ISOLATED SWITCHING POWER SUPPLY DEVICE - An isolated switching power supply device includes a main transformer having a primary coil on a primary circuit side and a secondary coil on a secondary circuit side. On the primary circuit side are disposed an input smoothing capacitor, a switching control circuit, a high-side driver, a low-side power switch, a high-side power switch, capacitors, and edge signal-generating circuits. A symmetrical control half bridge converter is thus provided. The secondary circuit side has a voltage clamping circuit including a clamp capacitor, a clamp switch and a diode. | 2010-07-29 |
20100188873 | COMPENSATING ON-TIME DELAY OF SWITCHING TRANSISTOR IN SWITCHING POWER CONVERTERS - A switch controller compensates the total on-time delay of the switch in a switching power converter. The intended on-time of the switching transistor for the present switching cycle is reduced by the time difference between the actual on-time and the intended on-time of the switching transistor in the previous switching cycle in the switching power converter. The total delay of the switch in the switching power converter, including propagation delay, switch turn-on delay, and switch turn-off delay, can be compensated in real time, cycle by cycle. | 2010-07-29 |
20100188874 | AC - DC CONVERTER - AC-DC converter is provided which comprises an auxiliary winding | 2010-07-29 |
20100188875 | High Voltage and Frequency Distributed Power System - A switching power supply transmits power between a single front end including electromagnetic interference filtering and power factor correction circuits to an output end at a high voltage and high frequency from which any desired DC voltage or waveform may be readily and directly derived with high efficiency in order to reduce size and weight of components including transformers at the output end and allow greater variety of connection wiring of reduced weight and volume to be used. The high frequency is limited at the low frequency end by the frequency at which significant power can be transferred through, for example, a ferrite core or other transformer of sufficiently low volume to accommodate closely spaced loads or power converters and at the high frequency end by the wavelength in the connection wiring such that 1/10 wavelength is greater than one thousand feet. Branches of the power distribution system which are not desired to be in use can be operated at zero power and be brought back on line within milliseconds, when needed. Power distribution among respective branches of the power distribution system can be controlled by varying the high frequency of power transmission and appropriate filtering. | 2010-07-29 |
20100188876 | Controller for a Power Converter - A controller for a power converter and method of operating the same employable with a bridge rectifier having first and second synchronous rectifier switches. In one embodiment, the controller includes an amplifier configured to enable a turn-on delay for the first synchronous rectifier switch SR. The controller also includes a discharge switch Q | 2010-07-29 |
20100188877 | Storage device - The object of the invention is to avoid an unselected data line being driven in a memory array composed of memory cells each of which uses a storage element depending upon variable resistance and a selection transistor when the selection transistors in all memory cells on a selected word line conduct. To achieve the object, a source line parallel to a data line is provided, a precharge circuit for equipotentially driving both and a circuit for selectively driving the source line are arranged. Owing to this configuration, a current path is created in only a cell selected by a row decoder and a column decoder and a read-out signal can be generated. Therefore, a lower-power, lower-noise and more highly integrated nonvolatile memory such as a phase change memory can be realized, compared with a conventional type. | 2010-07-29 |
20100188878 | SEMICONDUCTOR DEVICE THAT SUPRESSES MALFUNCTIONS DUE TO VOLTAGE REDUCTION - A semiconductor device includes a first pad that supplies power to sense amplifiers, a second pad that supplies power to a first circuit connected to the sense amplifiers, a third pad that receives a signal input or outputs a signal at a frequency equal to or higher than a first frequency, and a fourth pad that receives a signal input or outputs a signal at a second frequency lower than the first frequency. The first pad is arranged between and adjacent to the second pads respectively, or arranged between and adjacent to the second and fourth pads respectively. Additionally, the first pad is arranged between the third pads, which are respectively arranged on both sides of the first pad, to be adjacent to the second pad so as to hold the second pad or to be adjacent to the fourth pad so as to hold the fourth pad. | 2010-07-29 |
20100188879 | Cross-point semiconductor memory device and method of manufacturing the same - A cross-point semiconductor memory device includes: a plurality of first wirings extending in a first direction; a plurality of second wirings positioned on a layer different from the first wirings to extend in a second direction different from the first direction; and memory parts provided in overlap areas of the first wirings and the second wirings, wherein the odd-numbered first wirings and the even-numbered first wirings are arranged on different insulating interlayers in an up-down direction. | 2010-07-29 |
20100188880 | POWER SWITCHING FOR PORTABLE APPLICATIONS - A voltage generation and power switching apparatus, method and system is described. The apparatus includes a digital media processing chip. The digital media processing chip includes a control unit, a one-time programmable memory, a charge pump and a switching network. The control unit is to receive an operating state. The charge pump is connected to a first voltage and configured to generate a second voltage using the first voltage. The control unit activates the charge pump based upon the received operating state. The one-time programmable memory is connected to the charge pump via a switching network. The switching network is configured by the control unit to provide a voltage required by the received operating state to the one-time programmable memory. | 2010-07-29 |
20100188881 | Method and Device for Correcting and Obtaining Reference Voltage - The present invention discloses a method for adjusting a reference voltage, including: decoding a default code configured in a reference voltage register in a chip to obtain an actual reference voltage; comparing the actual reference voltage with a benchmark value to obtain a deviation value between the two; configuring an adjustment code according to the deviation value; and, burning the adjustment code into a nonvolatile storage medium. The present invention also discloses an apparatus for adjusting a reference voltage. According to the method and apparatus for adjusting a reference voltage provided by embodiments of the present invention, the reference voltage need not be adjusted according to an external power supply's different application schemes. Thus, adjustment on the reference voltage of the chip is standardized and costs of the chip's application schemes are saved. Embodiments of the present invention further provide a method and apparatus for obtaining a reference voltage, which makes it not necessary to configure a dedicated reference voltage pin in the chip for introducing an external reference voltage, and thus stability of the circuit's working is improved and costs of the chip's applications are decreased. | 2010-07-29 |
20100188882 | NONVOLATILE FERROELECTRIC MEMORY AND CONTROL DEVICE USING THE SAME - A nonvolatile ferroelectric memory immediately outputs data stored in a page buffer without performing a cell access operation when a page buffer is accessed. Since a block page address region and a column page address region are arranged in less significant bit region, and a row address region is arranged in more significant bit region, the cell operation is not performed in the access of the page address buffer, thereby improving reliability of the cell and reducing power consumption. | 2010-07-29 |
20100188883 | Simultaneously Writing Multiple Addressable Blocks of User Data to a Resistive Sense Memory Cell Array - Method and apparatus are disclosed for storing data to non-volatile resistive sense memory (RSM) memory cells of a semiconductor memory array, including but not limited to resistive random access memory (RRAM) and spin-torque transfer random access memory (STTRAM or STRAM) cells. In accordance with various embodiments, a plurality of addressable data blocks from a host device are stored in a buffer. At least a portion of each of the addressable data blocks are serially transferred to a separate register of a plurality of registers. The transferred portions of said addressable data blocks are thereafter simultaneously transferred from the registers to selected RSM cells of the array. | 2010-07-29 |
20100188884 | NONVOLATILE MEMORY ELEMENT, NONVOLATILE MEMORY APPARATUS, AND METHOD OF WRITING DATA TO NONVOLATILE MEMORY ELEMENT - A nonvolatile memory element comprises a first electrode ( | 2010-07-29 |
20100188885 | RESISTANCE CHANGE MEMORY DEVICE AND PROGRAMMING METHOD THEREOF - A method of programming a resistance change memory device includes: applying program voltage pulses to a memory cell for programming a target resistance value; setting thermal relaxation times between the respective program voltage pulses; and controlling the shape of each the program voltage pulse in accordance with the present cell's resistance value determined by the preceding program voltage pulse application. | 2010-07-29 |
20100188886 | Implementing Enhanced SRAM Stability and Enhanced Chip Yield With Configurable Wordline Voltage Levels - An array built in self test (ABIST) method and circuit for implementing enhanced static random access memory (SRAM) stability and enhanced chip yield using configurable wordline voltage levels, and a design structure on which the subject circuit resides are provided. A wordline is connected to a SRAM memory cell. A plurality of wordline voltage pulldown devices is connected to the wordline. A respective wordline voltage control input signal is applied to each of the plurality of wordline voltage pulldown devices to selectively adjust the voltage level of the wordline. | 2010-07-29 |
20100188887 | Semiconductor integrated circuit device - The invention provides a semiconductor integrated circuit device provided with an SRAM that satisfies the requirements for both the SNM and the write margin with a low supply voltage. The semiconductor integrated circuit device include: multiple static memory cells provided in correspondence with multiple word lines and multiple complimentary bit lines; multiple memory cell power supply lines that each supply an operational voltage to each of the multiple memory cells connected to the multiple complimentary bit lines each; multiple power supply circuits comprised of resistive units that each supply a power supply voltage to the memory cell power supply lines each; and a pre-charge circuit that supplies a pre-charge voltage corresponding to the power supply voltage to the complimentary bit lines, wherein the memory cell power supply lines are made to have coupling capacitances to thereby transmit a write signal on corresponding complimentary bit lines. | 2010-07-29 |
20100188888 | Implementing Enhanced Dual Mode SRAM Performance Screen Ring Oscillator - A method and circuit for implementing an enhanced dual-mode static random access memory (SRAM) performance screen ring oscillator (PSRO), and a design structure on which the subject circuit resides are provided. The dual-mode SRAM PSRO includes a plurality of SRAM base blocks connected together in a chain. Each of the plurality of SRAM base blocks includes an eight-transistor (8T) SRAM cell, a local evaluation circuit and a logic function coupled to the SRAM cell. The eight-transistor (8T) static random access memory (SRAM) cell is an unmodified 8T SRAM cell. The dual-mode SRAM PSRO includes one mode of operation, where the output frequency is determined by write-through performance of the 8T SRAM cell; and another mode of operation, where the output frequency is determined by read performance of the 8T SRAM cell. | 2010-07-29 |
20100188889 | BACK GATED SRAM CELL - Methods, devices and systems for a back gated static random access memory (SRAM) cell are provided. One method embodiment for operating an SRAM cell includes applying a potential to a back gate of a pair of cross coupled p-type pull up transistors in the SRAM during a write operation. The method includes applying a ground to the back gate of the pair of cross coupled p-type pull up transistors during a read operation. The charge stored on a pair of cross coupled storage nodes of the SRAM is coupled to a front gate and a back gate of a pair of cross coupled n-type pull down transistors in the SRAM during the write operation and during a read operation. | 2010-07-29 |
20100188890 | MAGNETORESISTANCE EFFECT ELEMENT AND MAGNETIC RANDOM ACCESS MEMORY - A magnetoresistance effect element includes: a magnetization free layer; a spacer layer provided adjacent to the magnetization free layer; a first magnetization fixed layer provided adjacent to the spacer layer on a side opposite to the magnetization free layer; and at least two second magnetization fixed layers provided adjacent to the magnetization free layer. The magnetization free layer, the first magnetization fixed layer, and the second magnetization free layers respectively have magnetization components in a direction substantially perpendicular to film surfaces thereof. The magnetization free layer includes: two magnetization fixed portions; and a domain wall motion portion arranged between the two magnetization fixed portions. Magnetizations of the two magnetization fixed portions constituting the magnetization free layer are fixed substantially antiparallel to each other in directions substantially perpendicular to the film surface. The domain wall motion portion is provided with magnetic anisotropy in a direction perpendicular to the film surface. | 2010-07-29 |
20100188891 | SEMICONDUCTOR DEVICE - The semiconductor device has: a first magnetoresistance element; a second magnetoresistance element. The first and second magnetoresistance elements each includes a free layer which can be changed in spin orientation therein and a pinned layer which is fixed in spin orientation therein. The first magnetoresistance element is coupled to a first transistor at the free layer, and to a first power-source terminal at the pinned layer. The second magnetoresistance element is coupled to a second transistor at the free layer, and to the first power-source terminal at the pinned layer. In this device, the reliability of stored data is increased by preventing an undesired resistance condition's change in a magnetoresistance memory cell. | 2010-07-29 |
20100188892 | ELECTRIC DEVICE COMPRISING PHASE CHANGE MATERIAL AND HEATING ELEMENT - An electric device has a resistor including a phase change material changeable between a first phase and a second phase within a switching zone. The resistor has a first resistance when the phase change material is in the first phase and a different second resistance, when the phase change material is in the second phase. The resistor may conduct a first current. The device has a heating element that may conduct a second current for enabling a transition of the phase change material from the first to the second phase. At the position of the switching zone, the resistor is arranged as a first line and the heating element is arranged as a second line. The first and second line may conduct the first current and the second current respectively, wherein the first line and the second line cross at the position of the switching zone. | 2010-07-29 |
20100188893 | Heat assisted switching and separated read-write MRAM - A MRAM structure is described that has a dedicated data storage layer formed between first and second electrodes and a dedicated data sensing layer between second and third electrodes to enable separate read and write functions. A diode between the storage layer and first electrode allows a heating current to flow between first and second electrodes to switch the data storage layer while a field is applied. A second diode between the sensing layer and third electrode enables a sensing current to flow only between second and third electrodes during a read process. Data storage and sensing layers and the three electrodes may be arranged in a vertical stack or the sensing layer, second diode, and third electrode may be shifted between adjacent stacks each containing first and second electrodes, a storage layer, and first diode. Second electrode and the sensing layer may be continuous elements through multiple MRAMs. | 2010-07-29 |
20100188894 | IN-SITU RESISTANCE MEASUREMENT FOR MAGNETIC RANDOM ACCESS MEMORY (MRAM) - A method of measuring resistance of a magnetic tunnel junction (MTJ) of an MRAM memory cell includes applying a voltage of a selected level to a memory cell comprising an MTJ in series with a memory cell transistor in a conducting state. A current through the memory cell is determined. A variable voltage is applied to a replica cell not having an MTJ and comprising a replica cell transistor in a conducting state. A value of the variable voltage is determined, wherein a resulting current through the replica cell is substantially the same as the current through the memory cell. The MTJ resistance is computed by taking the difference of the memory cell voltage and the determined variable replica cell voltage and dividing the result by the determined memory cell current. | 2010-07-29 |
20100188895 | STAGGERED STRAM CELL - Spin-transfer torque memory having a free magnetic layer having a thickness extending in a out-of-plane direction and extending in a lateral direction in an in-plane direction between a first end portion and an opposing second end portion. A tunneling barrier separates a reference magnetic layer from the first end portion and forms a magnetic tunnel junction. A first electrode is in electrical communication with the reference magnetic layer and a second electrode is in electrical communication with the free magnetic layer second end portion such that current flows from the first electrode to the second electrode and passes through the free magnetic layer in the lateral direction to switch the magnetic tunnel junction between a high resistance state and a low resistance state. | 2010-07-29 |
20100188896 | NONVOLATILE SEMICONDUCTOR MEMORY AND METHOD FOR DETECTING LEAKAGE DEFECTS OF THE SAME - There is provided a nonvolatile semiconductor memory wherein a normal mode voltage is provided to a selected word line when a normal mode is selected, and a test mode voltage lower than the normal mode voltage is provided to the selected word line when a test mode is selected, thus leakage current is detected by selecting the test mode. | 2010-07-29 |
20100188897 | APPARATUS FOR REDUCING THE IMPACT OF PROGRAM DISTURB - The unintentional programming of an unselected (or inhibited) non-volatile storage element during a program operation that intends to program another non-volatile storage element is referred to as “program disturb.” A system is proposed for programming and/or reading non-volatile storage that reduces the effect of program disturb. In one embodiment, different verify levels are used for a particular word line (or other grouping of storage elements) during a programming process. In another embodiment, different compare levels are used for a particular word (or other grouping of storage elements) during a read process. | 2010-07-29 |
20100188898 | REDUCING EFFECTS OF PROGRAM DISTURB IN A MEMORY DEVICE - The programming disturb effects in a semiconductor non-volatile memory device can be mitigated by biasing unselected memory cells with a negative voltage while a well containing the memory cells receives a positive voltage. A selected memory cell in the well can be biased with a negative voltage while the well is at the positive voltage then the selected memory cell bias transitions to a positive programming voltage when the well returns to a ground potential. | 2010-07-29 |
20100188899 | NONVOLATILE ANALOG MEMORY - A nonvolatile analog memory has a floating gate point. The nonvolatile analog memory includes a capacitor. a first current source, a second current source and a current adjuster. The first current source controlled by a voltage value at the floating gate point and generates a first current. The second current source controlled by the voltage value at the floating gate point and generates a second current. The current adjuster receives the output voltage and a reference voltage and adjusts the first current and the second current based on the output voltage and the reference voltage. The current adjuster charges or discharges the capacitor to equalize the output voltage to the reference voltage. | 2010-07-29 |
20100188900 | ARRAY AND PITCH OF NON-VOLATILE MEMORY CELLS - An array of non-volatile memory cells is arranged in a plurality of rows and columns, wherein each memory cell has at least three terminals: a first terminal for the read out of the signal from the memory cell, a second terminal to which high voltage is supplied during certain operation, and a third terminal to which low voltage is supplied in all operations. The cells in the same column have a common bit line connected to the first terminal of memory cells in the same column. The array comprises a first and second sub arrays of memory cells arranged adjacent to one another in the same row. A first decoder is positioned to one side of the first sub array in the same row as the first sub array. A second decoder is positioned to another side of the second sub array in the same row as the second sub array. A first high voltage line is connected to the second decoder and to only the second terminal of the memory cells in the same row in the first sub array. A second high voltage line, different from the first high voltage line, is connected to the second decoder and to only the second terminal of the memory cells in the same row in the second sub array. A low voltage line is connected to the first decoder and to the thirds terminal of the memory cells in the same row of the first and second sub arrays. | 2010-07-29 |
20100188901 | Three-Terminal Single Poly NMOS Non-Volatile Memory Cell - A three terminal non-volatile memory (NVM) cell for a CMOS IC is formed by a standard CMOS process flow. The NVM cell includes two transistors that share a common floating gate. The floating gate includes a first portion disposed over the channel region of the first (NMOS) transistor, a second portion disposed over the channel region of the second (NMOS or PMOS) transistor, and a third portion extending into an enlarged drain diffusion area away from the channel regions, whereby the gate-to-drain capacitance is higher than the gate-to-source capacitances. A pocket implant or CMOS standard LV N-LDD is formed under the second transistor to enhance CHE programming. Both HV LDD and LV LDD implants are introduced together enabling LDD implant merging under the floating gate extension. The floating gate is formed using substantially T-shaped, C-shaped, U-shaped, Y-shaped or O-shaped polysilicon structures. Various array addressing schemes are disclosed. | 2010-07-29 |
20100188902 | Differential, level-shifted EEPROM structures - Memory embodiments are provided to operate in memory systems which are configured to have a system ground and a system substrate that are biased at different voltages. At least one of these embodiments includes a memory cell and write and read circuits in which the memory cell is coupled to the system substrate and the write and read circuits are coupled to the system ground. The memory cell preferably has a cross-coupled pair of transistors which can be set in first and second states. The write circuit is arranged and level shifted to drive the cross-coupled pair into either selected one of the states and the read circuit is arranged and level shifted to provide a data signal indicative of the selected state. | 2010-07-29 |
20100188903 | METHOD OF OPERATING NONVOLATILE MEMORY DEVICE - A method of operating a nonvolatile memory device includes performing a first program operation and a first verification operation on memory cells until a cell, having a threshold voltage higher than a first reference voltage, occurs and, when a cell having the threshold voltage higher than the first reference voltage occurs, performing a second program operation and performing a second verification operation using a second reference voltage higher than the first reference voltage. | 2010-07-29 |
20100188904 | MEMORY VOLTAGE CYCLE ADJUSTMENT - The present disclosure includes various method, device, system, and module embodiments for memory cycle voltage adjustment. One such method embodiment includes counting a number of process cycles performed on a first memory block in a memory device. This method embodiment also includes adjusting at least one program voltage, from an initial program voltage to an adjusted voltage, in response to the counted number of process cycles. | 2010-07-29 |
20100188905 | Spin Device - According to an embodiment of the present invention, a spin device includes an intermediate semiconductor region arranged between a first terminal and a second terminal, wherein the first terminal is adapted to provide a current having a first degree of spin polarization to the intermediate semiconductor region, and wherein the second terminal is adapted to output the current having a second degree of spin polarization. The spin device further includes a spin selective scattering structure abutting the intermediate semiconductor region, the spin selective scattering structure being adapted such that the first degree of spin polarization is altered to be the second degree, wherein the spin selective scattering structure comprises a control electrode being electrically insulated from the intermediate semiconductor region, and wherein the control electrode is adapted to apply an electrical field perpendicular to a direction of the current through the intermediate semiconductor region to control a magnitude of the current. | 2010-07-29 |
20100188906 | STROBE APPARATUS, SYSTEMS, AND METHODS - A strobe signal is received in a device and execution of an operation in the device is delayed when the strobe signal includes a preamble. Additional apparatus, systems, and methods are disclosed. | 2010-07-29 |
20100188907 | SEMICONDUCTOR DEVICE, CONTROL METHOD FOR SEMICONDUCTOR DEVICE, AND ELECTRONIC DEVICE - A semiconductor device including a first switch coupled to a first power supply line, a second switch coupled to the first switch and to a second power supply line, and a storage part provided in a path which is between the second power supply line and the first switch, and having a high resistance state and a low resistance state, and wherein the first switch is turned on and the second switch is turned off when a resistance state of the storage part is in a high resistance state. | 2010-07-29 |
20100188908 | Setting Memory Device VREF in a Memory Controller and Memory Device Interface in a Communication Bus - A memory device is connected through an interface to a memory controller. The memory device's reference voltage is set based on a driver's impedance of the memory device and the controller driver drive strength during driver training. The voltage is applied to a reference resistor pair at the memory device and changed until the voltage level switches. The voltage is then set at the reference resistor pair of the memory device. | 2010-07-29 |
20100188909 | MEMORY HAVING NEGATIVE VOLTAGE WRITE ASSIST CIRCUIT AND METHOD THEREFOR - A method of writing data to a selected column of a memory includes selecting a first column. The data writing is initiated by applying a logic high to a first bit line of the first column and a first potential to a second bit line of the first column that is lower than the logic high. The first potential is removed and a second potential is applied to the second bit line. The second potential is less than the first potential. The first potential may be ground, and the second potential may be a negative voltage. Reducing the write voltage for the bit line that is receiving a logic low improves its ability to be written. By first bringing the logic low to the first potential, which may be ground, and then further reducing the applied voltage, the requirements on the source of the second potential are reduced. | 2010-07-29 |
20100188910 | CLOCK SYNCHRONIZATION IN A MEMORY SYSTEM - A system and method for synchronizing a strobed memory system | 2010-07-29 |
20100188911 | MEMORY-WRITE TIMING CALIBRATION INCLUDING GENERATION OF MULTIPLE DELAYED TIMING SIGNALS - A memory controller with multiple delayed timing signals. Control information is provided by a first output driver circuit to a first signal path. Write data, associated with the control information, is provided by a second output driver circuit to a second signal path. Timing information is provided by a third output driver to a third signal path. Rising and falling edge transitions of the timing information indicate times at which subsequent symbols of the write data are valid on the signal path. The timing information is delayed with respect to the control information to account for a difference between a time that the control information takes to reach the destination device while traversing the first signal path and a time that the write data takes to reach the destination device while traversing the second signal path. | 2010-07-29 |
20100188912 | SEMICONDUCTOR MEMORY CIRCUIT AND CONTROL METHOD FOR READING DATA - A semiconductor memory device includes a first memory circuits connecting to a first bit line, a second bit line and a word line, a first pre-charge control circuit connecting to a first pre-charge control line, the first bit line and the second bit line and that pre-charges the first bit line and the second bit line on the basis of the input from the first pre-charge control line, and a read control circuit having a first transistor, a second transistor, a third transistor and a fourth transistor, wherein the fourth transistor is brought into conduction on the basis of the input from a charged global-bit-line driver control line, the column having the first bit line and the second bit line is thus selected, and the information held in the memory circuit connecting to the driven word line among the memory circuits is output to the third bit line. | 2010-07-29 |
20100188913 | SEMICONDUCTOR MEMORY DEVICE HAVING SENSE AMPLIFIER - A semiconductor memory device includes a memory cell array, a page buffer, a data line pair, a differential amplifier and a precharger. The memory cell array includes a plurality of pages in which a plurality of memory cells are arranged. The page buffer is formed adjacent to the memory cell array, and includes a plurality of sense amplifiers configured to temporarily hold page data read from the memory cells in the page. The data line pair is arranged in the page buffer and is connected to the sense amplifiers. The differential amplifier is configured to amplify a potential difference between lines of the data line pair. The precharger is configured to precharge the data line pair to a predetermined potential. At least one of the differential amplifier and the precharger is formed in the page buffer, and the at least one circuit is electrically connected to the data line pair. | 2010-07-29 |
20100188914 | SELF REFRESH OPERATION OF SEMICONDUCTOR MEMORY DEVICE - A method for driving a semiconductor memory device, includes initializing first data corresponding to a refresh time of each corresponding row included in a cell array; storing second data corresponding to column data included in the first row after entering a self refresh mode; setting the first data corresponding to the first row by detecting the refresh time of the first row while performing refresh operations on the other rows in the cell array according to a refresh period selected based on the corresponding first data for predetermined refresh cycles, wherein the refresh operation is not performed on the first row during the predetermined refresh cycles; restoring the second data to the first row; and repeating the above steps for the other rows to thereby set the corresponding first data until the setting step is completed for all rows or the self refresh mode expires. | 2010-07-29 |
20100188915 | SELF REFRESH OPERATION OF SEMICONDUCTOR MEMORY DEVICE - A method for driving a semiconductor memory device, includes initializing first data corresponding to a refresh time of each corresponding row included in a cell array; storing second data corresponding to column data included in the first row after entering a self refresh mode; setting the first data corresponding to the first row by detecting the refresh time of the first row while performing refresh operations on the other rows in the cell array according to a refresh period selected based on the corresponding first data for predetermined refresh cycles, wherein the refresh operation is not performed on the first row during the predetermined refresh cycles; restoring the second data to the first row; and repeating the above steps for the other rows to thereby set the corresponding first data until the setting step is completed for all rows or the self refresh mode expires. | 2010-07-29 |
20100188916 | Setting Memory Controller Driver to Memory Device Termination Value in a Communication Bus - A method and system are provided for coupling a DRAM and a memory controller during driver training to reduce mismatches by controlling impedances within the system environment. A memory device initializes a bit level voltage on a data net. A driver impedance in a driving element in the controller is modified to yield improvements in timing margins. | 2010-07-29 |
20100188917 | Setting Memory Device Termination in a Memory Device and Memory Controller Interface in a Communication Bus - A memory device and memory controller are coupled during driver training to reduce mismatches. The impedances of the system are controlled through a termination at the memory device to yield improvements in timing margins. The coupling of the components on a shared electrical bus through adjustment of the termination values during training removes known offset issues. | 2010-07-29 |
20100188918 | Setting Controller VREF in a Memory Controller and Memory Device Interface in a Communication Bus - A memory device is connected through an interface to a memory controller. The controller's reference voltage is set based on a driver's impendence of the memory device during driver training. The voltage is applied to a reference resistor pair at the controller and changed until the voltage level switches. The voltage is then set at the reference resistor pair of the controller. | 2010-07-29 |
20100188919 | Calibration of Memory Driver With Offset in a Memory Controller and Memory Device Interface in a Communication Bus - A method and system are provided for coupling a DRAM and a memory controller during driver training to reduce mismatches by controlling impedances within the system environment. The memory device, which is typically the device initializing a bit level voltage on a data net, is adjusted through altering what appears to be the reference voltage value to the memory device. A current driven to the memory device is varied in small increments while impedance training is rerun until a desired value is achieved to set the 0 level voltage on the data net. | 2010-07-29 |
20100188920 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A nonvolatile semiconductor memory device has an internal step-down power generation circuit and a memory circuit. The internal step-down power generation circuit generates a first internal power supply voltage from an external power supply voltage in an active state, and generates a second internal power supply voltage different from the first internal power supply voltage from the external power supply voltage in a standby state. The memory circuit includes a cell array containing a nonvolatile memory cell and a sense amplifier detecting data read from the cell array. The sense amplifier is supplied with a voltage generated by the internal step-down power generation circuit as an internal power supply voltage. | 2010-07-29 |
20100188921 | VOLTAGE PROTECTION CIRCUIT FOR THIN OXIDE TRANSISTORS, AND MEMORY DEVICE AND PROCESSOR-BASED SYSTEM USING SAME - Devices, reference voltage generators, systems and methods are disclosed, including an embodiment of a voltage regulator output transistor using a thin gate insulator to provide a low output impedance despite having a semiconductor channel width that is relatively small. The output transistor is protected from damage by a clamping circuit provided to limit the gate-to-source voltage of the transistor such that damage to the output transistor should be reduced or prevented. One such clamping circuit includes a clamp transistor that receives a reference voltage at its gate. The magnitude of the reference voltage limits to voltage to which the gate of the transistor can be driven. A voltage reference circuit provides the reference voltage so that it compensates for process and temperature variations of the output transistor. | 2010-07-29 |
20100188922 | SEMICONDUCTOR STORAGE DEVICE AND ELECTRIC APPARATUS - A semiconductor storage device includes a plurality of memory macros including a plurality of memory cell arrays; a low-potential power supply boosting circuit coupling the low-potential power supply to the ground in a normal mode and coupling the low-potential power supply to a voltage higher than a ground voltage in a sleep mode; a virtual power control circuits including a plurality of switches which is turned on when switching from the sleep mode to the normal mode and is turned off when switching from the normal mode to the sleep mode; and a sleep cancellation detecting circuit outputting, when the mode control signal supplied to the plurality of switches in one of the plurality of memory macros indicates to switch form the sleep mode to the normal mode, the mode control signal to a subsequent memory macro subsequent to the one of the plurality of memory macros. | 2010-07-29 |
20100188923 | SEMICONDUCTOR DEVICE - A semiconductor device 110 has a plurality of memory cell blocks provided with a plurality of memory cells storing a predetermined amount of data. Each memory cell block has four or more inputs and outputs, and is internally provided with a read address decoder to the memory cell and a sense amplifier for amplifying a voltage in outputting outside. Each memory cell block is structured so as to store a truth table data for outputting a desired logic value in response to a specified address input, thereby operating as a logic circuit. The memory cell has a read word line correspondingly to the read address decoder. In the case when a voltage is applied to the read word line, the data that is held at that time is read from a read data line. The memory cell blocks are connected to each other such that the four or more outputs from one memory cell block are inputted to other four or more memory cell blocks through the sense amplifier. | 2010-07-29 |
20100188924 | DATA TRANSFER SYSTEM - The invention is directed to decreasing a circuit size of a system in which a plurality of devices or circuit blocks share and use one memory. A system is configured so that a memory block serves as a master and each of circuit blocks serves as a slave, and thus the slave side (the circuit blocks) receives necessary data from the memory block by only having decoders corresponding to addresses assigned thereto in advance and registers. In this case, since the registers have been also needed in a conventional system in order to hold data read out from a memory, the circuit size decreases in the whole system. Since this effect is enhanced in proportion to the number of the circuit blocks sharing the memory block, the effect is enhanced as the system size increases. | 2010-07-29 |
20100188925 | Mixer Truck - The present invention relates to a mixer truck with a water system and a water pump for generating the required water pressure in the water system and with further energy consumers, wherein the water pump and/or at least one further load is driven by an electric motor. | 2010-07-29 |
20100188926 | Centrifugal Mixing System - A mixing system may include a closed mixer having an inlet, a discharge, and an inlet/discharge. The mixing system may also include a recirculation line in fluid communication with the inlet and the inlet/discharge. | 2010-07-29 |
20100188927 | FLUID BLENDING APPARATUS AND ASSOCIATED METHOD - An apparatus and method for blending a predetermined fluid with a main fluid wherein a source of a predetermined fluid is mixed with a main fluid. The predetermined fluid flows through an inlet of a positive displacement pump assembly and transferred to a mixing chamber through an outlet of the positive displacement pump assembly. A turbine blade assembly located within the mixing chamber is used to mix a main fluid flowing into the mixing chamber with the predetermined fluid for eventual dispensing through an outlet in the mixing chamber when desired. | 2010-07-29 |
20100188928 | Covering Structure Of A Mixer - A covering structure of a mixer includes: a fixed ring connected to the head of a mixer; an upper ring; and a lower ring. The fixed ring is further surrounded by a protruding ring. The upper ring has a striding part on its inner wall to stride on the protruding ring. The upper ring further has at least two stopping parts at an interval. A concave part is formed between each pair of consecutive stopping parts. One end of the lower ring is formed with connecting parts whose number is the same as that of the stopping parts. Its other end is connected downward with a covering element. The connecting parts of the lower ring are inserted via the concave parts on the upper ring and above them. By rotating the lower ring, the connecting parts urge against the stopping parts to form a rotating ring that can rotate along the protruding ring. | 2010-07-29 |
20100188929 | Electronic apparatus operable by external sound - An apparatus includes sound sensors for converting sounds into electric signals. An angular position of a sound source of a first sound wave as seen from the apparatus is determined on the basis of moments of arrival of the first sound wave at the respective sound sensors which are represented by the electric signals. An angular position of a sound source of a second sound wave as seen from the apparatus is determined on the basis of moments of arrival of the second sound wave at the respective sound sensors which are represented by the electric signals. Calculation is given of a relative angle between the determined angular position of the sound source of the first sound wave and the determined angular position of the sound source of the second sound wave. A condition of the apparatus is controlled in response to the calculated relative angle. | 2010-07-29 |
20100188930 | BOTTOM REFERENCED VIBRATORY SOURCES FOR SHALLOW WATER ACQUISITION - The described invention relates to seismic acquisition means for use in shallow water marine environments, comprising: (a) a vessel ( | 2010-07-29 |
20100188931 | DESIGN AND METHOD FOR IMPROVING THE PERFORMANCE OF SUBMARINE AND OTHER WATER CRAFT SONAR SENSORS, ARRAYS AND/OR HYDROPHONES - Disclosed herein are exemplary embodiments of devices to attach to submarines or other water craft to enable a sonar array to function better at higher water speeds. When operated, the devices slow down or fully offset the mounted array's (hydrophones' or arrays') relative water speed and reduce the water friction noise on the array, allowing it to function more optimally. In an exemplary embodiment, a device includes a telescoping boom that can be alternately retracted and extended to provide cycles (or rotates to provide similar cycles for any one array) of higher performance reception and “hearing” by the array, as its relative water speed is reduced or offset. The device can be mounted on the external surface of the hull to “retrofit” existing craft or built so that in the telescoping embodiment, the housing can be fully retracted and hidden from view and otherwise protected more fully when not in use. | 2010-07-29 |
20100188932 | Low Power Sensor System - A sensor for a vehicle that conserves power by alternately switching between a power on and a reduced power state. The circuit compares a most recent sensor measurement with an earlier measurement while in the power-on state and then switches to a reduced power state. A time delay generation function determines when the circuit switches out of the reduced power state depending on the result of the comparison. The duration of the reduced power state can be increased depending on the similarity of the most recent measurement to an earlier measurement. | 2010-07-29 |
20100188933 | Thermoacoustic device - A thermoacoustic device includes at least one first electrode, at least one second electrode, a sound wave generator and two protection components. The sound wave generator is electrically connected to the at least one first electrode and the at least one second electrode. The sound wave generator includes a carbon nanotube structure. The two protection components are located on opposite sides of the sound wave generator. | 2010-07-29 |
20100188934 | Speaker - A speaker includes a thermoacoustic module, an amplifier circuit board, and a frame. The thermoacoustic module includes a sound wave generator, at least one first electrode and at least one second electrode. The at least one first electrode and the at least one second electrode are electrically connected to the sound wave generator. The sound wave generator includes a carbon nanotube structure. The amplifier circuit board is electrically connected to the carbon nanotube structure by the at least one first electrode and at least one second electrode. The frame secures the thermoacoustic module and the amplifier circuit board. | 2010-07-29 |
20100188935 | Thermoacoustic device - A thermoacoustic device includes a sound wave generator, a number of first electrodes and a number of second electrodes. The sound wave generator includes a carbon nanotube structure. The second electrodes and the first electrodes are separately connected to the sound wave generator. The second electrodes and the first electrodes are parallel to each other and are alternately arranged at uniform intervals. A working voltage applied to the first and second electrodes is less than or equal to about 50 volts. The sound wave generator and the first and second electrodes satisfy a formula of | 2010-07-29 |
20100188936 | STORAGE MEDIUM FOR STORING PROGRAM INVOLVED WITH CONTENT DISTRIBUTION AND INFORMATION PROCESSING DEVICE - A CPU of a game device has a weekly calendar screen displayed. In this calendar screen, dates in one week are displayed separately. In the calendar screen, a content display field is provided, in which a thumbnail image or the like of a content brought in correspondence with each day is displayed. A time and day of start of availability and a time and day of end of availability are determined for each content such as a motion picture, and downloading of the content by a user is permitted during a period from the time and day of start of availability to the time and day of end of availability. | 2010-07-29 |
20100188937 | Watch with calendar mechanism having two date indicators - The present invention aims to provide a watch with a calendar mechanism which has a first date indicator and a second date indicator and which is of a satisfactory operability. The watch with a calendar mechanism of the present invention is equipped with a second date indicator feeding lever adapted to move based on the rotation of the first date indicator and to rotate the second date indicator. The first date indicator includes first date indicator tooth portions, and calendar shift teeth. The calendar shift teeth consist of a first calendar shift tooth, a second calendar shift tooth formed at an interval of (360*2/31) degrees in a first direction using the first calendar shift tooth as a reference, a third calendar shift tooth formed at an interval of (360*9/31) degrees in the first direction using the second calendar shift tooth as a reference, and a fourth calendar shift tooth formed at an interval of (360*10/31) degrees in a direction opposite to the first direction using the first calendar shift tooth as a reference. | 2010-07-29 |