31st week of 2009 patent applcation highlights part 13 |
Patent application number | Title | Published |
20090189217 | Semiconductor Memory Devices Including a Vertical Channel Transistor - Semiconductor memory devices include a semiconductor substrate and a plurality of semiconductor material pillars in a spaced relationship on the semiconductor substrate. Respective surrounding gate electrodes surround ones of the pillars. A first source/drain region is in the semiconductor substrate between adjacent ones of the pillars and a second source/drain region is in an upper portion of at least one of the adjacent pillars. A buried bit line is in the first source/drain region and electrically coupled to the first source/drain region and a storage node electrode is on the upper portion of the at least one of the adjacent pillars and electrically contacting with the second source/drain region. | 2009-07-30 |
20090189218 | Structure and Method for Forming Power Devices with High Aspect Ratio Contact Openings - A field effect transistor (FET) includes body regions of a first conductivity type over a semiconductor region of a second conductivity type. Source regions of the second conductivity type extend over the body regions. Gate electrodes extend adjacent to but are insulated from the body regions by a gate dielectric layer. Contact openings extend into the body regions between adjacent gate electrodes. A seed layer extends along the bottom of each contact opening. The seed layer serves as a nucleation site for promoting growth of conductive fill material. A conductive fill material fills a lower portion of each contact opening. An interconnect layer fills an upper portion of each contact opening and is in direct contact with the conductive fill material. The interconnect layer is also in direct contact with corresponding source regions along upper sidewalls of the contact openings. | 2009-07-30 |
20090189219 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - The present invention provides a technique capable of attaining an improvement in current detection accuracy in a trench gate type power MISFET equipped with a current detection circuit. Inactive cells are disposed so as to surround the periphery of a sense cell. That is, the inactive cell is provided between the sense cell and an active cell. All of the sense cell, active cell and inactive cells are respectively formed of a trench gate type power MISFET equipped with a dummy gate electrode. At this time, the depth of each trench extends through a channel forming region and is formed up to the deep inside (the neighborhood of a boundary with a semiconductor substrate) of an n-type epitaxial layer. Further, a p-type semiconductor region is provided at a lower portion of each trench. The p-type semiconductor region is formed so as to contact the semiconductor substrate. | 2009-07-30 |
20090189220 | POWER MOS TRANSISTOR DEVICE AND LAYOUT - A power metal-oxide semiconductor (MOS) transistor device is provided. The power MOS transistor device includes a drain region disposed in a substrate, a gate structure layer disposed over the substrate, and enclosing a periphery of the drain region, and a source region formed in the substrate and distributed at an outer periphery of the gate structure layer. In addition, the MOS transistor device can, for example, form a transistor array. | 2009-07-30 |
20090189221 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - Provided are a semiconductor device and a method for manufacturing the semiconductor device. The semiconductor device includes: a gate electrode formed of polysilicon on a substrate with a gate insulating layer interposed between the gate electrode and the substrate; a source region and a drain region formed on the substrate on either side of the gate electrode; a PMD (poly-metal dielectric) liner nitride layer having a non-stoichiometric structure formed on the gate electrode, the source region, and the drain region; and an interlayer insulating layer formed on the PMD liner nitride layer. | 2009-07-30 |
20090189222 | SEMICONDUCTOR MEMORY DEVICE - A memory includes a U-shape layer on a substrate; a first diffusion layer provided at an upper part of the U-shaped layer; a second diffusion layer provided at a lower part of the U-shaped layer; a body formed at an intermediate portion of the U-shaped layer between the first and the second diffusion layers; a first gate dielectric film provided on an outer side surface of the U-shaped layer; a first gate electrode provided on the first gate dielectric film; a second gate dielectric film provided on an inner side surface of the U-shaped layer; a second gate electrode provided on the second gate dielectric film; a bit line contact connecting the bit line to the first diffusion layer; a source line contact connecting the source line to the second diffusion layer, wherein cells adjacent in the first direction alternately share the bit line contact and the source line contact. | 2009-07-30 |
20090189223 | Complementary Metal Gate Dense Interconnect and Method of Manufacturing - Complementary metal gate dense interconnects and methods of manufacturing the interconnects is provided. The method comprises forming a first metal gate on a wafer and second metal gate on the wafer. A conductive interconnect material is deposited in a space formed between the first metal gate and the second metal gate to provide an electrical connection between the first metal gate and the second metal gate. | 2009-07-30 |
20090189224 | SEMICONDUCTOR DEVICE AND FABRICATION PROCESS THEREOF - A semiconductor device includes: an insulated gate field effect transistor of a first conductivity type as a first transistor, the first transistor having a gate insulating film and a gate electrode; and an insulated gate field effect transistor of a second conductivity type opposite to the first conductivity type as a second transistor, the second transistor having a gate insulating film and a gate electrode. | 2009-07-30 |
20090189225 | SEMICONDUCTOR DEVICE AND ITS FABRICATION METHOD - A semiconductor device includes a first MIS transistor, and a second MIS transistor having a threshold voltage higher than that of the first MIS transistor. The first MIS transistor includes a first gate insulating film made of a high-k insulating film formed on a first channel region, and a first gate electrode having a first conductive portion provided on and contacting the first gate insulating film and a second conductive portion. The second MIS transistor includes a second gate insulating film made of the high-k insulating film formed on a second channel region, and a second gate electrode having a third conductive portion provided on and contacting the second gate insulating film and a fourth conductive portion. The third conductive portion has a film thickness smaller than that of the first conductive portion, and is made of the same composition material as that of the first conductive portion. | 2009-07-30 |
20090189226 | ELECTRICAL FUSE CIRCUIT - An electrical fuse circuit includes, in addition to an independent power supply switch circuit, a plurality of fuse bit cells, each including a fuse element one end of which is connected to an output of the power supply switch circuit, and a first MOS transistor connected to the other end of the fuse element, wherein a diode is connected between the ground potential and the power supply switch circuit as an ESD countermeasure. The gate oxide film thickness of transistors of the fuse bit cells is equal to that of a low-voltage logic-type transistor, not that of a high-voltage I/O-type transistor. | 2009-07-30 |
20090189227 | STRUCTURES OF SRAM BIT CELLS - A SRAM bit cell and an associated method of producing the SRAM bit cell with improved performance and stability is provided. In one configuration, channel mobility of the transistors within the SRAM bit cell may be adjusted to provide improved stability. In order to adjust the channel mobility, a stress memorization technique may be used, a wide spacer may be used, germanium may be implanted on tensile stress silicon nitride, a compressive liner may be used or silicon germanium may be embedded in one or more of the devices in the cell. In another configuration, the gate capacitance of each device within the SRAM bit cell may be adjusted to achieve high SRAM yield. For instance, a thick gate oxide may be used, phosphorous pre-doping may be used or fluorine pre-doping may be used in one or more of the devices within the cell. | 2009-07-30 |
20090189228 | SEMICONDUCTOR TRANSISTOR WITH P TYPE RE-GROWN CHANNEL LAYER - The invention is a device for controlling conduction across a semiconductor body with a P type channel layer between active semiconductor regions of the device and the controlling gate contact. The device, often a MOSFET or an IGBT, includes at least one source, well, and drift region. The P type channel layer may be divided into sections, or divided regions, that have been doped to exhibit N type conductivity. By dividing the channel layer into regions of different conductivity, the channel layer allows better control over the threshold voltage that regulates current through the device. Accordingly, one of the divided regions in the channel layer is a threshold voltage regulating region. The threshold-voltage regulating region maintains its original P type conductivity and is available in the transistor for a gate voltage to invert a conductive zone therein. The conductive zone becomes the voltage regulated conductive channel within the device. | 2009-07-30 |
20090189229 | Semiconductor devices and methods of fabricating the same - Provided are semiconductor devices and methods of fabricating the same, and more specifically, semiconductor devices having a W—Ni alloy thin layer that has a low resistance, and methods of fabricating the same. The semiconductor devices include the W—Ni alloy thin layer. The weight of Ni in the W—Ni alloy thin layer may be in a range from approximately 0.01 to approximately 5.0 wt % of the total weight of the W—Ni alloy thin layer. | 2009-07-30 |
20090189230 | METHOD AND SYSTEM FOR PACKAGING MEMS DEVICES WITH INCORPORATED GETTER - Methods and systems for packaging MEMS devices such as interferometric modulator arrays are disclosed. One embodiment of a MEMS device package structure includes a seal with a chemically reactant getter. Another embodiment of a MEMS device package comprises a primary seal with a getter, and a secondary seal proximate an outer periphery of the primary seal. Yet another embodiment of a MEMS device package comprises a getter positioned inside the MEMS device package and proximate an inner periphery of the package seal. | 2009-07-30 |
20090189231 | Electromagnectic wave detecting element - The present invention is to provide an electromagnetic wave detecting element that can prevent a decrease in light utilization efficiency at sensor portions. The sensor portions are provided so as to correspond to respective intersection portions of scan lines and signal lines, and have semiconductor layer that generate charges due to electromagnetic waves being irradiated, and at whose electromagnetic wave irradiation surface sides upper electrodes are formed, and at whose electromagnetic wave non-irradiation surface sides lower electrodes are formed. Bias voltage is supplied to the respective upper electrodes via respective contact holes by a common electrode line that is formed further toward an electromagnetic wave downstream side than the semiconductor layer. | 2009-07-30 |
20090189232 | Methods and apparatuses providing color filter patterns arranged to reduce the effect of crosstalk in image signals - Methods and apparatuses providing color filter patterns arranged to reduce cross talk in image signals. The apparatuses include an array of pixels, each pixel having an associated color filter, arranged such that cross-talk is distributed among pixel signals of each color of the color filters. | 2009-07-30 |
20090189233 | CMOS IMAGE SENSOR AND METHOD FOR MANUFACTURING SAME - An optical image sensor is fabricated by forming a pixel array and a peripheral region surrounding the pixel array on a semiconductor substrate, the peripheral region containing peripheral circuitry. An inter-level-dielectric layer is formed over the substrate and a plurality of interconnect wiring layers are formed over the inter-level-dielectric layer. Each interconnect wiring layer includes interconnecting metal features and a layer of inter-level-dielectric material covering the interconnecting metal features. The plurality of interconnect wiring layers are provided in a manner that there are N levels of wiring layers in the peripheral region and 1 to (N−1) levels of wiring layers over the pixel array. An etch-stop layer is formed over the top-most level interconnecting metal features in the peripheral region. | 2009-07-30 |
20090189234 | SOLID-STATE IMAGING DEVICE, PRODUCTION METHOD OF THE SAME, AND IMAGING APPARATUS - In a solid-state imaging device, the pixel circuit formed on the first surface side of the semiconductor substrate is shared by a plurality of light reception regions. The second surface side of the semiconductor substrate is made the light incident side of the light reception regions. The second surface side regions of the light reception regions formed in the second surface side part of the semiconductor substrate are arranged at approximately even intervals and the first surface side regions of the light reception regions formed in the first surface side part of the semiconductor substrate are arranged at uneven intervals, respectively, and the second surface side regions and the first surface side regions are joined respectively in the semiconductor substrate so that the light reception regions extend from the second surface side to the first surface side of the semiconductor substrate. | 2009-07-30 |
20090189235 | SOLID-STATE IMAGING DEVICE, MANUFACTURING METHOD FOR THE SAME, AND IMAGING APPARATUS - A solid-state imaging device having a light-receiving section that photoelectrically converts incident light includes an insulating film formed on a light-receiving surface of the light-receiving section and a film and having negative fixed charges formed on the insulating film. A hole accumulation layer is formed on a light-receiving surface side of the light-receiving section. A peripheral circuit section in which peripheral circuits are formed is provided on a side of the light-receiving section. The insulating film is formed between a surface of the peripheral circuit section and the film having negative fixed charges such that a distance from the surface of the peripheral circuit section to the film having negative fixed charges is larger than a distance from a surface of the light-receiving section to the film having negative fixed charges. | 2009-07-30 |
20090189236 | SOLID-STATE IMAGING DEVICE AND METHOD FOR MANUFACTURING THE SAME - A solid-state imaging device includes: a light-receiving pixel part configured to be formed on a semiconductor substrate; a black-level reference pixel part configured to be formed on the semiconductor substrate; and a multilayer interconnect part configured to be provided over the semiconductor substrate. The multilayer interconnect part includes an insulating layer formed over the semiconductor substrate and metal interconnect layers formed as a plurality of layers in the insulating layer. The multilayer interconnect part has a first light-blocking film formed above an area between first metal interconnects of a first metal interconnect layer as one of the metal interconnect layers above the black-level reference pixel part, and a second light-blocking film that is connected to the first light-blocking film and is formed of a second metal interconnect layer over the first metal interconnect layer. | 2009-07-30 |
20090189237 | SOLID-STATE IMAGING ELEMENT - The present invention provides a solid-state imaging element including: a silicon layer having a photodiode formed therein and a positive charge accumulation region formed on the surface thereof; and an optical waveguide formed above the photodiode to guide incident light into the photodiode, wherein an insulating layer is formed in the optical waveguide, and the insulating layer has a dielectric constant of 5 or greater and negative fixed charge. | 2009-07-30 |
20090189238 | PACKAGED MICROELECTRONIC IMAGERS AND METHODS OF PACKAGING MICROELECTRONIC IMAGERS - Microelectronic imagers, methods for packaging microelectronic imagers, and methods for forming electrically conductive through-wafer interconnects in microelectronic imagers are disclosed herein. In one embodiment, a microelectronic imaging die can include a microelectronic substrate, an integrated circuit, and an image sensor electrically coupled to the integrated circuit. A bond-pad is carried by the substrate and electrically coupled to the integrated circuit. An electrically conductive through-wafer interconnect extends partially through the substrate and is in contact with the bond-pad. The interconnect can include a passage extending partially through the substrate to the bond-pad, a dielectric liner deposited into the passage and in contact with the substrate, a conductive layer deposited onto at least a portion of the dielectric liner, a wetting agent deposited onto at least a portion of the conductive layer, and a conductive fill material deposited into the passage and electrically coupled to the bond-pad. | 2009-07-30 |
20090189239 | Thermoelectric Module - A thermoelectric module has a first substrate, a second substrate spaced from the first substrate, a plurality of P type thermoelectric elements and N type thermoelectric elements arranged in the space between the first and second substrates, and a plurality of electrodes which connect the P type and N type thermoelectric elements in series. Each electrode is connected to a respective one of the plurality of P type thermoelectric elements at a first connection and a respective one of the plurality of N type thermoelectric elements in the space, and a sealant is located at an edge portion of the space. Each one of a series of first or outer electrodes closest to the edge portion of the space has a concave portion that is concaved in a direction departing from the edge portion of the space and is at a position between the first connection and the second connection. | 2009-07-30 |
20090189240 | SEMICONDUCTOR DEVICE WITH AT LEAST ONE FIELD PLATE - A semiconductor component with at least one field plate. One embodiment provides the field plate to make contact with the semiconductor body at a connection contact. The semiconductor body has in the region of the connection contact a doping concentration that is less than 5·10 | 2009-07-30 |
20090189241 | Using floating fill metal to reduce power use for proximity communication - One embodiment of the present invention provides a system that facilitates reducing the power needed for proximity communication. This system includes an integrated circuit with an array of transmission pads that transmit a signal using proximity communication. A layer of fill metal is located in proximity to this array of transmission pads, wherein the layer of fill metal is “floating” (e.g., not connected to any signal). Leaving this layer of fill metal floating reduces the parasitic capacitance for the array of transmission pads, which can reduce the amount of power needed to transmit the signal. | 2009-07-30 |
20090189242 | METHOD FOR NON-SELECTIVE SHALLOW TRENCH ISOLATION REACTIVE ION ETCH FOR PATTERNING HYBRID-ORIENTED DEVICES COMPATIBLE WITH HIGH-PERFORMANCE HIGHLY-INTEGRATED LOGIC DEVICES - Disclosed are embodiments of a hybrid-orientation technology (HOT) wafer and a method of forming the HOT wafer with improved shallow trench isolation (STI) structures for patterning devices in both silicon-on-insulator (SOI) regions, having a first crystallographic orientation, and bulk regions, having a second crystallographic orientation. The improved STI structures are formed using a non-selective etch process to ensure that all of the STI structures and, particularly, the STI structures at the SOI-bulk interfaces, each extend to the semiconductor substrate and have an essentially homogeneous (i.e., single material) and planar (i.e., divot-free) bottom surface that is approximately parallel to the top surface of the substrate. Optionally, an additional selective etch process can be used to extend the STI structures a predetermined depth into the substrate. | 2009-07-30 |
20090189243 | SEMICONDUCTOR DEVICE WITH TRENCH ISOLATION STRUCTURE AND METHOD FOR FABRICATING THE SAME - The present invention relates to a semiconductor device with a device isolation structure and a method for fabricating the same. The semiconductor device includes: a substrate provided with a trench formed in the substrate; and at least one device isolation structure including an oxide layer formed on the trench, a nitride layer formed on the oxide layer disposed on sidewalls of the trench and a high density plasma oxide layer formed on the nitride layer to fill the trench. | 2009-07-30 |
20090189244 | INTEGRATED CIRCUIT DEVICES AND METHODS AND APPARATUSES FOR DESIGNING INTEGRATED CIRCUIT DEVICES - Methods and apparatuses to design an Integrated Circuit (IC) with a shielding of wires. In at least one embodiment, a shielding mesh of at least two reference voltages (e.g., power and ground) is used to reduce both the capacitive coupling and the inductive coupling in routed signal wires in IC chips. In some embodiments, a type of shielding mesh (e.g., a shielding mesh with a window surrounded by a power ring, or a window with a parser set of shielding wires) is selected to make more routing area available in locally congested areas. In other embodiments, the shielding mesh is used to create or add bypass capacitance. Other embodiments are also disclosed. | 2009-07-30 |
20090189245 | SEMICONDUCTOR DEVICE WITH SEAL RING - A semiconductor device according to the invention is a semiconductor device which includes a low dielectric constant film of which the relative dielectric constant is less than 3.5, is provided with one or more seal rings that are moisture blocking walls in closed loop form in a plan view, and where at least one of the seal rings includes a seal ring protrusion portion in inward protruding form in the vicinity of a chip corner. | 2009-07-30 |
20090189246 | METHOD OF FORMING TRENCH ISOLATION STRUCTURES AND SEMICONDUCTOR DEVICE PRODUCED THEREBY - A method for forming a trench isolation structure and a semiconductor device are provided. The method comprises the following steps: forming a patterned mask on a semiconductor substrate; defining a trench with a predetermined depth D by using the patterned mask, wherein the trench has a bottom and a side wall; forming a liner layer covering the bottom and the side wall of the trench; substantially filling the trench with a flowable oxide from the bottom to a thickness d1 to form an oxide layer; forming a barrier layer with a thickness d′ to cover and completely seal the surface of the oxide layer, wherein d′2009-07-30 | |
20090189247 | SEMICONDUCTOR DEVICE - An active barrier structure has a p-type region and an n-type region, each of which is in contact with a p-type impurity region and which are ohmic-connected to each other to attain a floating potential. A trench isolation structure is formed between an active barrier region and the other region (an output transistor formation region and a control circuit formation region). The trench isolation structure has a trench extending from the main surface of the semiconductor substrate through the n | 2009-07-30 |
20090189248 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device comprises an active region formed in a semiconductor substrate and a gate electrode formed on the active region via a gate insulating film formed on a surface of the active region. A peripheral portion of the gate electrode and a peripheral portion of the active region overlap each other at a position where the active region is not divided by the gate electrode when viewed in plan view, thus forming an overlap region. | 2009-07-30 |
20090189249 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes a first and second structures formed in a first insulating layer, a lower metal interconnection formed in the second structure, a metal-insulator-metal (MIM) capacitor formed in the first structure, and first, second and third electrodes formed in the first structure and electrically connected to the MIM capacitor. The first electrode is a chip bottom metal (CBM) layer, the second electrode is a first chip top metal (CTM) layer and the third electrode is a second chip top metal (CTM) layer. | 2009-07-30 |
20090189250 | Semiconductor Device and a Method of Manufacturing the Same - A capacitor has an MIM (Metal Insulator Metal) structure comprising a lower electrode formed in the interior of an electrode trench which is formed in an interlayer insulating film, a dielectric film formed over the lower electrode, and an upper electrode formed over the dielectric film. The upper electrode and the dielectric film are each formed with an area larger than the area of the lower electrode so that the whole of the lower electrode is positioned inside the upper electrode and the dielectric film. The reliability and production yield of the capacitor are improved. | 2009-07-30 |
20090189251 | CAPACITOR FORMATION FOR A PUMPING CIRCUIT - A capacitor structure for a pumping circuit includes a substrate, a U-shaped bottom electrode in the substrate, a T-shaped top electrode in the substrate and a dielectric layer disposed between the U-shaped bottom and T-shaped top electrode. The contact area of the capacitor structure between the U-shaped bottom and T-shaped top electrode is extended by means of the cubic engagement of the U-shaped bottom electrode and the T-shaped top electrode. | 2009-07-30 |
20090189252 | III-V MOSFET Fabrication and Device - A semiconductor fabrication process includes forming a gate dielectric layer ( | 2009-07-30 |
20090189253 | METHOD OF PRODUCING A NITRIDE SEMICONDUCTOR DEVICE AND NITRIDE SEMICONDUCTOR DEVICE | 2009-07-30 |
20090189254 | CIRCUIT CONNECTION STRUCTURE, METHOD FOR PRODUCING THE SAME AND SEMICONDUCTOR SUBSTRATE FOR CIRCUIT CONNECTION STRUCTURE - A circuit connection structure that exhibits excellent adhesiveness between a heat resistant resin film and a circuit adhesive member, even under high temperature and high humidity, is provided by introducing a chemically stable functional group into the heat resistant resin film by additional surface treatment to improve adhesiveness. In a circuit connection structure, a semiconductor substrate and a circuit member are adhered by a circuit adhesive member sandwiched therewith. First circuit electrode on the semiconductor substrate and second circuit electrode on the circuit member are connected electrically by conductive particles in the circuit adhesive member. A surface modification is given to the semiconductor substrate by plasma treatment using gas containing nitrogen, ammonia and the like. Therefore, the heat resistant resin film on the semiconductor substrate and the circuit adhesive member are firmly adhered for a long period of time even under high temperature and high humidity. | 2009-07-30 |
20090189255 | WAFER HAVING HEAT DISSIPATION STRUCTURE AND METHOD OF FABRICATING THE SAME - A wafer having a heat dissipation structure is provided. The wafer having the heat dissipation structure includes a wafer and a number of metallic heat dissipation parts. The wafer has a first surface and a second surface opposite thereto. Besides, a number of blind holes are formed on the second surface of the wafer. The metallic heat dissipation parts are partially embedded in the blind holes respectively and protrude from the second surface of the wafer. | 2009-07-30 |
20090189256 | MANUFACTURING PROCESS OF SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - After forming a ring-shaped trench penetrating through a semiconductor substrate from a rear surface side thereof and forming an insulating film inside the trench and on the rear surface of the semiconductor substrate, a through hole is formed in the insulating film and semiconductor substrate on an inner side of the ring-shaped trench from the rear surface side, thereby exposing a surface protection insulating film formed on a front surface of the semiconductor substrate at a bottom of the through hole. After removing the surface protection insulating film at the bottom of the through hole to form an opening to expose an element surface electrode, a contact electrode connected to the element surface electrode is formed on inner walls of the through hole and opening, and a pad electrode made of the same layer as the contact electrode is formed on the rear surface of the semiconductor substrate. | 2009-07-30 |
20090189257 | MESA TYPE SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A mesa type semiconductor device and its manufacturing method are offered to increase a withstand voltage as well as reducing a leakage current. An N | 2009-07-30 |
20090189258 | METHOD OF INTEGRATED CIRCUIT FABRICATION - A method for fabricating an integrated circuit including forming a first trench in a rear side of a semiconductor wafer, wherein the first trench has a depth extending partially through a thickness of the semiconductor wafer, coating the rear side with a layer of coating material, including filling the first trench with the coating material, and forming a second trench in a front side of the semiconductor wafer, wherein the second trench is aligned with and has a width less than a width of the first trench, and wherein the second trench has a depth extending at least through a remaining portion of the semiconductor wafer so as to be in communication with the coating material filling the first trench. | 2009-07-30 |
20090189259 | ELECTRONIC DEVICE AND METHOD OF MANUFACTURING - An electronic device and method of manufacturing. One embodiment includes attaching a first semiconductor chip to a first metallic clip. The first semiconductor chip is placed over a leadframe after the attachment of the first semiconductor chip to the first metallic clip. | 2009-07-30 |
20090189260 | SEMICONDUCTOR DEVICE - In a non-leaded type semiconductor device, a tab, tab suspension leads, and other leads are exposed to one surface of a seal member. A semiconductor element is positioned within the seal member and fixed to a surface of the tab with an adhesive. The tab is formed larger than the semiconductor element so that outer peripheral edges of the tab are positioned outside outer peripheral edges of the semiconductor element. A groove is formed in the tab surface portion positioned between the area to which the semiconductor element is fixed and wire connection areas to which the wires are connected, the groove being formed so as to surround the semiconductor element fixing area, thereby preventing peeling-off between the tab to which the semiconductor element is fixed and the resin which constitutes the package. | 2009-07-30 |
20090189261 | Ultra-Thin Semiconductor Package - Semiconductor packages with a reduced-height die pad and associated methods for making and using these semiconductor packages are described. The semiconductor packages include a lead frame with die pad of reduced height so the die pad has a height that is less than that of the lead frame. The semiconductor packages may comprise an isolated and/or a fused lead finger with a portion of an upper surface of the isolated lead finger that is removed to form a concavity to which one or more bond wires may be bonded. The upper surface of the isolated lead finger may be removed so the isolated lead finger has a height that is less than the height of the lead frame. And a perimeter of a bottom surface of the fused lead finger may be removed. Other embodiments are described. | 2009-07-30 |
20090189262 | MULTIPHASE SYNCHRONOUS BUCK CONVERTER - Disclosed in this specification is a multiphase buck converter package and process for forming such package. The package includes at least four dies and at least nine parallel leads. The dies are electrically connected through a plurality of die attach pads, thus eliminating the need for wirebonding. | 2009-07-30 |
20090189263 | Wiring device for semiconductor device, composite wiring device for semiconductor device, and resin-sealed semiconductor device - A wiring device for a semiconductor device, a composite wiring device for a semiconductor device and a resin-sealed semiconductor device are provided, each of which is capable of mounting thereon a semiconductor chip smaller than conventional chips and being manufactured at lower cost. The wiring device electrically connects an electrode provided on a semiconductor chip with an external wiring device, and has an insulating layer, a metal substrate and a copper wiring layer. The metal substrate is provided on one side of the insulating layer. The copper wiring layer is provided on another side of the insulating layer. The wiring device has a semiconductor chip support portion provided on the side of the copper wiring layer with respect to the insulating layer. The copper wiring layer includes a first terminal, a second terminal and a wiring portion. The first terminal is connected with the electrode provided on the semiconductor chip. The second terminal is connected with the external wiring device. The wiring portion connects the first terminal with the second terminal. | 2009-07-30 |
20090189264 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - The present invention enables improvement of bonding reliability of the conductive adhesive interposed between a semiconductor chip and a die pad portion. Provided is a semiconductor device, in which a silicon chip is mounted over the die pad portion integrally formed with a drain lead, has a source pad over the main surface and a drain electrode of a power MOSFET over the back side, and is bonded onto the die pad portion via an Ag paste. In the device, a source lead and the source pad are electrically coupled via an Al ribbon. Over the back surface of the silicon chip, an Ag nanoparticle coated film is formed, while another Ag nanoparticle coated film is formed over the die pad portion and lead (drain lead and source lead). | 2009-07-30 |
20090189265 | METHOD AND APPARATUS FOR MAKING SEMICONDUCTOR DEVICES INCLUDING A FOIL - A method for manufacturing a semiconductor device including covering a portion of at least one semiconductor device with a foil, including covering at least one target region of the semiconductor device, and illuminating the foil with a laser to singulate from the foil a portion covering the at least one target region of the at least one semiconductor device. | 2009-07-30 |
20090189266 | SEMICONDUCTOR PACKAGE WITH STACKED DICE FOR A BUCK CONVERTER - Disclosed in this specification is a buck converter package with stacked dice and a process for forming a buck converter. The package includes a die attach pad with a low side die mounted on one surface and a high side die mounted on the opposing surface. The die attach pad is conductive, such that the drain of the low side die is connected to the source of the high side die through the pad. A controller die controls the gates of the high and low side dies. A plurality of leads extends outside of the package to permit electrical connections to the inside of the package. The high side drain is exposed to one of the surfaces of the package. | 2009-07-30 |
20090189267 | SEMICONDUCTOR CHIP WITH CHIP SELECTION STRUCTURE AND STACKED SEMICONDUCTOR PACKAGE HAVING THE SAME - A semiconductor chip with a chip selection structure suitable for a stacked semiconductor chip includes a semiconductor chip body and a chip selection structure. The chip selection structure includes a chip selection pad disposed over the semiconductor chip body, a main through electrode electrically connected to the chip selection pad, and a sub through electrode interposed between the main through electrode and the chip selection pad. A plurality of the semiconductor chips, each having the same chip selection structure, can be stacked by offsetting the stacked semiconductor chips. | 2009-07-30 |
20090189268 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - Of three chips ( | 2009-07-30 |
20090189269 | Electronic Circuit Package - A electronic circuit package having a flexible substrate with metals layers on one or more of its surfaces forming a wiring pattern and/or surface mount bonding pads. Passive electronic components are integrated onto component packages that are mounted to the flexible substrate and electrically connected with the wiring pattern or bonding pad. An active electronic device is mounted on the flexible substrate or bonding pad. | 2009-07-30 |
20090189270 | MANUFACTURING PROCESS AND STRUCTURE FOR EMBEDDED SEMICONDUCTOR DEVICE - A manufacturing process for an embedded semiconductor device is provided. In the manufacturing process, at least one insulation layer and a substrate are stacked to each other, and a third metal layer is laminated on the insulation layer to embed a semiconductor device in the insulation layer. The substrate has a base, a first circuit layer, a second circuit layer, and at least a first conductive structure passing through the base and electrically connected to the first circuit layer and the second circuit layer. In addition, the third metal layer is patterned to form a third circuit layer having a plurality of third pads. | 2009-07-30 |
20090189271 | PRINTED CIRCUIT BOARD, SEMICONDUCTOR PACKAGE, CARD APPARATUS, AND SYSTEM - A printed circuit board providing high reliability using a packaging of high capacity semiconductor chip, a semiconductor package, and a card and a system using the semiconductor package. The semiconductor package includes a substrate having a first surface and a second surface, a semiconductor chip mounted on the first surface of the substrate, at least one land disposed on the second surface of the substrate, and whose circumference includes a plurality of first group arcs, a mask layer covering the second surface of the substrate and including at least one opening that exposes the at least one land, and at least one external terminal disposed on the at least one land, wherein a portion of the at least one land is covered by the mask layer, and a sidewall of another portion of the at least one land is exposed by the at least one opening, and the circumference of the at least one opening includes a plurality of second group arcs, and a radius of the outermost arc from among the plurality of first group arcs is equal to a radius of the outermost arc from among the plurality of second group arcs. | 2009-07-30 |
20090189272 | Wafer Level Chip Scale Packages Including Redistribution Substrates and Methods of Fabricating the Same - Provided are wafer level chip scale packages, each having a redistribution substrate in which a pad pitch is improved, and methods of fabricating the same. An exemplary wafer level chip scale package includes a semiconductor chip and a redistribution substrate. The semiconductor chip includes a plurality of pads arranged with a first pitch on a first surface thereof. The redistribution substrate includes a plurality of connection wires arranged with a second pitch, which is greater than the first pitch, on a first surface thereof. The redistribution substrate expands a pad pitch from the first pitch to the second pitch by electrically connecting the pads to the connection wires. | 2009-07-30 |
20090189273 | MULTIPHASE SYNCHRONOUS BUCK CONVERTER - Disclosed in this specification is a multiphase buck converter package and process for forming such package. The package includes at least four dice and several parallel leads. The dice are electrically connected through a plurality of die attach pads, thus eliminating the need for wirebonding. | 2009-07-30 |
20090189274 | TAPE WIRING SUBSTRATE AND TAPE PACKAGE USING THE SAME - A tape wiring substrate may have dispersion wiring patterns. The dispersion wiring patterns may be provided between input/output wiring pattern groups to compensate for the intervals therebetween. Connecting wiring patterns may be configured to connect the dispersion wiring patterns to a first end of the adjacent input/output wiring pattern. | 2009-07-30 |
20090189275 | INTEGRATED CIRCUIT PACKAGE SYSTEM WITH WAFER SCALE HEAT SLUG - An integrated circuit package system includes: providing a singulated, layered structure equivalent in size to an integrated circuit die and having an adhesive layer, an electrical insulator layer, and a heat slug; attaching the integrated circuit die to a base; attaching bond wires to a top of the base for electrical connection between the integrated circuit die and the base; attaching the singulated, layered structure to the integrated circuit die wherein the bond wires are surrounded by the adhesive layer; and encapsulating the integrated circuit die and a portion of the heat slug with a molding compound. | 2009-07-30 |
20090189276 | SEMICONDUCTOR CHIP AND SEMICONDUCTOR DEVICE - A semiconductor chip, including: a substrate including an front surface; an integrated circuit formed on the front surface and including a plurality of semiconductor elements; and a heat-radiating plug formed in a region of the substrate corresponding to at least one of the semiconductor elements. The heat-radiating plug is made of a material having a thermal conductivity greater than that of the substrate formed in a non-penetrating hole having its opening on a reverse surface of the substrate. | 2009-07-30 |
20090189277 | PHOTOSENSITIVE COMPOSITIONS BASED ON POLYCYCLIC POLYMERS FOR LOW STRESS, HIGH TEMPERATURE FILMS - Vinyl addition polymer compositions, methods for forming such compositions, methods for using such compositions to form microelectronic and optoelectronic devices are provided. The vinyl addition polymer encompassed by such compositions has a polymer backbone having two or more distinct types of repeat units derived from norbornene-type monomers independently selected from monomers of Formula I: | 2009-07-30 |
20090189278 | ULTRASONIC MEASURING METHOD, ELECTRONIC COMPONENT MANUFACTURING METHOD, AND SEMICONDUCTOR PACKAGE - The waveform signals of ultrasonic waves reflected by a plurality of interfaces in a measurement object are received, the waveform signal of a reflected wave on a reference interface inside the measurement object is detected based on the amplitudes of the received waveform signals, and evaluation is made on the bonded condition of an interface to be measured based on the waveform signal of the reflected wave on the reference interface. | 2009-07-30 |
20090189279 | METHODS AND SYSTEMS FOR PACKAGING INTEGRATED CIRCUITS - Methods of packaging integrated circuits are described. One method relates to attaching a singulated device wafer to a substrate. The singulated device wafer includes a multiplicity of integrated circuit dice arranged in a first configuration. The method also involves a substrate, which includes a sacrificial semiconductor wafer having device areas with metalized contacts. The device areas on the substrate may be arranged in a configuration matching that of the dice on the device wafer. The method also entails aligning the singulated device wafer as a whole with the substrate so that the dice of the device wafer are positioned substantially simultaneously over associated device areas on the substrate. The method also involves attaching the dice from the singulated wafer as a whole substantially simultaneously to the substrate such that each die of the device wafer is attached to an associated device area of the substrate. | 2009-07-30 |
20090189280 | Method of Forming a Non Volatile Memory Device - In one embodiment, a method of forming a semiconductor device is disclosed. A high-k dielectric is deposited of over a semiconductor body, and a portion of the high-k dielectric is wet etched an etchant selected from the group consisting of hot phos, piranha, and SC1. | 2009-07-30 |
20090189281 | SEMICONDUCTOR PACKAGE AND A METHOD FOR MANUFACTURING THE SAME - A semiconductor package and a method for manufacturing the same capable of supplying power easily without an increase in the number of pads for power supply. The semiconductor package includes a semiconductor chip having a plurality of pads including pads for power supply disposed in a center portion and an internal wiring disposed to be exposed to outside; an insulating film formed on the semiconductor to expose the pads for power supply and the internal wirings; and re-distribution lines formed on the insulating film to connect between the exposed portions of the pads for power supply and the internal wiring. | 2009-07-30 |
20090189282 | Semiconductor device - A semiconductor device according to the present invention includes: a low dielectric layer made of a low dielectric material; a high dielectric layer formed on the low dielectric layer and made of a high dielectric material having a higher dielectric constant than the low dielectric material; a protective layer formed on the high dielectric layer and made of an insulating material differing from the low dielectric material and the high dielectric material; a groove formed by digging in from an upper surface of the protective layer to the low dielectric layer; a barrier film coated onto a bottom surface and side surfaces of the groove and made of a material having a barrier property with respect to diffusion of Cu; and a wiring formed on the barrier film, made of a metal material having Cu as a main component, and completely filling the groove. | 2009-07-30 |
20090189283 | ALUMINUM METAL LINE OF A SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A method of forming an aluminum line of a semiconductor device where first A metal thin layer, a first aluminum layer, and a first B metal thin layer are sequentially applied on an interlayer insulating layer. A photolithography process is performed to form a metal line pattern, and etching is performed thereon. An intermetallic dielectric layer is applied on the metal line pattern. The first B metal thin layer is removed by a chemical mechanical planarization process to form a first stage metal line. A second aluminum layer and a second metal thin layer are sequentially applied. Photoresist is applied, a photolithography process is performed to form a metal line pattern, and etching is performed to form a second stage metal line. An intermetallic dielectric layer is applied on the second stage metal line. A chemical mechanical planarization process is performed on the second intermetallic dielectric layer. | 2009-07-30 |
20090189284 | SEMICONDUCTOR DEVICE HAVING A REDUCTANT LAYER AND MANUFACTURING METHOD THEREOF - A semiconductor device includes an inter-metal dielectric (IMD) formed on a substrate and having at least one via hole, a via hole formed by filling the via hole with a first metal, a reductant layer formed on the via plug and the inter-metal dielectric to a predetermined thickness, and a metal line layer formed by depositing a second metal on the reductant layer. | 2009-07-30 |
20090189285 | ON CHIP THERMOCOUPLE AND/OR POWER SUPPLY AND A DESIGN STRUCTURE FOR SAME - A thermocouple and power supply structure. The structure is interleaved through a substrate. The structure includes a first through via extending through the substrate and connected to a first contact on a top surface and a second contact on a bottom surface of the substrate, through via extending through the substrate and connected to the second contact and a third contact on the top surface of the substrate. The first contact, first through via and third contact formed from a first material and the second contact and second through via formed from a second material that is different from the first material. | 2009-07-30 |
20090189286 | FINE PITCH SOLDER BUMP STRUCTURE WITH BUILT-IN STRESS BUFFER - A fine pitch solder bump structure with a built-in stress buffer that is utilized in electronic packages, and a method of producing the fine pitch solder bump structure with built-in stress buffer. Employed is a very thick final passivation layer that is constituted of a polyimide as a so-called “cushion” for a minimal thickness of UBM (BLM) pad and solder material, while concurrently completely separating the resultingly produced polyimide islands, so that the polyimide material provides most of the physical height for the “standoff” of a modified C4 (controlled collapse chip connection) structure. In employing the polyimide material as the primary structural component of the vertical chip package interconnect in this particular inventive manner, the inherent stress buffering property of the polyimide material is utilized to full advantage by effectively reducing the high stresses encountered during chip manufacture processing steps, such as chip join, reflow, preconditioning and reliability thermal cycle stressing. | 2009-07-30 |
20090189287 | NOBLE METAL CAP FOR INTERCONNECT STRUCTURES - An interconnect structure that includes a dielectric material having a dielectric constant of about 3.0 or less is provided. This low k dielectric material has at least one conductive material having an upper surface embedded therein. The dielectric material also has a surface layer that is made hydrophobic prior to the formation of the noble metal cap. The noble metal cap is located directly on the upper surface of the at least one conductive material. Because of the presence of the hydrophobic surface layer on the dielectric material, the noble metal cap does not substantially extend onto the hydrophobic surface layer of the dielectric material that is adjacent to the at least one conductive material and no metal residues from the noble metal cap deposition form on this hydrophobic dielectric surface. | 2009-07-30 |
20090189288 | ANGLED FLYING LEAD WIRE BONDING PROCESS - A method is described having the steps of providing a surface having a plurality of wire bondable locations; wire bonding a wire to each of the wire bondable locations using a wire capillary tool; controlling the position of the capillary tool with respect to the substrate; after forming a wire bond of the wire to the wire bondable location moving the capillary tool relative to the surface as the capillary tool is moved away from the surface to form a wire having a predetermined shape. | 2009-07-30 |
20090189289 | EMBEDDED CONSTRAINER DISCS FOR RELIABLE STACKED VIAS IN ELECTRONIC SUBSTRATES - A substrate via structure for stacked vias includes: a plurality of stacked vias, wherein each via is disposed on a landing; and at least one constrainer disc surrounding at least one via, for constraining in-plane deformation of the substrate via structure. The constrainer disc is embedded such that the constrainer disc is disposed between two layers of resin. The constrainer discs may be made of copper. The constrainer disc may be circular or square-shaped. Preferably there is a dielectric gap between the constrainer disc and the via. | 2009-07-30 |
20090189290 | CLUSTERED STACKED VIAS FOR RELIABLE ELECTRONIC SUBSTRATES - A substrate via structure for stacked vias in a substrate/chip assembly includes: a center via stack and a plurality of stacked vias clustered around the center via stack. In this structure, the center via and the surrounding vias are made of copper. Some of the surrounding vias may be non-functional vias and these may be of a different height than the functional vias. | 2009-07-30 |
20090189291 | MULTI-CHIP MODULE - A multi-chip module and method is disclosed. One embodiment provides an electronic module having a first metal structure and a second metal structure. A first semiconductor chip is electrically connected with its back side to the first metal structure. A second semiconductor chip is arranged with its back side lying over the front side of the first semiconductor chip. The second metal structure includes multiple external contact elements attached over the front side of the second semiconductor chip. At least two of the multiple external contact elements are electrically connected to the front side of the second semiconductor chip. | 2009-07-30 |
20090189292 | Integrated Circuit, Semiconductor Module and Method for Manufacturing a Semiconductor Module - Embodiments of the invention relate to a semiconductor, a semiconductor module and to a method for manufacturing a semiconductor module. In an embodiment of the invention, an integrated circuit includes a plurality of connection pads on at least one side of the integrated circuit, which connection pads can be coupled electrically conductingly by means of a respective bond wire, wherein in at least an edge area on the side of the integrated circuit, on which the connection pads are arranged, a support frame portion is arranged which is configured such that bond wires adjacent to each other can be supported on the support frame portion at a distance from each other. | 2009-07-30 |
20090189293 | Semiconductor device - A semiconductor device having a chip-on-chip structure is constituted of a first semiconductor chip and even-numbered pairs of second semiconductor chips, all of which are laminated together on the surface of an interposer. The first semiconductor chip controls each pair of the second semiconductor chips so as to activate one second semiconductor chip while inactivating another second semiconductor chip. The second semiconductor chips are paired together in such a way that through-vias and electrodes thereof are positioned opposite to each other via bumps. Since drive voltage electrodes supplied with a drive voltage (VDD) and reference potential electrodes supplied with a reference potential (VSS) are mutually connected together between the paired second semiconductor chips, it is possible to increase the overall electrostatic capacitance of each second semiconductor chip so as to substantially reduce feed noise without increasing the overall layout area of the semiconductor device. | 2009-07-30 |
20090189294 | LARGE AREA INTEGRATION OF QUARTZ RESONATORS WITH ELECTRONICS - Methods for integrating quartz-based resonators with electronics on a large area wafer through direct pick-and-place and flip-chip bonding or wafer-to-wafer bonding using handle wafers are described. The resulting combination of quartz-based resonators and large area electronics wafer solves the problem of the quartz-electronics substrate diameter mismatch and enables the integration of arrays of quartz devices of different frequencies with the same electronics. | 2009-07-30 |
20090189295 | STACK CHIP PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF - A stack chip package structure and a manufacturing method thereof are disclosed. The method comprises: providing a first substrate; disposing a first chip on the first substrate; disposing a second chip and at least one second substrate on the first chip, wherein the second substrate is electrically connected to the first chip; bonding at least one first connecting wire connected between the second chip and the second substrate; bonding at least one second connecting wire connected between the first substrate and the second substrate; and forming a package body on the first substrate to encapsulate the first chip, the second chip, the second substrate, the first connecting wire and the second connecting wire. | 2009-07-30 |
20090189296 | FLIP CHIP QUAD FLAT NON-LEADED PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF AND CHIP PACKAGE STRUCTURE - A manufacturing method for a Flip Chip Quad Flat Non-leaded package structure is provided. A lead frame having a plurality of leads is provided at first in the manufacturing method. A dielectric layer is formed on the lead frame and exposes a top surface and a bottom surface of the leads. A redistribution layer including a plurality of pads and a plurality of conductive lines connected the pads and the top surface of the leads is formed on the dielectric layer. A solder resist layer is formed to cover the redistribution layer, the dielectric layer and the leads, and expose the surface of the pads. An adhesive layer is formed on the solder resist layer. A chip having a plurality of bumps is provided. The chip is adhered on the solder resist layer with the adhesive layer and each bump is electrically connected with one of the pads. | 2009-07-30 |
20090189297 | SEMICONDUCTOR DEVICE - To provide a semiconductor device having high reliability by reducing the bending of a semiconductor device and mitigating stress exerted on external terminals. In a semiconductor device | 2009-07-30 |
20090189298 | Bonding pad structure and debug method thereof - The bonding pad structure includes a main bonding pad and a blank path. The blank path crosses through the main bonding pad for dividing the main bonding pad into a first sub-bonding pad and a second sub-bonding pad. The bonding pad structure may further include a solder covered on the blank path and the main bonding pad selectively. The main bonding pad is regarded as a closed circuit when the solder is covered on the blank path and the main bonding pad. The main bonding pad is regarded as a open circuit when the solder is not covered on the blank path and the main bonding pad. A debug method with the bonding pad structure is also disclosed. | 2009-07-30 |
20090189299 | METHOD OF FORMING A PROBE PAD LAYOUT/DESIGN, AND RELATED DEVICE - A method of forming a probe pad layout/design, and related device. At least some of the illustrative embodiments are methods comprising testing a semiconductor device by electrically contacting a first portion of a semiconductor die by way of a first pad within a scribe street adjacent to the semiconductor die, and electrically contacting a second portion of the semiconductor die by way of a first bond pad within the semiconductor die. | 2009-07-30 |
20090189300 | Sealing Film and a Semiconductor Device Using the Same - The present invention provides a sealing film excellent in filling properties and adhesiveness as a sealing film which comprises a resin layer containing the following (A), (B) and (C) and having a flow within the range of 150 to 1800 μm at 80° C.: (A) a resin component containing (a1) a high-molecular-weight component comprising crosslinking functional groups and having a weight-average molecular weight of 100,000 or more and a Tg within the range of −50 to 50° C. and (a2) a thermoplastic component comprising an epoxy resin as main component, (B) a filler having an average particle size within the range of 1 to 30 μm, and (C) a colorant, as well as a method for manufacturing the same and a semiconductor device using the same. The present invention also provides a sealing film excellent in adhesiveness and shape retention as a sealing film which comprises a resin layer containing the above (A), (B) and (C) and having a resin layer having a viscosity within the range of 10000 to 100000 Pa·s in a B-stage state at 50 to 100° C. in thermosetting viscoelasticity measurement, as well as a semiconductor device using the same. | 2009-07-30 |
20090189301 | DOWNCOMER DISTRIBUTOR - A tray assembly is provided for improved gas/liquid contact when used in a large chemical process tower. Each tray has a downcomer wall of which the lower portion is a distributor. The distributor has discharge ports sized to control the rate of liquid flow at different positions across the distributor and flanges aligned individually to direct liquid flow from different discharge ports across different areas of the tray deck immediately below the downcomer. In combination, discharge ports and liquid flow directing flanges effect even liquid flow across the surface of the tray immediately below. Benefits of this invention are trays with better mass transfer efficiency and enhanced capacity compared with prior art trays. | 2009-07-30 |
20090189302 | METHOD FOR MANUFACTURING MICROLENS AND METHOD FOR MANUFACTURING SOLID-STATE IMAGE SENSOR - A method for manufacturing a microlens includes forming a microlens by pressing a microlens mold having a reverse shape of a microlens formed therein on a microlens-forming film formed on a substrate to transfer the reverse shape of the microlens to the microlens-forming film. The microlens mold is formed by irradiating an inorganic resist film which is formed on a mold substrate with exposure light by relative two-dimensional scanning, and etching an exposed region of the inorganic resist film to form the reverse shape of the microlens. The irradiation intensity of the exposure light is adjusted to correspond to the depth of the reverse shape of the microlens from the surface of the inorganic resist film on the basis of profile data of the reverse shape of the microlens. | 2009-07-30 |
20090189303 | METHODS FOR FORMING COATED HIGH INDEX OPTICAL ELEMENTS - Disclosed is a method of forming a coated optical element. The method includes providing a mould assembly having opposed mould sections and applying a UV-curable hard coat monomer composition to the casting face of at least one of the mould sections to form a hard coat monomer layer. The hard coat layer is irradiated with UV radiation under conditions to form a partially cured hard coat layer. The assembled mould is filled with a high index optical element precursor material the optical element precursor material and the partially cured hard coat layer are cured to form a high index optical element having a hard coat. | 2009-07-30 |
20090189304 | Encapsulation of oils by coacervation - The present invention describes the encapsulation of water insoluble oils by coacervation and the subsequent reduction in oxidative degradation of these oils in microencapsulated forms. Water insoluble oils useful in the process of the invention include food oils such as PUFA, flavor oils, and agriculturally and pharmaceutically active oils. | 2009-07-30 |
20090189305 | METHOD OF MAKING FLEXIBLE FOAMING MEMBER FROM RECYCLED MATERIALS - The present invention provides a method of making a flexible foaming member from recycled material. The first step is recycling wastes including rubber, plastic, fiber, and metal, and then crushing the wastes into pieces. Next, the pieces are separated according to specific weights of each of the pieces into a plurality of groups, and then choose predetermined groups of the pieces in a predetermined ration, and mixing the pieces with a flexible material and a foaming agent to form a mixture. The last step is pressing the mixture into a plate-like foaming material, and vulcanizing the foaming material to form a flexible foaming member. The chosen groups of the pieces and the ratio thereof may make a flexible foaming member with specific property. | 2009-07-30 |
20090189306 | MANUFACTURING METHOD OF STRUCTURE BY IMPRINT - A manufacturing method of a structure by an imprint process includes a first imprint step of forming a first resin material layer by applying a first resin material onto a substrate and then transferring an imprint pattern of a mold onto the first resin material layer, a second imprint step of forming a second resin material layer by applying a second resin material onto the first resin material layer formed in the first imprint step and onto an area of the substrate adjacent to the first resin material layer and then transferring the imprint pattern of the mold onto the second resin material layer, and a step of forming a pattern by etching the first and second resin material layers. | 2009-07-30 |
20090189307 | COMPOSITE STRUCTURES WITH INTEGRAL INTELLIGENT SKIN - Composite structures having an integral intelligent skin are made of one or more plies of a structural base material and an intelligent or smart film by molding one or more plies and the film into an integral unitary body with the intelligent film outermost. The intelligent or smart film contains or bears a functionally active or interactive component such as antennae, electronic sensors, electric and/or electronic circuitry, and/or spectrally tailored coatings. A method of making the composite structure in a very economical manner is disclosed. | 2009-07-30 |
20090189308 | Resin infusion potting - A process for forcibly infusing liquid potting compound into the exposed strands of a cable prior to forming a termination. The process uses a mold that encloses the exposed strands. Potting compound is then pumped into the mold, where it runs around and through the exposed strands. A second venting passage is preferably employed, so that the liquid potting compound flows through the mold without trapping any air pockets. | 2009-07-30 |
20090189309 | Method of resin sealing permanent magnets in laminated rotor core - A laminated rotor core ( | 2009-07-30 |
20090189310 | SEMICONDUCTOR CHIP COMPRESSION MOLDING METHOD AND MOLD FOR COMPRESSION MOLDING - By clamping upper and lower molds, a semiconductor chip and a stacking connection electrode are immersed in a resin material heated and molten in a cavity coated with a mold release film. The mold release film is pressed into contact with a tip portion of the connection electrode by a cavity bottom face member, so that a collective resin portion having a shape corresponding to the shape of the cavity is molded in the cavity. Accordingly, the semiconductor chip and the connection electrode are compression molded with the resin material. Here, a tip portion of the connection electrode is exposed from the collective resin portion. | 2009-07-30 |
20090189311 | Apparatus and Method for Re-Coloring, Recovering, Repairing and Reformulating Cosmetic Lip Products - A lip product remixing kit contains tools that provide for recovering unused cosmetic lip material from applicator containers, and remixing and remolding the materials to form reconstituted cosmetic lip products. Using the kit, one may re-color their lip product by combining two or more lip products so as to customize the overall appearance (color and shape) and consistency of the product as desired by the user. The kit also provides tools needed to recover the unused lipstick material in the base of an applicator tube and to re-mold the material into a new stick that may be inserted into a new or used applicator tube. Other uses for the kit are to repair a broken lipstick and reformulate a lipstick into lip gloss. In a preferred embodiment, the kit includes spatulas, mixing/measuring containers, storage containers, lip product applicator tubes with stickers, instructions, a tube of clear gloss and a mold for forming reconstituted sticks of lipstick. | 2009-07-30 |
20090189312 | DEVICE AND METHOD FOR REMOVING INVESTMENT FROM A DENTAL APPLIANCE - A method and device for removing the bulk of the casting investment surrounding a pressed ceramic dental appliance. | 2009-07-30 |
20090189313 | Fabrication of a Soft-Silicone Cover for a Hearing Instrument Shell - The manufacture of a hearing instrument having a hard inner shell and a softer outer covering, for insertion into the ear canal of the user, may be accomplished using rapid manufacturing and prototyping techniques. Starting with a digital model of the ear canal, a mold for the softer outer covering may be fabricated using a process such as stereo lithography. | 2009-07-30 |
20090189314 | TRANSPARENT THERMOPLASTIC POLYURETHANES HAVING LOW HAZE AND GOOD PROCESSABILITY, METHODS OF MAKING THE SAME, AND USES THEREFOR - Light-stable, thermoplastic polyurethanes with good processability and having an ASTM D-1003 haze value of less than 10%, the polyurethane prepared by a process comprising: reacting: (a) a diisocyanate component comprising 1,6-hexamethylene diisocyanate; (b) a chain extension component consisting of (b1) 1,4-di(β-hydroxyethyl)hydroquinone and (b2) at least one chain extender selected from the group consisting of diols having a 2 or 3 carbon atom chain length between the two OH groups, in a molar ratio of chain extender (b1) to chain extender (b2) of 10:1 to 1:4; and (c) at least one polyol component having a number average molecular weight of 450 to 10000 g/mol, and an average number of Zerewitinoff-active hydrogen atoms of at least 1.8 to at most 3.0; wherein the ratio of isocyanate groups in component (a) to isocyanate-reactive groups in components (b) and (c) is 0.9:1 to 1.1:1. | 2009-07-30 |
20090189315 | Method for the Production of a Ceramic Shaped Body and a Shaped Body Produced by the Method - The invention relates, inter alia, to a method for the production of a ceramic shaped body ( | 2009-07-30 |
20090189316 | METHOD FOR MANUFACTURING KEYPAD HAVING THREE-DIMENSIONAL PATTERNS - In a method for manufacturing keypad having three-dimensional patterns, curable resin is filled in a mold, and a ultra-violet lamp irradiates the curable resin, thereby curing the resin. A plurality of different materials is overlapped with each other, and a coating layer is coated on the surface of each three-dimensional pattern, thereby manufacturing a key having three-dimensional patterns. Via the above arrangement, the recognition and aesthetic feeling of each three-dimensional pattern can be increased. | 2009-07-30 |