31st week of 2009 patent applcation highlights part 53 |
Patent application number | Title | Published |
20090193225 | SYSTEM AND METHOD FOR APPLICATION SPECIFIC ARRAY PROCESSING - A processing architecture and methods therein for building application specific array processing utilizing a sequential data bus for control and data propagation. The methods of array processing provided by the architecture allows for numerical analysis of large numerical data such as simulation, image processing, computer modeling or other numerical functions. The architecture is unlimited in scalability and facilitates mixed mode processing of idealized, analytical and real data, in conjunction with real time input and output. | 2009-07-30 |
20090193226 | PROCESSOR FOR EXECUTING HIGHLY EFFICIENT VLIW - A 32-bit instruction | 2009-07-30 |
20090193227 | Multi-stream on-chip memory - An interface to on-chip memory is described, which provides for using on-chip memory by a RISC superscalar processor, enhanced with methods which execute vector operations by treating the vectors as “streams”, which are fed through one or two function units in a pipelined manner. The interface provides concurrent multiple streams, while at the same time serving “conventional” requests from the host RISC superscalar processor. | 2009-07-30 |
20090193228 | MULTIPROCESSOR SYSTEM AND METHOD OF SYNCHRONIZATION FOR MULTIPROCESSOR SYSTEM - Each of processors has a barrier write register and a barrier read register. Each barrier write register is wired to each barrier read register by a dedicated wiring block. For example, a 1-bit barrier write register of a processor is connected, via the wiring block, to a first bit of each 8-bit barrier read register contained in the processors, and a 1-bit barrier write register of another processor is connected, via a wiring block, to a second bit of each 8-bit barrier read register contained in the processors. For example, a processor writes information to its own barrier write register, thereby notifying synchronization stand-by to the other processors and reads its own barrier read register, thereby recognizing whether the other processors are in synchronization stand-by or not. Therefore, a special dedicated instruction is not required along barrier synchronization processing, and the processing can be made at a high speed. | 2009-07-30 |
20090193229 | HIGH-INTEGRITY COMPUTATION ARCHITECTURE WITH MULTIPLE SUPERVISED RESOURCES - The present invention relates to computers, the undetected errors of which have a very low rate of occurrence (approximately 10 | 2009-07-30 |
20090193230 | COMPUTER SYSTEM INCLUDING A MAIN PROCESSOR AND A BOUND SECURITY COPROCESSOR - A computer system includes a main processor and a security control processor that is coupled to the main processor and configured to control and monitor an operational state of the main processor. To ensure the computer system may be trusted, the security control processor may be configured to hold the main processor in a slave mode during initialization of the security control processor such that the main processor is not operable to fetch and execute instructions from an instruction source external to the main processor, for example. In addition, the security control processor may be configured to initialize the operational state of the main processor to a predetermined state by transferring to the main processor via a control interface one or more instructions and to cause the main processor to execute the one or more instructions while the main processor is held in the slave mode. | 2009-07-30 |
20090193231 | METHOD AND APPARATUS FOR THREAD PRIORITY CONTROL IN A MULTI-THREADED PROCESSOR OF AN INFORMATION HANDLING SYSTEM - An information handling system employs a processor that includes a thread priority controller. An issue unit in the processor sends branch issue information to the thread priority controller when a branch instruction of an instruction thread issues. In one embodiment, if the branch issue information indicates low confidence in a branch prediction for the branch instruction, the thread priority controller speculatively increases or boosts the priority of the instruction thread containing this low confidence branch instruction. In the manner, should a branch redirect actually occur due to a mispredict, a fetcher is ready to access a redirect address in a memory array sooner than would otherwise be possible. | 2009-07-30 |
20090193232 | Apparatus, processor and method of cache coherency control - An apparatus includes a plurality of processors each of which includes a cache memory, and a controller which suspends a request of at least one of the processors during a predetermined period when a processor fetches a data from a main memory to the cache memory, wherein the controller suspends the request of at least one of the processors except the processor which fetches the data from the main memory to the cache memory. | 2009-07-30 |
20090193233 | Mechanism for Avoiding Check Stops in Speculative Accesses While Operating in Real Mode - A method and processor for avoiding check stops in speculative accesses. An execution unit, e.g., load/store unit, may be coupled to a queue configured to store instructions. A register, coupled to the execution unit, may be configured to store a value corresponding to an address in physical memory. When the processor is operating in real mode, the execution unit may retrieve the value stored in the register. Upon the execution unit receiving a speculative instruction, e.g., speculative load instruction, from the queue, a determination may be made as to whether the address of the speculative instruction is at or below the retrieved value. If the address of the speculative instruction is at or below this value, then the execution unit may safely speculatively execute this instruction while avoiding a check stop since all the addresses at or below this value are known to exist in physical memory. | 2009-07-30 |
20090193234 | SEQUENCER CONTROLLED SYSTEM AND METHOD FOR CONTROLLING TIMING OF OPERATIONS OF FUNCTIONAL UNITS - The invention proposes a simple method for controlling distributed functional units (FU) in a system. It offloads the main system processor from intermediate status monitoring. The sequencer controlled system comprises a plurality of functional units, a processor operatively coupled to the plurality of functional units through a bus, a sequencer having a set of registers, and an interrupt source register configured for interrupt polling. The registers are configured to control the timing of at least one operation of the functional units with stored instructions for each of the functional units. The processor sets up at least some of the registers through the bus for the initial configuration and the sequencer is activated by the processor. | 2009-07-30 |
20090193235 | TRANSFER SYSTEM, AND TRANSFER METHOD - In response to a transfer request, for which a loading time at a transfer source and a loading time at a transfer target are designated by a production controller, there is created a transfer scenario, which contains a basic transfer (From) from the transfer source to a buffer near the transfer target, for example, and a basic transfer (To) from the buffer to the transfer target. In order that the basic transfers (From, To) may be able to be executed, the buffer is reserved, and a transfer vehicle is allocated. The time period for the transfer vehicle to run to the transfer source or the buffer and the time period for the transfer vehicle to run from the transfer source or the buffer are estimated to assign a transfer command to the transfer vehicle. The possibility that the loading and the loading time may deviate from a designated period is evaluated. In case this possibility is high, a production controller is informed that a just-in-time transfer is difficult. | 2009-07-30 |
20090193236 | CONDITIONAL MEMORY ORDERING - A system for conditional memory ordering implemented in a multiprocessor environment. A conditional memory ordering instruction executes locally using a release vector containing release numbers for each processor in the system. The instruction first determines whether a processor identifier of the release number is associated with the current processor. Where it is not, a conditional registered is examined and appropriate remote synchronization operations are commanded where necessary. | 2009-07-30 |
20090193237 | PARSING-ENHANCEMENT FACILITY - An instruction for parsing a buffer to be utilized within a data processing system including: an operation code field, the operation code field identifies the instruction; a control field, the control field controls operation of the instruction; and one or more general register, wherein a first general register stores an argument address, a second general register stores a function code, a third general register stores length of an argument-character buffer, and the fourth of which contains the address of the function-code data structure. | 2009-07-30 |
20090193238 | Reconfigurable apparatus and method for providing multiple modes - A reconfigurable processor (RP) structure is provided, and particularly, a multi-mode providing apparatus including an exclusive coarse-grained array unit for each mode and a multi-mode providing method thereof are provided. The multi-mode providing apparatus includes: at least one reconfigurable operation mode execution unit performing a plurality of operations for processing a predetermined operation mode; a common coarse-grained array unit shared temporally by the at least one reconfigurable operation mode execution unit, and performing a main processing operation set to be performed by the common coarse-grained array unit, among the plurality of operations; and a controller determining whether the common coarse-grained array unit is available, and according to the result of the determination controlling the at least one reconfigurable operation mode execution unit so that the common coarse-grained array unit or an exclusive coarse-grained array unit performs the main processing operation, the exclusive coarse-grained array unit included in the at least one reconfigurable operation mode execution unit. Therefore, it is possible to reduce a delay time for data processing while reducing the size of hardware. | 2009-07-30 |
20090193239 | COUNTER CONTROL CIRCUIT, DYNAMIC RECONFIGURABLE CIRCUIT, AND LOOP PROCESSING CONTROL METHOD - A counter control circuit that controls the operation of a counter arranged in a dynamic reconfigurable circuit executing an arbitrary instruction by dynamically switching an aggregation of reconfigurable processing elements (hereinafter referred to as “PEs”) according to a context reciting a processing content of the PE and a connection content between the PEs, the counter control circuit including: keeping means for keeping an operation instruction signal when the PE executing a conditional branching computation outputs, in a context being adapted to the dynamic reconfigurable circuit, the operation instruction signal of the counter for a subsequent context; output means for outputting the operation instruction signal kept in the keeping means to the counter; and control means for causing the output means to output the operation instruction signal when the context being adapted to the dynamic reconfigurable circuit is switched to the subsequent context. | 2009-07-30 |
20090193240 | METHOD AND APPARATUS FOR INCREASING THREAD PRIORITY IN RESPONSE TO FLUSH INFORMATION IN A MULTI-THREADED PROCESSOR OF AN INFORMATION HANDLING SYSTEM - An information handling system employs a processor that includes a thread priority controller. The processor includes a memory array that stores instruction threads including branch instructions. A branch unit in the processor sends flush information to the thread priority controller when a particular branch instruction in a particular instruction thread requires a flush operation. The flush information may indicate the correctness of incorrectness of a branch prediction for the particular branch instruction and thus the necessity of a flush operation. The flush information may also include a thread ID of the particular thread. If the flush information for the particular branch instruction of the particular thread indicates that a flush operation is necessary, the thread priority controller in response speculatively increases or boosts the priority of the particular instruction thread including the particular branch instruction. In this manner, a fetcher in the processor obtains ready access to the particular thread in the memory array. | 2009-07-30 |
20090193241 | Direct Register Access For Host Simulation - Methods and apparatuses are provided that enable software designed to be operated with an embedded system to be tested in the absence of a physical embodiment of the embedded system. A simulation of the embedded system may be employed to operate the software. Various implementations of the invention provide for the processing of requests by the software to access memory within the embedded system. Still, various implementations of the invention provide for the identification of these memory access request and for the mapping of the desired memory location to a valid memory location. | 2009-07-30 |
20090193242 | COMPUTER SYSTEM WITH DUAL BASIC INPUT OUTPUT SYSTEM AND OPERATION METHOD THEREOF - A computer system including a central processing unit (CPU), a chipset, a first bus, a second bus, a first memory, a second memory, and a logic control circuit is disclosed. The chipset is coupled to the CPU. The first bus and the second bus are respectively coupled to the chipset. The first memory is coupled to the chipset through the first bus for storing a first basic input output system (BIOS). The second memory is coupled to the chipset through the second bus for storing a second basic input output system (BIOS). The logic control circuit detects a state of the first bus and controls the chipset to select to access the first memory through the first bus or select to access the second memory through the second bus according to the state of the first bus. | 2009-07-30 |
20090193243 | Dual Mode Power-Saving Computing System - The present invention relates to a data processing system comprising both a high performance computing sub-system having typical high power consumption and a low performance subsystem requiring less power. The data processing system acts as a single computing device by moving the execution of software from the low performance subsystem to the high performance subsystem when high computing power is needed and vice versa when low computing performance is sufficient, allowing in the latter case to put the high performance subsystem into a power saving state. The invention relates also to related algorithms. | 2009-07-30 |
20090193244 | Computer System and Legacy Boot Method for the Computer System - A computer system including no basic input/output system (BIOS) for operating bootstrap used in initial activation of a legacy operation system is allowed to perform booting of legacy operation system therefor and includes a central processing unit (CPU) and a memory, in which extended firmware and bootstrap program are stored. The extended firmware includes BIOS emulator and a plurality of device drivers. The extended firmware uses the device driver to make the BIOS emulator perform emulation of BIOS operation in response to a BIOS call issued by the bootstrap program. | 2009-07-30 |
20090193245 | PARALLELIZING MULTIPLE BOOT IMAGES WITH VIRTUAL MACHINES - A system and method are presented for converting a multi-boot computer to a virtual machine. Existing boot images on a multi-boot computer are identified and converted into virtual machine instances. Each virtual machine instance represents an operating system and is capable of running at the same time. Finally, a new hosting operating system is installed. The new hosting operating system launches and manages the converted virtual machine instances. | 2009-07-30 |
20090193246 | DATA PROCESSING APPARATUS AND METHOD OF MOUNTING LOGICAL DRIVE - A data processing apparatus and a method of mounting a logical drive are provided which reduce the time required for completing start-up of an application. A priority level of each logical drive is determined based on access frequency by the automatically started applications in an initial setting processing of the applications in the previous start-up of the data processing apparatus. Higher priority is given to the logical drive having higher access frequency. For subsequently starting up the data processing apparatus, each logical drive is mounted in the order of the determined priority. | 2009-07-30 |
20090193247 | PROPRIETARY PROTOCOL TUNNELING OVER EAP - Methods and apparatus provide tunneling one authentication framework over a more widely accepted framework (e.g., EAP). In this manner, pluralities of strong authentication protocols are wirelessly enabled between a supplicant and server that are not otherwise wirelessly enabled. During use, packets are wirelessly transmitted and received between the supplicant and server according to EAP's prescribed message format, including a wireless access point. In a tunnel, various authentication protocols form the payload component of the message format which yields execution capability of more than one protocol, instead of the typical single protocol authentication. Certain tunneled frameworks include NMAS, LDAP/SASL, Open LDAP/SLAPD, or IPSEC. Computer program products, computing systems and various interaction between the supplicant and server are also disclosed. | 2009-07-30 |
20090193248 | Processing Multiple Wireless Communications Security Policies - A computer program product for processing wireless data packets allows for processing packets to consolidate security processing. Security processing is performed in accordance with multiple security policies. This processing is done in a single front end processing block. Different security processes can be performed in parallel. Processing overhead is reduced by eliminating the need to redundantly check packet characteristics to assess the different security requirements imposed by security policies. Further, the present invention also substantially reduces the CPU cycles required to transport data back and forth from memory to a cryptographic coprocessor. | 2009-07-30 |
20090193249 | PRIVACY-PRESERVING INFORMATION DISTRIBUTION SYSTEM - A system, device and method for keeping the identity of a user secret, while managing requests for information, in an information distribution system. The identity of the user is kept secret by the use of a persistent pseudonym and a temporary pseudonym, which are associated with a user identity device. The process of information distribution is enhanced by the use of licenses and certificates, which the user obtains by representing himself with the permanent pseudonym. When accessing the requested information, the user is represented by the temporary pseudonym. | 2009-07-30 |
20090193250 | AUTHENTICATION SYSTEM, SIGNATURE CREATING DEVICE, AND SIGNATURE VERIFYING DEVICE - A signature generating device for generating digital signature data that certifies authenticity of information of a person, and making the information obfuscated. The signature generating device comprises: a storage unit that stores attribute information concerning the person and a private key corresponding to the attribute information; an obfuscated information generating unit that selects one or more pieces of dummy information in relation to the attribute information, and generates the obfuscated information that includes the attribute information and the dummy information; a public key obtaining unit that obtains a public key corresponding to the attribute information and public keys respectively corresponding to the dummy information; and a signature generating unit that generates digital signature data by performing a ring signature generation process to the obfuscated information, using the private key and the public key corresponding to the attribute information and using the public keys corresponding to dummy information. | 2009-07-30 |
20090193251 | SECURE REQUEST HANDLING USING A KERNEL LEVEL CACHE - The present invention discloses a system, method, apparatus, and computer usable product code for handling requests. The invention can include a kernel level cache, a request handling service, and a transport layer security service. The kernel level cache can store request handling data. The request handling service can handle secure requests at a transport layer of a kernel when request handling data is present in the kernel level cache. The transport layer security service can handle encryption/decryption operations for the secure requests and request responses at the transport layer. | 2009-07-30 |
20090193252 | METHOD AND SYSTEM FOR SECURE PEER-TO-PEER COMMUNICATION - The invention provides a server system, client, method and program element for distributing content in a peer-to-peer network. The server system spits a file into segments and makes copies of the segments for clients to download. Each segment is encrypted with a unique encryption key and marked. Identifiers of encrypted segments are transmitted to clients such that each client receives a unique set of identifiers enabling the client to download a unique set of encrypted segments from other clients and/or from the server system. | 2009-07-30 |
20090193253 | METHOD AND SERVER FOR PROVIDING A MOBILE KEY - After a radio link is established between a mobile subscriber terminal and an access network, the subscriber is authenticated by a proxy server of an intermediate network forwarding, from the access network to a home network of the subscriber, authentication message(s) containing a subscriber identification. If the subscriber is authenticated and the subscriber identification is already stored in the proxy server, the proxy server assigns a group-specific mobile key to the subscriber identification. When the home agent receives a registration request message originating from a subscriber terminal and containing a subscriber identification and transmits a key request message, containing the subscriber identification, for a mobile key to the proxy server, if the subscriber identification in the key request message matches a subscriber identification stored by the proxy server, a mobile key for cryptographic protection of mobile signalling messages is provided to the home agent by the proxy server. | 2009-07-30 |
20090193254 | ANCHOR POINT-BASED DIGITAL CONTENT PROTECTION - Digital content protection can be effectively implemented through use of an anchor point and binding records in a user domain. An anchor point domain may include a secure anchor point, and data storage to store digital property instances and rights objects. The secure anchor point may be configured to receive a title pre-key from the rights object and use a binding key to decrypt the title pre-key to yield a title key. The binding key may include data uniquely associating the encrypted digital property instance with the secure anchor point. | 2009-07-30 |
20090193255 | Method and apparatus for determining and using the sampling frequency for decoding watermark information embedded in a received signal sampled with an original sampling frequency at encoder side - Many watermarking systems make use of correlation for calculating a detection metric, which means that reference patterns are generated at encoder side and are embedded inside the audio or video signal, dependent on the message to be embedded. The same reference patterns are generated at decoder side. The embedded message is decoded by correlating the reference patterns with the watermarked signal. The watermark detector decides, depending on the size of the correlation result values, whether or not a given reference pattern was embedded. However, decoding watermarked audio or video signals is difficult if the link between the watermark encoder and the watermark decoder is not a digital one, for example an acoustic path. According to the invention, a re-sampler control unit controls the sampling frequency of a re-sampler, in connection with a watermark decoder that outputs, in addition to the watermark information bits, a corresponding confidence value that is derived from the correlation result and that is used for synchronizing the re-sampler sampling frequency with the original sampling frequency of the watermarked signal. The synchronization processing includes a search mode and a synchronized mode. | 2009-07-30 |
20090193256 | ELECTRONIC SIGNATURE METHOD, APPARATUS, AND RECORDING MEDIUM HAVING ELECTRONIC SIGNATURE PROGRAM RECORDED THEREON - A computer divides a target electronic document into a plurality of document segments. Then, the computer generates a signature (s, t) that includes a set of two values having a signature value s forming a signature on the electronic document and a deletion signature value t used for deletion, the signature value s which serves as a body of the signature being formed by a superposition of signature information on the individual document segments. Then, in a case where one of the plurality of document segments obtained by the division is to be extracted, the computer superimposes deletion information of a document segment to be deleted on the deletion signature value t to generate a new signature value t′, and produces an updated signature (s, t′). | 2009-07-30 |
20090193257 | RIGHTS OBJECT AUTHENTICATION IN ANCHOR POINT-BASED DIGITAL RIGHTS MANAGEMENT - Digital lights management (DRM) can be effectively implemented through use of an anchor point and binding records in a user domain. Furthermore, authentication of a rights object defining the scope of access allowed for a digital property instance may be achieved through use of a signing key in the anchor point. The signing key may be used to assure no tampering has occurred with the rights object since acquisition of a digital property instance. A digital property owner may gain additional functionality and control through implementation of a play counter, rental duration limit, etc., using a signing key. | 2009-07-30 |
20090193258 | CONTROLLING THE DOWNLOADING AND RECORDING OF DIGITAL DATA - A method and apparatus for enabling a licensed end user to record digital data as described is particularly useful to the music industry as it enables them to make audio data available over the internet but to retain control of the uses to which that audio data can be put. Thus, upon completing a financial transaction to pay for the required audio tracks, the end user is enabled to download and decrypt encrypted music tracks and to play them on the end user's personal computer. The end user can also be allowed to burn a CD including the downloaded music tracks. However, the end user is only enabled to decrypt and record the music tracks onto the CD if the music tracks are recorded together with copy protection. | 2009-07-30 |
20090193259 | ELECTRONIC DOCUMENT AUTHENTICITY ASSURANCE METHOD AND ELECTRONIC DOCUMENT DISCLOSURE SYSTEM - An electronic document authenticity assurance technique and an information disclosure system both of which can compatibly realize the assurance of the authenticity of disclosure documents and the deletion of information inappropriate for disclosure. An electronic document is divided into constituent elements and an electronic signature is affixed to an arbitrary subset of a set including all the constituent elements. Otherwise, an electronic signature is affixed to data obtained by binding each of the constituent elements to information specifying the relationship between a respective one of the constituent elements and the structure of the electronic document. Otherwise, the hash values of the respective constituent elements are calculated and an electronic signature is affixed to data obtained by binding the calculated hash values together. Otherwise, random numbers generated for the respective constituent elements are bound together, then the hash values of the respective random-numbered constituent elements are calculated, and then an electronic signature is affixed to data obtained by binding the calculated hash values together. | 2009-07-30 |
20090193260 | METHOD AND APPARATUS FOR SECURE AND SMALL CREDITS FOR VERIFIABLE SERVICE PROVIDER METERING - A method and apparatus for obtaining access to services of service providers. In one embodiment, the method comprises requesting a desired service through a foreign service provider, generating a hash tree and generating a digital signature on a root value of the hash tree, sending the digital signature and the root value to the foreign service provider, providing one or more tokens to the foreign service provider with the next packet if the foreign service provider accepts the signature and continuing to use the service while the foreign service provider accepts tokens. | 2009-07-30 |
20090193261 | APPARATUS AND METHOD FOR AUTHENTICATING A FLASH PROGRAM - In one embodiment of the invention, an apparatus for authenticating a flash program is provided. The apparatus comprises a hardware unique key, a register storing a customer identity (ID) and a message authentication code (MAC) generation unit. The MAC generation unit acquires a root key corresponding to the hardware unique key and the customer ID, and generates a MAC for the flash program using the acquired root key, wherein the content of the register is locked to avoid modification of the stored customer ID until the next system reset. | 2009-07-30 |
20090193262 | SECURITY THRESHOLD ENFORCEMENT IN ANCHOR POINT-BASED DIGITAL RIGHTS MANAGEMENT - Digital rights management (DRM) can be effectively implemented through use of an anchor point and binding records within a user's anchor point domain. Assigning security levels to various components within an anchor point based DRM system and evaluating them against a security criterion provides additional protection against authorized access of the digital content. The content provider may specify the security criterion (e.g., a security level threshold), and the ability to use the digital content is denied or granted based on the ability of components to satisfy this criterion. For example, the ability to use a digital property instance is granted to a content handler that satisfies the security criterion and denied to a content handle that does not satisfy the security criterion. | 2009-07-30 |
20090193263 | Identifying and processing an unauthorized access request - The system reuses the classic User ID & Password combination for authentication and adds a third component called a USE code for additional authorization check, as an example. This method allows access to a system when it is requested with correct User ID and Password (i.e., with correct pass code) but with an unauthorized USE code, the system identifies it as an unauthorized access and triggers the proper security measures to minimize the damage and monitor the actions in a way not to alarm the unauthorized user who is using the owner's credential to access the system. The USE Code is an extension to the pass code to raise various alarms and have a stepwise access level control based on different inputted values. | 2009-07-30 |
20090193264 | AUTHENTICATION SYSTEM AND METHOD - A strong authentication method and system using a Secure ICC component coupled with a Personal device, and relying on the existing cryptographic protocols and keys for managing the secure ICC to generate One-Time-Passwords when the necessary authentication keys or cryptographic protocols are not already present in the Secure ICC configuration for that purpose. | 2009-07-30 |
20090193265 | FAST DATABASE INTEGRITY PROTECTION APPARATUS AND METHOD - An apparatus and method of protecting the integrity of a database is provided. Protection of the database is implemented by randomly selecting part of the database that is to be authenticated, the part of the database being less than the entire database to be authenticated. Then, only the selected part of the database is processed through a security function to generate a representation of authentication of the database for comparison with another representation of authentication of the database. Based on a comparison of the representation of authentication and the another representation of authentication, it is determined if integrity of the database has been maintained. | 2009-07-30 |
20090193266 | Access control for protected and clear AV content on same storage device - A method and apparatus for storing both protected and clear data on a single storage device | 2009-07-30 |
20090193267 | Secure electronic medical record storage on untrusted portal - Patients' medical records are encrypted using a symmetric encryption algorithm and stored on a server that is accessible via a distributed data network. The keys used for encrypting the records are also encrypted, using a public key of a creator of the record, and the encrypted record keys are stored on the server. Facilities for sharing records with other users and for modifying records are also described. | 2009-07-30 |
20090193268 | Packetized Power - Methods, systems, and devices are disclosed for producing and delivering packetized power within a DC computing environment. Within the DC computing environment a power requirement or request is communicated to a power router. The power router then determines a power source capable of fulfilling the power requirement and then causes the power to be delivered in packetized form. The packetized power is appended to a message header which allows the power packet to be received by the requesting device. | 2009-07-30 |
20090193269 | DATA NETWORK AND METHOD OF CONTROLLING THEREOF - A data network that includes a plurality of nodes for storing data and a plurality of control units, the adapted to control at least one of the nodes in which individual nodes are powered-up when the assigned control unit receives a request from a client to access the data stored in the node. | 2009-07-30 |
20090193270 | Power Management in Federated/Distributed Shared Memory Architecture - This invention is a power management scheme for a shared memory multiprocessor system which splits the control logic between the master-specific logic and memory bank logic. Power-down is initiated from a central power-down controller. This central power-down controller informs the master and target specific logic. Further memory accesses are blocked. All pending activities complete. The central controller then proceeds to power down the memory and informs the master and target specific logic upon completion. No requests for wakeup are initiated by master-specific logic from the time a power-down request is received until the completion of power-down. | 2009-07-30 |
20090193271 | POWER MESH MANAGEMENT METHOD - The invention discloses a power mesh managing method utilized in an integrated circuit. The integrated circuit includes a standard cell and a standard-cell power supplying mesh corresponding to a first direction. The power mesh managing method includes: defining a power supplying network including a first plurality of power meshes growing along the first direction and a second plurality of power meshes growing along a second direction, and defining an assistant connecting network on a third metal layer, wherein the assistant connecting network includes a plurality of assistant connecting lines growing along the second direction, the first plurality of power meshes are formed on a first metal layer, the second plurality of power meshes on a second metal layer, the third metal layer is below the first metal layer, and the second metal layer is above the first metal layer. | 2009-07-30 |
20090193272 | Storage system and power consumption reduction method for the same - In a storage system that includes two or more file servers each including an arbitrary number of operating virtual file servers, a management server: holds a load information table regarding a load on each virtual file server for each time period and redundancy information table for the storage system; judges, with reference to the load information table and redundancy information table, whether or not the loads on the virtual file servers can be handled by a smaller number of file servers than the number of currently-operating file servers; selects, if the judgment result is positive, a power-off target file server and makes another file server fail over a virtual file server in the power-off target file server; and turns off the power-off target file server. | 2009-07-30 |
20090193273 | ELECTRONIC CONTROL SYSTEM WITH CONTROLLERS AND POWER SUPPLY UNIT - An electronic control unit has a primary microcomputer producing a supply control signal or a cutoff control signal, a secondary microcomputer, and a power supply unit receiving the signal from the primary microcomputer through a signal line. Each signal has a level changing with time. The supply unit detects a level change of the signal line as a line transmission signal and performs pattern judgment for the level pattern of the line transmission signal. When the level pattern of the line transmission signal matches with a registered pattern of one control signal, the supply unit starts supplying or cuts off electric power to the secondary microcomputer. In response to the level pattern of the line transmission signal different from a registered pattern of any control signal, the supply unit invalidates the level change of the signal line to continue the power supply or cutoff. | 2009-07-30 |
20090193274 | System And Method of Coherent Data Transfer During Processor Idle States - Systems and methods of managing power provide for placing a processor in a non-snoopable state, where the processor is associated with a system memory. One or more data transfers between a controller and the system memory can be serviced while the processor is in the non-snoopable state. In one embodiment, it is determined that the processor has flushed an internal cache of the processor to the system memory before placing the processor in the non-snoopable state. | 2009-07-30 |
20090193275 | Quick-Stop Feature For Multiple Output Power Systems - A quick-stop feature built into power systems enables deactivating the power output of output supplies in the shortest possible time. This feature prevents damage to the power system and to the electrical devices connected to the output supplies. The quick-stop feature can be implemented as a hardware or a software solution. A button on the front panel of the power system can initiate the quick-stop feature. Alternatively, the power system can be connected to a network to watch over and provide fault protection mechanisms. A processor within the power system can execute the quick-stop feature by deactivating the power output. Deactivating the power output can follow a programmed shutdown, a sequenced shutdown or a complete shutdown. Downprogrammers ensure deactivating the power output in the shortest time. | 2009-07-30 |
20090193276 | System and Method for Dynamic Utilization-Based Power Allocation in a Modular Information Handling System - Power from a modular chassis to plural modular information handling systems contained by the chassis is dynamically allocated according to power consumed at each modular information handling system and a priority associated with each modular information handling system. A power manager of the modular chassis allocates power by setting a maximum power for each modular information handling system based upon a priority for each modular information handling system. A power monitor on a modular information handling system requests additional power allocation if power consumed is within a predetermined amount of the maximum power for that system. The power manager allocates additional power in response to the request if another modular information handling system has excess power allocated or if the requesting modular information handling system has a higher priority than another modular information handling system. The requesting system's maximum power is increased and the other system maximum power is decreased so that the maximum power available from the chassis is not exceeded. | 2009-07-30 |
20090193277 | Battery Under-Voltage Protection - A battery includes a cell and a battery management unit coupled to the cell. The battery management unit is operable to determine whether a battery controller is operating when the cell is coupled to an information handling system that includes the battery controller. In response to determining that the battery controller is not operating, the battery management unit is operable to determine whether the cell comprises a battery voltage that is below a predetermined voltage level. | 2009-07-30 |
20090193278 | SYSTEM AND METHOD FOR PRESERVING PROCESSOR MEMORY DURING POWER LOSS - A method, and a system of using the method, of preserving memory of a processor powered by an external source. The method includes determining a drop in a first power to be supplied to the processor, generating a reset signal when the drop falls below a threshold, supplying a second power from a power store to the processor based on the reset signal, and holding the reset signal until the first power rises above the threshold. | 2009-07-30 |
20090193279 | METHOD FOR ENABLING MULTI-PROCESSOR SYNCHRONIZATION - A method for providing at least one sequence of values to a plurality of processors is described. In the method, a sequence generator from one or more sequence generators is associated with a memory location. The sequence generator is configured to generate the at least one sequence of values. One or more read accesses of the memory location are enabled by a processor from the plurality of processors. In response to enabling the read access, the sequence generator is executed so that it returns a first value from the sequence of values to the processor. After executing the sequence generator, the sequence generator is advanced so that the next access generates a second value from the sequence of values. The second value is sequentially subsequent to the first value. | 2009-07-30 |
20090193280 | Method and System for In-doubt Resolution in Transaction Processing - A method and system are provided for in-doubt resolution in transaction processing involving at least two distributed transaction processing systems. The method includes a resynchronization method when re-establishing a connection between two distributed transaction processing systems. The method includes re-establishing a connection between a first transaction processing system and a second transaction processing system following a failure; the first transaction processing system searching for any unresolved units of recovery and resynchronizing each unresolved unit of recovery with the second transaction processing system; and when the first transaction processing system has finished processing its unresolved units of recovery, the second transaction processing system then searches for any unresolved units of recovery and resynchronizes each unresolved unit of recovery with the first transaction processing system. | 2009-07-30 |
20090193281 | APPARATUS AND METHOD FOR IMPLEMENTING SPECULATIVE CLOCK GATING OF DIGITAL LOGIC CIRCUITS - A method for implementing speculative clock gating of digital logic circuits in a multiple stage pipeline design includes generating, in a first pipeline stage n, a valid control signal that is input to a first register in a second pipeline stage n+1, the valid control signal indicative of when an operation is qualified to be performed by the second pipeline stage n+1; and generating, in the first pipeline stage, a speculative valid control signal that is used to gate a clock signal to a plurality of additional registers in the second pipeline stage, wherein the speculative valid control signal is generated using only a subset of a total number of control inputs used in generating the valid control signal, and wherein the clock signal is sent directly, without gating, to the first register in the second pipeline stage. | 2009-07-30 |
20090193282 | Method for processing time values in a computer or programmable machine - Modern computers ( | 2009-07-30 |
20090193283 | DESIGN STRUCTURE FOR IMPLEMENTING SPECULATIVE CLOCK GATING OF DIGITAL LOGIC CIRCUITS - A design structure embodied in a machine readable medium used in a design process includes an apparatus for implementing speculative clock gating of digital logic circuits, including operation valid logic configured to generate, in a first pipeline stage n, a valid control signal that is input to a first register in a second pipeline stage n+1, the valid control signal indicative of when an operation is qualified to be performed by the second pipeline stage n+1; and speculative valid logic configured to generate, in the first pipeline stage, a speculative valid control signal that is used to gate a clock signal to a plurality of additional registers in the second pipeline stage, wherein the speculative valid control signal is generated using only a subset of a total number of control inputs used in generating the valid control signal, and wherein the clock signal is sent directly to the first register. | 2009-07-30 |
20090193284 | METHODS FOR SYNCHRONIZING APPLICATIVE CLOCK SIGNALS IN A SYNCHRONOUS COMMUNICATIONS NETWORK, CORRESPONDING EMITTER AND RECEIVER DEVICES, COMPUTER-READABLE STORAGE MEANS - A method for transmitting information is proposed, enabling a synchronization of applicative clocks signals between a transmission device and at least one reception device connected to a communications network. For each stream of a source application, the transmission device: writes to a buffer memory associated with the stream, at the rate of a source applicative clock, pieces of applicative data of the stream coming from the source application, transmits, via the network, pieces of applicative data of the stream at the rate of the network clock. For at least one stream of the source application, the transmission device performs the following steps upon detection of a clock adjustment event: determining a piece of time offset information between a starting instant of a current network cycle and an instant of writing one of the pieces of applicative data of the stream, called a reference piece of data, to the buffer memory associated with the stream; determining a piece of information on position of the reference piece of data from among the pieces of applicative data of this stream to be transmitted via the network during a determined network cycle; transmission on the communications network of the information on time offset and position during the same network cycle as the one in which the reference piece of data is transmitted. | 2009-07-30 |
20090193285 | Method for the data transfer between at least two clock domains - The invention describes a method for transferring data between a first clock domain having a first clock rate (CLK | 2009-07-30 |
20090193286 | Method and System for In-doubt Resolution in Transaction Processing - A method and system are provided for in-doubt resolution in transaction processing involving at least two distributed transaction processing systems. The method includes an initial exchange of information to establish an identifier for coordinating units of recovery in distributed transaction processing systems. The method includes a first transaction processing system creating a local unit of recovery and sending a request to a second transaction processing system to create a coordinating unit of recovery, the request including an identifier of the local unit of recovery. The second transaction processing system starts a coordinating unit of recovery and recording the identifier in association with the coordinating unit of recovery. In the event of a failure, one of the first and second transaction processing systems uses the identifier to locate the unit of recovery on the other of the first and second transaction processing systems to resynchronize the units of recovery. | 2009-07-30 |
20090193287 | Memory management method, medium, and apparatus based on access time in multi-core system - A memory management method and apparatus based on an access time in a multi-core system. In the memory management method of the multi-core system, it is easy to estimate the execution time of a task to be performed by a processing core and it is possible to secure the same memory access time when a task is migrated between processing cores by setting a memory allocation order according to distances from the processing cores to the memories in correspondence with the processing cores, translating a logical address to be processed by one of the processing cores according to the set memory allocation order into a physical address of one of the memories, and allocating a memory corresponding to the translated physical address to the processing core. | 2009-07-30 |
20090193288 | ROUTING TOKEN TRANSFER AND RECOVERY PROTOCOL IN RENDEZVOUS FEDERATION - Systems and methods that provide for assignment and recovery of tokens as part of a plurality of nodes and distributed application framework/network. The assignment component assigns numbers and tasks to candidates and facilitates multiple leader election. Moreover, a recovery component can recover a token for a node that leaves the network (e.g., crashes). Such recovery component ensures consistency, wherein only one server is assigned recovery of the token and associated tasks. | 2009-07-30 |
20090193289 | Reducing data loss and unavailability by integrating multiple levels of a storage hierarchy - A method for reducing data loss and unavailability by integrating multiple levels of a storage hierarchy is provided. The method includes receiving a read request. In addition, the method includes recognizing a data failure in response to the read request. The method further includes locating an alternate source of the data to be read in response to recognizing the data failure. The alternate source includes data cached at devices in the storage hierarchy, data in a backup system, and cumulative changes to the data since the last backup. Moreover, the method includes responding to the read request with data from the alternate source. | 2009-07-30 |
20090193290 | System and Method to Use Cache that is Embedded in a Memory Hub to Replace Failed Memory Cells in a Memory Subsystem - A memory system, data processing system, and method are provided for using cache that is embedded in a memory hub device to replace failed memory cells. A memory module comprises an integrated memory hub device. The memory hub device comprises an integrated memory device data interface that communicates with a set of memory devices coupled to the memory hub device and a cache integrated in the memory hub device. The memory hub device also comprises an integrated memory hub controller that controls the data that is read or written by the memory device data interface to the cache based on a determination whether one or more memory cells within the set of memory devices has failed. | 2009-07-30 |
20090193291 | Equipment controlling system and controlling method thereof - An equipment controlling system and a controlling method thereof are disclosed. The system includes a first controller connected to equipments of a first group to monitor and control operations of the equipments; and a second controller connected to equipments of a second group to monitor and control operations of the equipments; the first controller emergently controlling the equipments of the second group when the second controller malfunctions, and the second controller emergently controlling the equipments of the second group when the first controller malfunctions. When control problem of equipments such as indoor and outdoor unit due to malfunction of a controller is solved, a systemic and consistent control are enabled by consistently controlling the equipments so that control efficiency is enhanced and the equipments are kept in operating to provide a comfortable condition and an improved convenience to a user. | 2009-07-30 |
20090193292 | Methods And Computer Program Products For Defing Synchronous Replication Devices In A Subchannel Set Other Than Subchannel Set Zero - Exemplary embodiments of the present invention define PPRC devices within subchannel sets other than subchannel set zero. Further, for all PPRC paired n devices an additional N/2 PPRC primary device numbers and subchannels are provided within subchannel set zero by moving PPRC secondary devices to any subchannel set other than subchannel set zero. | 2009-07-30 |
20090193293 | Systems, Methods, and Media for Outputting Data Based Upon Anomaly Detection - Systems, methods, and media for outputting data based on anomaly detection are provided. In some embodiments, methods for outputting data based on anomaly detection include: receiving a known-good dataset; storing distinct n-grams from the known-good dataset to form a binary anomaly detection model; receiving known-good new n-grams; computing a rate of receipt of distinct n-grams in the new n-grams; determining whether further training of the anomaly detection model is necessary based on the rate of receipt on distinct n-grams; using the binary anomaly detection model to determine whether an input dataset contains an anomaly; and outputting the input dataset based on whether the input dataset contains an anomaly. | 2009-07-30 |
20090193294 | SYSTEM AND METHOD FOR VERIFYING OPERATION OF A TARGET SYSTEM - A system and method for verifying operation of a target system to be inspected. The system includes an abstract binary tree generation unit and a matching unit. The abstract binary tree generation unit obtains information about a functional specification of the target system and generates one or more binary trees that associate one or more states that can occur in the target system with respective nodes and that associate state transitions of objects constituting the target system and interactions between the objects with connection relationships between the nodes. The matching unit receives an event sequence in an application model of the target system obtained in response to the operation of the target system and matches the event sequence against the binary trees generated by the abstract binary tree generation unit. The method includes steps for accomplishing the functionality of the system. | 2009-07-30 |
20090193295 | VOLTAGE MARGIN TESTING FOR PROXIMITY COMMUNICATION - A method of testing a proximity communication system for voltage margin by impressing a voltage upon the data link between the transmitter on one chip and the receiver on the other chip coupled to the transmitter through a capacitively coupling circuit formed by juxtaposed capacitor pads on the respective two chips. The impressed voltage is varied and the output of the receiver is monitored to determine an operational voltage margin. The floating inputs on the receiver may be continuously biased by connecting them to variable biasing supply voltages through high impedances. When the floating inputs are periodically refreshed to a refresh voltage during a quiescent data period, the refresh voltage is varied between successive refresh cycles. The variable test voltage may be applied to transmitter output when it is in a high-impedance state, and the output of the receiver is measured. | 2009-07-30 |
20090193296 | Method and Apparatus for Testing a Full System Integrated Circuit Design by Statistical Fault Injection Using Hardware-Based Simulation - A test system tests a full system integrated circuit (IC) model that includes a device under test (DUT) IC model and a support IC model. A test manager information handling system (IHS) maps the full system IC model on a hardware accelerator simulator via an interface bus. The hardware accelerator simulator thus emulates the full system IC model. Of all possible fault injection points in the model, the test manager IHS selects a subset of those injection points for fault injection via a statistical sampling method in one embodiment. In response to commands from the test manager IHS, the simulator serially injects faults into the selected fault injection points. The test manager IHS stores results for respective fault injections at the selected injection points. If a machine checkstop or silent data corruption error occurs as a result of an injected fault, the DUT IC model may return to a stored checkpoint and resume operation from the stored checkpoint. The result information is useful in determining a soft error rate (SER) for the DUT IC. | 2009-07-30 |
20090193297 | Diagnostic context construction and comparison - A data processing system 1 has a processor core | 2009-07-30 |
20090193298 | SYSTEM AND METHOD OF FAULT DETECTION, DIAGNOSIS AND PREVENTION FOR COMPLEX COMPUTING SYSTEMS - A method is provided for diagnosing failures in an object-oriented software system. The method comprises collecting runtime diagnostic information; maintaining a record of the diagnostic information in a storage buffer; and dynamically updating the record of the diagnostic information to include a group of the diagnostic information collected over a most recent occurrence of a predetermined interval. The diagnostic information includes at least one set of call stack information for at least one currently running application and at least one set of other information. Each of the at least one set of other information is selected from a set of memory access information, a set of data access information, and a set of paging information for each currently executing process. | 2009-07-30 |
20090193299 | MEDICAL SUPPORT CONTROL SYSTEM - A medical support control device to which are connected a display manipulation device and a medical device control device connected to a medical device and controlling the medical device, comprising: a detection unit for detecting abnormality in an image signal line outputting an image signal to the display manipulation unit; and an interruption unit for interrupting communications to the medical device control device in accordance with the detection unit. | 2009-07-30 |
20090193300 | SYSTEM AND METHOD FOR PSEUDORANDOM PERMUTATION FOR INTERLEAVING IN WIRELESS COMMUNICATIONS - A system and method for pseudorandom permutation for interleaving in wireless communication is disclosed. In one embodiment, the method comprises receiving a first ordered sequence of communication symbols having a first order, permuting the first ordered sequence of communication symbols to generate a second ordered sequence of communication symbols having a second order, and outputting the second ordered sequence of communication symbols, wherein the second order is based, at least in part, on a third order having a greater size than the second order, the third order being a pseudorandom permutation defined by the input-output relationship | 2009-07-30 |
20090193301 | Semiconductor memory device and refresh period controlling method - Disclosed is a memory device including an error rate measurement circuit and a control circuit. The error rate measurement circuit, carrying a BIST circuit, reads out and writes data for an area for monitor bits every refresh period to detect an error rate (error count) with the refresh period. The control circuit performs control for elongating and shortening the refresh period so that a desired error rate will be achieved. The BIST circuit issues an internal command and an internal address and drives the DRAM from inside. The BIST circuit writes and reads out desired data, compares the monitor bits to expected values (error decision) and counts the errors. | 2009-07-30 |
20090193302 | SEMICONDUCRTOR DEVICE - A semiconductor device capable of reducing a memory area of a test circuit required for storing fail-information is provided. In the test circuit, for determining right/wrong of information obtained by memory access, specific fail-information among pieces of fail-information sequentially obtained in response to wrong-determination result is held in a first memory section; and differences in serial two pieces of fail-information sequentially continuing from the specific fail-information are held in a second memory section. The test circuit, when it obtains differences based on pieces of fail-information sequentially obtained with a wrong-determination result at the time of holding the specific fail-information as a base point, sequentially adds subsequent differences to the specific fail-information to decompress subsequent pieces of fail-information. | 2009-07-30 |
20090193303 | TEST ACCESS MECHANISM FOR MULTI-CORE PROCESSOR OR OTHER INTEGRATED CIRCUIT - A processor having a pipelined test access mechanism (TAM). The processor includes a plurality of processor cores. Each of the processor cores includes a scan chain including plurality of serially-coupled scan elements. The processor further includes the pipelined TAM, which includes a plurality of pipeline stages each corresponding to one of the plurality of processor cores. The pipelined TAM includes a command channel, a scan data input (SDI) channel, a scan data output (SDO) channel, and a compare channel. Each pipeline stage is operable to convey commands to its corresponding processor core via the command channel, to convey scan input data to its corresponding processor core via the SDI channel, to receive scan output data conveyed from the corresponding processor core to the SDO channel and the compare channel, and convey compare data downstream via the compare channel, wherein the compare data is based on the scan output data. | 2009-07-30 |
20090193304 | Apparatus and Method for Isolating Portions of a Scan Path of a System-on-Chip - The invention includes an apparatus and method for dynamically isolating a portion of a scan path of a system-on-chip. In one embodiment, an apparatus includes a scan path and control logic. The scan path includes at least a first hierarchical level, where the first hierarchical level includes a plurality of components, and a second hierarchical level having at least one component. The second hierarchical level is adapted for being selected and deselected such that the second hierarchical level is active or inactive. The control logic is adapted to filter application of at least one control signal to the at least one component of the second hierarchical level in a manner for controlling propagation of data within the second hierarchical level independent of propagation of data within the first hierarchical level. In one embodiment, when the second hierarchical level is deselected, the control logic prevents data from being propagated within the second hierarchical level while data is propagated within the first hierarchical level. In one embodiment, the second hierarchical level may be used for independent, parallel testing while data continues to be propagated through the first hierarchical level. | 2009-07-30 |
20090193305 | TEST MODE SOFT RESET CIRCUITRY AND METHODS - An integrated circuit chip having testing logic for testing circuitry of the integrated circuit chip is provided. The integrated circuit chip includes at least a scan-in pin, a scan clock pin, and a test controller. The test controller has test mode registers for storing a type of test mode to be executed, and the test controller accepting signals from the scan-in pin and the scan clock pin. The scan-in pin and the scan clock pin receiving a test program for the type of test mode and a soft-reset pattern. Also included is a state machine logic that is part of the integrated circuit chip. The state machine logic, during execution of the test program, being configured to direct sampling of a scan clock waveform provided through the scan clock pin as dictated by transitions of a scan-in waveform provided through the scan-in pin. The sampling by the state machine circuitry identifying a bit match from the sampled scan clock waveform upon executing the soft-reset pattern. The identified bit match triggering a soft reset by updating the test mode registers of the test controller. The soft reset therefore eliminates the need for an extra reset pin, when testing in scan mode. The communication channel defined through the use of the scan-in and scan clock pins can be used to trigger other soft actions. | 2009-07-30 |
20090193306 | APPARATUS AND METHOD FOR CONTROLLING DYNAMIC MODIFICATION OF A SCAN PATH - The invention includes an apparatuses and associated methods for controlling dynamic modification of a testing scan path using a control scan path. In one embodiment, an apparatus includes a testing scan path and a control scan path. The testing scan path includes testing components and at least one hierarchy-enabling component. In one embodiment, the control scan path includes at least one control component coupled to the at least one hierarchy-enabling component for controlling dynamic modification of the testing scan path. In one embodiment, the control scan path includes the at least one hierarchy-enabling component, wherein the at least one hierarchy-enabling component is adapted for dynamically modifying the testing scan path using the control scan path. The dynamic modification of the testing scan path may include modifying a hierarchy of the testing scan path, such as selecting or deselecting one or more hierarchical levels of the testing scan path. | 2009-07-30 |
20090193307 | Scan chain modification for reduced leakage - A leakage power control vector is loaded into existing test scan chain elements for application to circuit elements of a circuit in which the leakage currents are to be controlled. The vector is designed to configure the circuit elements into states in which leakage currents are reduced. A multiplexer selects the power control vector for loading into the scan chain elements, and a clock generator clocks the configuration vector into the scan chain elements. A sleep mode detector may be provided to configure the multiplexer to select the power control vector and to operate the clock generator to clock the power control vector into the scan chain elements when a sleep mode of the circuit is detected. | 2009-07-30 |
20090193308 | Method and an Apparatus for Controlling an Unreliable Data Transfer in a Data Channel - Controlling an unreliable data transfer in a data channel from a transmitting unit to a receiving unit. A bypass mode or a buffer mode is activated depending on the error rate in the data channel. If bypass mode is selected, data packets are directly transferred in probation from the transmitting unit to the receiving unit by a bypass line. The data packets are error checked after the data transfer. If buffer mode is selected, data is transfer from the transmitting unit to the receiving unit by a buffer line via an error detecting and correcting unit and a buffer unit. The errors are detected and corrected during the data transfer. | 2009-07-30 |
20090193309 | DEVICE AND METHOD FOR CORRECTING A DATA ERROR IN COMMUNICATION PATH - There are provided a transmission and reception device having a function for correcting a data error in a communication path. In the transmission device, a redundant bit addition unit adds a redundant bit to each data bit which has been divided by one bit by a division unit; and an interleaver performs interleave. The transmission device transmits a signal which has been subjected to FM modulation by an FM modulation unit. In the reception device, a symbol decision unit performs a symbol decision at a Nyquist point for a signal which has been FM-demodulated by an FM demodulation unit; a bit conversion unit performs bit conversion according to the result of symbol decision; and a frame recovery unit deletes the redundant bit added by the redundant bit addition unit of the transmission device, from the bit string de-interleaved by a de-interleaver. Thus, it is possible to surely perform an error correction with a simple configuration even when the communication state is not in a preferable environment. | 2009-07-30 |
20090193310 | Data Transfer Method - A data transfer method having a data retransmission function, in which a sending side saves data that was sent in memory, a receiving side uses a transmission confirmation signal to request the sending side to retransmit the data when the data was not properly received, then monitors the elapsed time, and when the data is not retransmitted after the elapsed time has exceeded a set time, uses a transmission confirmation signal again to request that the data be retransmitted, and where in response to that transmission confirmation signal, the sending side retransmits the saved data to the receiving side. | 2009-07-30 |
20090193311 | RETRANSMISSION OF ERRONEOUS DATA - A method for retransmission of erroneous data in a communications system includes receiving data blocks at a receiver that have been generated in a transmitter by the use of an error correcting code. The received data blocks are decoded by a linear programming algorithm. One or more symbols in the decoded data block are identified by subjecting the symbols in the decoded data block to an integrality criterion. A retransmission of a part of the data block based on the one or more identified symbols is then initiated. | 2009-07-30 |
20090193312 | FIXED-SPACING PARITY INSERTION FOR FEC (FORWARD ERROR CORRECTION) CODEWORDS - Fixed-spacing parity insertion for FEC (Forward Error Correction) codewords. Fixed spacing is employed to intersperse parity bits among information bits when generating a codeword. According to this fixed spacing, a same number of information bits is placed between each of the parity bits within the codeword. If desired, the order of the parity bits may be changed before they are placed into the codeword. Moreover, the order of the information bits may also be modified before they are placed into the codeword. The FEC encoding employed to generate the parity bits from the information bits can be any of a variety of codes include Reed-Solomon (RS) code, LDPC (Low Density Parity Check) code, turbo code, turbo trellis coded modulation (TTCM), or some other code providing FEC capabilities. | 2009-07-30 |
20090193313 | Method and apparatus for decoding concatenated code - Provided are apparatuses for decoding a concatenated code and methods for the same that may improve the decoding speed of a concatenated code based on a likelihood value with respect to output from a plurality of decoders. | 2009-07-30 |
20090193314 | FORWARD ERROR CORRECTION FOR BURST AND RANDOM PACKET LOSS FOR REAL-TIME MULTI-MEDIA COMMUNICATION - This invention relates generally to a packet recovery algorithm for real-time (live) multi-media communication over packet-switched networks, such as the Internet. Such multi-media communication includes video, audio, data or any combination thereof. More specifically, the invention comprises a forward error correction (FEC) algorithm that addresses both random and burst packet loss and errors, and that can be adjusted to tradeoff the recoverability of missing packets and the latency incurred. The transmitter calculates parity packets for the rows, columns and diagonals of a block of multi-media data packets using the exclusive or (XOR) operation and communicates the parity packets along with the multi-media data packets to the receiver. The receiver uses the parity packets to recover missing multi-media data packets in the block. The FEC algorithm is designed to be able to recover long bursts of consecutive missing data packets. If some parity packets are missing, they too can be recovered using an extra single parity packet, so that they can be used to recover other missing data packets. The invention applies to both one-way real-time streaming applications and two-way real-time interactive applications, and to both wired and wireless networks. The invention retains backwards compatibility with existing standards governing FEC for professional video over IP networks. | 2009-07-30 |
20090193315 | System for a Combined Error Correction Code and Cyclic Redundancy Check Code for a Memory Channel - A memory system is provided that performs error correction at a memory device level. The memory system comprises a memory hub device integrated in the memory module and a link interface integrated in the memory hub device that provides a communication pathway between the memory hub device and an external memory controller. The link interface comprises first error correction logic integrated in the link interface that performs error correction operations on first data that is received from the external memory controller via a first memory channel to be transmitted to a set of memory devices. The first error correction logic generates a first error signal to the external memory controller in response to the first error correction logic detecting a first error in the first data. Link interface control logic integrated in the link interface controls the transmission of the first data to the set of memory devices. | 2009-07-30 |
20090193316 | MEMORY SUBSYSTEMS WITH FAULT ISOLATION - An exemplary memory subsystem with fault isolation comprises a first data bus routing data groupings in a lower 72 bits to a first memory expander, and a second data bus routing data groupings in an upper 72 bits to a second memory expander. A first memory module receives all of the data groupings in the lower 72 bits of each memory expander. A second memory module receives all of the data groupings in the upper 72 bits of each memory expander. A failure in any one or more bytes in an ECC word indicate failures in the computer memory system. | 2009-07-30 |
20090193317 | METHOD AND SYSTEM FOR SIGNAL ERROR DETERMINATION AND CORRECTION IN A FLEXRAY COMMUNICATION SYSTEM - A signal error determination and correction system is provided which comprises an error correction value calculation means which processes a predetermined segment of a signal to calculate an error correction value, and a signal correction means and prediction which applies the error correction value to at least part of the signal to correct the part of the signal. The invention further provides a method of signal error determination and correction. | 2009-07-30 |
20090193318 | FORWARD ERROR CORRECTION AND INTERLEAVING OF NETWORK FRAMES - A network stream transmitter receives a transport stream having content packets and packets to be filtered out and is adapted to selectively encapsulate content packets into network frames. | 2009-07-30 |
20090193319 | DATA BUS SYSTEM, ITS ENCODER/DECODER AND ENCODING/DECODING METHOD - The present application relates to a data bus system, its encoder/decoder and encoding/decoding method. The data bus encoder comprises: a bus-invert encoder for generating encoded data and invert-indication information by performing bus-invert encoding on data according to a predetermined bus-invert encoding scheme; a virtual bit-group generator for converting the invert-indication information into a virtual bit-group according to a predetermined code mapping; and an error-checking-and-correction encoder for generating an error-checking-and-correction code for a virtual word according to a predetermined error-checking-and-correction encoding scheme, wherein the number of error-checking bits is more than the number of error-correction bits at least by one in the predetermined error-checking-and-correction encoding scheme, the mapping is such that the Hamming distance between any possible value of the virtual bit-group and a reference virtual bit-group which cannot be converted into under the mapping is a fixed value, and not greater than the number of error-correction bits of the error-checking-and-correction encoding scheme, and the virtual word includes the data to be output, the virtual bit-group corresponding to the data, and at least one padding bit of a fixed value, which is configured as required by the error-checking-and-correction encoding scheme. | 2009-07-30 |
20090193320 | APPARATUS, AND ASSOCIATED METHOD, FOR DECODING CONVOLUTIONALLY ENCODED DATA - An apparatus, and an associated method, for correcting errors in decoded data, decoded by a convolutional decoder, such as an SOVA (Soft Output Viterbi Algorithm). A CRC check is performed upon the decoded data. If the CRC check fails, a conclusion is made that the decoded data contains errors. Portions of the decoded data indicated to exhibit low levels of reliability are toggled with values of most-likely error events. A corrected sequence of the decoded data is formed that corrects for the errors in the decoded data. | 2009-07-30 |
20090193321 | VITERBI DECODER AND VITERBI DECODING METHOD - A Viterbi decoder and a Viterbi decoding method are provided for simplifying hardware and increasing an operation speed by using a decision feedback unit selecting one of at least two levels based on at least one survivor symbol fed back from a path memory unit. The Viterbi decoder includes a path memory unit (PMU) storing a survivor path, a decision feedback unit (DFU) selecting one of at least two levels based on at least one survivor symbol fed back from the PMU, a branch metric calculation unit (BMCU) calculating a branch metric by using the level selected by the DFU and the received symbol, and an add-compare-selection unit (ACSU) deciding the survivor path by using the branch metric calculated by the BMCU and a previously stored state metric and transmitting the decided survivor path to the PMU. | 2009-07-30 |
20090193322 | INFORMATION PROCESSING APPARATUS INCLUDING TRANSFER DEVICE FOR TRANSFERRING DATA - According to an aspect of an embodiment, an apparatus has a first storage, a read write unit for reading and writing data from/into the first storage, a first error detector for detecting an error of data read out from the first storage, an address storage for storing an address of the first storage, a determining unit for determining whether an address of the first storage in which data to be written is matched with the error detected address, a second storage for storing data to be written into the first storage when the address of the first storage in which the data to be written is matched with the error detected address, a second error detector for detecting an error of data read out from the second storage and a selector for outputting one of the data stored in the first storage or the second storage. | 2009-07-30 |
20090193323 | APPARATUS AND METHOD FOR DECODING IN MOBILE COMMUNICATION SYSTEM - Provided are an apparatus and a method for improving the performance of a decoder by improving a decoding speed when correcting an error of a control signal in Long Term Evolution (LTE). The apparatus includes an error determination unit for performing a traceback operation on a received signal, and simultaneously determining if an error has been generated to the received signal. | 2009-07-30 |
20090193324 | IMAGE DATA TEST UNIT, IMAGE APPARATUS HAVING THE SAME, AND METHOD OF TESTING IMAGE DATA USING THE SAME - An image data test unit includes a data acquisition unit configured to acquire image data having individual frames, an image data temporary storage unit configured to receive the acquired image data from the data acquisition unit to store a certain amount of the image data, and a test calculation unit configured to sequentially receive the image data from the image data temporary storage unit to store a certain amount of the image data, and compare the stored image data with pre-set test elements. In addition, an image apparatus having the image data test unit and a method of testing image data using the image data test unit are also provided. | 2009-07-30 |