31st week of 2015 patent applcation highlights part 53 |
Patent application number | Title | Published |
20150213782 | TOUCH ELECTRONIC DEVICE AND DATA TRANSMISSION METHOD - The present invention provides a touch electronic device and a data transmission method including a touch panel, a touch link module, a wireless transmission module and a control module. The touch link module is utilized to establish a first communication channel with at least one first touch electronic device through the touch panel, and receive at least one information from the at least one first touch electronic device through the first communication channel. The wireless transmission module is utilized to establish a second communication channel. The control module is utilized to receive the at least one information from the touch link module, divide an initial data into a plurality of sub-data according to the at least one information, and determine to transmit which sub-data of the plurality of sub-data to the at least one first touch electronic device through the first communication channel or the second communication channel. | 2015-07-30 |
20150213783 | TOUCH ELECTRONIC DEVICE AND TOUCH LINK METHOD - The present invention provides a touch electronic device and a touch link method. The touch electronic device includes a touch panel and a touch connection module. The touch connection module includes a sensing module and a connection module. The sensing module is utilized to detect a physical adjacency between the touch electronic device and a plurality of first touch electronic devices. The connection module is utilized to develop a touch link between the touch electronic device and the plurality of first touch electronic devices through the touch panel when the sensing module detects the physical adjacency. The touch electronic device and the touch link method of the preset invention could be utilized to easily develop the touch link among at least two electronic devices for data transmission. | 2015-07-30 |
20150213784 | MOTION-BASED LENTICULAR IMAGE DISPLAY - The display of images, such as lenticular images, in a limited display space can be aided through the use of motion-based control, whereby a user can rotate and/or translate a computing device in order to cause different views of a lenticular image to be displayed. Sensors can be used to determine the motion in order to select the appropriate view to display. Approaches can further assist the user in creating lenticular images. The user can specify various configurations in which to display different views in a lenticular. If the user is capturing the images, one or more previously-acquired images can be used as a guide to help the user to align the images. Various processing can be performed to cause the individual views of the lenticular to match as closely as possible in factors such as alignment, brightness, and color range, among other such options. | 2015-07-30 |
20150213785 | MAP DISPLAY DEVICE AND MAP DISPLAY SYSTEM - A map display device includes: a processor that defines a coordinate system on a map including element polygons showing constituent elements of an urban map; a processor that sets coordinates located inside the element polygons as inner coordinates and sets coordinates located outside the element polygons as outer coordinates; a processor that calculates, for each coordinate in the coordinate system, a moving average value; a processor that resets each of the outer coordinates which has the moving average value larger than a predetermined value as the inner coordinate; a processor that sets, as an urban polygon, a polygon along an outer periphery of a region formed of an aggregate of the set and reset inner coordinates; and a processor that enables the urban map to be displayed when a current location is present inside the urban polygon. | 2015-07-30 |
20150213786 | METHOD FOR CHANGING A RESOLUTION OF AN IMAGE SHOWN ON A DISPLAY - Provided is a method for changing a resolution of an image shown on a display. The method, in one embodiment, includes, providing an image on a display, and detecting a relative distance of an object to the display. The method, in this embodiment, further includes changing a resolution of the image as the relative distance changes. | 2015-07-30 |
20150213787 | DISPLAY CONTROLLER AND DISPLAY SYSTEM INCLUDING THE SAME - A display controller includes a scaler which is configured to receive a frame image, scale up the frame image to generate a high resolution frame image based on a quality of the frame image and information about a display device, and output the frame image or the high resolution frame image to the display device for display. A method of controlling image display includes: receiving a frame image; determining whether to scale up the frame image to generate a high resolution frame image based on a quality of the frame image and information about a display device; scaling up the frame image according to a result of the determining; and outputting the frame image or the high resolution frame image for display at the display device. | 2015-07-30 |
20150213788 | Guitar Bridge Pin Anchor - An apparatus for securing one end of a guitar string to a guitar is disclosed. The apparatus includes a mount adapted to be secured to and extend upwardly from the bridge of the guitar. The apparatus also can include a string holder connected to the mount, the string holder comprising an anchor portion for securely holding the end of the guitar string, the string holder having a first end portion and a second end portion, the first end portion positioning the guitar string below a saddle height of the bridge, and a position adjuster operatively connected to the mount and the string holder, the position adjuster adjusting the pivot angle of the string holder to adjust tension on the guitar string. | 2015-07-30 |
20150213789 | SYSTEMS AND METHODS FOR MUSICAL SONIFICATION AND VISUALIZATION OF DATA - The current disclosure is directed to systems and methods for automatically converting multi-dimensional, complex data sets to musical symbols while representing the converted data in an animated graph. The system groups the data into a number of subsets of data according to a set of user-configured rules and maps the grouped data points to musical notes according to configurable mapping parameters. | 2015-07-30 |
20150213790 | DEVICE AND METHOD FOR PROCESSING AUDIO SIGNAL - The present invention relates to a method for encoding audio signals of at least two channels, according to the present invention, comprises the steps of: receiving a first audio signal and a second audio signal; obtaining a correlation between the first audio signal and the second audio signal; determining whether the correlation is equal to or greater than a reference value; calculating a first gain value and a second gain value by using the first audio signal and the second audio signal if the determination result is true; and generating a first transmission audio signal and a second transmission audio signal by using the first audio signal, the second audio signal, the first gain value and the second gain value, wherein the first transmission audio signal and the second transmission audio signal are encoded by using a perceptual coding technique. | 2015-07-30 |
20150213791 | OSCILLATORS FOR WIRELESS POWER TRANSFER - A signal generator generates an electrical signal that is sent to an amplifier, which increases the power of the signal using power from a power source. The amplified signal is fed to a sender transducer to generate ultrasonic waves that can be focused and sent to a receiver. The receiver transducer converts the ultrasonic waves back into electrical energy and stores it in an energy storage device, such as a battery, or uses the electrical energy to power a device. In this way, a device can be remotely charged or powered without having to be tethered to an electrical outlet. | 2015-07-30 |
20150213792 | SUB-APERTURES FOR WIRELESS POWER TRANSFER - A signal generator generates an electrical signal that is sent to an amplifier, which increases the power of the signal using power from a power source. The amplified signal is fed to a sender transducer to generate ultrasonic waves that can be focused and sent to a receiver. The receiver transducer converts the ultrasonic waves back into electrical energy and stores it in an energy storage device, such as a battery, or uses the electrical energy to power a device. In this way, a device can be remotely charged or powered without having to be tethered to an electrical outlet. | 2015-07-30 |
20150213793 | METHODS AND SYSTEMS FOR CONVERTING TEXT TO VIDEO - The present application is directed at the conversion of text to visual speech, and in particular its application to the provision of educational, instructional or technical information. The technique uses a library of pre-recorded video. The pre-recorded video contains spoken words and phrases. A desired piece of text is provided as an input and a video is assembled from the pre-recorded video by identifying appropriate video segments from the input text. | 2015-07-30 |
20150213794 | SYSTEM AND METHOD FOR SPEECH PERSONALIZATION BY NEED - Disclosed herein are systems, computer-implemented methods, and tangible computer-readable storage media for speaker recognition personalization. The method recognizes speech received from a speaker interacting with a speech interface using a set of allocated resources, the set of allocated resources including bandwidth, processor time, memory, and storage. The method records metrics associated with the recognized speech, and after recording the metrics, modifies at least one of the allocated resources in the set of allocated resources commensurate with the recorded metrics. The method recognizes additional speech from the speaker using the modified set of allocated resources. Metrics can include a speech recognition confidence score, processing speed, dialog behavior, requests for repeats, negative responses to confirmations, and task completions. The method can further store a speaker personalization profile having information for the modified set of allocated resources and recognize speech associated with the speaker based on the speaker personalization profile. | 2015-07-30 |
20150213795 | Automated Learning For Speech-Based Applications - Systems and methods for modifying a computer-based speech recognition system. A speech utterance is processed with the computer-based speech recognition system using a set of internal representations, which may comprise parameters for recognizing speech in a speech utterance, such as parameters of an acoustic model and/or a language model. The computer-based speech recognition system may perform a first task in response to the processed speech utterance. The utterance may also be provided to a human who performs a second task based on the utterance. Data indicative of the first task, performed by the computer system, is compared to data indicative of a second task, performed by the human in response to the speech utterance. Based on the comparison, the set of internal representations may be updated or modified to improve the speech recognition performance and capabilities of the speech recognition system. | 2015-07-30 |
20150213796 | ADJUSTING SPEECH RECOGNITION USING CONTEXTUAL INFORMATION - An embodiment provides a method, including: obtaining, using a processor, contextual information relating to an information handling device; adjusting, using a processor, an automated speech recognition engine using the contextual information; receiving, at an audio receiver of the information handling device, user speech input; and providing, using a processor, recognized speech based on the user speech input received and the contextual information adjustment to the automated speech recognition engine. Other aspects are described and claimed. | 2015-07-30 |
20150213797 | Voice Recognition System And Method - The present invention discloses a voice recognition system and method, wherein the voice recognition system comprises: a microphone array for receiving a voice signal, converting the voice signal into an analog audio signal, and outputting the analog audio signal to an audio coding circuit; the audio coding circuit for converting the received analog audio signal into a digital audio signal, and outputting the digital audio signal to a main control integrated circuit; a Bluetooth transmitting module for receiving a voice signal, converting the voice signal into a digital audio signal, and sending the digital audio signal to a Bluetooth receiving module via Bluetooth; the Bluetooth receiving module for sending the received digital audio signal to the main control integrated circuit; the main control integrated circuit for selecting the digital audio signal from the audio coding circuit or the digital audio signal from the Bluetooth receiving module to perform recognition. The technical solution of the present invention solve the problem of the incapability of a voice recognition system, with audio input being from only a microphone array, in recognizing a long-distance voice. | 2015-07-30 |
20150213798 | Method and Apparatus for Evaluating Voice Quality - A method for evaluating voice quality includes performing human auditory modeling processing on a voice signal to obtain a first signal; performing variable resolution time-frequency analysis on the first signal to obtain a second signal; and performing, based on the second signal, feature extraction and analysis to obtain a voice quality evaluation result of the voice signal. According to the foregoing technical solutions, a problem that accuracy of a voice quality evaluation is not high can be solved. A voice quality evaluation result with relatively high accuracy is finally obtained by performing human auditory modeling processing, then converting a to-be-detected signal into a multi-resolution signal, further analyzing the time-frequency signal of variable resolution, extracting a feature corresponding to the signal, and performing further analysis. | 2015-07-30 |
20150213799 | DISPLAY APPARATUS FOR PERFORMING VOICE CONTROL AND VOICE CONTROLLING METHOD THEREOF - A display apparatus and a voice controlling method thereof are provided. The voice controlling method includes receiving a voice of a user; converting the voice into text; and sequentially changing and applying a plurality of different determination criteria to the text until a control operation corresponding to the text is determined; and performing the determined control operation to control the display apparatus | 2015-07-30 |
20150213800 | METHODS FOR ADAPTIVE VOICE INTERACTION - A method for adaptive voice interaction includes monitoring voice communications between a service recipient and a service representative, measuring a set of features based upon the voice communications, and analyzing the set of features to generate emotion metric values. | 2015-07-30 |
20150213801 | MESSAGE-TRIGGERED VOICE COMMAND INTERFACE IN PORTABLE ELECTRONIC DEVICES - The embodiments provided herein are directed to a system and method of message-triggered voice command interface in portable electronic devices. The voice command interface is normally not activated until a message (e.g., an e-mail, a text message, or a voice mail) has been received by a portable electronic device. The arriving of a message is used to trigger the voice command interface by activating one or more speech recognition routines in a predetermined time period corresponding to the one or more speech recognition routines. The voice command interface come to an end when the predetermined time period expires or the user has no further commands. | 2015-07-30 |
20150213802 | IMAGE DISPLAY APPARATUS AND METHOD OF CONTROLLING THE SAME - Provided are an image display apparatus and a method of controlling the same. The image display apparatus enabling voice recognition includes: a first voice inputter which receives a user-side audio signal; an audio outputter which outputs an audio signal processed by the image display apparatus; a first voice recognizer which recognizes the user-side audio signal received through the first voice inputter; and a controller which decreases a volume of the audio signal output through the audio outputter to a predetermined level if a voice recognition start command is received. | 2015-07-30 |
20150213803 | TRANSITIONING OF AMBIENT HIGHER-ORDER AMBISONIC COEFFICIENTS - In general, techniques are described for transitioning an ambient higher order ambisonic coefficient. A device comprising a memory and a processor may be configured to perform the techniques. The processor may obtain, from a frame of a bitstream of encoded audio data, a bit indicative of a reduced vector. The reduced vector may represent, at least in part, a spatial component of a sound field. The processor may also obtain, from the frame, a bit indicative of a transition of an ambient higher-order ambisonic coefficient. The ambient higher-order ambisonic coefficient may represent, at least in part, an ambient component of the sound field. The reduced vector may include a vector element associated with the ambient higher-order ambisonic coefficient in transition. The memory may be configured to store the frame of the bitstream. | 2015-07-30 |
20150213804 | BITSTREAM SYNTAX FOR MULTI-PROCESS AUDIO DECODING - An audio decoder provides a combination of decoding components including components implementing base band decoding, spectral peak decoding, frequency extension decoding and channel extension decoding techniques. The audio decoder decodes a compressed bitstream structured by a bitstream syntax scheme to permit the various decoding components to extract the appropriate parameters for their respective decoding technique. | 2015-07-30 |
20150213805 | INDICATING FRAME PARAMETER REUSABILITY FOR CODING VECTORS - In general, techniques are described for indicating frame parameter reusability for decoding vectors. A device comprising a processor and a memory may perform the techniques. The processor may be configured to obtain a bitstream comprising a vector representative of an orthogonal spatial axis in a spherical harmonics domain. The bitstream may further comprise an indicator for whether to reuse, from a previous frame, at least one syntax element indicative of information used when compressing the vector. The memory may be configured to store the bitstream. | 2015-07-30 |
20150213806 | ENCODER, DECODER AND METHODS FOR BACKWARD COMPATIBLE MULTI-RESOLUTION SPATIAL-AUDIO-OBJECT-CODING - A decoder for generating an un-mixed audio signal including a plurality of un-mixed audio channels is provided. Moreover, an encoder and an encoded audio signal is provided. The decoder includes an un-mixing-information determiner for determining un-mixing information by receiving first parametric side information and second parametric side information on the at least one audio object signal, wherein the frequency resolution of the second parametric side information is higher than that of the first parametric side information. Moreover, the decoder includes an un-mix module for applying the un-mixing information on a downmix signal, to obtain an un-mixed audio signal including the plurality of un-mixed audio channels. The un-mixing-information determiner is configured to determine the un-mixing information by modifying the first parametric information and the second parametric information, such that the modified parametric information has a frequency resolution which is higher than the first frequency resolution. | 2015-07-30 |
20150213807 | AUDIO ENCODING AND DECODING - An audio encoder comprises a multi-channel receiver which receives an M-channel audio signal where M>2. A down-mix processor down-mixes the M-channel audio signal to a first stereo signal and associated parametric data and a spatial processor modifies the first stereo signal to generate a second stereo signal in response to the associated parametric data and spatial parameter data for a binaural perceptual transfer function, such as a Head Related Transfer Function (HRTF). The second stereo signal is a binaural signal and may specifically be a (3D) virtual spatial signal. An output data stream comprising the encoded data and the associated parametric data is generated by an encode processor and an output processor. The HRTF processing may allow the generation of a (3D) virtual spatial signal by conventional stereo decoders. A multi-channel decoder may reverse the process of the spatial processor to generate an improved quality multi-channel signal. | 2015-07-30 |
20150213808 | APPARATUS AND METHOD FOR EFFICIENT SYNTHESIS OF SINUSOIDS AND SWEEPS BY EMPLOYING SPECTRAL PATTERNS - An apparatus for generating an audio output signal based on an encoded audio signal spectrum is provided. The apparatus has a processing unit for processing the encoded audio signal spectrum to obtain a decoded audio signal spectrum having a plurality of spectral coefficients, wherein each of the spectral coefficients has a spectral location within the encoded audio signal spectrum and a spectral value. Moreover, the apparatus has a pseudo coefficients determiner for determining one or more pseudo coefficients. Furthermore, the apparatus has a replacement unit for replacing at least one or more pseudo coefficients by a determined spectral pattern to obtain a modified audio signal spectrum, wherein each of at least two pattern coefficients has a spectral value. Moreover, the apparatus has a spectrum-time-conversion unit for converting the modified audio signal spectrum to a time-domain. | 2015-07-30 |
20150213809 | CODING INDEPENDENT FRAMES OF AMBIENT HIGHER-ORDER AMBISONIC COEFFICIENTS - In general, techniques are described for coding an ambient higher order ambisonic coefficient. An audio decoding device comprising a memory and a processor may perform the techniques. The memory may store a first frame of a bitstream and a second frame of the bitstream. The processor may obtain, from the first frame, one or more bits indicative of whether the first frame is an independent frame that includes additional reference information to enable the first frame to be decoded without reference to the second frame. The processor may further obtain, in response to the one or more bits indicating that the first frame is not an independent frame, prediction information for first channel side information data of a transport channel. The prediction information may be used to decode the first channel side information data of the transport channel with reference to second channel side information data of the transport channel. | 2015-07-30 |
20150213810 | APPARATUS FOR ENCODING A SPEECH SIGNAL EMPLOYING ACELP IN THE AUTOCORRELATION DOMAIN - An apparatus for encoding a speech signal by determining a codebook vector of a speech coding algorithm is provided. The apparatus includes a matrix determiner for determining an autocorrelation matrix R, and a codebook vector determiner for determining the codebook vector depending on the autocorrelation matrix R. The matrix determiner is configured to determine the autocorrelation matrix R by determining vector coefficients of a vector r, wherein the autocorrelation matrix R includes a plurality of rows and a plurality of columns, wherein the vector r indicates one of the columns or one of the rows of the autocorrelation matrix R, wherein R(i, j)=r(|i−j|), wherein R(i, j) indicates the coefficients of the autocorrelation matrix R, wherein i is a first index indicating one of a plurality of rows of the autocorrelation matrix R, and wherein j is a second index indicating one of the plurality of columns of the autocorrelation matrix R. | 2015-07-30 |
20150213811 | NOISE-REDUCING DIRECTIONAL MICROPHONE ARRAY - In one embodiment, a directional microphone array having (at least) two microphones mounted on opposite sides of a device generates forward and backward base signals from two (e.g., omnidirectional) microphone signals using diffraction filters and equalization filters. Each diffraction filter implements a (possibly different) transfer function representing the response of an audio signal traveling from a corresponding microphone around the device to the other microphone. A scale factor is applied to, for example, the backward base signal, and the resulting scaled backward base signal is combined with (e.g., subtracted from) the forward base signal to generate a first-order differential audio signal. After low-pass filtering, spatial noise suppression can be applied to the first-order differential audio signal. Microphone arrays having one (or more) additional microphones can be designed to generate second- (or higher-) order differential audio signals. | 2015-07-30 |
20150213812 | COMMUNICATION DEVICE - A communication device includes a memory, and a processor coupled to the memory, configured to extract a component of a voice signal that is input, detect a speech rate of the voice signal, adjust the extracted component, based on the detected speech rate, and add the adjusted component to the voice signal to expand a band of the voice signal. | 2015-07-30 |
20150213813 | PREAMPLIFIER FOR ADJUSTABLE WRITE CURRENT - The implementations disclosed herein provide for a storage device including a preamplifier that dynamically adjusts at least one of a rise time and fall time of an analog write current pulse based on a length of a corresponding write transition and/or characteristics of a media location where the write transition is to be recorded. | 2015-07-30 |
20150213814 | PARTIAL MAIN POLE LAMINATION FOR POLE ERASURE IMPROVEMENT - The embodiments of the present invention relate to a magnetic write head and a method for forming the magnetic write head. The magnetic write head includes a partially laminated main pole that has a magnetic layer that is recessed from a media facing surface, a nonmagnetic spacer layer disposed on and adjacent to the magnetic layer and a laminated stack disposed on at least a portion of the nonmagnetic layer. The nonmagnetic spacer layer has a first end at the media facing surface and a second end at a distance from the media facing surface and the laminated stack has a first end at the media facing surface and as second end at a distance from the media facing surface. | 2015-07-30 |
20150213815 | SYNTHETIC ANTIFERROMAGNETIC READER - Implementations disclosed herein provide for an apparatus, comprising a synthetic antiferromagnetic reader structure, wherein total moment of a pinned layer is substantially greater than total moment of a reference layer. In one implementation, the pinning strength of the pinned layer is substantially reduced. | 2015-07-30 |
20150213816 | DUAL CAPPING LAYER UTILIZED IN A MAGNETORESISTIVE EFFECT SENSOR - The present disclosure generally relates to a read head sensor in a magnetic recording head. The read head sensor comprises a dual capping layer in a sensor stack that may reduce magnetic coupling so as to enhance magnetic bias field, e.g., domain control, in the read head sensor. Furthermore, an upper shield with multiple film stack having different film properties may also be utilized to enhance bias field generated to the read head sensor. Additionally, a coil structure may be positioned adjacent to a side shield to enhance bias field generation in the read head sensor. | 2015-07-30 |
20150213817 | HEATER TO KEEP READER HEAD IN STABLE TEMPERATURE RANGE - Technologies are described herein for utilizing a head heater to test temperature stability of a head of a storage device and to prevent the head from operating in an unstable temperature condition. A temperature condition of a read/write head in a storage device is ascertained and it is determined whether the temperature condition is within a predetermined range of temperature conditions in which the read/write head exhibits instability. If the temperature condition of the read/write head is within the predetermined range, a power level of a head heater of the read/write head is adjusted to change the temperature condition of the read/write head to be outside of the predetermined range. | 2015-07-30 |
20150213818 | Dual Stage Microactuator Flexure Feature For Minimizing Electrical Shorts - Approaches to a flexure gimbal assembly for a hard-disk drive (HDD), having a feature for reducing the risk of electrical shorts, include a flexure having an electrically conductive layer and an insulating layer having a flexure tongue with which one or more microactuator piezo actuating device is coupled, where the flexure tongue comprises a gap positioned to inhibit contact between the conductive adhesive and the conductive layer of the flexure which may otherwise cause an electrical short. | 2015-07-30 |
20150213819 | LASER MOUNTED ON EDGE - An apparatus that includes a slider having a mounting surface, the mounting surface opposite a media-facing surface of the slider. The apparatus includes a laser diode mounted on a side surface to the mounting surface. The laser diode has an active region of the laser diode is disposed substantially perpendicular to the mounting surface. | 2015-07-30 |
20150213820 | MAGNETIC RECORDING HEAD HAVING THERMAL FLY HEIGHT CONTROL ELEMENT WITH NEAR ZERO MAGNETOMOTIVE FORCE - A magnetic recording head with thermal fly height control, wherein the heating element is configured to eliminate magnetic field effects on the writing pole, which would cause otherwise cause non-symmetric writing or pole erasure. Non-symmetric writing is a phenomenon wherein magnetic writing favors one direction over another, thereby causing a timing shift in recorded data. The pole erasure is a phenomenon wherein the erasure would occur even without write current. The heating element can be formed as a plurality of electrically conductive layers separated by a non-magnetic, electrically insulating layer such as alumina. The electrically conductive layers are configured so that current flows in opposite directions through each of the electrically conductive layers such that any magnetic field generated by the current flow through one electrically conductive layer is cancelled out by a magnetic field from another electrically conductive layer. | 2015-07-30 |
20150213821 | PERPENDICULAR MAGNETIC RECORDING MEDIUM - A perpendicular magnetic recording medium includes a non-magnetic substrate; and a magnetic recording layer that includes magnetic crystal grains and a non-magnetic crystal grain boundary that surrounds the magnetic crystal grains, wherein the magnetic crystal grains contain an ordered alloy and the non-magnetic crystal grain boundary contains Ge oxides. The magnetic recording layer may have a granular structure. The magnetic crystal grains may be micronized to be sufficiently ordered and separated, and the perpendicular magnetic recording medium may have a high magnetic anisotropy constant Ku and high coercivity Hc. | 2015-07-30 |
20150213822 | Fe-Pt Based Magnetic Material Sintered Compact - Provided is an Fe—Pt based magnetic material sintered compact, comprising BN and SiO | 2015-07-30 |
20150213823 | MAGNETIC RECORDING MEDIUM - A perpendicular magnetic recording medium includes a non-magnetic substrate; an underlayer including first and second underlayers; and a magnetic recording layer including a layer having a granular structure including grains of a magnetic crystal and grain boundary portions, wherein the first underlayer has a NaCl structure with a (001) orientation and contains a nitride or an oxide of at least one element. The first underlayer may contain a nitride of at least one of Cr, V, Ti, Sc, Mo, Nb, Zr, Y, Al, and B, and the second underlayer may include a plurality of island-shaped regions and contain at least one of Mg, Ca, Co, and Ni. The first underlayer may contains an oxide of at least one of Mg, Ca, Co, and Ni, and the second underlayer may include net-shaped regions and contain at least one of Cr, V, Ti, Sc, Mo, Nb, Zr, Y, Al, B, and C. | 2015-07-30 |
20150213824 | STORAGE MEDIUM FOR STORING DATA AND SERVO INFORMATION - A storage medium including a servo layer, a data recording layer, a heat sink layer, and a diamond-like carbon layer with a lubricant covering. The servo layer is configured to store servo information on the storage medium. The servo information is used to position a read/write head over the storage medium during a read/write operation performed by the read/write head on the storage medium. The data recording layer is configured to store data on the storage medium during the read/write operation performed by the read/write head on the storage medium. The heat sink layer is disposed between the servo layer and the data recording layer. The diamond-like carbon layer with the lubricant covering is disposed above the data recording layer. | 2015-07-30 |
20150213825 | MAGNETIC RECORDING MEDIUM FOR HEAT-ASSISTED RECORDING SYSTEM AND METHOD FOR MANUFACTURING SAME - The magnetic recording medium for a heat-assisted recording system has a magnetic recording layer on a non-magnetic substrate and a protective layer on top of the magnetic recording layer. The protective layer includes a first lower protective layer on top of the magnetic recording layer, a first upper protective layer on the first lower protective layer, and a second protective layer on the first upper protective layer. The first lower protective layer is composed mainly of an element selected from the group consisting of Si, Al and Cu, and the first upper protective layer is a layer configured by an oxide of the material of the first lower protective layer. | 2015-07-30 |
20150213826 | MAGNETIC-DISK GLASS SUBSTRATE AND MAGNETIC DISK - A magnetic-disk glass substrate of the present invention has an average value of squares of inclinations of 0.0025 or less and a frequency at which squares of inclinations are 0.004 or more of 15% or less, in a case where samples of inclinations on a main surface are obtained at intervals of 10 nm. | 2015-07-30 |
20150213827 | INCREASED SPECTRAL EFFICIENCY AND REDUCED SYNCHRONIZATION DELAY WITH BUNDLED TRANSMISSIONS - Techniques are provided for increasing spectral efficiency over data channels in a storage or communication system. In some embodiments, data may be encoded and transmitted over multiple channels. The transmitted data from the multiple channels may be considered together as a channel bundle, thereby increasing the edge transitions of the group of signals to improve clock recovery and reduce coding constraints. In some embodiments, the channel bit size is reduced to maximize data rates based on the reduced coding constraints. Furthermore, the channel bundle has only one channel with timing markers, so that a receiver may receive information from the channel bundle and recover clocking based on the timing markers in the one channel. | 2015-07-30 |
20150213828 | OPTICAL DISK INSPECTION METHOD AND OPTICAL DISK LIBRARY DEVICE - An optical disk library device includes an optical disk storage unit that stores a plurality of optical disks, a plurality of record and reproduction units that record and reproduce data with respect to the optical disk, a. transporting mechanism that transports the optical disk between the optical disk storage unit and record and reproduction unit, a library control unit that controls the optical disk library device, and an interface that transmits data and commands to and receives data and commands from a higher device, in which the library control unit controls a record and reproduction unit so as to inspect a predetermined inspection area of an optical disk on which data is recorded based on data recording conditions, and stores an acquisition value obtained by the inspection. | 2015-07-30 |
20150213829 | DISK-SHAPED INFORMATION RECORDING MEDIUM, DISK CARTRIDGE AND INFORMATION RECORDING AND REPRODUCING APPARATUS - An information recording medium of the present exemplified embodiment is configured by laminating a substrate having a predetermined thickness and a substrate having a predetermined thickness to each other. A film forming region including a recording region, a clamp region and a rib are formed on one surface of the information recording medium. A film forming region including a recording region, a clamp region and a rib are formed on the other surface of the information recording medium. On both surfaces, the components are formed in the order of the rib, the clamp region and the film forming region toward an outer peripheral side from an inner peripheral side. | 2015-07-30 |
20150213830 | SPINDLE MOTOR AND HARD DISK DRIVE INCLUDING THE SAME - There is provided a spindle motor including: a shaft having a lower end portion fixed to a lower thrust member and having a flange part disposed at an upper end portion thereof; a rotating member rotating around the shaft and including a sleeve part disposed between the lower thrust member and the flange part; a sealing member fixed to an outer peripheral surface of the flange part of the shaft; a cap member fixed to the rotating member to be disposed to face the sealing member; and a cover member having a region surrounding amounting hole seated on an upper surface of the flange part of the shaft and forming a labyrinth seal together with the cap member. | 2015-07-30 |
20150213831 | SPINDLE MOTOR AND HARD DISK DRIVE INCLUDING THE SAME - There are provided a spindle motor and a hard disk drive including the same. The spindle motor includes: a lower thrust member fixedly attached to a base member; a shaft having a lower end portion coupled to the lower thrust member and an upper end portion provided with a flange portion; a rotating member including a sleeve rotating based on the shaft; and a fixed member including a fitting protrusion protruding upwardly in an axial direction and fitted into and fixed to a fixation groove recessed upwardly from a lower end of the shaft in the axial direction and a flange caught by a lower surface of the lower thrust member. | 2015-07-30 |
20150213832 | SPINDLE MOTOR AND HARD DISK DRIVE INCLUDING THE SAME - There is provided a spindle motor including: a lower thrust member fixed to a base member; a shaft having a lower end portion fixed to the lower thrust member; and a rotating member rotating around the shaft and having a circulating hole formed therein in order to circulate a lubricating fluid, wherein a thrust dynamic groove is formed in at least one of facing surfaces of the rotating member and the lower thrust member, and an air bubble collecting groove having a ring shape is formed in at least one of the facing surfaces of the rotating member and the lower thrust member so as to be overlapped with the circulating hole. | 2015-07-30 |
20150213833 | ROTATING DEVICE AND A METHOD FOR MANUFACTURING A ROTATING DEVICE - In a rotating device, a recording disk is mounted on a hub. A base rotatably supports the hub via a bearing unit. A core is fixed to the base with a ring portion and a plurality of teeth, with coils wound there around. The bearing unit includes a cylindrical portion that surrounds a radial dynamic pressure groove. The base includes an integrated surrounding portion protruding toward the hub, with the ring portion glued there around. The base further includes an integrated increasing-thickness portion arranged outside of the surrounding portion such that the increasing-thickness portion becomes thicker the closer it is to the surrounding portion. The cylindrical portion is surrounded by the surrounding portion, the surrounding portion is surrounded by the increasing-thickness portion, and a surface of the increasing-thickness portion at least partly overlaps the radial dynamic pressure groove in the axial direction. | 2015-07-30 |
20150213834 | Video Frame Still Image Sequences - An electronic device may determine to present a video frame still image sequence version of a video instead of the video. The electronic device may derive a plurality of still images from the video. The electronic device may generate the video frame still image sequence by associating the plurality of still images. The electronic device may present the video frame still image sequence. The video frame still image sequence may be displayed according to timing information to resemble play of the video. In some cases, audio may also be derived from the video. In such cases, display of the video frame still image sequence may be performed along with play of the audio. | 2015-07-30 |
20150213835 | SYSTEMS AND METHODS FOR CONVERTING INTERACTIVE MULTIMEDIA CONTENT AUTHORED FOR DISTRIBUTION VIA A PHYSICAL MEDIUM FOR ELECTRONIC DISTRIBUTION - Systems and methods for converting interactive multimedia content authored for distribution via a physical medium for electronic distribution are disclosed. One embodiment of the invention includes building an object model of interactive multimedia content authored for distribution via a physical medium using a content authoring system, automatically authoring a user interface based upon the object model using the content authoring system, and packing the transcoded multimedia content into at least one container. | 2015-07-30 |
20150213836 | APPARATUS AND METHOD FOR EDITING - An editing machine comprises: generating, from a material data which is generated according to a first time and which a first time range to be specified, a playback data that is to be played back according to a second time different from the first time, and locating a second time range, which includes the material data within the first time range, in the playback data. | 2015-07-30 |
20150213837 | IMAGE PROCESSING DEVICE, PRINT PRODUCTION SYSTEM, PHOTOGRAPH ALBUM PRODUCTION SYSTEM, IMAGE PROCESSING METHOD, AND PROGRAM - The image processing device includes an image data input unit for receiving data of moving images and still images; an image grouping unit for classifying the moving images and the still images into groups; an image analyzer for analyzing the moving images and the still images classified by group, and obtaining analysis information of the images, and information on relationship between the moving images and the still images; a frame image extractor for extracting frame images from the moving images according to at least one of the analysis information and the relationship information; a layout determining unit for determining a layout of the still images and the frame images according to at least one of the analysis information and the relationship information; and an image arranging unit for arranging the still images and the frame images according to the layout. | 2015-07-30 |
20150213838 | NETWORK BASED VIDEO EVENT RECORDING SYSTEM - The present description provides a novel Ethernet/IP process or network based video event recording system, which is to be embedded into any production line (conveyor belt), providing a continuous high speed loop recording with a specially designed video recording and viewing software, synchronized with the factory precision time protocol server (IEEE 1588 server), and able to store and retrieve files on or from a remote server. A web based management interface is provided for remote control, as well as to retrieve and view the recorded images and videos. The video recording system is designed to be connected to the factory network and to work seamlessly with the standard factory timing protocols and standards, as well as the standard factory programmable logic controllers. | 2015-07-30 |
20150213839 | MEDIA APPLICATION BACKGROUNDING - A media application is disclosed. The media application provides a playback of a media item that includes a video portion and an audio portion. The media application stops the playback of the video portion of the media item while continuing to provide the audio portion of the media item. The media application resumes the playback of the video portion of the media item in synchronization with the audio portion being provided. | 2015-07-30 |
20150213840 | DYNAMICALLY CREATING VIDEO BASED ON STRUCTURED DOCUMENTS - An electronic system dynamically creates video based on a structured document by associating video clips with items in a structured document includes a server that is connected to a user terminal. The user terminal sends to the server, as a selected item, at least one item in a structured document selected by the user. The server receives the item sent by the user terminal, identifies the item in the structured document selected by the user, identifies at least one dependent item having a dependent relationship with the selected item, dynamically creates a video on the basis of at least one video clip associated with each identified item and at least one video clip associated with each identified dependent item, and sends the video for playback on the user terminal. | 2015-07-30 |
20150213841 | MEMORY CHIP AND MEMORY STORAGE DEVICE - A memory chip is disclosed. The memory comprises a substrate and a plurality of memory pads. The plurality of memory pads are disposed around the substrate so as to form a | 2015-07-30 |
20150213842 | SEMICONDUCTOR DEVICE AND DRIVING METHOD THEREOF - In a memory module including a memory cell array including memory cells arranged in matrix, each including a first transistor using an oxide semiconductor and a first capacitor; a reference cell including a p-channel third transistor, a second capacitor, and a second transistor using an oxide semiconductor; and a refresh timing detection circuit including a resistor and a comparator, wherein when a potential is supplied to the first capacitor through the first transistor, a potential is supplied to the second capacitor through the second transistor, wherein a drain current value of the third transistor is changed in accordance with the potential stored in the second capacitor, and wherein when the drain current value of the third transistor is higher than a given value, a refresh operation of the memory cell array and the reference cell are performed. | 2015-07-30 |
20150213843 | MEMORY DEVICE AND SEMICONDUCTOR DEVICE - An object of one embodiment of the present invention is to propose a memory device in which a period in which data is held is ensured and memory capacity per unit area can be increased. In the memory device of one embodiment of the present invention, bit lines are divided into groups, and word lines are also divided into groups. The word lines assigned to one group are connected to the memory cell connected to the bit lines assigned to the one group. Further, the driving of each group of bit lines is controlled by a dedicated bit line driver circuit of a plurality of bit line driver circuits. In addition, cell arrays are formed on a driver circuit including the above plurality of bit line driver circuits and a word line driver circuit. The driver circuit and the cell arrays overlap each other. | 2015-07-30 |
20150213844 | DIGITAL RAMP RATE CONTROL FOR CHARGE PUMPS - Methods for controlling a ramp rate of an output voltage derived from one or more charge pumps and reducing variation in the ramp rate due to process, voltage, and temperature (PVT) variations are described. In some embodiments, the ramp rate of the output voltage from one or more charge pumps may be controlled using a ramp rate control circuit that uses a digital counter to adjust (or step up) the output voltage from the one or more charge pumps based on a ramp rate schedule. The ramp rate schedule may specify varying output voltage levels for the one or more charge pumps during a time period in which the output voltage charges up from a first voltage to a second voltage greater than the first voltage. | 2015-07-30 |
20150213845 | SYSTEM USING MINIMUM OPERATION POWER AND POWER SUPPLY VOLTAGE SETTING METHOD OF MEMORY DEVICE - A system includes a memory device, a controller, and a power supply. The controller stores a write data in the memory device, and generates a voltage control signal by comparing a read data outputted from the memory device with the write data. The power supply controls a level of a power supply voltage supplied to the memory device in response to the voltage control signal. | 2015-07-30 |
20150213846 | SEMICONDUCTOR DEVICE - To provide a semiconductor device having a novel configuration, in which a malfunction and power consumption are reduced. A data holding circuit which includes a flipflop including first and second latch circuits and a shadow register including a nonvolatile memory portion; and a control signal generation circuit which generates a first control signal supplied to the first latch circuit and a second control signal supplied to the second latch circuit are included. The shadow register is a circuit which controls data saving or data restoring between the first and second latch circuits on the basis of a saving control signal or a restore control signal. The control signal generation circuit is a circuit which generates the first and second control signals at L level in a period during which data is saved or restored, on the basis of a clock signal, the saving control signal, and the restore control signal. | 2015-07-30 |
20150213847 | Retention optimized memory device using predictive data inversion - A method for storing data. The method includes providing an addressable memory including a memory space, wherein the memory space includes a plurality of memory cells. The method includes configuring the addressable memory such that a majority of the plurality of memory cells in the memory space stores internal data values in a preferred bias condition when a first external data state of one or more external data states is written to the memory space, wherein the first external data state is opposite the preferred bias condition. | 2015-07-30 |
20150213848 | METHODS AND APPARATUSES FOR PROVIDING A PROGRAM VOLTAGE RESPONSIVE TO A VOLTAGE DETERMINATION - Apparatuses and methods for providing a program voltage responsive to a voltage determination are described. An example apparatus includes a memory array comprising a plurality of access lines. The example apparatus further includes a memory access circuit coupled to the memory array. The memory access circuit is configured to, during a memory program operation, provide an inhibit voltage to the plurality of access lines. The memory access circuit is further configured to, during the memory program operation, provide a program voltage to a target access line of the plurality of access lines responsive to a determination that an access line of the plurality of access lines has a voltage equal to or greater than a threshold voltage. The threshold voltage is less than the inhibit voltage. | 2015-07-30 |
20150213849 | PROVIDING MEMORY TRAINING OF DYNAMIC RANDOM ACCESS MEMORY (DRAM) SYSTEMS USING PORT-TO-PORT LOOPBACKS, AND RELATED METHODS, SYSTEMS, AND APPARATUSES - Providing memory training of dynamic random access memory (DRAM) systems using port-to-port loopbacks, and related methods, systems, and apparatuses are disclosed. In one aspect, a first port within a DRAM system is coupled to a second port via a loopback connection. A training signal is sent to the first port from a System-on-Chip (SoC), and passed to the second port through the loopback connection. The training signal is then returned to the SoC, where it may be examined by a closed-loop training engine of the SoC. A training result corresponding to a hardware parameter may be recorded, and the process may be repeated until an optimal result for the hardware parameter is achieved at the closed-loop training engine. By using a port-to-port loopback configuration, the DRAM system parameters regarding timing, power, and other parameters associated with the DRAM system may be trained more quickly and with lower boot memory usage. | 2015-07-30 |
20150213850 | SERIAL DATA TRANSMISSION FOR DYNAMIC RANDOM ACCESS MEMORY (DRAM) INTERFACES - Serial data transmission for dynamic random access memory (DRAM) interfaces is disclosed. Instead of the parallel data transmission that gives rise to skew concerns, exemplary aspects of the present disclosure transmit the bits of a word serially over a single lane of the bus. Because the bus is a high speed bus, even though the bits come in one after another (i.e., serially), the time between arrival of the first bit and arrival of the last bit of the word is still relatively short. Likewise, because the bits arrive serially, skew between bits becomes irrelevant. The bits are aggregated within a given amount of time and loaded into the memory array. | 2015-07-30 |
20150213851 | MANAGEMENT OF MEMORY REFRESH POWER CONSUMPTION - Embodiments include a system, an apparatus, a device, and a method. The apparatus includes a processor, a dynamic memory, and a hardware-implemented memory control circuit. The hardware-implemented control circuit includes a control circuit for establishing an extended refresh period of the dynamic memory based at least in part on a monitored result that indicates an occurrence of a memory loss in the dynamic memory. The hardware-implemented control circuit also includes a control circuit for causing a refresh of the dynamic memory during each of at least two extended refresh periods. | 2015-07-30 |
20150213852 | CHIP HAVING REGISTER TO STORE VALUE THAT REPRESENTS ADJUSTMENT TO OUTPUT DRIVE STRENGTH - An integrated circuit device includes a transmitter circuit including an output driver. The integrated circuit device includes a first register to store a value representative of a drive strength setting associated with the transmitter circuit such that the output driver outputs data in accordance with the drive strength setting. The integrated circuit device also includes a second register to store a value representative of an equalization setting associated with the transmitter circuit such that the output driver outputs data in accordance with the equalization setting. The integrated circuit device further includes a third register to store a value representative of a slew rate setting associated with the transmitter circuit such that the output driver outputs data in accordance with the slew rate setting. | 2015-07-30 |
20150213853 | IMPLEMENTING SIMULTANEOUS READ AND WRITE OPERATIONS UTILIZING DUAL PORT DRAM - A method, system and memory controller are provided for implementing simultaneous read and write operations in a memory subsystem utilizing a dual port Dynamic Random Access Memory (DRAM) configuration. A DRAM includes a first partition and a second partition. A memory controller determines if memory requirements are above or below a usage threshold. If the memory requirements are below the usage threshold, the memory is partitioned into a read buffer and a write buffer, with writes going to the write buffer and reads coming from the read buffer, data being transferred from the write buffer to the read buffer through an Error Correction Code (ECC) engine. If the memory requirements are above the usage threshold, the entire memory is used for reads and writes. | 2015-07-30 |
20150213854 | IMPLEMENTING SIMULTANEOUS READ AND WRITE OPERATIONS UTILIZING DUAL PORT DRAM - A method, system and memory controller are provided for implementing simultaneous read and write operations in a memory subsystem utilizing a dual port Dynamic Random Access Memory (DRAM) configuration. A DRAM includes a first partition and a second partition. A memory controller determines if memory requirements are above or below a usage threshold. If the memory requirements are below the usage threshold, the memory is partitioned into a read buffer and a write buffer, with writes going to the write buffer and reads coming from the read buffer, data being transferred from the write buffer to the read buffer through an Error Correction Code (ECC) engine. If the memory requirements are above the usage threshold, the entire memory is used for reads and writes. | 2015-07-30 |
20150213855 | MODE-CHANGEABLE DUAL DATA RATE RANDOM ACCESS MEMORY DRIVER WITH ASYMMETRIC OFFSET AND MEMORY INTERFACE INCORPORATING THE SAME - A memory driver, a method of driving a command bus for a synchronous dual data rate (sDDR) memory and a memory controller for controlling dynamic random-access memory (DRAM). In one embodiment, the memory driver includes: (1) pull-up and pull-down transistors couplable to a command bus of a memory controller and operable in 1N and 2N timing modes and (2) gear down offset circuitry coupled to the pull-up transistor and operable to offset the command bus when transitioning out of the 1N timing mode and increase an extent and duration of | 2015-07-30 |
20150213856 | PRECHARGE CIRCUIT AND SEMICONDUCTOR MEMORY APPARATUS USING THE SAME - A precharge circuit may include a precharge control unit, a first precharge unit, and a second precharge unit. The precharge control unit may generate a read precharge signal and a write precharge signal in response to a read signal, a write signal, and a precharge signal. The first precharge unit may precharge a data input/output line to a first voltage level in response to the read precharge signal. The second precharge unit may precharge the data input/output line to either a second voltage level or a third voltage level in response to the write precharge signal. | 2015-07-30 |
20150213857 | TRACKING MECHANISMS - A tracking circuit in a memory macro includes a data line, a tracking cell electrically coupled with the data line, a logical gate, a feedback transistor, and a plurality of pulling devices. The logical gate has an input terminal and an output terminal. The input terminal of the logical gate is electrically coupled with the data line. The feedback transistor has a first terminal, a second terminal, and a gate terminal. The first terminal of the feedback transistor is electrically coupled with the data line, and the gate terminal of the feedback transistor is electrically coupled with the output terminal of the logical gate. The plurality of pulling devices is configured to pull the second terminal of the feedback transistor toward a first voltage. | 2015-07-30 |
20150213858 | READING DATA FROM A MEMORY CELL - In response to a write operation to a memory cell that causes a data line of the memory cell to have a first voltage direction, causing the data line to have a second voltage direction opposite the first voltage direction. | 2015-07-30 |
20150213859 | BURST LENGTH CONTROL CIRCUIT - A burst length control circuit includes a burst length input circuit that outputs a mode register burst length signal and a burst length on-the-fly signal, a burst length generator circuit that outputs a burst length signal, and a burst length adjuster that delays the burst length signal by a write latency time to produce a write burst length control signal. A selection circuit selects any one of the burst length signal and the write burst length control signal according to a write read command signal and an on-the-fly signal received from the burst length input circuit, and outputs a burst length control signal. A burst stop counter counts the burst length control signal according to an internal write command signal and an internal read command signal, and outputs a burst stop signal corresponding to a selected burst length. | 2015-07-30 |
20150213860 | SEMICONDUCTOR DEVICE INCLUDING SPIRAL DATA PATH - A semiconductor device disclosed in this disclosure includes a first terminal formed above a first surface of a semiconductor substrate, a second terminal formed above a second surface of the semiconductor substrate opposite to the first surface, a first through substrate via (TSV) penetrating the semiconductor substrate, and a first-in first-out (FIFO) circuit, wherein the first TSV and the FIFO circuit are coupled in series between the first terminal and the second terminal. | 2015-07-30 |
20150213861 | SEMICONDUCTOR DEVICES - The semiconductor device includes a first data aligner, an input strobe signal generator and a second data aligner. The first data aligner aligns input data in synchronization with an internal strobe signal to generate alignment data. The input strobe signal generator generates first and second delay signals from the internal strobe signal. The input strobe signal generator also latches an input clock signal generated from an external clock signal after a write latency period from a period when a write operation commences, in response to the first and second delay signals to generate an input strobe signal. The second data aligner re-aligns the alignment data in synchronization with the input strobe signal to generate internal data. | 2015-07-30 |
20150213862 | MEMORY DECODING - Memories, and methods of operating such memories, having a memory cell, sense circuitry having a gate, program circuitry and a decoder having a first signal line connected to the gate of the sense circuitry, a second signal line connected to the program circuitry, and an output selectively connected to the memory cell. The decoder is configured to selectively connect the output to the first signal line responsive to a first control signal and to selectively connect the output to the second signal line responsive to the first control signal and a second control signal. The sense circuitry is configured to selectively activate the gate responsive to a third control signal. | 2015-07-30 |
20150213863 | SUB-BLOCK DISABLING IN 3D MEMORY - Some embodiments relate to apparatuses and methods associated with blocks of memory cells. The blocks of memory cells may include two or more sub-blocks of memory cells. One such sub-block may comprise a vertical string of memory cells including a select transistor. An apparatus may include a sub-block disabling circuit. The sub-block disabling circuit may include a content-addressable memory. The content-addressable memory may receive an address, including a block address and a sub-block address. The content addressable memory may output a signal to disable a tagged sub-block if the received address includes the block address and the sub-block address associated with the tagged sub-block. The sub-block disabling circuit may further include a plurality of drivers to drive one or more of the select transistors based on the signal. Other apparatus and methods are described. | 2015-07-30 |
20150213864 | METHOD AND SYSTEM FOR OPERATING MEMORY - A method and a system for operating a memory are provided. The memory includes a plurality of memory cells which are configured to store data. The method includes the following steps. A counting number recorded in a counter is counted by 1, if the memory is written. The memory is set as a frequently using device, if the counting number recoded in the counter reaches a predetermined value. | 2015-07-30 |
20150213865 | HIGH DENSITY LOW POWER GSHE-STT MRAM - Systems and methods are directed to a memory element comprising a hybrid giant spin Hall effect (GSHE)-spin transfer torque (STT) magnetoresistive random access memory (MRAM) element, which includes a GSHE strip formed between a first terminal (A) and a second terminal (B), and a magnetic tunnel junction (MTJ), with a free layer of the MTJ interfacing the GSHE strip, and a fixed layer of the MTJ coupled to a third terminal (C). The orientation of the easy axis of the free layer is perpendicular to the magnetization created by electrons traversing the GSHE strip between the first terminal and the second terminal, such that the free layer of the MTJ is configured to switch based on a first charge current injected from/to the first terminal to/from the second terminal and a second charge current injected/extracted through the third terminal into/out of the MTJ via the third terminal (C). | 2015-07-30 |
20150213866 | HIGH DENSITY LOW POWER GSHE-STT MRAM - Systems and methods are directed to a memory element comprising a hybrid giant spin Hall effect (GSHE)-spin transfer torque (STT) magnetoresistive random access memory (MRAM) element, which includes a GSHE strip formed between a first terminal (A) and a second terminal (B), and a magnetic tunnel junction (MTJ), with a free layer of the MTJ interfacing the GSHE strip, and a fixed layer of the MTJ coupled to a third terminal (C). The orientation of the easy axis of the free layer is perpendicular to the magnetization created by electrons traversing the GSHE strip between the first terminal and the second terminal, such that the free layer of the MTJ is configured to switch based on a first charge current injected from/to the first terminal to/from the second terminal and a second charge current injected/extracted through the third terminal into/out of the MTJ via the third terminal (C). | 2015-07-30 |
20150213867 | MULTI-LEVEL CELL DESIGNS FOR HIGH DENSITY LOW POWER GSHE-STT MRAM - Systems and methods are directed to multi-level cell (MLC) comprising: two or more programmable elements coupled to a common access transistor, wherein each one of the two or more programmable elements has a corresponding unique set of two or more switching resistances and two or more switching currents characteristics, such that combinations of the two or more programmable elements configured in the respective two or more switching resistance correspond to multi-bit binary states controllable by passing switching currents through the common access transistor. Each one of the two or more programmable elements includes one or more hybrid giant spin Hall effect (GSHE)-spin transfer torque (STT) magnetoresistive random access memory (MRAM) cell, with two or more hybrid GSHE-STT MRAM cells coupled in parallel. | 2015-07-30 |
20150213868 | THREE-PHASE GSHE-MTJ NON-VOLATILE FLIP-FLOP - Systems and methods are directed to a three-phase non-volatile flip-flop (NVFF), which includes a master stage formed from a dual giant spin Hall effect (GSHE)-magnetic tunnel junction (MTJ) structure, with a first GSHE-MTJ and a second GSHE-MTJ coupled between a first combined terminal and a second combined terminal, and a slave stage formed from a first inverter cross-coupled with a second inverter. A first data value is read out from the slave stage during a read phase of the same clock cycle that a second data value is written into the master stage during a write phase. The three-phase NVFF includes three control signals, for controlling an initialization phase of the slave stage, the read phase, and the write phase. | 2015-07-30 |
20150213869 | SINGLE-PHASE GSHE-MTJ NON-VOLATILE FLIP-FLOP - Systems and methods are directed to a single-phase non-volatile flip-flop (NVFF), which includes a master stage formed from a dual giant spin Hall effect (GSHE)-magnetic tunnel junction (MTJ) structure, the dual GSHE-MTJ structure comprising a first GSHE-MTJ and a second GSHE-MTJ coupled between a first combined terminal and a second combined terminal, and a slave stage formed from a first inverter coupled to a second inverter. During a single clock cycle of a clock, a first data value is read out from the slave stage when a clock is in a high state and a second data value is written into the master stage, when the clock is in a low state. The first and second inverters are cross coupled in a latch configuration to hold the first data value as an output, when the clock is in the low state. | 2015-07-30 |
20150213870 | SEMICONDUCTOR STORAGE DEVICE - A semiconductor storage device according to the present embodiment includes a plurality of memory units respectively comprising a plurality of memory cells. A data bus is shared by the memory units and transfers data from the memory units or to the memory units. A timing controller includes a delay time unit shared by the memory units sharing the data bus. The timing controller is configured to output a control signal for driving the memory units after a predetermined delay time elapses since receiving an input signal. | 2015-07-30 |
20150213871 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR REFRESHING MEMORY CELLS - A semiconductor memory device is provided. The semiconductor memory device includes a memory block including a plurality of memory cells; a default refresh controller configured to receive a refresh command from a host, to generate a default refresh signal, and to control the memory cells to be refreshed; and a weak cell refresh controller configured to receive the default refresh signal, to generate a weak cell refresh signal, and to control a weak cell among the memory cells to be refreshed. The weak cell may be refreshed at least one more time during a refresh period during which all of the memory cells are refreshed by the default refresh controller. The semiconductor memory device performs at least one more refresh on a weak cell having a data retention time shorter than a refresh period apart from a normal default refresh, thereby preventing data loss. | 2015-07-30 |
20150213872 | APPARATUSES AND METHODS FOR ADDRESS DETECTION - Apparatuses and methods for address detection are disclosed herein. An example apparatus includes an address filter and an address tracking circuit. The address filter may be configured to receive a first address and to determine whether the first address matches an address of a plurality of addresses associated with the address filter. The address tracking circuit may be coupled to the address filter and configured to store the first address responsive to a determination that the first address matches an address of the plurality of addresses associated with the address filter. The address tracking circuit may further be configured to receive a second address and to change a count associated with the first address based on the second address matching the first address. The address tracking circuit may be configured to selectively provide the first address responsive to the count. | 2015-07-30 |
20150213873 | INJECTION-LOCKED PHASE LOCKED LOOP CIRCUITS USING DELAY LOCKED LOOPS - An injection-locked phase-locked loop (ILPLL) circuit includes a delay-locked loop (DLL) and an ILPLL. The DLL is configured to generate a DLL clock by performing a delay-locked operation on a reference clock. The ILPLL includes a voltage-controlled oscillator (VCO), and is configured to generate an output clock by performing an injection synchronous phase-locked operation on the reference clock. The DLL clock is injected into the VCO as an injection clock of the VCO. | 2015-07-30 |
20150213874 | RECORDING APPARATUS AND CONTROL METHOD FOR RECORDING APPARATUS - In a recording apparatus, a generating unit generates a timing signal by delaying a clock signal. A control unit controls so that a predetermined command is output multiple times to a storage device and each piece of data sent by the storage device in response to the multiple predetermined commands is received in accordance with the timing signal having a different delay amount for each of the multiple predetermined commands. A detection unit detects, in order of the delay amounts, a range of the delay amounts of the timing signals for which predetermined data has been successfully received. A setting unit sets, in a case where a plurality of the ranges have been detected by the detection unit, a single delay amount in a single predetermined range among the plurality of ranges, as the delay amount of the timing signal. | 2015-07-30 |
20150213875 | MEMORY CONTROLLER AND INFORMATION PROCESSING DEVICE - A memory controller has a first variable delay circuit that delays a data strobe signal received from a memory, and a second variable delay circuit that variably delays a data signal which is received from the memory and is synchronous with the data strobe signal, and that is set a second delay amount which is different from a first delay amount of the first variable delay circuit. | 2015-07-30 |
20150213876 | SEMICONDUCTOR DEVICE WITH FLOATING BODY STRUCTURE - A semiconductor device is disclosed, which comprises: a memory cell, first and second bit lines, a switch between the first and second bit lines, a sense amplifier, a sense amplifier driving circuit driving the sense amplifier with first and second voltages, a precharge circuit precharging the first bit line, and a control circuit. The control circuit performs a read operation so that the first and second bit lines are disconnected from each other and the first bit line is precharged to a precharge voltage, during a first period. Thereafter, the control circuit performs a restoring operation in a state where the first and second bit lines are connected to each other and the precharging of the first bit line is cancelled, during a second period after the first period. The sense amplifier is driven with the second voltage for increasing its driving ability during the second period | 2015-07-30 |
20150213877 | REFRESHING A GROUP OF MEMORY CELLS IN RESPONSE TO POTENTIAL DISTURBANCE - A detection circuit is provided for a particular group of memory cells in a memory device, where the detection circuit is to be updated in response to at least one access of data and at least one neighboring group of memory cells. The particular group of memory cells is refreshed in response to an indication from the detection circuit, where the indication indicates presence of potential disturbance of the particular group of memory cells. | 2015-07-30 |
20150213878 | MEMORY CONTROLLER, INFORMATION PROCESSING DEVICE, AND REFERENCE VOLTAGE ADJUSTMENT METHOD - A memory controller has a first input buffer that determines a data signal that is to be received, on the basis of a reference voltage, a second inputs buffer that inputs a data strobe signal that is to be received, a data latch circuit that fetches an internal data signal, which is outputted by the first input buffer, on the basis of a phase of a rising edge and a falling edge of an internal data strobe signal, which is outputted by the second input buffer, a duty ratio detection circuit that detects a duty ratio of the internal data strobe signal, and a reference voltage generating circuit that adjusts the reference voltage on the basis of the duty ratio detected by the duty ratio detection circuit. | 2015-07-30 |
20150213879 | MEMORY DEVICES AND CONTROL METHODS THEREOF - A memory device includes a first signal line; a memory cell array divided into a first area and a second area and having a plurality of first memory cells and second memory cells in the first area and second area, respectively. The plurality of first and second memory cells are coupled the first signal line, and each has a reference node. A first voltage adjustment circuit adjusts voltages at the reference nodes of the plurality of first memory cells, wherein the first voltage adjustments circuit includes: a first switch coupled between the reference nodes of the plurality of first memory cells and the ground, controlled by an address signal; and a first bias element coupled to the reference nodes of the plurality of first memory cells. A second voltage adjustment circuit adjusts voltages at the reference nodes of the plurality of second memory cells. | 2015-07-30 |
20150213880 | WRITING DATA TO A MEMORY CELL - A circuit comprises a first transistor, a capacitive component, a second transistor, and a data line. The first transistor has a threshold voltage value. A first terminal of the first transistor is coupled with a first terminal of the capacitive component and a second terminal of the second transistor. A second terminal of the first transistor is configured to receive a second-terminal voltage value. A third terminal of the first transistor is configured to receive a third-terminal voltage value. A first terminal of the second transistor is coupled with the data line. A third terminal of the second transistor is configured to receive a second-transistor control signal. The first transistor is configured to be on and off to maintain the data line at a data line voltage value. | 2015-07-30 |
20150213881 | INTEGRATED READ/WRITE TRACKING IN SRAM - Systems and methods presented herein provide for integrated read/write tracking in an SRAM device. In one embodiment, an SRAM device includes a clock, a memory cell array, a column of dummy bit cells operable to mirror bit line loading of the memory cell array, and a row of dummy bit cells operable to mirror word line loading of the memory cell array. The SRAM devices also includes a read/write tracking cell operable to track read operations from the memory cell array via the dummy bit cells, to track write operations to the memory cell array via the dummy bit cells, and to reset the clock based on the tracked read operations and the tracked write operations. | 2015-07-30 |