31st week of 2014 patent applcation highlights part 46 |
Patent application number | Title | Published |
20140212980 | HYDROPHILIC THIOL PROBE - The present invention provides a probe that further promotes ionization in proteomic analysis using mass spectrometry, and a high-sensitive mass spectrometry method for a protein using such a probe. Further, the present invention provides an ionization-enhancing probe that can be used even for a protein that has a high degree of hydrophobicity and quickly turns over, and a high-sensitive mass spectrometry method for a protein using such a probe. | 2014-07-31 |
20140212981 | METHODS AND SYSTEMS FOR DETERMINING THE AMOUNT OF THIOPURINE METABOLITES IN A SAMPLE - Disclosed are methods and systems for the analysis of thiopurine drug metabolites in a sample using liquid chromatography/mass spectrometry. | 2014-07-31 |
20140212982 | METHODS OF SELECTIVELY DETECTING THE PRESENCE OF A COMPOUND IN A GASEOUS MEDIUM - Methods of selectively detecting the presence of at least one compound in a gaseous medium. A silicon substrate can be exposed to the gaseous medium under conditions to adsorb the at least one compound to the silicon substrate to form a modified silicon substrate. The modified silicon substrate can be analyzed to determine if the at least one compound was present in the gaseous medium. The step of analyzing can include using X-ray spectroscopy. | 2014-07-31 |
20140212983 | THERMAL H2S DETECTION IN DOWNHOLE FLUIDS - An apparatus for detecting a chemical of interest in a fluid or estimating a concentration of the chemical in the fluid includes: a carrier configured to be conveyed through a borehole penetrating an earth formation; a first temperature sensor disposed at the carrier and configured to sense a temperature of the fluid and provide a first temperature output; and a second temperature sensor disposed at the carrier and covered with an exothermic reaction material that experiences an exothermic reaction when exposed to the chemical of interest and configured to sense a temperature and provide a second temperature output. The apparatus further includes a processor coupled to the first temperature sensor and the second temperature sensor and configured to detect the chemical or estimate the concentration using the first temperature output and the second temperature output. | 2014-07-31 |
20140212984 | FLUORESCENCE READER - A fluorescence reader for an optical assay arrangement that includes a polymeric sample substrate having a reaction site-surface and a substrate surface. The fluorescence reader includes a light source arranged to illuminate the reaction site-surface through the substrate surface, and a detector device arranged to detect fluorescent light emitted from the reaction site-surface and transmitted through the substrate surface, the substrate surface being configured to increase transmission of emitted fluorescent light by suppression of total internal reflection. | 2014-07-31 |
20140212985 | PREPARATION OF REACTION CHAMBERS WITH DRIED PROTEINS - The present invention relates to a method of applying a spot of an unlabelled biomolecule, e.g. antibody or protein antigen, to a surface of a reaction chamber of a diagnostic assay. This method comprising the steps of applying to the surface of the reaction chamber a solution comprising a sugar and comprising a non-labelled biomolecule, e.g. antibody or protein antigen, and allowing the solution to dry. In this method the biomolecule is in a concentration sufficient to saturate the binding places for a protein on the surface where the solution has been applied to. The present invention relates to a reaction chamber of a diagnostic device for performing a biomolecule, e.g. antibody or protein antigen, based detection assay. Herein,the reaction chamber comprises a detection region with one or more spots of an unlabelled biomoleculespots bound to the detection region. The one or more spots have a diameter of between 0.1 to 0.5 mm. The spot comprises a sugar and a protein and comprises between 0.01 and 0.5 ng biomolecule. | 2014-07-31 |
20140212986 | Passive Micro-vessel and Sensor - An electrically passive device and method for in-situ acoustic emission, and/or releasing, sampling and/or measuring of a fluid or various material(s) is provided. The device may provide a robust timing mechanism to release, sample and/or perform measurements on a predefined schedule, and, in various embodiments, emits an acoustic signal sequence(s) that may be used for triangulation of the device position within, for example, a hydrocarbon reservoir or a living body. | 2014-07-31 |
20140212987 | Signal Ratio in Assay Calibrators - Methods of enhancing signal ratio between calibrators in an assay for an analyte include conducting an assay for the analyte with zero concentration of analyte in a first calibrator to determine a first signal level. The reagents employed in the assay comprise an antibody reagent comprising an antibody for the analyte wherein a hinge region of the antibody is conjugated to a moiety. The assay for the analyte is also conducted with a second concentration of analyte in a second calibrator to determine a second signal level wherein the second analyte concentration is greater than zero and wherein the reagents employed in the assay comprise the antibody reagent. A ratio of the first signal level to the second signal level is determined and evaluated. | 2014-07-31 |
20140212988 | METHOD OF DETECTING AN ANALYTE USING COATED HOLLOW MICROSPHERES AND METHOD OF PRODUCING SAME - Disclosed in this specification is a method for detecting an analyte using buoyant particles and chemical moieties to give buoyant particle composites that exhibit SERS and can be used for detecting the analytes in a liquid sample. A method is provided for detecting analytes of interest by contacting the analyte with a buoyant particle that comprises a first chemical moiety, such as a SERS-active component, allowing the analyte of interest to bind to the first chemical moiety. The resulting composite localizes in a discrete location of the liquid sample through a buoyant force. The composite is then detected by measuring the Raman scattered light in the discrete location of the liquid sample. | 2014-07-31 |
20140212989 | PHENYTOIN BIOSENSOR AND METHOD FOR MEASURING CONCENTRATION OF PHENYTOIN - The present disclosure relates to a phenytoin biosensor. In some embodiments, the phenytoin biosensor may comprise a microcantilever, a self-assembly monolayer, and a phenytoin antibody layer. The self-assembly monolayer may immobilize on the microcantilever surface. The phenytoin antibody layer may immobilize on the self-assembly monolayer. The phenytoin antibody layer may be used to bind with phenytoin drug samples. The present disclosure further relates to methods for measuring the concentration of phenytoin drug samples. | 2014-07-31 |
20140212990 | DETECTION ASSAYS EMPLOYING MAGNETIC NANOPARTICLES - The present invention is directed to novel assays for detecting target molecules. The assays employ small size, detectably labeled, magnetic nanoparticles associated with a capture molecule. The detection assay is accelerated by applying magnetic field during the assay. The assays of the invention can be used to enhance the efficiency of the detection step in dot blot, Western blot and ELISA. | 2014-07-31 |
20140212991 | IMMUNOASSAY METHOD AND IMMUNOASSAY APPARATUS - In order to provide an immunoassay method and an immunoassay apparatus capable of further reducing errors due to non-target substances, a detector measures a measurement specimen and detects information regarding the binding number of carrier particles included in the measurement specimen. A controller classifies, based on the information regarding the binding number, particles included in the measurement specimen into groups, the groups being classified in accordance with the binding numbers. Further, for each classified group, the controller performs either one of a first removing process for removing, from a processing target, data of non-target substances different from the carrier particles, and a second removing process for removing, from the processing target, data of the non-target substances through a process different from the first removing process, and obtains information regarding the agglutination degree of the carrier particles, based on data of the carrier particles obtained by performing the removing process. | 2014-07-31 |
20140212992 | CENTRIFUGALLY-ENHANCED CAPTURE METHOD AND DEVICE - In a centrifugal microfluidic device for conducting capture assays, a microfluidic platform rotates in a plane of rotation and has at least one capture surface for immobilizing a target particle of interest in the device. The capture surface oriented so that it is not parallel to the plane of rotation of the device and is positionally fixed in the device during operation of the device. The centrifugal force arising from rotation of the device forces the target particles against the capture surface. Capture efficiency is independent of the rate of flow of the fluid and independent of the rate of rotation of the microfluidic platform. | 2014-07-31 |
20140212993 | METHOD OF MANUFACTURING A MAGNETORESISTIVE DEVICE - A method of manufacturing a magnetoresistive-based device includes etching a hard mask layer, the etching having a selectivity greater than 2:1 and preferably less than 5:1 of the hard mask layer to a photo resist thereover. Optionally, the photo resist is trimmed prior to the etch, and oxygen may be applied during or just subsequent to the trim of the photo resist to increase side shrinkage. An additional step includes an oxygen treatment during the etch to remove polymer from the structure and etch chamber. | 2014-07-31 |
20140212994 | SELF ALIGNED DUAL PATTERNING TECHNIQUE ENHANCEMENT WITH MAGNETIC SHIELDING - Embodiments of the present disclosure generally provide apparatus and method for improving processing uniformity by reducing external magnetic noises. One embodiment of the present disclosure provides an apparatus for processing semiconductor substrates. The apparatus includes a chamber body defining a vacuum volume for processing one or more substrate therein, and a shield assembly for shielding magnetic flux from the chamber body disposed outside the chamber body, wherein the shield assembly comprises a bottom plate disposed between the chamber body and the ground to shield magnetic flux from the earth. | 2014-07-31 |
20140212995 | RESIN APPLICATION APPARATUS, OPTICAL PROPERTY CORRECTION APPARATUS AND METHOD, AND METHOD FOR MANUFACTURING LED PACKAGE - A resin application apparatus includes: an optical property measurement unit measuring an optical property of light emitted from a light emitting diode (LED) chip which is mounted on a package body and to which transparent resin is not applied; and a resin application unit applying light conversion material-containing transparent resin to the LED chip in accordance with a resin application amount which is decided depending on the optical property measured by the optical measurement unit. | 2014-07-31 |
20140212996 | MICROELECTRONIC PACKAGE WITH STACKED MICROELECTRONIC UNITS AND METHOD FOR MANUFACTURE THEREOF - A microelectronic package may include a first microelectronic unit including a semiconductor chip having first chip contacts, an encapsulant contacting an edge of the semiconductor chip, and first unit contacts exposed at a surface of the encapsulant and electrically connected with the first chip contacts. The package may include a second microelectronic unit including a semiconductor chip having second chip contacts at a surface thereof, and an encapsulant contacting an edge of the chip of the second unit and having a surface extending away from the edge. The surfaces of the chip and the encapsulant of the second unit define a face of the second unit. Package terminals at the face may be electrically connected with the first unit contacts through bond wires electrically connected with the first unit contacts, and the second chip contacts through metalized vias and traces formed in contact with the second chip contacts. | 2014-07-31 |
20140212997 | PROCESS FOR PRODUCING SUBSTRATE FOR LIQUID EJECTION HEAD AND PROCESS FOR PROCESSING SILICON SUBSTRATE - A process for producing a substrate for a liquid ejection head in which a depressed portion is formed on a second surface that is a surface opposite to a first surface of a silicon substrate having an element formation region on the first surface with a peripheral side region left, the process including the steps of (1) forming an etching mask layer covering the second surface of the silicon substrate; (2) subjecting the etching mask layer and the silicon substrate to laser abrasion processing to form a pattern opening that does not pass through the silicon substrate; and (3) performing a wet etching process to the silicon substrate where the pattern opening is formed from a side of the second surface to form the depressed portion. The depressed portion is formed over a center side region including a position corresponding to the element formation region. | 2014-07-31 |
20140212998 | PROCESS FOR PRODUCING A SEMICONDUCTOR CHIP - A process for producing a semiconductor chip having a substrate and a bump formed on the substrate including (1) forming, on a substrate, a conductor gold for plating to be a base of plating growth; (2) forming a mask for plating on the conductor gold for plating; (3) performing plating using the mask for plating to form the bump and a dummy pattern; (4) removing the mask for plating; (5) etching the conductor gold for plating; and (6) applying a shock to at least the dummy pattern. The amount of side etching of the conductor gold for plating is grasped from a state of separation of the dummy pattern due to the shock in the step (6). | 2014-07-31 |
20140212999 | PHOTOELECTRIC CONVERSION DEVICE, IMAGE DISPLAY, METHOD OF MANUFACTURING PHOTOELECTRIC CONVERSION DEVICE, AND METHOD OF MANUFACTURING IMAGE DISPLAY - A photoelectric conversion device includes a plurality of photoelectric conversion regions disposed over a substrate, and a colored region disposed among the photoelectric conversion regions over the substrate, the colored region forming an image over the substrate. | 2014-07-31 |
20140213000 | GaN Based LED Having Reduced Thickness and Method for Making the Same - A device having a carrier, a light-emitting structure, and first and second electrodes is disclosed. The light-emitting structure includes an active layer sandwiched between a p-type GaN layer and an n-type GaN layer, the active layer emitting light of a predetermined wavelength in the active layer when electrons and holes from the n-type GaN layer and the p-type GaN layer, respectively, combine therein. The first and second electrodes are bonded to the surfaces of the p-type and n-type GaN layers that are not adjacent to the active layer. The n-type GaN layer has a thickness less than 1.25 μm. The carrier is bonded to the light emitting structure during the thinning of the n-type GaN layer. The thinned light-emitting structure can be transferred to a second carrier to provide a device that is analogous to conventional LEDs having contacts on the top surface of the LED. | 2014-07-31 |
20140213001 | WHITE LIGHT DEVICES USING NON-POLAR OR SEMIPOLAR GALLIUM CONTAINING MATERIALS AND PHOSPHORS - A packaged optical device includes a substrate having a surface region with light emitting diode devices fabricated on a semipolar or nonpolar GaN substrate. The light emitting diodes emit polarized light and are characterized by an overlapped electron wave function and a hole wave function. Phosphors within the package are excited by the polarized light and, in response, emit electromagnetic radiation of a second wavelength. | 2014-07-31 |
20140213002 | METHOD FOR MANUFACTURING LIGHT EMITTING DEVICE PACKAGE - A method for manufacturing a light emitting device package is provided. In the method, a growth substrate including a plurality of light emitting devices disposed on a top surface of the growth substrate is prepared. A first package substrate having a bonding pattern corresponding to a portion of the plurality of light emitting devices is prepared, and the bonding pattern is disposed on a top surface of the first package substrate. The portion of the plurality of light emitting devices and the bonding pattern are bonded by disposing the top surface of the growth substrate to face the top surface of the first package substrate. The portion of the plurality of light emitting devices is separated from the growth substrate. The portion of the plurality of light emitting devices joined to the bonding pattern is packaged. | 2014-07-31 |
20140213003 | GAN TYPE LIGHT EMITTING DIODE DEVICE AND METHOD OF MANUFACTURING THE SAME - The present invention relates to a GaN type LED device and a method of manufacturing the same. More particularly, there are provided a GaN type LED device including an LED chip; and a submount eutectic-bonded with the LED chip through an adhesive layer, wherein the adhesive layer is configured by soldering a plurality of metallic layers in which a first metallic layer and a second metallic layer are sequentially stacked, and the second metallic layer is formed in a paste form. Further, the present invention provides a method of manufacturing the GaN type LED device. | 2014-07-31 |
20140213004 | LIGHT-EMITTING DEVICE, DISPLAY DEVICE, AND METHOD FOR MANUFACTURING THE SAME - It is known that a light-emitting element utilizing organic EL deteriorates due to moisture. Therefore, a sealing technique to prevent moisture permeation is important. A light-emitting device including a light-emitting element utilizing organic EL is manufactured over a support substrate having flexibility and a high heat dissipation property (e.g., stainless steel or duralumin), and the light-emitting device is sealed with a stack body having moisture impermeability and a high light-transmitting property or with glass having moisture impermeability and a high light-transmitting property and having a thickness greater than or equal to 20 μm and less than or equal to 100 μm. | 2014-07-31 |
20140213005 | DEFECT-CONTROLLING STRUCTURE FOR EPITAXIAL GROWTH, LIGHT EMITTING DEVICE CONTAINING DEFECT-CONTROLLING STRUCTURE, AND METHOD OF FORMING THE SAME - A method for reducing dislocations or other defects in a light emitting device, such as light emitting diode (LED), by in-situ introducing nanoparticles into at least one of a defect-controlling layer, an n-type layer, a p-type layer, and a quantum well of the light emitting device. A light emitting device is provided, and nanoparticles are dispensed in-situ in at least one of a defect-controlling layer, an n-type layer, a p-type layer, and a quantum well of the light emitting device. | 2014-07-31 |
20140213006 | METHOD FOR FORMING VERTICAL TYPE SENSOR - The present invention provides a vertical type sensor, including a substrate; a first electrode formed on the substrate; a sensing layer formed on the first electrode layer and reactive to a target substance, wherein the first electrode layer is interposed between the substrate and the sensing layer; and a second electrode layer formed on the sensing layer and having a plurality of openings, wherein the sensing layer is interposed between the first electrode layer and the second electrode layer, and the target substance contacts the sensing layer via the plurality of openings. The vertical type sensor of the present invention provides instant, sensitive and rapid detection. | 2014-07-31 |
20140213007 | INTERNAL ELECTRICAL CONTACT FOR ENCLOSED MEMS DEVICES - A method of fabricating electrical connections in an integrated MEMS device is disclosed. The method comprises forming a MEMS wafer. Forming a MEMS wafer includes forming one cavity in a first semiconductor layer, bonding the first semiconductor layer to a second semiconductor layer with a dielectric layer disposed between the first semiconductor layer and the second semiconductor layer, and etching at least one via through the second semiconductor layer and the dielectric layer and depositing a conductive material on the second semiconductor layer and filling the at least one via. Forming a MEMS wafer also includes patterning and etching the conductive material to form one standoff and depositing a germanium layer on the conductive material, patterning and etching the germanium layer, and patterning and etching the second semiconductor layer to define one MEMS structure. The method also includes bonding the MEMS wafer to a base substrate. | 2014-07-31 |
20140213008 | Capacitive Sensors and Methods for Forming the Same - A device includes a semiconductor substrate, and a capacitive sensor having a back-plate, wherein the back-plate forms a first capacitor plate of the capacitive sensor. The back-plate is a portion of the semiconductor substrate. A conductive membrane is spaced apart from the semiconductor substrate by an air-gap. A capacitance of the capacitive sensor is configured to change in response to a movement of the polysilicon membrane. | 2014-07-31 |
20140213009 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - An optical component is fixed precisely on a sensor chip. After a sensor chip including a front surface having a sensor plane with a plurality of light receiving elements is mounted face-up over a wiring substrate, an adhesive is disposed on the front surface of the sensor chip at a plurality of positions, and a plurality of spacers having adherence is formed by curing this adhesive. Then, an adhesive paste is disposed on the front surface of the sensor chip. Then, an optical component held by a bonding tool is disposed on the front surface via the spacer and the adhesive. After that, the bonding tool is separated from the optical component and the optical component is fixed by curing the adhesive in a state in which a load is not applied to the optical component. | 2014-07-31 |
20140213010 | WAFER PACKAGING METHOD - A wafer packaging method includes the following steps. A light transmissive carrier is provided. A hydrolytic temporary bonding layer is formed on the light transmissive carrier. A first surface of a light transmissive protection sheet is bonded to the hydrolytic temporary bonding layer, such that the hydrolytic temporary bonding layer is located between the light transmissive protection sheet and the light transmissive carrier. A second surface of the light transmissive protection sheet facing away from the first surface is bonded to a third surface of a wafer. The light transmissive carrier, the hydrolytic temporary bonding layer, the light transmissive protection sheet, and the wafer are immersed in a high temperature liquid, such that adhesion force of the hydrolytic temporary bonding layer is eliminated. The light transmissive protection sheet and the wafer are obtained from the high temperature liquid. | 2014-07-31 |
20140213011 | METHOD OF MANUFACTURING CMOS IMAGE SENSOR - A CIS and a method of manufacturing the same, the CIS including a substrate having a first surface and second surface opposite thereto, the substrate including an APS array region including a photoelectric transformation element and a peripheral circuit region; an insulating interlayer on the first surface of the substrate and including metal wirings electrically connected to the photoelectric transformation element; a light blocking layer on the peripheral circuit region of the second surface of the substrate, exposing the APS array region, and including a plurality of metal wiring patterns spaced apart from one another to form at least one drainage path along a boundary region between the APS array region and the peripheral circuit region; a color filter layer on the second surface of the substrate covering the APS array region and the light blocking layer; and a microlens on the color filter layer on the APS array region. | 2014-07-31 |
20140213012 | METHOD AND SYSTEM FOR IMAGE SENSOR AND LENS ON A SILICON BACK PLANE WAFER - A method for forming image sensors includes providing a substrate and forming a plurality of photo diode regions, each of the photo diode regions being spatially disposed on the substrate. The method also includes forming an interlayer dielectric layer overlying the plurality of photo diode regions, forming a shielding layer formed overlying the interlayer dielectric layer, and applying a silicon dioxide bearing material overlying the shielding layer. The method further includes etching portions of the silicon dioxide bearing material to form a plurality of first lens structures, and continuing to form each of the plurality of first lens structures to provide a plurality of finished lens structures. | 2014-07-31 |
20140213013 | PHOTOVOLTAIC INTERCONNECT SYSTEMS, DEVICES, AND METHODS - Photovoltaic modules may include multiple flexible thin film photovoltaic cells electrically connected in series by a substantially transparent top sheet having an embedded conductive wire grid pattern. Methods of manufacturing photovoltaic modules including integrated multi-cell interconnections are provided. | 2014-07-31 |
20140213014 | ION IMPLANTATION BASED EMITTER PROFILE ENGINEERING VIA PROCESS MODIFICATIONS - A method of tailoring the dopant profile of a workpiece by modulating one or more operating parameters is disclosed. In one embodiment, the workpiece may be a solar cell and the desired dopant profile may include a heavily doped surface region and a highly doped region. These two regions can be generated by varying one or more of the parameters of the ion implanter. For example, the extraction voltage may be changed to affect the energy of the implanted ions. The ionization energy can be changed to affect the species of ions being generated from the source gas. In another embodiment, the source gasses that are ionized may be changed to affect the species being generated. After the implant has been performed, thermal processing is performed which minimizes the diffusion of the ions in the workpiece. | 2014-07-31 |
20140213015 | LASER PATTERNING PROCESS FOR BACK CONTACT THROUGH-HOLES FORMATION PROCESS FOR SOLAR CELL FABRICATION - Embodiments of the invention contemplate formation of a high efficiency solar cell utilizing a laser patterning process to form openings in a passivation layer while maintaining good film properties of the passivation layer on a surface of a solar cell substrate. In one embodiment, a method of forming an opening in a passivation layer on a back surface of a solar cell substrate includes transferring a substrate having a passivation layer formed on a back surface of a substrate into a laser patterning apparatus, the substrate having a first type of doping atom on the back surface of the substrate and a second type of doping atom on a front surface of the substrate, providing laser radiation generated by the laser patterning apparatus from the front surface transmitting through the substrate to the passivation layer disposed on the back surface of the substrate, and forming openings in the passivation layer. | 2014-07-31 |
20140213016 | IN SITU SILICON SURFACE PRE-CLEAN FOR HIGH PERFORMANCE PASSIVATION OF SILICON SOLAR CELLS - Embodiments of the invention generally relate to methods for fabricating photovoltaic devices, and more particularly to methods for in-situ cleaning of a solar cell substrates. In one embodiment, a method of manufacturing a solar cell device is provided. The method comprises exposing a single or poly crystalline silicon substrate to a wet clean process to clean the surfaces of the crystalline substrate, loading the crystalline silicon substrate into a processing system having a vacuum environment, exposing at least one surface of the crystalline silicon substrate to an in-situ cleaning process in the vacuum environment of the processing system, and forming one or more passivation layers on at least one surface of the crystalline silicon substrate in the processing system. | 2014-07-31 |
20140213017 | METHOD OF FABRICATING SEMICONDUCTOR DEVICE - A method of fabricating a semiconductor device includes attaching a semiconductor substrate to a carrier using a carrier fixing layer, where the semiconductor substrate including a plurality of semiconductor chips. The method further includes forming gaps between adjacent ones of the chips. The gaps may be formed using one or more chemicals or light which act to remove portions of the semiconductor substrate to expose the carrier fixing layer. Additional portions of the carrier fixing layer are then removed to allow for removal of the chips from the carrier. | 2014-07-31 |
20140213018 | METHOD FOR FORMNG A SEMICONDUCTOR DEVICE ASSEMBLY HAVING A HEAT SPREADER - A method includes providing an integrated circuit (IC) die assembly that includes a substrate and an IC die mounted on a portion of a major surface of the substrate, dispensing an interface material on the IC die, positioning a portion of a heat spreader in contact with the interface material, and dispensing an adhesive between one side of the heat spreader facing the IC die assembly and exposed portions of a major surface of an encapsulant on the substrate. | 2014-07-31 |
20140213019 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device includes: forming, in element regions of a semiconductor wafer, electrodes and a insulator on peripheral part of the electrodes so that a height of the insulator is higher than that of the electrodes; forming, on the front face of the semiconductor wafer, a groove for surrounding a periphery of the electrodes with the insulator being sandwiched between the electrodes and the groove, the groove being formed so that a height of the groove is lower than that of the insulator and the groove extends to an outer circumferential edge of the semiconductor wafer; bonding adhesives onto the electrodes in the element regions so that a height of the adhesives is higher than that of the insulator, and bonding, onto the adhesives, a base material for covering the front face of the semiconductor wafer; and processing a rear face of the semiconductor wafer. | 2014-07-31 |
20140213020 | SEMICONDUCTOR DIE MOUNT BY CONFORMAL DIE COATING - A conformal coating on a semiconductor die provides adhesion between the die and a support. No additional adhesive is necessary to affix the die on the support. The conformal coating protects the die during assembly, and serves to electrically insulate the die from electrically conductive parts that the die may contact. The conformal coating may be an organic polymer, such as a parylene, for example. Also, a method for adhering a die onto a support, which may optionally be another die, includes providing a coating of a conformal between the die and the support, and heating the coating between the die and the support. The conformal coating may be provided on a die attach area of a surface of the die, or on a die mount region of a surface of the support, or on both a die attach area of a surface of the die and on a die mount region of a surface of the support; and the conformal coating may be provided following placement of the die on the support. | 2014-07-31 |
20140213021 | MICROELECTRONIC PACKAGES AND METHODS THEREFOR - A method of making a microelectronic assembly can include molding a dielectric material around at least two conductive elements which project above a height of a substrate having a microelectronic element mounted thereon, so that remote surfaces of the conductive elements remain accessible and exposed within openings extending from an exterior surface of the molded dielectric material. The remote surfaces can be disposed at heights from said surface of said substrate which are lower or higher than a height of the exterior surface of the molded dielectric material from the substrate surface. The conductive elements can be arranged to simultaneously carry first and second different electric potentials: e.g., power, ground or signal potentials. | 2014-07-31 |
20140213022 | Method of Manufacturing a Reduced Free-Charge Carrier Lifetime Semiconductor Structure - A method of manufacturing a reduced free-charge carrier lifetime semiconductor structure includes forming a plurality of transistor gate structures in trenches arranged in a semiconductor substrate, forming a body region between adjacent ones of the transistor gate structures and forming an end-of-range irradiation region between adjacent ones of the transistor gate structures, the end-of-range irradiation region having a plurality of vacancies. | 2014-07-31 |
20140213023 | METHOD FOR FABRICATING POWER SEMICONDUCTOR DEVICE - A method for fabricating a power semiconductor device is disclosed. A substrate having thereon a plurality of die regions and scribe lanes is provided. A first epitaxial layer is formed on the substrate. A hard mask is formed on the first epitaxial layer. A trench is etched into the first epitaxial layer through an opening in the hard mask. The opening and the trench both traverse the die regions and scribe lanes in their longitudinal direction. The hard mask is then removed. A second epitaxial layer is formed in the trench. After polishing the second epitaxial layer, a third epitaxial layer is formed to cover the first and second epitaxial layers. | 2014-07-31 |
20140213024 | PRODUCTION OF MULTIPLE SEMICONDUCTOR DEVICES USING A SEMICONDUCTOR PROCESS - In one general aspect, a method can include implanting a first dopant, simultaneously, in a portion of a laterally diffused metal oxide semiconductor (LDMOS) device and in a portion of a resistor device included in a semiconductor device. The method can also include implanting a second dopant, simultaneously, in a portion of the LDMOS device and in a portion of a bipolar junction transistor (BJT) device in the semiconductor device. | 2014-07-31 |
20140213025 | METHOD FOR PRODUCING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - A SGT production method includes a step of forming first and second fin-shaped silicon layers, forming a first insulating film, and forming first and second pillar-shaped silicon layers; a step of forming diffusion layers by implanting an impurity into upper portions of the first and second pillar-shaped silicon layers, upper portions of the first and second fin-shaped silicon layers, and lower portions of the first and second pillar-shaped silicon layers; a step of forming a gate insulating film and first and second polysilicon gate electrodes; a step of forming a silicide in upper portions of the diffusion layers formed in the upper portions of the first and second fin-shaped silicon layers; and a step of depositing an interlayer insulating film, exposing and etching the first and second polysilicon gate electrodes, then depositing a metal, and forming first and second metal gate electrodes. | 2014-07-31 |
20140213026 | TRENCH METAL OXIDE SEMICONDUCTOR FIELD EFFECT TRANSISTOR WITH EMBEDDED SCHOTTKY RECTIFIER USING REDUCED MASKS PROCESS - A trench MOSFET with embedded schottky rectifier having at least one anti-punch through implant region using reduced masks process is disclosed for avalanche capability enhancement and cost reduction. The source regions have a higher doping concentration and a greater junction depth along sidewalls of the trenched source-body contacts than along adjacent channel regions near the gate trenches. | 2014-07-31 |
20140213027 | MEMORY DEVICE HAVING BURIED BIT LINE AND VERTICAL TRANSISTOR AND FABRICATION METHOD THEREOF - A method of forming a buried bit line is provided. A substrate is provided and a line-shaped trench region is defined in the substrate. A line-shaped trench is formed in the line-shaped trench region of the substrate. The line-shaped trench includes a sidewall surface and a bottom surface. Then, the bottom surface of the line-shaped trench is widened to form a curved bottom surface. Next, a doping area is formed in the substrate adjacent to the curved bottom surface. Lastly, a buried conductive layer is formed on the doping area such that the doping area and the buried conductive layer together constitute the buried bit line. | 2014-07-31 |
20140213028 | EPITAXIAL PROCESS - An epitaxial process includes the following steps. A substrate including a first area and a second area is provided. A first gate and a second gate are formed respectively on the substrate of the first area and the second area. A first spacer and a second spacer are respectively formed on the substrate beside the first gate and the second gate at the same time. A first epitaxial structure is formed beside the first spacer and then a second epitaxial structure is formed beside the second spacer by the first spacer and the second spacer respectively. | 2014-07-31 |
20140213029 | PRE-GATE, SOURCE/DRAIN STRAIN LAYER FORMATION - A method produces a transistor. The method forms a strain-producing layer on a base layer and then removes at least one portion of the strain-producing layer to create at least one opening in the strain-producing layer. This leaves first and second portions of the strain-producing layer on the substrate. The first and second portions of the strain-producing layer comprise source and drain stressor regions of the transistor. The method then grows a channel region in the opening of the strain-producing layer from the base layer, forms a gate insulator on the channel region, and forms a gate conductor on the gate insulator. | 2014-07-31 |
20140213030 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - To provide a manufacturing method of a semiconductor device including a memory cell having a higher reliability. | 2014-07-31 |
20140213031 | FinFETs and Methods for Forming the Same - A method includes recessing isolation regions, wherein a portion of a semiconductor strip between the isolation regions is over top surfaces of the recessed isolation regions, and forms a semiconductor fin. A dummy gate is formed to cover a middle portion of the semiconductor fin. An Inter-Layer Dielectric (ILD) is formed to cover end portions of the semiconductor fin. The dummy gate is then removed to form a first recess, wherein the middle portion is exposed to the first recess. The middle portion of the semiconductor fin is removed to form a second recess. An epitaxy is performed to grow a semiconductor material in the second recess, wherein the semiconductor material is between the end portions. A gate dielectric and a gate electrode are formed in the first recess. The gate dielectric and the gate electrode are over the semiconductor material. | 2014-07-31 |
20140213032 | Process For Forming Resistive Switching Memory Cells Using Nano-Particles - A process for forming reversible resistance-switching memory cells having resistance-switching nano-particles which provide a reduced contact area to top and bottom electrodes of the memory cells, thereby limiting a peak current. Recesses are formed in a layered semiconductor material above the bottom electrodes, and one or more coatings of nano-particles are applied. The nano-particles self-assemble in the recesses so that they are positioned in a controlled manner. A top electrode material is then deposited. In one approach, the recesses are formed by spaced-apart trenches, and the nano-particles self-assemble along the spaced-apart trenches. In another approach, the recesses for each resistance-switching memory cell are separate from one another, and the resistance-switching memory cells are pillar-shaped. The coatings can be provided in one layer, or in multiple layers which are separated by an insulation layer. | 2014-07-31 |
20140213033 | METHODS FOR FABRICATING ELECTRICALLY-ISOLATED FINFET SEMICONDUCTOR DEVICES - Fabrication methods for semiconductor device structures are provided. In an exemplary embodiment, a method of fabricating an electrically-isolated FinFET semiconductor device includes the steps of forming a silicon oxide layer over a semiconductor substrate including a silicon material and forming a first hard mask layer over the silicon oxide layer. The method further includes the steps of forming a first plurality of void spaces in the first hard mask layer and forming a second hard mask layer in the first plurality of void spaces. Still further, the method includes the steps of removing the remaining portions of the first hard mask layer, thereby forming a second plurality of void spaces in the second hard mask layer, extending the second plurality of void spaces into the silicon oxide layer, and forming a plurality of fin structures in the extended second plurality of void spaces. | 2014-07-31 |
20140213034 | METHOD FOR FORMING ISOLATION STRUCTURE - A method for forming an isolation structure includes the following steps. A hard mask layer is formed on a substrate and a trench is formed in the substrate and the hard mask layer. A protective layer is formed to cover the trench and the hard mask layer. A first isolation material is filled into the trench. An etching process is performed to etch back part of the first isolation material. | 2014-07-31 |
20140213035 | METHOD OF FORMING BURIED WORD LINE STRUCTURE - A method of forming a buried word line structure is provided. A first mask layer, an interlayer and a second mask layer are sequentially formed on a substrate, wherein the second mask layer has a plurality of mask patterns and a plurality of gaps arranged alternately, and the gaps includes first gaps and second gaps arranged alternately. A dielectric pattern is formed in each first gap and spacers are simultaneously formed on sidewalls of each second gap, wherein a first trench is formed between the adjacent spacers and exposes a portion of the first mask layer. The mask patterns are removed to form second trenches. An etching process is performed by using the dielectric patterns and the spacers as a mask, so that the first trenches are deepened to the substrate and the second trenches are deepened to the first mask layer. | 2014-07-31 |
20140213036 | FORMING STRUCTURES ON RESISTIVE SUBSTRATES - A substrate includes a first region having a first resistivity, for optimizing a field effect transistor, a second region having a second resistivity, for optimizing an npn subcollector of a bipolar transistor device and triple well, a third region having a third resistivity, with a high resistivity for a passive device, a fourth region, substantially without implantation, to provide low perimeter capacitance for devices. | 2014-07-31 |
20140213037 | METHODS FOR FABRICATING INTEGRATED CIRCUITS HAVING CONFINED EPITAXIAL GROWTH REGIONS - Methods are provided for fabricating integrated circuits. In accordance with one embodiment, the method includes forming a portion of a semiconductor substrate at least partially bounded by a confinement isolation material. A liner dielectric is formed overlying the confinement isolation material and is treated to passivate a surface thereof An epitaxial layer of semiconductor material is then grown overlying the portion of semiconductor substrate. | 2014-07-31 |
20140213038 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE AND MANUFACTURING APPARATUS OF SEMICONDUCTOR DEVICE - According to one embodiment, a method of manufacturing a semiconductor device includes providing a substrate, supplying a first liquid including a terpene to a surface of the substrate, supplying a second liquid including a silicon-containing compound to the surface of the substrate, and converting the silicon-containing compound to a silicon oxide compound. | 2014-07-31 |
20140213039 | METHODS OF PROCESSING SUBSTRATES - Methods processing substrates are provided. The method may include providing a bonding layer between a substrate and a carrier to bond the substrate to the carrier, processing the substrate while the substrate is supported by the carrier, and removing the bonding layer to separate the substrate from the carrier. The bonding layer may include a thermosetting glue layer and thermosetting release layers provided on opposing sides of the thermosetting glue layer. | 2014-07-31 |
20140213040 | LASER PROCESSING METHOD - A laser processing method for performing laser processing to a workpiece. The laser processing method includes: a filament forming step of applying a first pulsed laser beam having a transmission wavelength to the workpiece to thereby form a filament as an optical transmission line in the workpiece so that the filament extends from the surface of the workpiece to be irradiated with the first pulsed laser beam to the inside of the workpiece, the filament having a refractive index higher than that of the workpiece; and a laser processing step of applying a second pulsed laser beam to the filament after performing the filament forming step to thereby transmit the second pulsed laser beam along the filament, thereby processing the workpiece with the second pulsed laser beam. | 2014-07-31 |
20140213041 | LASER AND PLASMA ETCH WAFER DICING WITH ETCH CHAMBER SHIELD RING FOR FILM FRAME WAFER APPLICATIONS - Laser and plasma etch wafer dicing where a mask is formed covering ICs formed on the wafer, as well as any bumps providing an interface to the ICs. The semiconductor wafer is coupled to a film frame by an adhesive film. The mask is patterned by laser scribing to provide a patterned mask with gaps. The laser scribing exposes regions of the semiconductor wafer, below thin film layers from which the ICs are formed. The semiconductor wafer is plasma etched through the gaps in the patterned mask while the film frame is maintained at an acceptably low temperature with a chamber shield ring configured to sit beyond the wafer edge and cover the frame. The shield ring may be raised and lowered, for example, on lifter pins to facilitate transfer of the wafer on frame. | 2014-07-31 |
20140213042 | SUBSTRATE DICING BY LASER ABLATION & PLASMA ETCH DAMAGE REMOVAL FOR ULTRA-THIN WAFERS - Methods of dicing substrates having a plurality of ICs. A method includes forming a mask, patterning the mask with a femtosecond laser scribing process to provide a patterned mask with gaps, and ablating through an entire thickness of a semiconductor substrate to singulate the IC. Following laser-based singulation, a plasma etch is performed to remove a layer of semiconductor sidewall damaged by the laser scribe process. In the exemplary embodiment, a femtosecond laser is utilized and a 1-3 μm thick damage layer is removed with the plasma etch. Following the plasma etch, the mask is removed, rendering the singulated die suitable for assembly/packaging. | 2014-07-31 |
20140213043 | METHOD OF RADIATIVELY GROOVING A SEMICONDUCTOR SUBSTRATE - A method of radiatively scribing a substantially planar semiconductor substrate using a laser scribing apparatus, uses a laser scribing head configured and arranged to produce a two-dimensional array of laser beam spots to effect the scribing. In an embodiment, the spots of the array extend substantially parallel to X and Y directions in the plane of the substrate. In an embodiment, spots at a periphery in one or both directions of the array have a lower intensity than laser beams in a central portion of the array. | 2014-07-31 |
20140213044 | METHOD FOR PRODUCING PERIODIC CRYSTALLINE SILICON NANOSTRUCTURES - A method for producing periodic crystalline silicon nanostructures of large surface area by: generating a periodic structure having a lattice constant of between 100 nm and 2 μm on a substrate, the substrate used being a material which is stable at up to at least 570° C., and the structure being produced with periodically repeating shallow and steep areas/flanks, and, subsequently, depositing silicon by directed deposition onto the periodically structured substrate, with a thickness in the range from 0.2 to 3 times the lattice constant, or 40 nm to 6 μm, at a substrate temperature of up to 400° C., followed by thermally treating the deposited Si layer to effect solid-phase crystallization, at temperatures between 570° C. and 1400° C., over a few minutes up to several days, and optionally subsequently wet-chemically selective etching to remove resultant porous regions of the Si layer. | 2014-07-31 |
20140213045 | NITRIDE ELECTRONIC DEVICE AND METHOD FOR MANUFACTURING THE SAME - The present disclosure relates to a nitride electronic device and a method for manufacturing the same, and particularly, to a nitride electronic device and a method for manufacturing the same that can implement various types of nitride integrated structures on the same substrate through a regrowth technology (epitaxially lateral over-growth: ELOG) of a semi-insulating gallium nitride (GaN) layer used in a III-nitride semiconductor electronic device including Group III elements such as gallium (Ga), aluminum (Al) and indium (In) and nitrogen. | 2014-07-31 |
20140213046 | Fabrication of III-Nitride Layers - A method that includes implantation of dopants while a III-nitride body is being grown on a substrate, and an apparatus for the practice of the method. | 2014-07-31 |
20140213047 | FABRICATION OF ULTRA-SHALLOW JUNCTIONS - A method of forming an ultra-shallow junction in a semiconductor substrate. The method includes forming an amorphous region in a semiconductor substrate by performing a pre-amorphization implant step and implanting one or more dopants in the amorphous region by performing a monolayer doping step. The semiconductor substrate is then thermally treated to activate the implanted dopant in the amorphous region to thereby form an ultra-shallow junction in the semiconductor substrate. The thermal treatment can be performed without any oxide cap overlying the implanted amorphous region. | 2014-07-31 |
20140213048 | Method of Making a FinFET Device - A FinFET device is fabricated by first receiving a FinFET precursor. The FinFET precursor includes a substrate, fins on the substrate, isolation regions on sides of the fins and dummy gate stacks on the substrate including wrapping a portion of the fin, which is referred to as a gate channel region. The dummy gate stacks is removed to form a gate trench and a gate dielectric layer is deposited in the gate trench. A metal stressor layer (MSL) is conformably deposited on the gate dielectric layer. A capping layer is deposited on the MSL. A thermal treatment is applied to the MSL to achieve a volume expansion. Then the capping layer is removed and a metal gate (MG) is formed on the MSL. | 2014-07-31 |
20140213049 | METHOD FOR PROCESSING A CARRIER, METHOD FOR FABRICATING A CHARGE STORAGE MEMORY CELL, METHOD FOR PROCESSING A CHIP, AND METHOD FOR ELECTRICALLY CONTACTING A SPACER STRUCTURE - A method for processing a carrier accordance with various embodiments may include: forming a structure over the carrier, the structure including at least two adjacent structure elements arranged at a first distance between the same; depositing a spacer layer over the structure, wherein the spacer layer may be deposited having a thickness greater than half of the first distance, wherein the spacer layer may include electrically conductive spacer material; removing a portion of the spacer layer, wherein spacer material of the spacer layer may remain in a region between the at least two adjacent structure elements; and electrically contacting the remaining spacer material. | 2014-07-31 |
20140213050 | METHOD OF MAKING A DIE WITH RECESSED ALUMINUM DIE PADS - A method for making a semiconductor device comprises forming an electrical interconnect layer, forming a first dielectric layer over the interconnect layer, forming an opening in the first dielectric layer over a first electrical interconnect of the interconnect layer, forming an aluminum layer over the first dielectric layer, etching the aluminum layer to form an aluminum die pad, forming a second dielectric layer over the aluminum die pad and the first dielectric layer, and forming a conductive via through the first and second dielectric layers to contact a second electrical interconnect of the interconnect layer. | 2014-07-31 |
20140213051 | Hybrid Interconnect Scheme and Methods for Forming the Same - A device includes a first low-k dielectric layer, and a copper-containing via in the first low-k dielectric layer. The device further includes a second low-k dielectric layer over the first low-k dielectric layer, and an aluminum-containing metal line over and electrically coupled to the copper-containing via. The aluminum-containing metal line is in the second low-k dielectric layer. | 2014-07-31 |
20140213052 | System for Self-Aligned Contacts - A system for forming self-aligned contacts includes electroplating a first metal contact onto a Group III-V semiconductor substrate, the first metal contact having a greater height than width and having a straight sidewall profile, etching back the semiconductor substrate down to a base layer to expose an emitter semiconductor layer under the first metal contact, conformally depositing a dielectric layer on a vertical side of the first metal contact, a vertical side of the emitter semiconductor layer and on the base layer, anisotropically etching the dielectric layer off of the semiconductor substrate to form a dielectric sidewall spacer on the vertical side of the first metal contact and providing a second metal contact immediately adjacent the dielectric sidewall spacer. | 2014-07-31 |
20140213053 | SEMICONDUCTOR DEVICE INCLUDING SUBSTRATE CONTACT AND RELATED METHOD - A method of forming a contact on a semiconductor device is disclosed. The method includes: forming a mask on the semiconductor device, the mask exposing at least one contact node disposed within a trench in a substrate of the semiconductor device; performing a first substrate contact etch on the semiconductor device, the first substrate contact etch recessing the exposed contact node within the trench; removing a set of node films disposed above the exposed contact node and on the sides of the trench; and forming a contact region within the trench above the exposed contact node, the contact region contacting the substrate. | 2014-07-31 |
20140213054 | EXPOSING METHOD AND METHOD OF FORMING A PATTERN USING THE SAME - An exposing method includes irradiating a first light having a first energy to a first exposed region of a photoresist film through a first shot region of a mask, and irradiating a second light having a second energy to the first exposed region of the photoresist film through a second shot region of the mask. | 2014-07-31 |
20140213055 | SEMICONDUCTOR MANUFACTURING DEVICE AND PROCESSING METHOD - A semiconductor manufacturing device includes a stage, a plurality of pins, and a driving unit. The stage includes a mounting surface. The mounting surface has a first region for mounting thereon a substrate, and a second region for mounting thereon a focus ring. The second region is provided to surround the first region. A plurality of holes is formed in the stage. The holes extend in a direction that intersects the mounting surface while passing through the boundary between the first region and the second region. The pins are provided in the respective holes. Each of the pins has a first and a second upper end surface. The second. upper end surface is provided above the first upper end surface, and is offset towards the first region with respect to the first upper end surface. The driving unit moves the pins up and down in the aforementioned direction. | 2014-07-31 |
20140213056 | APPARATUS, METHOD, AND COMPOSITION FOR FAR EDGE WAFER CLEANING - A wafer cleaning apparatus includes a polishing unit used in chemical mechanical polishing (CMP) of a wafer and a cleaning dispensing unit arranged to direct cleaning fluids toward a far edge of the wafer after the CMP of the wafer. A wafer cleaning method includes CMP of a wafer by a polishing unit and directing cleaning fluids toward a far edge of the wafer after the CMP of the wafer by a cleaning dispensing unit. Another method can include CMP, applying deionized water, and applying pH adjuster having a pH range from about 2 to about 13. | 2014-07-31 |
20140213057 | CHEMICAL MECHANICAL POLISHING (CMP) COMPOSITION COMPRISING A GLYCOSIDE - A chemical mechanical polishing (CMP) composition comprising (A) inorganic particles, organic particles, or a mixture or composite thereof, (B) a glycoside of the formulae 1 to 6 wherein R | 2014-07-31 |
20140213058 | PATTERN FORMATION METHOD AND PATTERN FORMATION APPARATUS - According one embodiment, a pattern formation method forming a resist layer on a pattern formation surface by pressing a template provided with a concave-convex from above the resist layer to form a resist pattern on the pattern formation surface, includes: forming a resist layer in a first region having an area smaller than an area of the pattern formation surface and in a second region other than the first region of the pattern formation surface; pressing a template against the resist layer; irradiating the resist layer with light via the template to form a first resist layer in the first region, curing of the first resist layer being suppressed, and form the resist pattern including a second resist layer, curing of the second resist layer proceeds in the second region; and removing the first resist layer from the first region, the curing of the first resist layer being suppressed. | 2014-07-31 |
20140213059 | BORON-DOPED CARBON-BASED HARDMASK ETCH PROCESSING - Boron-doped carbon-based hardmask etch processing is described. In an example, a method of patterning a film includes etching a boron-doped amorphous carbon layer with a plasma based on a combination of CH | 2014-07-31 |
20140213060 | METHOD OF PATTERNING A LOW-K DIELECTRIC FILM - Methods of patterning low-k dielectric films are described. In an example, In an embodiment, a method of patterning a low-k dielectric film involves forming and patterning a metal nitride mask layer above a low-k dielectric layer. The low-k dielectric layer is disposed above a substrate. The method also involves passivating the metal nitride mask layer by treating with a plasma based on O | 2014-07-31 |
20140213061 | DUCTILE MODE DRILLING METHODS FOR BRITTLE COMPONENTS OF PLASMA PROCESSING APPARATUSES - A method of drilling holes comprises ductile mode drilling the holes in a component of a plasma processing apparatus with a cutting tool wherein the component is made of a nonmetallic hard and brittle material. The method comprises drilling each hole in the component by controlling a depth of cut while drilling such that a portion of the brittle material undergoes high pressure phase transformation and forms amorphous portions of the brittle material during chip formation. The amorphous portions of the brittle material are removed from each hole such that a wall of each hole formed in the component has an as drilled surface roughness (Ra) of about 0.2 to 0.8 μm. | 2014-07-31 |
20140213062 | SILICON DIOXIDE-POLYSILICON MULTI-LAYERED STACK ETCHING WITH PLASMA ETCH CHAMBER EMPLOYING NON-CORROSIVE ETCHANTS - Multilayered stacks having layers of silicon interleaved with layers of a dielectric, such as silicon dioxide, are plasma etched with non-corrosive process gas chemistries. Etching plasmas of fluorine source gases, such as SF | 2014-07-31 |
20140213063 | METHOD AND SYSTEM FOR ENERGIZED AND PRESSURIZED LIQUIDS FOR CLEANING/ETCHING APPLICATIONS IN SEMICONDUCTOR MANUFACTURING - A wet chemical processing method and apparatus for use in semiconductor manufacturing and in other applications, is provided. The method and apparatus provide for energizing a processing liquid such as a cleaning or etching liquid using ultrasonic, megasonic or other energy waves or by combining the liquid with a pressurized gas to form a pressurized spray, or using both. The energized, pressurized fluid is directed to a substrate surface using a fluid delivery system and overcomes any surface tensions associated with liquids, solids, or air and enables the processing liquid to completely fill any holes such as contact holes, via holes or trenches, formed on the semiconductor substrate. | 2014-07-31 |
20140213064 | SEMICONDUCTOR MANUFACTURING APPARATUS AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - A semiconductor manufacturing apparatus according to the present embodiment comprises a chamber. A chemical-agent supply part is configured to supply a water-repellent agent or an organic solvent to a surface of a semiconductor substrate having been cleaned with a cleaning liquid in the chamber. A spray part is configured to spray a water-capture agent capturing water into an atmosphere in the chamber. | 2014-07-31 |
20140213065 | Method for Forming Layer Constituted by Repeated Stacked Layers - A method for forming a layer constituted by repeated stacked layers includes: forming a first layer and a second layer on a substrate under different deposition conditions to form a stacked layer, wherein the film stresses of the first and second layers are tensile or compressive and opposite to each other, and the wet etch rates of the first and second layers are at least 50 times different from each other; and repeating the above step to form a layer constituted by repeated stacked layers, wherein the deposition conditions for forming at least one stacked layer are different from those for forming another stacked layer. | 2014-07-31 |
20140213066 | LAYOUT DECOMPOSITION METHOD AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE APPLYING THE SAME - A layout decomposition method and a method for manufacturing a semiconductor device applying the same are provided. According to the layout decomposition method, a design layout is received by the logic processor of a computing system. A design rule for layout decomposition is then identified by the logic processor, including identifying dense areas (areas with densely distributed features) on a substrate, and identifying areas with odd-numbered features on the substrate. Next, a first mask with a first pattern and a second mask with a second pattern are generated corresponding to results of design rule identification by the computing system for fabricating patterns of features in at least two of the areas with odd-numbered features in one of the dense areas. | 2014-07-31 |
20140213067 | FILM FORMING METHOD AND FILM FORMING APPARATUS - A film forming method for forming a thin film composed of a SiOCN layer containing at least silicon (Si), oxygen (O), carbon (C) and nitrogen (N) on a surface of a workpiece within an evacuable processing vessel optionally using a silane-based gas, a hydrocarbon gas, a nitriding gas or an oxidizing gas includes forming a first film including at least Si, C and N, and forming a second film including at least Si, C and O. The forming a first film and the forming a second film are set as a cycle and the cycle is performed once or more. | 2014-07-31 |
20140213068 | FILM DEPOSITION APPARATUS AND FILM DEPOSITION METHOD - A film deposition apparatus includes a separation member that extends to cover a rotation center of the turntable and two different points on a circumference of the turntable above the turntable, thereby separating the inside of the chamber into a first area and a second area; a first reaction gas supplying portion that supplies a first reaction gas toward the turntable in the first area; a second reaction gas supplying portion that supplies a second reaction gas toward the turntable in the second area; a first evacuation port that evacuates the first reaction gas and the first separation gas that converges with the first reaction gas; and a second evacuation port that evacuates the second reaction gas and the first separation gas that converges with the second reaction gas. The separation member has a bent portion that substantially fills in a gap between the turntable and the chamber. | 2014-07-31 |
20140213069 | Substrate Processing Apparatus, Method of Manufacturing Semiconductor Device and Non-transitory Computer-readable Recording Medium - A substrate processing apparatus includes a process chamber in which a substrate is accommodated; a source gas supply system configured to supply a source gas onto the substrate; first and second reactive gas supply systems configured to supply a reactive gas onto the substrate via first and second interconnected reactive gas supply pipes, wherein a gas storage unit is installed at the second reactive gas supply pipe to store the reactive gas and the reactive gas is supplied onto the substrate via the gas storage unit; and a control unit configured to control the source gas supply system to supply the source gas onto the substrate and to control the first and second reactive gas supply systems to supply the reactive gas onto the substrate via the first and second reactive gas supply pipes. | 2014-07-31 |
20140213070 | LOW SHRINKAGE DIELECTRIC FILMS - Methods of forming a dielectric layer on a substrate are described, and may include introducing a first precursor into a remote plasma region fluidly coupled with a substrate processing region of a substrate processing chamber A plasma may be formed in the remote plasma region to produce plasma effluents. The plasma effluents may be directed into the substrate processing region. A silicon-containing precursor may be introduced into the substrate processing region, and the silicon-containing precursor may include at least one silicon-silicon bond. The plasma effluents and silicon-containing precursor may be reacted in the processing region to form a silicon-based dielectric layer that is initially flowable when formed on the substrate. | 2014-07-31 |
20140213071 | LASER ANNEALING METHOD AND DEVICE - A laser annealing method for executing laser annealing by irradiating a semiconductor film formed on a surface of a substrate with a laser beam, the method including the steps of, generating a linearly polarized rectangular laser beam whose cross section perpendicular to an advancing direction is a rectangle with an electric field directed toward a long-side direction of the rectangle or an elliptically polarized rectangular laser beam having a major axis directed toward a long-side direction, causing the rectangular laser beam to be introduced to the surface of the substrate, and setting a wavelength of the rectangular laser beam to a length which is about a desired size of a crystal grain in a standing wave direction. | 2014-07-31 |
20140213072 | ROTARY PLUG - A rotary plug includes a base, a plurality of annular slot structures, a plurality of conductive components, a bridging component and a plurality of terminals. An accommodating space is formed on the base. The annular slot structures are respectively disposed on an inner wall of the accommodating space. Each conductive component is disposed inside the corresponding annular slot structure. A protrusion of the conductive component inserts into a hole formed on the annular slot structure. The bridging component is rotatably disposed inside the accommodating space. A first end of the terminal protrudes from a bottom of the bridging component. A second end of the terminal protrudes from a lateral surface of the bridging component and movably inserts into the annular slot structure to electrically contact the conductive component. | 2014-07-31 |
20140213073 | CONDUCTIVE HINGE - Embodiments described herein disclose a conductive hinge that is configured to transfer power across a hinge regardless of the orientation of the faces of the hinge. In embodiments, the conductive hinge may be configured to be a conductive conduit to transfer constant power across the hinge. The conductive hinge may be used in conjunction with a conventional hinge, retrofitted to an existing hinge, and/or disposed within a hinge. | 2014-07-31 |
20140213074 | ELECTRICAL CONNECTOR - A wearable connector includes a housing having a base and a shroud that extends from the base. The shroud includes a tunnel having an open end and an interior surface. The open end of the tunnel is configured to receive a mating connector therein. The base is configured to be mounted to a wearable article. Terminals are held directly by the shroud such that mating segments of the terminals extend at least one of directly on or through the interior surface of the tunnel. The tunnel of the shroud is configured to receive the mating connector into the tunnel through the open end such that the mating segments of the terminals mate with mating terminals of the mating connector within the tunnel. | 2014-07-31 |
20140213075 | SIGNAL TEST DEVICE - A signal test device includes a metal housing, a circuit board, a protection housing, and a number of fasteners. The circuit board is received in the metal housing. A number of sub-miniature-A (SMA) connectors are mounted to a first side of the circuit board. Each SMA connector includes a base body connected to the circuit board, and a connection head connected to the base body and extending out of the metal housing. An interface is mounted to a second side of the circuit board and extending out of the metal housing. The protection housing is mounted to the second end of the circuit board and is received in the metal housing. The first fasteners extend through and fastened to the base bodies and the circuit board. Opposite ends of each first fastener abut against top and bottom of the inner surface of the metal housing. | 2014-07-31 |
20140213076 | ELECTRICAL CONNECTION DEVICE - An electrical connection device is used to be provided in an electronic device casing, and comprises a first circuit board and a second circuit board which are substantially coplanar, a receptacle connector provided to the first circuit board and a plug connector provided to the second circuit board. The receptacle connector comprises a housing and a plurality of first terminals. The housing has a first mating surface, and a pair of sliding contact grooves respectively adjacent to both sides of the first mating surface. The plug connector comprises a body and a plurality of second terminals. The body has a pair of side flanges respectively engaged with and received in the sliding contact grooves. The plug connector is mated with the receptacle connector in a direction perpendicular to a board surface of the first circuit board. | 2014-07-31 |
20140213077 | Primary circuit board non-conductive void having different planar dimensions through board thickness to secure non-conducting locking member of holder - A primary circuit board has a front surface, a back surface, and a non-conductive void. The void has first planar dimensions through a first portion of a thickness of the primary circuit board extending from the front surface to a position between the front and back surfaces, and second planar dimensions through a second portion of the thickness extending from the position at least towards the back surface. A secondary circuit board holder includes a non-conducting locking member insertable into the non-conductive void at the primary circuit board's front surface to secure the holder while a conductive part of the holder is conductively affixed to a conductive part of the primary circuit board. The first planar dimensions are different than the second planar dimensions to permit the primary circuit board's thickness to be greater than a maximum thickness specification of the holder's non-conducting locking member. | 2014-07-31 |
20140213078 | ELECTRONIC DEVICE AND CIRCUIT BOARD MODULE OF THE SAME - An electronic device includes an enclosure and a circuit board module received in the enclosure. The circuit board module includes a printed circuit board defining cutouts, connector units are arranged in the cutouts and electronically connected to the printed circuit board, creating a printed circuit board with a lower profile to allow utilization of more of the saved space above within the electronic device. | 2014-07-31 |
20140213079 | CONNECTOR - A connector comprises a contact and a housing. The contact has a fixed portion, a contact portion, a spring portion and a held portion. The spring portion supports the contact portion. The held portion is located between the fixed portion and the support portion. The housing has a sidewall portion and a bottom portion. The sidewall portion is located outward of the spring portion in a predetermined direction and holds the held portion. The bottom portion is located under the spring portion in a vertical direction perpendicular to the predetermined direction. The housing has a gap between a lower surface of the spring portion and the bottom portion. The bottom portion and the sidewall portion hide the contact except the held portion both when the connector is seen from below along the vertical direction and when the connector is seen from the outside along the predetermined direction. | 2014-07-31 |