31st week of 2019 patent applcation highlights part 66 |
Patent application number | Title | Published |
20190237360 | NANOSHEET STRUCTURE WITH ISOLATED GATE - Structures and methods for making nanosheet structures with an electrically isolating feature associated therewith. The structure includes: a substrate, an epitaxial oxide layer over the substrate, a plurality of stacked nanosheets of semiconductor channel material over the epitaxial layer, and a source/drain semiconductor material located laterally adjacent and on each side of the plurality of stacked nanosheets of semiconductor channel material, where the plurality of nanosheets are decoupled from the source/drain semiconductor material by the epitaxial oxide layer. | 2019-08-01 |
20190237361 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - In a semiconductor device, among first wirings, second wirings and a third wiring formed in the same wiring layer, the first wirings having small wiring width are each composed of a stacked film of a first barrier conductor film, a first conductor film made of a material mainly containing a metal element whose mean free path of electrons is smaller than that of copper, and a second barrier conductor film. Also, among the first wirings, the second wirings and the third wiring formed in the same wiring layer, the second wirings and the third wiring having large wiring width are each composed of a stacked film of a third barrier conductor film and a second conductor film made of copper. | 2019-08-01 |
20190237362 | MEMORY DEVICES AND RELATED METHODS - Apparatuses and methods for stair step formation using at least two masks, such as in a memory device, are provided. One example method can include forming a first mask over a conductive material to define a first exposed area, and forming a second mask over a portion of the first exposed area to define a second exposed area, the second exposed area is less than the first exposed area. Conductive material is removed from the second exposed area. An initial first dimension of the second mask is less than a first dimension of the first exposed area and an initial second dimension of the second mask is at least a second dimension of the first exposed area plus a distance equal to a difference between the initial first dimension of the second mask and a final first dimension of the second mask after a stair step structure is formed. | 2019-08-01 |
20190237363 | CAP STRUCTURE - The present disclosure relates to semiconductor structures and, more particularly, to a cap structure and methods of manufacture. The structure includes: a gate structure composed of conductive gate material; sidewall spacers on the gate structure, extending above the conductive gate material; and a capping material on the conductive gate material and extending over the sidewall spacers on the gate structure. | 2019-08-01 |
20190237364 | Replacement Contacts - The present disclosure describes a method of forming a replacement contact. For example, the replacement contact can include a metal with one or more first sidewall surfaces and a top surface. A first dielectric can be formed to abut the one or more first sidewall surfaces of the metal. A second dielectric can be formed over the first dielectric and the top surface of the metal. An opening in the second dielectric can be formed. A metal oxide structure can be selectively grown on the top surface of the metal, where the metal oxide structure has one or more second sidewall surfaces. One or more spacers can be formed to abut the one or more second sidewall surfaces of the metal oxide structure. Further, the metal oxide structure can be removed. | 2019-08-01 |
20190237365 | MECHANICALLY STABLE COBALT CONTACTS - A cobalt contact includes a dual silicide barrier layer. The barrier layer, which may be formed in situ, includes silicides of titanium and cobalt, and provides an effective adhesion layer between the cobalt contact and a conductive device region such as the source/drain junction of a semiconductor device, eliminating void formation during a metal anneal. | 2019-08-01 |
20190237366 | BEOL SELF-ALIGNED INTERCONNECT STRUCTURE - An interconnect structure is provided that includes an interconnect level that contains an interconnect dielectric material layer having a first electrically conductive via feature, an electrically conductive line feature, and a second electrically conductive via feature embedded in the interconnect dielectric material layer, wherein the first and second via features are self-aligned perpendicularly to, and along the direction of, the electrically conductive line feature. | 2019-08-01 |
20190237367 | METHOD FOR PRODUCING PILLAR-SHAPED SEMICONDUCTOR DEVICE - The method for producing a pillar-shaped semiconductor device includes a step of forming a tubular SiO | 2019-08-01 |
20190237368 | FIN-FET DEVICES - Fin-FET device is provided including a substrate, fin structures protruding from the substrate, and an isolation structure covering a portion of sidewall surfaces of the fin structures with a top surface lower than the fin structures. Gate structures are formed on the isolation layer across the fin structures. Doped source/drain regions are formed in the fin structures on opposite sides of each gate structure. A metal contact layer is formed on entire surfaces of the doped source/drain regions and converted from a metal layer through a reaction annealing process. A dielectric layer is formed on the metal contact layer and the gate structures. A top surface of the dielectric layer is higher than the top surfaces of the gate structures. Conductive plugs are formed through the dielectric layer and in contact with a portion of the metal contact layer. | 2019-08-01 |
20190237369 | METHOD FOR CHARACTERIZING OHMIC CONTACT ELECTRODE PERFORMANCE OF SEMICONDUCTOR DEVICE - The present disclosure provides a method for characterizing ohmic contact electrode performance of a semiconductor device. The method comprises: preparing two sets of testing patterns on a semiconductor device; testing resistance values of the two sets of testing patterns respectively; calculating a sheet resistance of an ohmic contact area according to the obtained resistance values; and evaluating the ohmic contact electrode performance of the semiconductor device according to the sheet resistance of the ohmic contact electrode. | 2019-08-01 |
20190237370 | System and Method for Test Key Characterizing Wafer Processing State - Disclosed herein is a method for forming a test key system for characterizing wafer processing states, the method comprising forming a plurality of shallow trench isolation structures (STIs) on a substrate of a wafer and in a scribe line of the wafer and forming a test key on the substrate of a wafer and in the scribe line of the wafer. Forming the test key comprises forming at least one test key group having a plurality of test key series, each of the plurality of test key series having a plurality of test pads, each one of the plurality of test key series having a first physical characteristic different from the first physical characteristic of other test key series the at least one first test key group. | 2019-08-01 |
20190237371 | STIFFENER FOR PROVIDING UNIFORMITY IN MICROELECTRONIC PACKAGES - In one embodiment, an apparatus includes a microelectronic package comprising a plurality of semiconductor chips connected to a substrate and a stiffener mounted on the substrate. The stiffener is mounted on the substrate with the semiconductor chips disposed within an opening in the stiffener and the opening defines an asymmetric shape relative to the semiconductor chips to control overall warpage in the microelectronic package by the stiffener. | 2019-08-01 |
20190237372 | Power Semiconductor Module Arrangement and Method for Producing the Same - A power semiconductor module arrangement includes a substrate arranged in a housing. The substrate includes a first metallization layer arranged on a first side of a dielectric insulation layer and a second metallization layer arranged on a second side of the dielectric insulation layer. At least one semiconductor body is mounted on a first surface of the first metallization layer facing away from the dielectric insulation layer. A connecting element is arranged on and electrically connected to the first surface. A contact element is inserted into and electrically connected to the connecting element, and extends from the connecting element through an interior of the housing and through an opening in the cover of the housing to an outside of the housing in a direction perpendicular to the first surface. A hard encapsulation is arranged adjacent to the first metallization layer and at least partly fills the inside of the housing. | 2019-08-01 |
20190237373 | CHIP PACKAGE MODULE AND CIRCUIT BOARD STRUCTURE COMPRISING THE SAME - A chip package module includes an encapsulation layer, a chip, a substrate and a plurality of blind-hole electrodes. The encapsulation layer includes a first surface and a second surface opposite to the first surface. The chip includes a third surface and a fourth surface opposite to the third surface. A metal bump is fabricated on the third surface of the chip. The chip is embedded into the encapsulation layer from the first surface of the encapsulation layer. The metal bump is exposed from the first surface of the encapsulation layer. The substrate includes a metal layer, wherein the metal layer of the substrate is bonded to the chip through the metal bump. The plurality of blind-hole electrodes pass through the second surface of the encapsulation layer and are electrically connected to the metal layer of the substrate. | 2019-08-01 |
20190237374 | ELECTRONIC PACKAGE AND METHOD FOR FABRICATING THE SAME - An electronic package and a method for fabricating the same are provided. The method includes: forming a circuit structure on an encapsulant; embedding a first electronic component and a plurality of conductive posts in the encapsulant; and disposing a second electronic component on the circuit structure. Since the first and second electronic components are arranged on opposite sides of the circuit structure, the electronic package can provide multi-function and high efficiency. | 2019-08-01 |
20190237375 | FAN-OUT SENSOR PACKAGE - A fan-out sensor package includes: a redistribution portion having a through-hole and including a wiring layer and vias; a first semiconductor chip having an active surface having a sensing region of which at least a portion is exposed through the through-hole and first connection pads disposed in the vicinity of the sensing region; a second semiconductor chip disposed side by side with the first semiconductor chip in a horizontal direction and having second connection pads; dam members disposed in the vicinity of the first connection pads; an encapsulant encapsulating the redistribution portion, the first semiconductor chip, and the second semiconductor chip; and electrical connection structures electrically connecting the first connection pads and the second connection pads to the wiring layer or the vias of the redistribution portion. | 2019-08-01 |
20190237376 | SEMICONDUCTOR PACKAGES AND METHODS OF FORMING THE SEMICONDUCTOR PACKAGES - A package substrate of a semiconductor package includes conductive lines of a first layer disposed on a first surface of a base layer and conductive lines of a second layer disposed on a second surface of the base layer. An opening hole located between a first remaining portion and a second remaining portion to separate the first and second remaining portions from each other. The first remaining portion is electrically connected to a first conductive line among the conductive lines of the second layer, and the second remaining portion is electrically connected to a second conductive line among the conductive lines of the second layer. | 2019-08-01 |
20190237377 | ELECTRONIC DEVICE - An electronic device has a substrate | 2019-08-01 |
20190237380 | IMAGING UNIT AND IMAGING APPARATUS - An imaging unit comprising an imaging chip and a mounting substrate that has the imaging chip mounted thereon and includes a first metal layer for outputting a signal generated by the imaging chip to the outside. An imaging apparatus comprises an imaging unit that includes an imaging chip and a mounting substrate that has the imaging chip mounted thereon and includes a first metal layer for outputting a signal generated by the imaging chip to the outside. | 2019-08-01 |
20190237381 | SEMICONDUCTOR DEVICE - A semiconductor device includes a first semiconductor element having an upper electrode and a lower electrode, a first upper heat sink connected to the upper electrode, and a first lower heat sink connected to the lower electrode. The first lower heat sink is opposed to the first upper heat sink such that the first semiconductor element is sandwiched between the upper and lower heat sinks. One of the first upper heat sink and the first lower heat sink is a laminated substrate having an insulator substrate (such as a ceramic substrate) and conductor layers disposed on opposite surfaces of the insulator substrate, and the other of the first upper heat sink and the first lower heat sink is a conductor plate that is a conductor having higher thermal conductivity than the insulator substrate. | 2019-08-01 |
20190237382 | SEMICONDUCTOR PACKAGE INCLUDING A THERMAL CONDUCTIVE LAYER AND METHOD OF MANUFACTURING THE SAME - A semiconductor package includes a semiconductor chip having a first surface that is an active surface and a second surface opposing the first surface, a first redistribution portion disposed on the first surface, the first redistribution portion including a lower wiring layer electrically connected to the semiconductor chip, a thermal conductive layer disposed on the second surface of the semiconductor chip, a sealing layer surrounding a side surface of the semiconductor chip and a side surface of the thermal conductive layer, and a second redistribution portion disposed on the sealing layer, the second redistribution portion including a first upper wiring layer connected to the thermal conductive layer, the second redistribution portion including a second upper wiring layer electrically connected to the semiconductor chip. | 2019-08-01 |
20190237383 | HEAT SINK INTERFACE FOR A DEVICE - This application discloses an device disposed on a substrate, and a heat sink disposed on the substrate over the device. The heat sink disposed on the substrate forms a cavity to hold a fluid between the heat sink and the device. The fluid can absorb heat emitted by the device and transfer at least a portion of the absorbed heat to the heat sink. A gasket can be disposed between and in contact with the substrate and the heat sink. The gasket can prevent the fluid from exiting the cavity formed by the heat sink disposed on the substrate. The heat sink can have an opening to the cavity, which can be detachably sealed by a plug. The plug can reduce a pressure within the cavity or allow removal of gas bubbles in the fluid held in the cavity. | 2019-08-01 |
20190237384 | POWER MODULE - For a power module comprising at least three levels stacked one above another, including: at least one heat sink ( | 2019-08-01 |
20190237385 | SEMICONDUCTOR STRUCTURE AND ASSOCIATED METHOD FOR MANUFACTURING THE SAME - A method for manufacturing a semiconductor structure is disclosed. The method includes: providing a semiconductor substrate having a plurality of dies thereon; dispensing an underfill material and a molding compound to fill spaces beneath and between the dies; disposing a temporary carrier over the dies; thinning a thickness of the semiconductor substrate; performing back side metallization upon the thinned semiconductor substrate; removing the temporary carrier; and attaching a plate over the dies. An associated semiconductor structure is also disclosed. | 2019-08-01 |
20190237386 | SWITCHGEAR CABINET COMPRISING A CLOSED HOUSING AND A COOLING DEVICE - A switchgear cabinet includes a closed housing, and a cooling device for cooling items of electrical and/or electronic equipment disposed inside the housing. The cooling device includes a first closed cooling circuit containing a first cooling medium for removing heat generated during operation of at least one of the items of equipment from the housing. The first cooling circuit is connected inside the housing to a first heat exchanger for transferring the heat from the at least one item of equipment to the first cooling medium and, outside the housing, to a second heat exchanger for dissipating the heat to an external cooling medium, with the second heat exchanger disposed above the first heat exchanger. The first cooling circuit, the first cooling medium and the first and second heat exchangers are designed to implement heat transfer according to the two-phase thermosiphon principle. | 2019-08-01 |
20190237387 | Delivery roll and method for manufacturing thereof - A delivery roll ( | 2019-08-01 |
20190237388 | POWER ELECTRONICS ASSEMBLIES WITH CIO BONDING LAYERS AND DOUBLE SIDED COOLING, AND VEHICLES INCORPORATING THE SAME - A 2-in-1 power electronics assembly includes a frame with a lower dielectric layer, an upper dielectric layer spaced apart from the lower dielectric layer, and a sidewall disposed between and coupled to the lower dielectric layer and the upper dielectric layer. The lower dielectric layer includes a lower cooling fluid inlet and the upper dielectric layer includes an upper cooling fluid outlet. A first semiconductor device assembly and a second semiconductor device assembly are included and disposed within the frame. The first semiconductor device is disposed between a first lower metal inverse opal (MIO) layer and a first upper MIO layer, and the second semiconductor device is disposed between a second lower MIO layer and a second upper MIO layer. An internal cooling structure that includes the MIO layers provides double sided cooling for the first semiconductor device and the second semiconductor device. | 2019-08-01 |
20190237389 | COOLING BOND LAYER AND POWER ELECTRONICS ASSEMBLIES INCORPORATING THE SAME - A cooling bond layer for a power electronics assembly is provided. The cooling bond layer includes a first end, a second end spaced apart from the first end, a metal matrix extending between the first end and the second end, and a plurality of micro-channels extending through the metal matrix from the first end to the second end. The plurality of micro-channels are configured for a cooling fluid to flow through and remove heat from the cooling bond layer. In some embodiments, the plurality of micro-channels are cylindrical shaped micro-channels. In such embodiments, the plurality of micro-channels may have a generally constant average inner diameter along a thickness of the cooling bond layer. In the alternative, the plurality of micro-channels may have a graded average inner diameter along a thickness of the cooling bond layer. In other embodiments, the plurality of micro-channels may have a wire mesh layered structure. | 2019-08-01 |
20190237390 | SEMICONDUCTOR DEVICE INCLUDING THROUGH SILICON VIAS DISTRIBUTING CURRENT - A semiconductor device includes first to M-th semiconductor dies stacked in a first direction. Each of the first to M-th semiconductor dies includes a substrate, first to K-th through silicon vias passing through the substrate in the first direction, and a first circuit to receive power through a power supply line electrically connected to the first through silicon via. Each of first to K-th through silicon vias of the N-th semiconductor die is electrically connected to a through silicon via of first to K-th through silicon vias of the (N+1)-th semiconductor die that is spaced apart therefrom in a plan view. | 2019-08-01 |
20190237391 | CHIP ASSEMBLIES EMPLOYING SOLDER BONDS TO BACK-SIDE LANDS INCLUDING AN ELECTROLYTIC NICKEL LAYER - A stacked-chip assembly including a plurality of IC chips or die that are stacked, and electrically coupled by solder bonds. In accordance with some embodiments described further below, the solder bonds are to contact a back-side land that includes a diffusion barrier to reduce intermetallic formation and/or other solder-induced reliability issues. The back-side land may include an electrolytic nickel (Ni) barrier layer separating solder from a back-side redistribution layer trace. This electrolytic Ni may be of high purity, which at least in part, may enable the backside metallization stack to be of minimal thickness while still functioning as a diffusion barrier. In some embodiments, the back-side land composition and architecture is distinct from a front-side land composition and/or architecture. | 2019-08-01 |
20190237392 | SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF - Provided is a method of manufacturing a semiconductor package, the method including a first step for forming a primary solder ball on an under bump metallurgy (UBM) structure, and a second step for forming a secondary solder ball on an upper surface of the UBM structure by performing a reflow process on the primary solder ball while a side wall of the UBM structure is exposed. | 2019-08-01 |
20190237393 | Integrated Circuit (IC) Package with a Solder Receiving Area and Associated Methods - A single chip integrated circuit (IC) package includes a die pad, and a spacer ring on the die pad defining a solder receiving area. A solder body is on the die pad within the solder receiving area. An IC die is on the spacer ring and is secured to the die pad by the solder body within the solder receiving area. Encapsulating material surrounds the die pad, spacer ring, and IC die. For a multi-chip IC package, a dam structure is on the die pad and defines multiple solder receiving areas. A respective solder body is on the die pad within a respective solder receiving area. An IC die is within each respective solder receiving area and is held in place by a corresponding solder body. Encapsulating material surrounds the die pad, dam structure, and plurality of IC die. | 2019-08-01 |
20190237394 | PACKAGE STRUCTURE OF CAPACITIVE COUPLING ISOLATOR - A package structure for a capacitive coupling isolator is provided. The package structure includes a first and a second leadframes, a transmitter, a receiver and a packaging body. The first leadframe includes a first and a second signal input pins and a first electrode plate, and the second leadframe includes a first and a second signal output pins and a second electrode plate. The first and second electrode plates are arranged one above another and aligned with each other for forming a plurality of capacitors. The transmitter is disposed on the first leadframe and the receiver is disposed on the second leadframe. The packaging body encloses the first and second leadframes and is filled therebetween for electrically isolating the first and second leadframes from each other. | 2019-08-01 |
20190237395 | Semiconductor Systems Having Premolded Dual Leadframes - A dual leadframe ( | 2019-08-01 |
20190237396 | Direct Selective Adhesion Promotor Plating - A semiconductor device includes a die paddle, a plurality of electrically conductive leads extending away from the die paddle, and an adhesion promoter plating material selectively formed on the electrically conductive leads such that outer portions of the leads are covered by the adhesion promoter plating material, and interior portions of the leads that are disposed between the die paddle and the respective outer portions of each lead are substantially devoid of the adhesion promoter plating material. | 2019-08-01 |
20190237397 | SEMICONDUCTOR PACKAGES - There is provided a method of forming a semiconductor package and a semiconductor package. The semiconductor package includes a package substrate. The package substrate includes a base layer, a first group of conductive lines disposed on a first surface of the base layer, and a second group of conductive lines disposed on a second surface of the base layer and electrically connected to respective ones of the first group of conductive lines. The package substrate further includes a plating lead line connected to one of the first group of conductive lines. | 2019-08-01 |
20190237398 | SEMICONDUCTOR PACKAGES - A semiconductor package includes a semiconductor chip and a package substrate. The package substrate includes a base layer, a first group of conductive lines disposed on a first surface of the base layer, and a second group of conductive lines disposed on a second surface of the base layer and electrically connected to respective ones of the first group of conductive lines. The package substrate further includes a plating lead line connected to one of the first group of conductive lines, opening holes located between remaining portions of the second group of conductive lines to separate the second group of conductive lines from each other. | 2019-08-01 |
20190237399 | CROSS TALK REDUCTION DIFFERENTIAL CROSS OVER ROUTING SYSTEMS AND METHODS - In one embodiment, a system comprises: a plurality of aggressor bus lines; and a plurality of differential pair bus lines that are located in relatively parallel close proximity to the plurality of aggressor bus lines, wherein at least two of the plurality of differential pair bus lines change location with respect to each other at a point that has a cancelling affect on cross talk from the plurality of aggressor bus lines, wherein the change includes cross over routing. The plurality of differential pair bus lines can convey differential clock signals. The routing of the plurality of differential pair bus lines is substantially parallel to one another before and after the change. | 2019-08-01 |
20190237400 | INTEGRATED CIRCUIT WITH METALLIC INTERLOCKING STRUCTURE - An integrated component having a metallic interlocking structure; the integrated component comprising an integrated circuit integrated in a substrate having a top surface; the integrated circuit comprising a first conducting line; and a first metallic interlocking structure comprising a first array of free-standing metallic columns formed on said top surface and electrically connected to said first conducting line. | 2019-08-01 |
20190237401 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device has a semiconductor substrate, a first insulating film formed on a surface of the semiconductor substrate, a first recess formed in the first insulating film, a first barrier film formed on an inner surface of the first insulating film except a top peripheral region of the first trench, a first conductive film formed in the first trench, and a covering film formed on an upper surface and a top peripheral region of the first conductive film and an upper surface of the first barrier film. The first conductive film includes copper. | 2019-08-01 |
20190237402 | METHOD AND STRUCTURE TO CONSTRUCT CYLINDRICAL INTERCONNECTS TO REDUCE RESISTANCE - A method for manufacturing a semiconductor device includes forming a plurality of trenches in a dielectric layer, wherein the plurality of trenches each comprise a rounded surface, depositing a liner layer on the rounded surface of each of plurality of trenches, and depositing a conductive layer on the liner layer in each of the plurality of trenches, wherein the conductive layer and the liner layer form a plurality of interconnects, and each of the plurality of interconnects has a cylindrical shape. | 2019-08-01 |
20190237403 | TRENCH MOSFET WITH SELF-ALIGNED BODY CONTACT WITH SPACER - Trench MOSFET with self-aligned body contact with spacer. In accordance with an embodiment of the present invention, a plurality of gate trenches are formed into a semiconductor substrate. A body contact trench is formed into the semiconductor substrate in a mesa between the gate trenches. Spacers are deposited on sidewalls of the body contact trench. An ohmic body contact is implanted into the semiconductor substrate through the body contact trench utilizing the spacers to self-align the implant. A body contact trench extension may be etched into the semiconductor substrate through the body contact trench utilizing the spacers to self-align the etch, prior to the implant. | 2019-08-01 |
20190237404 | METHOD OF FORMING STACKED TRENCH CONTACTS AND STRUCTURES FORMED THEREBY - Methods and associated structures of forming a microelectronic device are described. Those methods may include forming a structure comprising a first contact metal disposed on a source/drain contact of a substrate, and a second contact metal disposed on a top surface of the first contact metal, wherein the second contact metal is disposed within an ILD disposed on a top surface of a metal gate disposed on the substrate. | 2019-08-01 |
20190237405 | INTEGRATED FAN-OUT PACKAGING - The present disclosure provides a packaged device that includes a first dielectric layer; a second dielectric layer, formed over the first dielectric layer, that includes a device substrate and a via extending from the first dielectric layer and through the second dielectric layer; and a third dielectric layer, formed over the second dielectric layer, that includes a conductive pillar extending through the third dielectric layer, wherein the conductive pillar is electrically coupled to the via of the second dielectric layer. | 2019-08-01 |
20190237406 | FAN-OUT SEMICONDUCTOR PACKAGE - A fan-out semiconductor package includes: a core member having at least one through-hole formed therein and having a metal layer disposed on an internal surface thereof; an electronic component disposed in the through-hole; an encapsulant encapsulating the core member and the electronic component; a metal plate disposed on an upper surface of the encapsulant; and a wall penetrating the encapsulant to connect the metal layer and the metal plate to each other. The wall includes sections spaced apart from each other. | 2019-08-01 |
20190237407 | SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME - Provided are a semiconductor package and a method of manufacturing the same, the semiconductor package including an interconnection part including an insulation layer and an interconnection layer, a semiconductor chip disposed on the interconnection part and electrically connected to the interconnection layer through a bonding pad, and an EMI shielding part connected to the interconnection layer while covering the semiconductor chip and the interconnection part. | 2019-08-01 |
20190237408 | ELECTRONIC CONTROL UNIT - The electronic control unit ECU includes: a base | 2019-08-01 |
20190237409 | METHOD OF MAKING PLURAL ELECTRONIC COMPONENT MODULES - A method of manufacturing a plurality of identical electronic component modules includes: preparing an assembly substrate that includes a plurality of electronic components mounted thereon; digging a first groove along the dicing lines from a top surface of a sealing member that seals each electronic component, the first groove penetrating the sealing member and reaching an intermediate depth within a base substrate; widening an upper portion of the first grove to define a second groove that is continuous with the lower portion of the first groove; forming a shielding film by depositing a film made of a conductive material on the top surface of the sealing member and on inner walls of the first and second grooves that include the sidewalls of the sealing member; and thereafter, cutting the base substrate at a bottom of the lower portion of the first groove along dicing lines. | 2019-08-01 |
20190237410 | SEMICONDUCTOR PACKAGES - A semiconductor package including a heat spreading layer having at least one hole, a first semiconductor chip below the heat spreading layer, a redistribution structure below the first semiconductor chip, a first mold layer between the heat spreading layer and the redistribution structure, a shielding wall extending from the redistribution structure and the heat spreading layer and surrounding the first semiconductor chip, and a first conductive pillar extending from the redistribution structure into the hole may be provided. | 2019-08-01 |
20190237411 | PACKAGE STIFFENER FOR PROTECTING SEMICONDUCTOR DIE - The subject matter of this specification generally relates to electronic packages. In some implementations, a lidless electronic package includes a substrate having a surface and a die disposed on the surface of the substrate. The die has an outside perimeter, a bottom surface adjacent to the surface of the substrate, and a top surface. The electronic package includes a stiffener disposed on the surface of the substrate. The stiffener includes a first surface that is a first distance from the surface of the substrate and a second surface disposed between the die and the first surface. The first distance is greater than a distance between the surface of the substrate and the top surface of the die. The second surface is a second distance from the surface of the substrate that is less than the distance between the surface of the substrate and the top surface of the die. | 2019-08-01 |
20190237412 | SEMICONDUCTOR PACKAGE - A semiconductor package includes a substrate having a first surface and a second surface opposing the first surface; a plurality of first pads disposed on the first surface of the substrate and a plurality of second pads disposed on the second surface of the substrate and electrically connected to the plurality of first pads; a semiconductor chip disposed on the first surface of the substrate and connected to the plurality of first pads; a dummy chip having a side surface facing one side surface of the semiconductor chip, disposed on the first surface of the substrate spaced apart from the semiconductor chip in a direction parallel to the first surface of the substrate, the dummy chip having an upper surface positioned lower than an upper surface of the semiconductor chip in a direction perpendicular to the first surface of the substrate; an underfill disposed between the semiconductor chip and the first surface of the substrate, and having an extension portion extended along the facing side surfaces of the semiconductor chip and the dummy chip in the direction perpendicular to the first surface of the substrate, an upper end of the extension portion being disposed to be lower than the upper surface of the semiconductor chip; and a sealing material disposed on the first surface of the substrate, and sealing the semiconductor chip and the dummy chip. | 2019-08-01 |
20190237413 | PACKAGE ASSEMBLY FOR EMBEDDED DIE AND ASSOCIATED TECHNIQUES AND CONFIGURATIONS - Embodiments of the present disclosure are directed towards a package assembly for embedded die and associated techniques and configurations. In one embodiment, an apparatus includes a package assembly comprising a die attach layer, a die coupled with the die attach layer, the die having an active side including active devices of the die and an inactive side disposed opposite to the active side, a reinforced plate coupled with the die attach layer, the reinforced plate having a first side and a second side disposed opposite to the first side and a cavity disposed in the reinforced plate and one or more build-up layers coupled with the second side of the reinforced plate, the one or more build-up layers including an insulator and conductive features disposed in the insulator, the conductive features being electrically coupled with the die, wherein the inactive side of the die is in direct contact with the die attach layer, the first side of the reinforced plate is in direct contact with the die attach layer and the die is disposed in the cavity. Other embodiments may be described and/or claimed. | 2019-08-01 |
20190237414 | SEMICONDUCTOR DEVICES - The semiconductor devices may include a semiconductor substrate, and a guard ring and a crack sensing circuit on the semiconductor substrate. The semiconductor substrate may include a main chip region that is defined by the guard ring and includes the crack sensing circuit, a central portion of the main chip region surrounded by the crack sensing circuit, and a chamfer region that is in a corner portion of the main chip region and is defined by the guard ring and the crack sensing circuit. The semiconductor devices may also include at least one gate structure on the semiconductor substrate in the main chip region, a plurality of metal pattern structures on the at least one gate structure in the chamfer region, and an insulating layer on the plurality of metal pattern structures. The plurality of metal pattern structures may extend in parallel to one another and may have different lengths. | 2019-08-01 |
20190237415 | Device Comprising a Stack of Electronic Chips - A method of protecting a first chip in a multi-chip stack includes determining an electrical characteristic of a conductive loop. The conductive loop extends over a top portion of the first chip. The conductive loop also extends through the first chip and within a top portion of a second chip. The top portion of the second chip is adjacent to a bottom portion of the first chip. The method further includes determining whether the electrical characteristic indicates that an attack is being made to determine contents or operation of the first chip. | 2019-08-01 |
20190237416 | POWER DEVICE PACKAGE - A power device package includes a substrate, a high side power device, a low side power device and a driver device. The substrate includes a top surface, a bottom surface and a plurality of vias that extend through the substrate. The high side and low side power devices are disposed on the top surface of the substrate and connected with each other. The driver device is disposed on the bottom surface of the substrate and electrically connected with the high side and low side power devices through the vias to drive the high side and low side power devices in response to a control signal. The distance between the driver device and the high side and low side power devices is determined by the thickness of the substrate such that that a parasitic inductance between the driver device and the high side power device or the low side power device is reduced. | 2019-08-01 |
20190237417 | RESISTANCE AND CAPACITANCE BALANCING SYSTEMS AND METHODS - Systems and methods that facilitate resistance and capacitance balancing are presented. In one embodiment, a system comprises: a plurality of ground lines configured to ground components; and a plurality of signal bus lines interleaved with the plurality of ground lines, wherein the interleaving is configured so that plurality of signal bus lines and plurality of ground lines are substantially evenly spaced and the plurality of signal bus lines convey a respective plurality of signals have similar resistance and capacitance constants that are balanced. The plurality of signals can see a substantially equal amount ground surface and have similar amounts of capacitance. The plurality of signal bus lines can have similar cross sections and lengths with similar resistances. The plurality of signal bus lines interleaved with the plurality of ground lines can be included in a two copper layer interposer design with one redistribution layer (RDL). | 2019-08-01 |
20190237418 | Coaxial-Interconnect Structure for a Semiconductor Component - The present disclosure describes a coaxial-interconnect structure that is integrated into a semiconductor component and methods of forming the coaxial-interconnect structure. The coaxial interconnect-structure, which electrically couples circuitry of an integrated-circuit (IC) die to traces of a packaging substrate, comprises a signal core elongated about an axis, a ground shield elongated about the axis, and an insulator disposed between the signal core and the ground shield. | 2019-08-01 |
20190237419 | CONDUCTIVE BARRIER DIRECT HYBRID BONDING - A method for forming a direct hybrid bond and a device resulting from a direct hybrid bond including a first substrate having a first set of metallic bonding pads, preferably connected to a device or circuit, capped by a conductive barrier, and having a first non-metallic region adjacent to the metallic bonding pads on the first substrate, a second substrate having a second set of metallic bonding pads capped by a second conductive barrier, aligned with the first set of metallic bonding pads, preferably connected to a device or circuit, and having a second non-metallic region adjacent to the metallic bonding pads on the second substrate, and a contact-bonded interface between the first and second set of metallic bonding pads capped by conductive barriers formed by contact bonding of the first non-metallic region to the second non-metallic region. | 2019-08-01 |
20190237420 | INTERCONNECT USING NANOPOROUS METAL LOCKING STRUCTURES - Embodiments relate to the design of a device capable of maintaining the alignment an interconnect by resisting lateral forces acting on surfaces of the interconnect. The device comprises a first body comprising a first surface with a nanoporous metal structure protruding from the first surface. The device further comprises a second body comprising a second surface with a locking structure to resist a lateral force between the first body and the second body during or after assembly of the first body and the second body. | 2019-08-01 |
20190237421 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes a pad electrode formed over a semiconductor substrate, a conductor pillar formed on the pad electrode, a cap film formed on the conductor pillar and made of a nickel film, a terminal formed in a wiring board, a metal film formed on the terminal and made of a nickel film containing phosphorus, a solder layer interposed between the cap film and the metal film and containing tin as a main component, and an alloy layer interposed between the solder layer and the metal film and containing tin and copper. | 2019-08-01 |
20190237422 | SEMICONDUCTOR DEVICE HAVING A BOUNDARY STRUCTURE, A PACKAGE ON PACKAGE STRUCTURE, AND A METHOD OF MAKING - The present disclosure, in some embodiments, relates to a semiconductor structure. The semiconductor structure includes a substrate and a first conductive pad arranged over the substrate. A boundary structure is on an upper surface of the substrate around the first conductive pad. The boundary structure has one or more sidewalls defining an opening with a round shape over the first conductive pad. | 2019-08-01 |
20190237423 | PACKAGE STRUCTURE AND METHOD OF MANUFACTURING THE SAME - A package structure and a method of forming the same are provided. The package structure includes a first die, an encapsulant, a first RDL structure, and a conductive terminal. The encapsulant is aside the first die, encapsulating sidewalls of the first die. The first RDL structure is on the first die and the encapsulant. The conductive terminal is electrically connected to first die through the RDL structure. The first RDL structure comprises a first polymer layer and a first RDL, the first polymer layer comprises a non-shrinkage material and a top surface of the first polymer layer is substantially flat. | 2019-08-01 |
20190237424 | CONNECTION STRUCTURE AND METHOD FOR MANUFACTURING CONNECTION STRUCTURE - A method for manufacturing connection structure, the method includes arranging conductive particles and a first composite on a first electrode located on a first surface of a first member, arranging a second composite on the first electrode and a region other than the first electrode of the first surface, ranging the first surface and a second surface of a second member where a second electrode is located, so that the first electrode and the second electrode are opposed to each other, pressing the first member and the second member, and curing the first composite and the second composite. | 2019-08-01 |
20190237425 | POWER ELECTRONICS ASSEMBLIES WITH METAL INVERSE OPAL BONDING, ELECTRICAL CONTACT AND COOLING LAYERS, AND VEHICLES INCORPORATING THE SAME - A power electronics assembly includes a substrate, a semiconductor device and a metal inverse opal (MIO) bonding layer positioned between and bonded to the substrate and the semiconductor device. A first electrode is disposed on a first surface, a second electrode is disposed on a second surface, and a third electrode is disposed on a third surface. The first surface may be a top surface of the semiconductor device, the second surface may be a bottom surface of the semiconductor device, the third surface may be spaced apart from the bottom surface of the semiconductor device, and the second electrode is in electrical communication with the third electrode through the MIO bonding layer. A cooling fluid circuit with a cooling fluid inlet, a cooling fluid outlet and a cooling fluid path through the MIO bonding layer may be included. | 2019-08-01 |
20190237426 | ANISOTROPIC ELECTRICALLY CONDUCTIVE FILM - An anisotropic electrically conductive film has a structure wherein the electrically conductive particles are disposed on or near the surface of an electrically insulating adhesive base layer, or a structure wherein an electrically insulating adhesive base layer and an electrically insulating adhesive cover layer are laminated together and the electrically conductive particles are disposed near the interface therebetween. Electrically conductive particle groups configured from two or more electrically conductive particles are disposed in a lattice point region of a planar lattice pattern. A preferred lattice point region is a circle centered on a lattice point. A radius of the circle is not less than two times and not more than seven times the average particle diameter of the electrically conductive particles. | 2019-08-01 |
20190237427 | CLEANING SYSTEMS FOR WIRE BONDING TOOLS, WIRE BONDING MACHINES INCLUDING SUCH SYSTEMS, AND RELATED METHODS - A wire bonding machine is provided. The wire bonding machine includes: (a) a wire bonding tool; (b) a wire guide for guiding a wire to a position beneath a bonding surface of the wire bonding tool, the wire guide being configured for movement between (i) an engagement position with respect to the wire bonding tool and (ii) a non-engagement position with respect to the wire bonding tool; and a cleaning station for cleaning at least a portion of a tip of the wire bonding tool when the wire guide is in the non-engagement position. | 2019-08-01 |
20190237428 | METHOD FOR CALIBRATING WIRE CLAMP DEVICE, AND WIRE BONDING APPARATUS - A method for calibrating a wire clamp device includes: preparing a wire clamp device provided with a pair of arm parts having tips for clamping a wire, the arms extending from the tips toward base ends, and a drive part provided with a piezoelectric element for drive, connected to the base ends of the pair of arm parts and opening/closing the tips of the pair of arm parts; a step of detecting, by electrical continuity between the tips, a timing at which the pair of arm parts enters a closed state when the piezoelectric element for drive is driven, and acquiring a reference voltage; and a step of calibrating, on the basis of the reference voltage, an application voltage to be applied to the piezoelectric element for drive. Thus, it is possible to perform accurate and stable wire bonding. | 2019-08-01 |
20190237429 | HYBRID WAFER-TO-WAFER BONDING AND METHODS OF SURFACE PREPARATION FOR WAFERS COMPRISING AN ALUMINUM METALIZATION - A surface treatment solution includes a fluoride source; a first solvent; and a water transforming agent to transform water produced during wafer surface treatment into a second solvent, which can be the same as, or different from, the first solvent. The solution can be used, for example, in surface preparation for wafers having a backend including an electrical interconnect that includes aluminum or an aluminum alloy. | 2019-08-01 |
20190237430 | 3D IC PACKAGE WITH RDL INTERPOSER AND RELATED METHOD - A 3D IC package includes a bottom die having a back interconnect side opposing a front device side, the back interconnect side having a plurality of bottom die interconnects extending thereto. A top die has a front device side opposing a back side, the front device side having a plurality of top die interconnects. An interposer includes a redistribution layer (RDL) between the bottom die and the top die, the RDL including a plurality of wiring layers extending from back side RDL interconnects thereof to front side RDL interconnects thereof. An under bump metallization (UBM) couples the back side RDL interconnects to the plurality of top die interconnects at a first location, and the front side RDL interconnects are coupled to the plurality of bottom die interconnects at a second location. The first location and second location may not overlap. | 2019-08-01 |
20190237431 | SEMICONDUCTOR PACKAGE - A semiconductor package includes a substrate, a master chip on the substrate, a first slave chip on a top surface of the master chip and partially exposing the top surface of the master chip, the first slave chip having a same size as the master chip and having a same storage capacity as the master chip, and a first chip connector on the exposed top surface of the master chip and coupled to the master chip and the first slave chip. | 2019-08-01 |
20190237432 | SEMICONDUCTOR PACKAGES - A semiconductor package includes a substrate including a signal pattern on an upper surface thereof, a chip stack on the substrate, and a first semiconductor chip and one or more spacers between the substrate and the chip stack. The chip stack includes one or more second semiconductor chips stacked on the substrate. The one or more spacers and the first semiconductor chip are adjacent to respective corners of a lowermost second semiconductor chip, in plan view. The one or more spacers have the same planar shape as the first semiconductor chip. | 2019-08-01 |
20190237433 | METHODS TO FORM REDUCED FORM FACTOR RADIO FREQUENCY SYSTEM-IN-PACKAGE - Methods to form stacked circuit assemblies include mounting a first wireless device component to a first surface of a substrate and placing a second wireless device component over the first wireless device component such that the first wireless device component is disposed between the second wireless device component and the first surface of the substrate such that a first overhanging portion of the second wireless device component extends beyond a periphery of the first wireless device component. The first wireless device component is in communication with the second wireless device component and second wireless device component is in communication with the substrate. | 2019-08-01 |
20190237434 | INTERCONNECT STRUCTURES WITH INTERMETALLIC PALLADIUM JOINTS AND ASSOCIATED SYSTEMS AND METHODS - Interconnect structures with intermetallic palladium joints are disclosed herein. In one embodiment, an interconnect structure includes a first conductive element, a second conductive element, and an intermetallic palladium joint. The intermetallic palladium joint includes an intermetallic crystallite spanning between the first and second conductive elements. The intermetallic crystallite includes a first end portion and a second end portion. The first end portion directly contacts the first conductive element. The second end portion directly contacts the second conductive element. | 2019-08-01 |
20190237435 | Method of Manufacturing a Semiconductor Device - A link device with a large density routing is attached to a package in order to provide a high-density interconnect pathway to interconnect semiconductor devices. In an embodiment the package is an integrated fan out package. The link device may be bonded on either side of the package, and the package may optionally comprise through package vias. The link device may also be an integrated passive device that includes resistors, inductor, and capacitor components. | 2019-08-01 |
20190237436 | SYSTEM IN PACKAGE (SIP) WITH DUAL LAMINATE INTERPOSERS - There is provided a semiconductor device assembly with an interposer and method of manufacturing the same. More specifically, in one embodiment, there is provided a semiconductor device assembly comprising a semiconductor substrate, at least one semiconductor die attached to the semiconductor substrate, an interposer disposed on the semiconductor die, and a controller attached to the interposer. There is also provided a method of manufacturing comprising forming a first subassembly by coupling a substrate and a semiconductor die, and forming second subassembly by attaching a controller to an interposer, and coupling the first subassembly to the second subassembly. | 2019-08-01 |
20190237437 | NANOSCALE INTERCONNECT ARRAY FOR STACKED DIES - A microelectronic assembly including an insulating layer having a plurality of nanoscale conductors disposed in a nanoscale pitch array therein and a pair of microelectronic elements is provided. The nanoscale conductors can form electrical interconnections between contacts of the microelectronic elements while the insulating layer can mechanically couple the microelectronic elements together. | 2019-08-01 |
20190237438 | DUAL SIDED FAN-OUT PACKAGE HAVING LOW WARPAGE ACROSS ALL TEMPERATURES - Semiconductor devices including a dual-sided redistribution structure and having low-warpage across all temperatures and associated systems and methods are disclosed herein. In one embodiment, a semiconductor device includes a first semiconductor die electrically coupled to a first side of a redistribution structure and a second semiconductor die electrically coupled to a second side of the redistribution structure opposite the first side. The semiconductor device also includes a first molded material on the first side, a second molded material on the second side, and conductive columns electrically coupled to the first side and extending through the first molded material. The first and second molded materials can have the same volume and/or coefficients of thermal expansion to inhibit warpage of the semiconductor device. | 2019-08-01 |
20190237439 | SILICON CARBIDE POWER MODULE - A power module includes a case, a first terminal, a second terminal, and a number of silicon carbide semiconductor die. The case has a footprint less than 30 cm | 2019-08-01 |
20190237440 | POWER MODULE - A power module may include a first bus bar having a first plurality of tabs, wherein each of the first plurality of tabs is electrically coupled to a respective conductive trace of a plurality of conductive traces disposed on a first side; a second bus bar having a second plurality of tabs, wherein each of the second plurality of tabs is electrically coupled to a respective conductive trace of a plurality of conductive traces disposed on a second side; and a third bus bar having a third plurality of tabs, wherein at least one tab of the third plurality of tabs is electrically coupled to a respective conductive trace of the plurality of conductive traces disposed on the first side and at least one tab of the third plurality of tabs is electrically coupled to a respective conductive trace of the plurality of conductive traces disposed on the second side. | 2019-08-01 |
20190237441 | DISPLAY DEVICE, DISPLAY SYSTEM, AND MANUFACTURING METHOD OF DISPLAY DEVICE - A display device includes plural pixel elements that are arranged on a foundation substrate in a matrix manner. Among the plural pixel elements, outside pixel elements positioned in an outer periphery are set as a non-display region, and inside pixel elements positioned on an inside are set as a display region. | 2019-08-01 |
20190237442 | COLOUR INORGANIC LED DISPLAY FOR DISPLAY DEVICES WITH A HIGH NUMBER OF PIXEL - An image generator for use in a display device, the image generator comprising a plurality of ILED array chips each comprising a plurality of ILED emitters and arranged in an array such that each of a plurality of pixels of the image generator comprises an ILED emitter from each of a plurality of adjacent ILED array chips. The toal area of ILED emitter material be less than 50% of the area of each pixel. The image generator may comprise secondary optics in optical communication with an output of the plurality of ILED emitters of an ILED array chip and configured to direct light from the ILED emitters towards an emission region of the associated pixel. | 2019-08-01 |
20190237443 | MODULE FOR A VIDEO WALL, AND METHOD OF PRODUCING SAME - A module for a video wall includes a plurality of light-emitting components; and a carrier including conduction regions, wherein the light-emitting components each include a top side including a top-side contact and an underside including an underside contact, the light-emitting components are configured to emit electromagnetic radiation via the top side, the underside contacts of the light-emitting components electrically conductively connect to the conduction regions, the top-side contacts electrically contact a conductive layer, the light-emitting components each include at least four light-emitting semiconductor chips, the light-emitting semiconductor chips within a light-emitting component interconnect in parallel with one another, the light-emitting semiconductor chips within a light-emitting component each electrically conductively connect to the top-side contacts and the underside contacts of the light-emitting component, a plurality of adjacent light-emitting components constitute a cluster, and the light-emitting semiconductor chips of the light-emitting components of a cluster includes an identical nominal wavelength. | 2019-08-01 |
20190237444 | LIGHT EMITTING STRUCTURE TO AID LED LIGHT EXTRACTION - Display panels and methods of manufacture are described for down converting a peak emission wavelength of a pump LED within a subpixel with a quantum dot layer. In some embodiments, pump LEDs with a peak emission wavelength below 500 nm, such as between 340 nm and 420 nm are used. QD layers in accordance with embodiments can be integrated into a variety of display panel structures including a wavelength conversion cover arrangement, QD patch arrangement, or QD layers patterned on the display substrate. | 2019-08-01 |
20190237445 | METHOD FOR IMPROVED TRANSFER OF SEMICONDUCTOR DIE - A system to effectuate improved transfer of semiconductor die. A first frame secures a first substrate having the semiconductor die. A second frame secures a second substrate adjacent the first substrate. A needle is disposed adjacent to the first frame. The needle includes: a longitudinal surface extending in a direction toward the second frame, and a base end having a cross-sectional dimension being based, at least in part, on a cross-sectional dimension of the semiconductor die. A needle actuator is operably connected to the needle and is configured to actuate the needle such that, during the transfer operation, when the first substrate is secured in the first frame and the second substrate is secured in the second frame, the needle presses the semiconductor die into contact with the second substrate so as to transfer the semiconductor die onto the second substrate. | 2019-08-01 |
20190237446 | MICRO-LED 3D DISPLAY MODULES AND METHODS FOR FABRICATING THE SAME - Micro-LED 3D display modules are disclosed. Each of the micro-LED 3D display module includes a module substrate and a micro-LED array mounted on the module substrate. The micro-LED array includes first micro-LED pixels attached with a first polarization film having a first phase retardation property and second micro-LED pixels attached with a second polarization film having a second phase retardation property. | 2019-08-01 |
20190237447 | Light Emitting Display System Having Improved Fire Performance - Disclosed are embodiments of fire resistant display components, systems and associated methods. The system comprises a plurality of light emitting display modules, each display module being constructed to have improved fire resistance as measured by one or more fire performance characteristics including heat release, smoke density, smoke toxicity, flame spread or drip. | 2019-08-01 |
20190237448 | POWER SEMICONDUCTOR MODULE AND POWER SEMICONDUCTOR DEVICE - Gates of semiconductor switching elements are connected to a gate control wiring pattern. The gate control wiring pattern is further connected to a gate control terminal and a filter terminal which are connected by an element for forming a filter outside a housing. The filter terminal and the gate control terminal are connected to the gate control wiring pattern in such a manner that a section electrically connecting the filter terminal and the gate control terminal overlaps with at least a part of a section electrically connecting the gates of the semiconductor switching elements on the gate control wiring pattern. | 2019-08-01 |
20190237449 | LIGHT EMITTING DIODE PANEL AND METHOD FOR MANUFACTURING THE LIGHT EMITTING DIODE PANEL - A light emitting diode (LED) panel is provided. The LED panel includes a thin-film transistor (TFT) backplane which includes a plurality of LED bonding areas, and a plurality of LEDs which are respectively bonded to the plurality of LED bonding areas, wherein the plurality of LED bonding areas are formed to have different heights on the TFT backplane according to an LED type bonded thereto, and wherein a relatively thin LED from among the plurality of LEDs is bonded to an LED bonding area of a relatively low height from among the plurality of LED bonding areas. | 2019-08-01 |
20190237450 | Micro LED Display Module Having Light Transmissive Substrate - A micro LED display module having a light transmissive substrate and a manufacturing method thereof are provided. The light transmissive substrate has good transmissivity with respect to the visible band. The micro LED display module comprises a driver chip block, a LED block, a circuit board and a color layer. The LED block is disposed in the driver chip block and has two semiconductor layers and a plurality of trenches. One of the two semiconductor layers is electrically connected to pixel electrodes and the other is electrically connected to the light transmissive substrate. The trenches define a plurality of micro LED pixels arranged in an array. Each micro LED pixel corresponds to one of the pixel electrodes. The circuit board is electrically connected to the driver chip block, the color layer is disposed in the light transmissive conductive layer, and one of the semiconductor layers has a common electrode. | 2019-08-01 |
20190237451 | Micro LED Display Module - A micro LED display module and a manufacturing method thereof are provided. The micro LED display module comprises a driver chip block, a LED block, a circuit board and a color layer. The driver chip block has a plurality of pixel electrodes. The LED block is disposed in the driver chip block and has two semiconductor layers and a plurality of trenches. One of the two semiconductor layers is electrically connected to the pixel electrodes and the other is electrically connected to the light transmissive conductive layer. The trenches define a plurality of micro LED pixels arranged in an array. Each trench at least penetrates through the light emitting layer and one of the semiconductor layers. Each micro LED pixel corresponds to one of the pixel electrodes. The circuit board is electrically connected to the driver chip block, the color layer is disposed in the light transmissive conductive layer, and one of the semiconductor layers has a common electrode. | 2019-08-01 |
20190237452 | DISPLAY DEVICE HAVING A PLURALITY OF BANK STRUCTURES - The embodiment provides a display device including an array substrate, an opposite substrate, a plurality of micro light-emitting diodes and a plurality of bank structures. The opposite substrate is disposed opposite to the array substrate. The micro light-emitting diodes are arranged in an array on the array substrate, wherein the micro light-emitting diodes are electrically connected to the array substrate. The bank structures are located between the array substrate and the opposite substrate, wherein the bank structures form a plurality of accommodating regions, and one of the micro light-emitting diodes is located in one of the accommodating regions. A height of the bank structures is more than or equal to a height of the micro light-emitting diodes. | 2019-08-01 |
20190237453 | SEMICONDUCTOR DEVICE - A semiconductor device includes a first semiconductor chip formed with an IGBT, a second semiconductor chip formed with a MOSFET, a first metal member electrically connected to a collector electrode and a drain electrode, and a second metal member electrically connected to an emitter electrode and a source electrode. The IGBT and the MOSFET connected in parallel to each other are turned on in the order of the IGBT and the MOSFET, and turned off in the order of the MOSFET and the IGBT. The second metal member has a main body portion on which the first and second semiconductor chips are mounted, and a joint portion as a terminal portion connected to the main body portion. In a plan view, a shortest distance between the joint portion and the first semiconductor chip is shorter than a shortest distance between the joint portion and the second semiconductor chip. | 2019-08-01 |
20190237454 | INTEGRATED CIRCUIT PACKAGE AND METHOD OF FORMING SAME - An integrated circuit package and a method of forming the same are provided. The method includes attaching an integrated circuit die to a first substrate. A dummy die is formed. The dummy die is attached to the first substrate adjacent the integrated circuit die. An encapsulant is formed over the first substrate and surrounding the dummy die and the integrated circuit die. The encapsulant, the dummy die and the integrated circuit die are planarized, a topmost surface of the encapsulant being substantially level with a topmost surface of the dummy die and a topmost surface of the integrated circuit die. An interior portion of the dummy die is removed. A remaining portion of the dummy die forms an annular structure. | 2019-08-01 |
20190237455 | CONDUCTIVE LAYER STRUCTURES FOR SUBSTRATES - An example substrate includes a surface, a plurality of thin film layers disposed on the surface, and a conductive layer disposed on the surface. The conductive layer includes a bending structure. The bending structure includes a wavy edge and includes a plurality of openings, where a shape of at least one opening of the plurality of openings has a contour having a first curved portion, and a curvature of a portion of the wavy edge is different from a curvature of the first curved portion. | 2019-08-01 |
20190237456 | ELECTROSTATIC DISCHARGE PROTECTION CIRCUIT AND SEMICONDUCTOR CIRCUIT - The present disclosure provides a electrostatic discharge (ESD) protection circuit, coupled between a first reference terminal and a second reference terminal; the ESD protection circuit includes a first voltage divider, a second voltage divider, a first trigger circuit and a second trigger circuit. The first trigger circuit includes a first terminal and a second terminal, wherein the first terminal is coupled to the first reference terminal, and the second terminal is coupled to the second reference terminal via the first voltage divider. The second trigger circuit includes a first terminal and a second terminal, wherein the first terminal is coupled to the second reference terminal, the second terminal is coupled to the first reference terminal via the second voltage divider, and the second trigger circuit and the first trigger circuit are in parallel connection. | 2019-08-01 |
20190237457 | SEMICONDUCTOR DEVICE - A semiconductor device configures a protection element that protects a protection target element connected between a cathode electrode and an anode electrode when a parasitic transistor configured by a cathode region, a first conductivity type well layer, and a second conductivity type well is turned on and electrical continuity is established between the cathode electrode and the anode electrode. The semiconductor device includes a plurality of body regions in one cell of the protection element, and the plurality of body regions is brought in contact with the cathode electrode. | 2019-08-01 |
20190237458 | SEMICONDUCTOR DEVICE HAVING MULTIPLE GATE PADS - Disclosed are semiconductor devices that include additional gate pads, and methods of fabricating and testing such devices. A device may include a first gate pad, a second gate pad, and a third gate pad. The first gate pad is connected to a gate including a gate oxide layer. The second and third gate pads are part of an electro-static discharge (ESD) protection network for the device. The ESD protection network is initially isolated from the first gate pad and hence from the gate and gate oxide layer. Accordingly, gate oxide integrity (GOI) testing can be effectively performed and the reliability and quality of the gate oxide layer can be checked. The second gate pad can be subsequently connected to the first gate pad to enable the ESD protection network, and the third gate pad can be subsequently connected to an external terminal when the device is packaged. | 2019-08-01 |
20190237459 | SEMICONDUCTOR DEVICE, METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE, AND PID PROTECTION DEVICE - The present disclosure relates to a semiconductor device, a method for manufacturing a semiconductor device, and a plasma-induced damage (PID) protection device capable of, without increasing a chip area, releasing a large PID with high efficiency and protecting an element to be protected from the PID with higher accuracy. There are provided a protection metal-oxide-semiconductor field-effect transistor (MOSFET) that includes a drain connected to a gate electrode of a MOSFET to be protected and a grounded source and protects the MOSFET to be protected from a plasma-induced damage (PID), and a dummy antenna connected to a gate electrode of the protection MOSFET, the dummy antenna turning on the protection MOSFET prior to the MOSFET to be protected due to PID charge. The present disclosure can be applied to a semiconductor device. | 2019-08-01 |
20190237460 | METHOD OF FABRICATING SEMICONDUCTOR DEVICE - A method for fabricating a semiconductor device includes the steps of providing a semiconductor substrate; forming a tunnel dielectric on the semiconductor substrate; forming a floating gate on the tunnel dielectric; forming an insulation layer conformally disposed on the top surface and the sidewall surface of the floating gate; forming a control gate disposed on the insulation layer and the floating gate; and forming a spacer continuously distributed on the sidewall surfaces of the floating gate and the control gate, where the spacer overlaps portions of the top surface of the floating gate | 2019-08-01 |
20190237461 | 3D SEMICONDUCTOR DEVICE - A 3D semiconductor device including: a first die, comprising a first die area and a plurality of first die top contacts; a second die, comprising a second die area and a plurality of first bottom contacts; and a third die, comprising a third die area and a plurality of second bottom contacts, wherein said first die area is greater than the sum of said second die area and said third die area, wherein said second die and said third die are both placed on top of said first die laterally with respect to each other, wherein said plurality of first bottom contacts are connected to said first die top contacts, and wherein said plurality of second bottom contacts are connected to said first die top contacts. | 2019-08-01 |